TPS629206QDRLRQ1 [TI]
采用 SOT-583 封装的汽车类 3V 至 17V、0.6A、低 IQ 同步降压转换器 | DRL | 8 | -40 to 150;
| 型号： | TPS629206QDRLRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-583 封装的汽车类 3V 至 17V、0.6A、低 IQ 同步降压转换器 | DRL | 8 | -40 to 150 转换器 |
| 文件： | 总51页 (文件大小：4414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS629210-Q1
SLVSFS6B – MAY 2021 – REVISED DECEMBER 2021
TPS629210-Q1 3-V to 17-V, 1-A Low IQ Buck Converter in a SOT-583 Package
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– –40°C to 150°C operating junction temperature
range
– Level 2 device HBM ESD classification
– Level C4B CDM ESD classification
Functional Safety-Capable
– Documentation available to aid functional safety
system design
High-efficiency DCS-Control™ topology
4-µA typical low quiescent current
Dynamically selectable forced PWM or auto power
save mode operations
2.5-MHz or 1.0-MHz selectable switching
frequencies
Output current up to 1 A
RDSON: 250-mΩ high side, 85-mΩ low side
Output voltage accuracy of ± 1%
Configurable output voltage options:
– VFB external divider: 0.6 V to 5.5 V
– VSET internal divider:
The automotive-qualified TPS6292xx-Q1 family of
devices are highly efficient, small, and highly flexible
synchronous step-down DC-DC converters that are
easy to use. A wide 3-V to 17-V input voltage range
supports a wide variety of systems powered from
either 12-V, 5-V, or 3.3-V supply rails, or single-cell
or multi-cell Li-Ion batteries. The TPS629210-Q1 can
be configured to run at either 2.5 MHz or 1 MHz
in a forced PWM mode or a variable frequency
(auto PFM) mode. In auto PFM mode, the device
automatically transitions to power save mode at
light loads to maintain high efficiency. The low 4-µA
typical quiescent current also provides high efficiency
down to the smallest loads. TI's automatic efficiency
enhancement (AEE) mode holds a high conversion
efficiency through the whole operation range without
the need of using different inductors by automatically
adjusting the switching frequency based on input and
output voltages. In addition to selecting the switching
frequency behavior, the MODE/S-CONF input pin can
also be used to select between different combinations
of external and internal feedback dividers and
enabling and disabling the output voltage discharge
capability. In the internal feedback configuration, a
resistor between the FB/VSET pin and GND can be
used to select between 18 different output voltage
options (see Table 8-2).
•
•
•
•
•
•
•
•
•
•
18 options between 0.4 V and 5.5 V
•
•
•
•
•
•
•
No external bootstrap capacitor required
Output overcurrent and overtemperature protection
100% duty cycle mode
Precise enable input
Power-good output
Selectable active output discharge
Pin-to-pin compatible with the TPS629206-Q1 and
TPS629203-Q1 devices
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
0.5-mm pitch, 8-pin SOT-583 package
1.60 mm × 2.10 mm
(including pins)
TPS629210-Q1
SOT-583 (8)
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
VIN
ADAS and infotainment
Telecom and wireless infrastructure
Factory automation and control
100
90
80
70
60
50
40
VOUT
0.4V œ 5.5V
2.2 µH
3V œ 17V
VIN
EN
SW
22 ꢀF
4.7 ꢀF
VOS
FB/
VSET
MODE/
S-CONF
30
PG
VIN = 6V
VIN = 9V
20
GND
VIN = 12V
VIN = 15V
10
0
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
Simplified Schematic
Efficiency Versus Output Current
VOUT = 3.3 V at 2.5 MHz Auto PFM/PWM
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS629210-Q1
SLVSFS6B – MAY 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................15
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
9.3 System Examples..................................................... 38
10 Power Supply Recommendations..............................39
11 Layout...........................................................................40
11.1 Layout Guidelines................................................... 40
11.2 Layout Example...................................................... 40
12 Device and Documentation Support..........................42
12.1 Device Support....................................................... 42
12.2 Documentation Support.......................................... 42
12.3 Receiving Notification of Documentation Updates..42
12.4 Support Resources................................................. 42
12.5 Trademarks.............................................................42
12.6 Electrostatic Discharge Caution..............................43
12.7 Glossary..................................................................43
13 Mechanical, Packaging, and Orderable
Information.................................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2021) to Revision B (December 2021)
Page
•
Changed device status from Advance Information to Production Data.............................................................. 1
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5 Device Comparison Table
DEVICE NUMBER OUTPUT CURRENT
OPERATING
TEMPERATURE
RANGE
INPUT
VOLTAGE
SWITCHING
FREQUENCY
PWM MODE
VO ADJUST
TPS629203-Q1
TPS629206-Q1
TPS629210-Q1
0 A–0.3 A
0 A–0.6 A
0 A–1 A
Externally
programmable or 18
internal options
Selectable 1-MHz or Selectable auto PWM/PFM
3 V–17 V
–40°C to 150°C
2.5-MHz options
or forced PWM
6 Pin Configuration and Functions
/
F
E
N
D
D
O
N
N
I
C
N
-
MO
G
E
V
S
8
1
7
6
5
2
3
4
/
T
B
S
G
P
E
F
W
S
O
V
S
Figure 6-1. TPS629210-Q1 Pinout
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Dependent upon device configuration (see Section 8.3.1)
•
•
FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to Table 8-2.
FB/VSET
1
I
PG
2
3
4
5
O
I
Open-drain power-good output
VOS
SW
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
Switch pin of the converter. Connected to the internal power switches
Ground pin
GND
Power supply input. Make sure the input capacitor is connected as close as possible between
the VIN pin and GND.
VIN
EN
6
7
8
I
I
I
Enable/disable pin including a threshold comparator. Connect to logic low to disable the device.
Pull high to enable the device. Do not leave this pin unconnected.
Device mode selection (auto PFM/PWM or forced PWM operation) and Smart-CONFIG pin.
Connect a resistor to configure the device according to Table 8-1.
MODE/S-CONF
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3.0
–0.3
MAX
UNIT
V
Voltage(2)
Voltage(2)
Voltage(2)
Voltage(2)
Current
Tstg
VIN, EN, PG, MODE/S-CONF
SW(3)
18
VIN + 0.3
V
SW (AC, less than 10 ns)(3)
23
6
V
FB/VSET, VOS
V
PG
10
mA
°C
Storage temperature
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.
(3) While switching
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
V(ESD)
Electrostatic discharge
Electrostatic discharge
±2000
V
Charged device model (CDM), per AEC
Q100-011
V(ESD)
±750
V
CDM ESD classification level C4B
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.4
3
NOM
MAX
17
UNIT
V
VI
Input voltage range
VO
Output voltage range
Effective input capacitance
Effective output capacitance(1)
Output inductance(2)
5.5
V
CI
4.7
22
µF
µF
µH
A
CO
L
10
100
4.7(4)
1
1.0(3)
2.2
IOUT
ISINK_PG
TJ
Output current
0
Sink current at the PG pin
Junction temperature (5)
1
mA
°C
-40
150
(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
(2) Nominal inductance value
(3) Not recommended for 1-MHz operation
(4) Larger values of inductance may be used to reduce the ripple current, but they can have a negative impact on efficiency and the
overall transient response.
(5) Operating lifetime is derated at junction temperatures greater than 150°C.
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7.4 Thermal Information
TPS629210-Q1
THERMAL METRIC(1)
SOT583 (8)
UNIT
JEDEC PCB
TPS6292xx EVM
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
120
45
25
1
60
n/a
n/a
n/a
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ΨJB
20
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VI = 3 V to 17 V, TJ = –40°C to +150°C , Typical values at VI = 12 V and TA = 25°C,unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Operating quiescent current (power
save mode)
IQ
IOUT = 0 mA, device not switching
4
5
µA
Operating quiescent current (PWM
mode)
VIN = 12 V, VOUT = 1.2 V; IOUT = 0 mA,
device switching
IQ;PWM
ISD
VUVLO
VUVLO
mA
Shutdown current into the VIN pin
Undervoltage lockout
EN = 0 V
VIN rising
VIN falling
0.25
2.95
2.75
200
3
3.0
µA
V
2.85
2.65
Undervoltage lockout
2.85
V
Undervoltage lockout hysteresis
mV
CONTROL and INTERFACE
ILKG
EN Input leakage current
EN = VIN
3
300
nA
V
High-level input voltage at the
MODE/S-CONF pin
VIH;MODE
1.0
Low-level input voltage at the
MODE/S-CONF pin
VIL;MODE
0.15
V
VIH
VIL
High-level input voltage at the EN pin
Low-level input voltage at the EN pin
0.97
0.87
93%
89%
1.0
0.9
1.03
0.93
99%
96%
V
V
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
hysteresis
96%
93%
3%
32
VPG
Power-good threshold
VPG_HYS
tPG,DLY
tPG,DLY
VPG,OL
IPG,LKG
Power-good threshold hysteresis
Power-good delay time
µs
Ω
Power-good pulldown resistance
10
Low-level output voltage at the PG pin ISINK = 1 mA
0.1
1
V
Input leakage current into the PG pin
VPG = 5 V
0.01
µA
POWER SWITCHES
High-side FET on resistance
250
85
RDS;ON
mΩ
Low-side FET on resistance
High-side FET current limit
Low-side FET current limit
Low-side FET sink current limit
Thermal shutdown threshold
Thermal shutdown hysteresis
Switching frequency
1.5
1.3
0.8
1.8
1.6
1
2.1
1.9
1.2
A
A
A
ILIM
ILIM;SINK
TSD
TJ rising
170
20
°C
TJ falling
fSW
fSW
2.5-MHz selection (FPWM mode)
1.0-MHz selection (FPWM Mode)
2.5
1.0
MHz
MHz
Switching frequency
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VI = 3 V to 17 V, TJ = –40°C to +150°C , Typical values at VI = 12 V and TA = 25°C,unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
TON(MIN)
ILKG;SW
Minimum on time
40
Leakage current into the SW pin
EN = 0 V, VSW = VOS = 5.5 V
0.1
5
µA
OUTPUT
VSET Configuration selected, 0°C ≤ TJ
≤ 85°C
VO
VO
Output voltage regulation
Output voltage regulation
–1%
+1%
VSET Configuration selected, –40°C ≤
TJ ≤ 150°C
–1.4%
+1.1%
VFB
VFB
Feedback regulation voltage
Feedback voltage regulation
Adjustable configuration selected
FB option selected, 0°C ≤ TJ ≤ 85°C
0.6
V
–0.75%
–1.2%
+0.75%
+0.75%
100
FB option selected, –40°C ≤ TJ ≤
150°C
VFB
IFB
Feedback voltage regulation
Input leakage current into the FB pin
Adjustable configuration, VFB = 0.6 V
1
nA
µs
IO = 0 mA, time from EN rising
edge until start switching, external FB
configuration selected
Start-up delay time
Start-up delay time
700
1500
1800
Tdelay
IO = 0 mA, time from EN rising
edge until start switching, VSET
configuration selected
1000
µs
IO = 0 mA after Tdelay, from first
switching pulse until target VO
TSS
Soft-start time
600
7.5
700
20
µs
Ω
Discharge = ON - option selected, EN
= LOW,
RDISCH
Active discharge resistance
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7.6 Typical Characteristics
10
9
8
7
6
5
4
3
2
1
0
1.4
1.2
1
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
0.8
0.6
0.4
0.2
0
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
Measured with the device not switching
Figure 7-2. Typical Shutdown Current vs Temperature
Figure 7-1. Typical Quiescent Current vs Temperature
0.5
5.05
Vin = 3V
Vin = 6V
Vin = 6V
Vin = 12V
0.4
5.04
Vin = 17V
Vin = 12V
Vin = 17V
5.03
0.3
0.2
5.02
5.01
5
0.1
0
4.99
4.98
4.97
4.96
4.95
-0.1
-0.2
-0.3
-0.4
-0.5
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VOUT = 5.0 V
Figure 7-4. Output Voltage Accuracy – VSET Selected
Figure 7-3. Output Voltage Accuracy – External Feedback
1.818
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
1.812
1.806
1.8
1.794
1.788
1.782
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
VOUT = 3.3 V
VOUT = 1.8 V
Figure 7-5. Output Voltage Accuracy – VSET Selected
Figure 7-6. Output Voltage Accuracy – VSET Selected
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7.6 Typical Characteristics (continued)
VOUT = 1.2 V
VOUT = 0.6 V
Figure 7-8. Output Voltage Accuracy – VSET Selected
Figure 7-7. Output Voltage Accuracy – VSET Selected
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
Vin = 3V
Vin = 6V
2
Vin = 12V
Vin = 17V
1.8
1.9
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
FSW = 2.5 MHz
FPWM
VOUT = 1.2 V
Fsw = 1.0 MHz
FPWM
IOUT = 0 A
VOUT = 1.2 V
IOUT = 0 A
Figure 7-10. Switching Frequency vs Temperature
Figure 7-9. Switching Frequency vs Temperature
Figure 7-11. High-Side RDSON vs Temperature
Figure 7-12. Low-Side RDSON vs Temperature
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7.6 Typical Characteristics (continued)
1.85
1.65
1.64
1.63
1.62
1.61
1.6
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.5
Vin = 3V
1.84
1.83
1.82
1.81
1.8
Vin = 6V
Vin = 12V
Vin = 17V
1.79
1.78
1.77
1.76
1.75
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
-40 -20
0
20
40
60
80
100 120 140 160
-40 -20
0
20
40
60
80
100 120 140 160
Temperature (C)
Temperature (C)
Figure 7-14. Low-Side ILIM vs Temperature
Figure 7-13. High-Side ILIM vs Temperature
1.03
1.02
1.01
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
Vin = 3V
Vin = 6V
Vin = 12V
Vin = 17V
-40 -20
0
20
40
60
80
100 120 140 160
Temperature (C)
Figure 7-15. Low-Side INEG vs Temperature
Figure 7-16. VIN UVLO Thresholds vs Temperature
Figure 7-17. Precision Enable Threshold vs Temperature
Figure 7-18. Precision Enable Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The TPS629210-Q1 synchronous switched mode power converter is based on DCS-Control (Direct Control with
Seamless Transition into power save mode), an advanced regulation topology that combines the advantages
of hysteretic, voltage mode, and current mode control. This control loop takes information about output voltage
changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for
steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate
DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves
fast and stable operation with small external components and low-ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
VI
Ref
1.0V
–
+
HS Limit
EN
VO
Internal/External
Divider
Device Control
& Logic
Power Control
FB/VSET
SW
Power Save Mode
Forced PWM
100% Mode
Resistor-to-
Digital
Gate
Driver
Smart-Enable
Ref-System
VFB
UVLO
Start-up Handling
Smart-CONFIG
PG-Control
Thermal Shutdown
Resistor-to-
Digital
MODE/
S-CONF
LS Limit
MODE Detection
VO
Direct
Control
VI
VOS
TON timer
VFB
–
VO
+
Device
Control
VREF
DCS-Control
GND
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8.3 Feature Description
8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
The MODE/S-CONF pin is an input with two functions. It can be used to customize the device behavior in two
ways:
1. Select the device mode (forced PWM or auto PFM/PWM operation) traditionally with a HIGH or LOW level.
2. Select the device configuration (switching frequency, internal and external feedback, output discharge, and
PFM/PWM mode) by connecting a single resistor to this pin.
The device interprets this pin during its start-up sequence after the internal OTP readout and before it starts
switching in soft start. If the device reads a HIGH or LOW level, dynamic mode change is active and PFM/PWM
mode can be changed during operation. If the device reads a resistor value, there is no further interpretation
during operation and the device mode or other configurations cannot be changed afterward.
EN & UVLO
Precise
Enable
detection
PG -> High
Switching
Operation
OTP
Readout
S-CONF
Readout
VSET
Readout
Softstart
Resistor-to-Digitial
readout &
interpretation
No interpretation of
MODE/S-CONF or VSET
MODE-Pin toggling detection
VOUT
Figure 8-1. Interpretation of S-CONF and VSET Flow
Table 8-1. Smart-CONFIG Setting Table
DYNAMIC
MODE
CHANGE
M ODE/S-CONF LEVEL OR
RESISTOR VALUE [Ω] (1)
FB/VSET
PIN
OUTPUT
DISCHARGE
MODE (AUTO OR FORCED
PWM)
#
FSW (MHz)
Setting Options by Level
1
2
GND
HIGH (> 1.8 V)
Setting Options by Resistor
7.50 k
external FB
external FB
up to 2.5(2)
2.5
yes
yes
Auto PFM/PWM with AEE
Forced PWM
Active
3
4
external FB
external FB
external FB
external FB
external FB
external FB
VSET
up to 2.5(2)
no
no
Auto PFM/PWM with AEE
Forced PWM
9.31 k
2.5
5
11.50 k
1
yes
yes
no
Auto PFM/PWM
Forced PWM
6
14.30 k
1
7
17.80 k
1
Auto PFM/PWM
Forced PWM
8
22.10 k
1
no
9
27.40 k
up to 2.5(2)
yes
yes
no
Auto PFM/PWM with AEE
Forced PWM
not active
10
11
12
13
14
15
16
34.00 k
VSET
2.5
42.20 k
VSET
up to 2.5(2)
Auto PFM/PWM with AEE
Forced PWM
52.30 k
VSET
2.5
1
no
64.90 k
VSET
yes
yes
no
Auto PFM/PWM
Forced PWM
80.60 k
VSET
1
100.00 k
VSET
1
Auto PFM/PWM
Forced PWM
124.00 k
VSET
1
no
(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C
(2) FSW varies based on VIN and VOUT. See Section 8.4.3 for more details.
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8.3.2 Adjustable VO Operation (External Voltage Divider)
If the device is configured to operate in classical adjustable VO operation, the FB/VSET pin is used as
the feedback pin and needs to sense VO through an external divider network. Figure 8-2 shows the typical
schematic for this configuration.
VIN
3V œ 17V
VOUT
0.6V œ 5.5V
2.2 µH
VIN
EN
SW
22 ꢀF
4.7 ꢀF
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
Figure 8-2. Adjustable VO Operation Schematic
8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/
S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the
output voltage cannot be changed afterward without toggling the EN pin.
Figure 8-3 shows the typical schematic for this configuration, where VO is directly sensed at the VOS pin of the
device. VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by
an external resistor connected between VSET and GND (see Table 8-2).
VIN
3V œ 17V
VOUT
0.4V œ 5.5V
2.2 µH
VIN
EN
SW
22 ꢀF
4.7 ꢀF
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
Figure 8-3. Selectable VO Operation Schematic
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Table 8-2. VSET Selection Table
VSET #
RESISTOR VALUE [Ω](1)
TARGET VO [V]
1
2
GND
4.87 k
1.2
0.4
0.6
0.8
0.85
1.0
1.1
1.25
1.3
1.35
1.8
1.9
2.5
3.8
5.0
5.1
5.5
3.3
3
6.04 k
4
7.50 k
5
9.31 k
6
11.50 k
7
14.30 k
8
17.80 k
9
22.10 k
10
11
12
13
14
15
16
17
18
27.40 k
34.00 k
42.20 k
52.30 k
64.90 k
80.60 k
100.00 k
124.00 k
249.00 k or larger/open
(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal to ±200 ppm/°C
8.3.4 Smart Enable with Precise Threshold
The voltage applied at the EN pin of the TPS629210-Q1 is compared to a fixed threshold rising voltage. This
allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to
achieve a power-up delay.
The precise enable input allows the use of a user-programmable undervoltage lockout by adding a resistor
divider to the input of the EN pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS629210-Q1 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an uncontrolled
start-up of the device in case the EN pin cannot be driven to a low level safely. With EN low, the device is in
shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit disconnects the
pulldown resistor on the EN pin once the internal control logic and the reference have been powered up. With
EN set to a low level, the device enters shutdown mode and the pulldown resistor is activated again.
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8.3.5 Power Good (PG)
The TPS629210-Q1 has a built-in power-good (PG) feature to indicate whether the output voltage has reached
its target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG
pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage
level. PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN
must remain present for the PG pin to stay low.
If the power-good output is not used, it is recommended to tie to GND or leave open.
Table 8-3. Power-Good Indicator Functional Table
LOGIC SIGNALS
PG STATUS
VI
EN PIN
THERMAL SHUTDOWN
VO
VO on target
High Impedance
LOW
NO
HIGH
VO < target
VVIN > UVLO
YES
x
x
x
x
LOW
LOW
x
x
x
LOW
1.8 V < VVIN < UVLO
VI < 1.8 V
x
x
LOW
Undefined
8.3.6 Output Discharge Function
The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage
when the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The
output discharge feature is only active once the TPS629210-Q1 has been enabled at least once since the supply
voltage was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is
enabled as soon as the device is disabled (EN pin = low), in thermal shutdown, or in undervoltage lockout. The
minimum supply voltage required for the discharge function to remain active typically is 2 V.
8.3.7 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both
the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
8.3.8 Current Limit and Short Circuit Protection
The TPS629210-Q1 is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIM_HS, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below
the low-side current limit threshold ILIM_LS
.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given in Equation 1.
V
L
Ipeak(typ) = ILIMH
+
´tPD
(1)
where:
•
•
•
•
ILIMH is the static current limit as specified in the electrical characteristics.
L is the effective inductance at the peak current.
VL is the voltage across the inductor (VIN – VOUT).
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
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V IN - VO U T
I
peak ( typ ) = IL IM H
+
´ 50 ns
L
(2)
The TPS629210-Q1 also includes a low-side negative current limit (ILIM:SINK) to protect against excessive
negative currents that can occur in forced PMW mode under heavy to light load transient conditions. If the
negative current in low-side switch exceeds the ILIM:SINK threshold, the low-side switch is disabled. Both the
low-side and high-side switches remain off until an internal timer re-enables the high-side switch based on the
selected PWM switching frequency.
CAUTION
It is recommended that the inductor be sized such that the inductor ripple current (ΔIL see Equation
9) does not exceed 1.6 A to avoid the potential for continuous operation of the negative current limit
with no output load (IO = 0 A).
8.3.9 Thermal Shutdown
The junction temperature of the device, TJ, is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A
shutdown or restart is only triggered during a switching cycle. See Section 8.4.2.
8.4 Device Functional Modes
8.4.1 Forced Pulse Width Modulation (PWM) Operation
The TPS629210-Q1 has two operating modes: forced PWM mode discussed in this section and auto PFM/PWM
mode as discussed in Section 8.4.2.
With the MODE/S-CONF pin set to forced PWM mode, the device operates with pulse width modulation in
continuous conduction mode (CCM) with a nominal switching frequency of either 1.0 MHz or 2.5 MHz. The
frequency variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time in forced
PWM mode is given by Equation 3.
VOUT
VIN
1
TON =
ì
fsw
(3)
For very small output voltages, an absolute minimum on time of about 40 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high.
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8.4.2 Power Save Mode Operation (Auto PFM/PWM)
When the MODE/S-CONF pin is configured for auto PFM/PWM mode, power save mode is allowed. The device
operates in PWM mode as long the output current is higher than half the ripple current of the inductor. To
maintain high efficiency at light loads, the device enters power save mode at the boundary to discontinuous
conduction mode (DCM). This happens if the output current becomes smaller than half the ripple current of the
inductor. Power save mode is entered seamlessly to make sure there is high efficiency in light-load operation.
The device remains in power save mode as long as the inductor current is discontinuous.
In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of power save mode is seamless in both directions.
The TPS629210-Q1 adjusts the on time (TON) in power save mode, depending on the input voltage and the
output voltage to maintain highest efficiency. The on time in steady-state operation can be estimated as:
With the MODE/S-CONF pin set to 1.0-MHz operation:
VOUT
610 (µO) =
8+0
(4)
(5)
With the MODE/S-CONF pin set to 2.5-MHz operation:
VIN
TON =100´
[ns]
VIN -VOUT
Using TON, the typical peak inductor current in power save mode is approximated by:
(V IN - VO U T )´ TO N
=
IL P SM ( peak )
L
(6)
(7)
The output voltage ripple in power save mode is given by Equation 7:
2 æ
ç
ö
÷
ø
L´VIN
1
1
DV =
+
200´C VIN -VOUT VOUT
è
Note
When VIN decreases to typically 15% above VOUT, the device will not enter power save mode
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 AEE (Automatic Efficiency Enhancement)
When the MODE/S-CONF pin is configured for Auto PFM/PWM with AEE mode, the TPS629210-Q1 provides
the highest efficiency over the entire input voltage and output voltage range by automatically adjusting the
switching frequency of the converter (see Equation 8). To keep the efficiency high over the entire duty
cycle range, the switching frequency is adjusted while maintaining the ripple current amplitudes. This feature
compensates for the very small duty cycles of high VIN to low VOUT conversions, which can limit the control
range in other topologies.
VIN -VOUT
VIN
F (MHz) =10ìVOUT
ì
sw
2
(8)
Traditionally, the efficiency of a switched mode converter decreases if VOUT decreases, VIN increases, or both.
By decreasing the switching losses at lower VOUT values or higher VIN values, the AEE feature provides an
efficiency enhancement across various duty cycles, especially for the lower VOUT values, where fixed frequency
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converters suffer from a significant efficiency drop. Furthermore, when used with the recommended 2.2-μH
inductor, the ripple current amplitudes remains low enough to deliver the full output current without reaching
current limit across the entire range of input and output voltages (see Figure 8-4).
By using the same TON configuration (see Equation 5) across the entire load range in AEE mode, the inductor
ripple current in AEE mode becomes effectively independent of the output voltage and can be approximated by
Equation 9:
(9)
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
2
4
6
8
10
Input Voltage (V)
12
14
16
18
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM with AEE
Figure 8-4. Typical Inductor Ripple Current Versus Input Voltage in AEE mode
The TPS629210-Q1 operates in AEE mode as long as the output current is higher than half the ripple current
of the inductor. To maintain high efficiency at light loads, the device enters power save mode at the boundary
to discontinuous mode (DCM), which happens when the output current becomes smaller than half the inductor
ripple current.
8.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operated in PWM mode is given in Equation 10.
VOUT
& =
8+0
(10)
The duty cycle increases as the input voltage comes close to the output voltage and the off time of the high-side
switch gets smaller. When the minimum off time of typically 80 ns is reached, the TPS629210-Q1 scales down
its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch
on continuously as long as the output voltage is below the internal set point. This allows the conversion of
small input to output voltage differences. For example, getting the longest operation time of battery-powered
applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
VIN(min) =VOUT + IOUT(RDS(on) + R
L
)
(11)
where:
•
•
IOUT is the output current.
RDS(on) is the on-state resistance of the high-side FET.
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•
RL is the DC resistance of the inductor used.
8.4.5 Starting into a Pre-Biased Load
The TPS629210-Q1 is capable of starting into a pre-biased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPS629210-Q1 does not start switching unless the voltage at the
feedback pin drops to the target. Performance is the same for devices configured for VSET operation (internal
feedback), however the switching will be delayed until the soft-start ramp reaches the internal feedback voltage.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
L1
VIN
VOUT
0.6V œ 5.5V
2.2 µH
3V œ 17V
VIN
EN
SW
VOS
C2
22 ꢀF
C1
4.7 ꢀF
FB/
VSET
R1
MODE/
S-CONF
PG
R2
R3
GND
Figure 9-1. Typical Application Setup
Table 9-1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
IC
17-V, 1-A Step-Down Converter
2.2-µH inductor
TPS629210-Q1; Texas Instruments
XGL3530-222; Coilcraft
L1
C1
C2
4.7 µF, 25 V, Ceramic, 1206
22 µF, 6.3 V, Ceramic, 0805
CGA5L1X7R1E475K160AC, TDK
GCM21BD70J226ME36L, MuRata
R1
R2
R3
Depending on VOUT; see Section 9.2.2.2.
Depending on VOUT; see Section 9.2.2.2.
Depending on device setting, see Section 8.3.1.
Standard 1% metal film
Standard 1% metal film
Standard 1% metal film
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9.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629210-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
The output voltage of the TPS629210-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to
5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value
of the output voltage is set by the selection of the resistor divider from Table 9-1. It is recommended to choose
resistor values that allow a current of at least 2 μA, meaning the value of R2 should not exceed 300 kΩ. Lower
resistor values are recommended for highest accuracy and most robust design.
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(12)
where
VFB is 0.6 V.
•
Table 9-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
R1
R2
EXACT OUTPUT VOLTAGE
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5 V
51 kΩ
150 kΩ
130 kΩ
100 kΩ
237 kΩ
165 kΩ
137 kΩ
84.5 kΩ
0.804 V
1.200 V
1.500 V
1.803 V
2.502 V
3.311 V
4.995 V
130 kΩ
150 kΩ
475 kΩ
523 kΩ
619 kΩ
619 kΩ
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the control
loop of the device. The TPS629210-Q1 is optimized to work within a range of external components.
9.2.2.3.1 Output Filter and Loop Stability
The TPS629210-Q1 is internally compensated to be stable with and range of L-C filter combinations. The LC
output filters inductance and capacitance have to be considered together, creating a double pole, responsible for
the corner frequency of the converter using Equation 13.
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1
fLC
=
2p L × C
(13)
Table 9-3 can be used to simplify the output filter component selection. The values in Table 9-3 are nominal
values, and the effective capacitance was considered to be +20% and - 50%. Different values can work, but
care has to be taken on the loop stability which is affected. More information on the sizing of the LC filter of a
DCS-Control regulator can be found in the Optimizing the TPS62130/40/50/60 Output Filter Application Note.
Table 9-3. Recommended LC Output Filter Combinations
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
1 µH (3) (4)
1.5 µH
√
√
√
√
√
√
√
√
(2)
(2)
√
√
√
√
√
(1)
(2)
2.2 µH
√
√
3.3 µH
√
√
√
√
(2)
4.7 µH
√
(1) This LC combination is the standard value and recommended for most applications.
(2) Output capacitance needs to have a ESR of ≥ 10 mΩ for stable operation. See Section 9.3.1.
(3) Not recommended for 1-MHz operation
(4) At full load, ILpeak may exceed ILIM_HS at higher input or output voltages
Although the TPS629210-Q1 is stable without the pole and zero being in a particular location, an external
feedforward capacitor can also be added to adjust their location based on the specific needs of the application.
This can provide better performance in power save mode, improved transient response, or both.
A more detailed discussion on the optimization for stability versus transient response can be found in
the Optimizing Transient Response of Internally Compensated DC-DC Converters Application Note and
Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family Application Note.
9.2.2.3.2 Inductor Selection
The TPS629210-Q1 is designed for a nominal 2.2-µH inductor. Larger values can be used to achieve a lower
inductor current ripple but they can have a negative impact on efficiency and transient response. Smaller values
than 2.2 µH cause larger inductor current ripple, which cause larger negative inductor currents in forced PWM
mode and higher peak currents at full load. Therefore, they are not recommended at larger voltages across the
inductor as it is the case for high input voltages and low output voltages. With low output current in forced PWM
mode, this causes a larger negative inductor current peak that can exceed the negative current limit. At low or
no output current and small inductor values, the output voltage can therefore not be regulated any more. More
detailed information on further LC combinations can be found in the Optimizing the TPS62130/40/50/60 Output
Filter Application Note.
The inductor selection is affected by several effects like the following:
•
•
•
•
Inductor ripple current
Output ripple voltage
PWM-to-PFM transition point
Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR).
Equation 14 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(14)
(15)
VIN(max)
DIL(max)
=
´100ns
L
(min)
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where:
•
•
•
IL(max) is the maximum inductor current.
ΔIL is the peak-to-peak inductor ripple current.
L(min) is the minimum effective inductor value.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to add a margin of about 20%. A larger inductor value is
also useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS629210-Q1 and are recommended for use:
Table 9-4. List of Inductors
DIMENSIONS
TYPE
INDUCTANCE [µH]
DCR [mΩ] CURRENT [A](1)
MANUFACTURER
[L×B×H] mm
2.5 × 2.0 × 1.2
3.5 × 3.2 × 3
4 × 4 × 2.1
DFE252012PD-2R2M(2)
XGL3530-222ME
XGL4020-222ME
XGL3530-332ME
XGL4020-472ME
2.2 µH, ±20%
2.2 μH, ±20%
2.2 µH, ±20%
3.3 μH, ±20%
4.7 µH, ±20%
84
20
2.8
4.0
6.2
3.3
4.1
muRata
Coilcraft
Coilcraft
Coilcraft
Coilcraft
19.5
33
3.5 × 3.2 × 3
4 × 4 × 2.1
43
(1) ISAT at 30% drop
(2) For smaller size solutions that do not require maximum efficiency at the full output current.
The inductor value also determines the load current at which power save mode is entered:
1
Iload(PSM )
=
DIL
2
(16)
9.2.2.3.3 Capacitor Selection
9.2.2.3.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS629210-Q1 allows the
use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide
low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get
narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher
value has advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode (see
Optimizing the TPS62130/40/50/60 Output Filter Application Note for more information).
In power save mode, the output voltage ripple depends on the following:
•
•
•
•
Output capacitance
ESR
ESL
Peak inductor current
Using ceramic capacitors provides small ESR, ESL, and low ripple.
The output capacitor needs to be as close as possible to the device, and it is recommended to have the VOS
signal and feedback resistors (if used) should be connected to the positive terminal of the output capacitor.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to
be observed.
9.2.2.3.3.2 Input Capacitor
For most applications, 4.7-µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
should be placed between VIN and GND as close as possible to those pins.
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Table 9-5. List of Capacitors
TYPE
NOMINAL CAPACITANCE [µF]
VOLTAGE RATING [V]
SIZE
MANUFACTURER
CGA5L1X7R1E475K160AC
CGA5L1X7R1E106K160AC
4.7
10
25
25
1206(1)
1206(1)
TDK
TDK
(1) Smaller (0805 or 0603) options may be used and are available from various manufacturers.
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9.2.3 Application Curves
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 7V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 7V
VIN = 9V
VIN =12V
VIN = 15V
1E-5
0.0001
0.001
0.01
0.1 0.2 0.5 1
Iout (A)
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Figure 9-2. Efficiency vs Output Current
Figure 9-3. Efficiency vs Output Current
3.5
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
6
8
10
12
14
16
18
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-4. Switching Frequency vs Input Voltage
Figure 9-5. Switching Frequency vs Input Voltage
0.5
VIN = 7V
0.45
0.4
VIN = 9V
VIN = 12V
VIN = 15V
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 5.0 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Figure 9-6. Output Voltage vs Output Current
Figure 9-7. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 7V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 7V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
F/PWM
Auto PFM/PWM
Figure 9-8. Efficiency vs Output Current
Figure 9-9. Efficiency vs Output Current
1.8
1.1
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
IOUT = 0.1A
IOUT = 0.1A
1.6
1.4
1.2
1
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.8
0.6
0.4
0.2
0
6
8
10
12
14
16
18
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-11. Switching Frequency vs Input Voltage
Figure 9-10. Switching Frequency vs Input Voltage
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VIN = 7V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 7V
VIN = 9V
VIN = 12V
VIN = 15V
-0.005
-0.01
-0.015
-0.02
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 5.0 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-12. Output Voltage vs Output Current
Figure 9-13. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-14. Efficiency vs Output Current
Figure 9-15. Efficiency vs Output Current
3.5
3.25
3
3
2.8
2.6
2.4
2.2
2
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.8
1.6
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
4
6
8
10
12
14
16
18
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-16. Switching Frequency vs Input Voltage
Figure 9-17. Switching Frequency vs Input Voltage
0.55
0.085
VIN = 6V
0.5
0.45
0.4
0.35
0.3
0.08
0.075
0.07
0.065
0.06
VIN = 9V
VIN = 12V
VIN = 15V
0.055
0.05
0.25
0.2
0.045
0.04
0.15
0.1
0.035
0.03
0.025
0.02
0.015
0.01
0.05
0
-0.05
-0.1
-0.15
-0.2
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
VOUT = 3.3 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-19. Output Voltage vs Output Current
Figure 9-18. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Auto PFM/PWM
Figure 9-20. Efficiency vs Output Current
Figure 9-21. Efficiency vs Output Current
1.15
1.8
IOUT = 0.1A
IOUT = 0.1A
1.6
1.4
1.2
1
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.125
1.1
1.075
1.05
1.025
1
0.8
0.6
0.4
0.2
0
0.975
0.95
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-23. Switching Frequency vs Input Voltage
Figure 9-22. Switching Frequency vs Input Voltage
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.06
0.055
0.05
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.045
0.04
0.035
0.03
0.15
0.1
0.05
0
-0.05
-0.1
0.025
VIN = 3V
VIN = 6V
VIN = 9V
0.02
0.015
VIN = 12V
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 3.3 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-24. Output Voltage vs Output Current
Figure 9-25. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-26. Efficiency vs Output Current
Figure 9-27. Efficiency vs Output Current
4
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3.5
3
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
0
2
4
6
8
10
12
14
16
18
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-28. Switching Frequency vs Input Voltage
Figure 9-29. Switching Frequency vs Input Voltage
0.16
0.75
0.65
0.55
0.45
0.35
0.25
0.15
0.05
-0.05
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.14
0.12
0.1
0.08
0.06
0.04
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 1.8 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Figure 9-30. Output Voltage vs Output Current
Figure 9-31. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Auto PFM/PWM
Figure 9-32. Efficiency vs Output Current
Figure 9-33. Efficiency vs Output Current
1.225
1.2
1.4
IOUT = 0.1A
1.3
1.2
1.1
1
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.175
1.15
1.125
1.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.075
1.05
1.025
1
0.975
2
4
6
8
10
12
14
16
18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-35. Switching Frequency vs Input Voltage
Figure 9-34. Switching Frequency vs Input Voltage
0.5
0.025
0.02
0.015
0.01
0.005
0
VIN = 3V
0.45
0.4
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.35
0.3
0.25
0.2
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-0.035
-0.04
-0.045
0.15
0.1
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.05
0
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 1.8 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-36. Output Voltage vs Output Current
Figure 9-37. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-38. Efficiency vs Output Current
Figure 9-39. Efficiency vs Output Current
4
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
3.5
3
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
0
2
4
6
8
10
12
14
16
18
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-40. Switching Frequency vs Input Voltage
Figure 9-41. Switching Frequency vs Input Voltage
0.16
1.2
VIN = 3V
0.14
0.12
0.1
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1
0.8
0.6
0.4
0.2
0
0.08
0.06
0.04
0.02
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
-0.02
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
VOUT = 1.2 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-42. Output Voltage vs Output Current
Figure 9-43. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Auto PFM/PWM
Figure 9-44. Efficiency vs Output Current
Figure 9-45. Efficiency vs Output Current
1.4
1.3
1.25
1.2
IOUT = 0.1A
1.3
1.2
1.1
1
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.15
1.1
1.05
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.95
2
4
6
8
10
12
14
16
18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-47. Switching Frequency vs Input Voltage
0.06
Figure 9-46. Switching Frequency vs Input Voltage
0.3
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.25
0.2
0.04
0.02
0
0.15
0.1
-0.02
-0.04
-0.06
-0.08
-0.1
0.05
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-48. Output Voltage vs Output Current
VOUT = 1.2 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Figure 9-49. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-50. Efficiency vs Output Current
Figure 9-51. Efficiency vs Output Current
2.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
IOUT = 0.1A
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
2
4
6
8
10
12
14
16
18
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-52. Switching Frequency vs Input Voltage
Figure 9-53. Switching Frequency vs Input Voltage
3
2.75
2.5
2.25
2
1.75
1.5
0.15
0.125
0.1
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.075
0.05
0.025
0
1.25
1
-0.025
0.75
0.5
0.25
0
-0.25
-0.5
-0.05
VIN = 3V
-0.075
-0.1
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
-0.125
-0.15
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
FPWM
VOUT = 0.6 V
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-55. Output Voltage vs Output Current
Figure 9-54. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Auto PFM/PWM
Figure 9-56. Efficiency vs Output Current
Figure 9-57. Efficiency vs Output Current
1.45
1.5
1.45
1.4
IOUT = 0.1A
IOUT = 0.1A
1.4
1.35
1.3
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.35
1.3
1.25
1.2
1.25
1.2
1.15
1.1
1.15
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
2
4
6
8
10
12
14
16
18
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
Input Voltage (V)
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Auto PFM/PWM
Figure 9-58. Switching Frequency vs Input Voltage
Figure 9-59. Switching Frequency vs Input Voltage
0.4
0.5
VIN = 3V
VIN = 3V
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0.35
0.3
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 15V
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
Iout (A)
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-60. Output Voltage vs Output Current
VOUT = 0.6 V
L = 3.3 μH
Fsw = 1.0 MHz
FPWM
Figure 9-61. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
VIN = 12 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
VIN = 12 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
VOUT = 3.3 V
Auto PFM/PWM
VOUT = 3.3 V
FPWM
Figure 9-62. Start-Up Timing
Figure 9-63. Start-Up Timing
VIN = 12 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
VIN = 12 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
FPWM
Auto PFM/PWM
Figure 9-65. Shutdown Timing with Output Discharge Enabled
Figure 9-64. Start-Up into Prebiased Output
VIN = 12 V
L = 3.3 μH
IO = 10 mA
Fsw = 1.0 MHz
VIN = 12 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
FPWM
VOUT = 3.3 V
Auto PFM/PWM
VOUT = 3.3 V
Figure 9-67. Shutdown Timing with Output Discharge Enabled
Figure 9-66. Shutdown Timing with Output Discharge Disabled
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9.2.3 Application Curves (continued)
VIN = 12 V
L = 3.3 μH
IO = 10 mA
Fsw = 1.0 MHz
FPWM
VIN = 12 V
L = 3.3 μH
IO = 10 mA
Fsw = 1.0 MHz
VOUT = 3.3 V
VOUT = 3.3 V
Auto PFM/PWM
Figure 9-69. Shutdown Timing with Output Discharge Enabled
Figure 9-68. Shutdown Timing with Output Discharge Disabled
VIN = 12 V
L = 3.3 μH
IO = 10 mA
Fsw = 1.0 MHz
FPWM
VIN = 12 V
L = 2.2 μH
Fsw = 2.5 MHz
VOUT = 3.3 V
VOUT = 3.3 V
IO = 0 A to 0.5 A
Auto PFM/PWM
Figure 9-70. Shutdown Timing with Output Discharge Disabled
Figure 9-71. Load Transient Response
VIN = 12 V
L = 2.2 μH
Fsw = 2.5 MHz
VIN = 12 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 3.3 V
IO = 0.5 A to 1 A
Auto PFM/PWM
Figure 9-72. Load Transient Response
Figure 9-73. Output Voltage Ripple
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9.2.3 Application Curves (continued)
VIN = 12 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
FPWM
VIN = 12 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 3.3 V
VOUT = 3.3 V
Figure 9-74. Output Voltage Ripple
Figure 9-75. Output Voltage Ripple
VIN = 12 V
VOUT = 3.3 V
L = 3.3 μH
IO = 1 A
Fsw = 1.0 MHz
Auto PFM/PWM
VIN = 12 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
FPWM
Figure 9-77. Output Voltage Ripple
Figure 9-76. Output Voltage Ripple
VIN = 12 V
L = 3.3 μH
IO = 1 A
Fsw = 1.0 MHz
FPWM
VIN = 12 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 3.3 V
Figure 9-78. Output Voltage Ripple
Figure 9-79. Input Voltage Ripple
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9.2.3 Application Curves (continued)
40
35
30
25
20
15
10
5
240
210
180
150
120
90
60
30
0
0
-5
-30
-60
-90
-120
-150
-180
-10
-15
-20
-25
-30
Gain
Phase
1000 2000
5000 10000
100000
Frequency (Hz)
1000000
VIN = 12 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
FPWM
VIN = 12 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
FPWM
VOUT = 0.6 V
VOUT = 3.3 V
Figure 9-81. Bode Plot
Figure 9-80. Input Voltage Ripple
40
35
30
25
20
15
10
5
240
210
180
150
120
90
60
30
0
0
-5
-30
-60
-90
-120
-150
-180
-10
-15
-20
Gain
Phase
-25
-30
1000 2000
5000 10000
100000
Frequency (Hz)
1000000
VIN = 12 V
L = 3.3 μH
IO = 1 A
Fsw = 1.0 MHz
FPWM
VOUT = 0.6 V
Figure 9-82. Bode Plot
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9.3 System Examples
9.3.1 Powering Multiple Loads
In applications where the TPS629210-Q1 is used to power multiple load circuits, it is possible that the total
capacitance on the output is very large. In order to properly regulate the output voltage, there needs to be an
appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output
voltage ripple sufficiently high on the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can
get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are
several load circuits with their associated input capacitor on a PCB, these loads are typically distributed across
the board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for
proper regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × CIN in Figure
9-83 was 32 × 47 μF of ceramic X7R capacitors.
Load1
Rtrace
CIN
VIN
3V – 17V
VOUT
0.4V – 5.5V
L1
TPS6292xx
VIN
SW
Load2
Rtrace
C2
22 F
EN
VOS
CIN
C1
4.7 F
FB/
VSET
R2
MODE/
S-CONF
PG
R1
GND
Loadn
Rtrace
CIN
Figure 9-83. Multiple Loads Example
9.3.2 Inverting Buck-Boost (IBB)
The need to generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 17-V
input voltage range of the TPS629210-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the
output voltage is inverted or negative with respect to ground.
The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the
components are connected the same as with a traditional buck converter, the output voltage terminals are
reversed. See Figure 9-84 and Figure 9-85.
The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can
be applied to the TPS629210-Q1 in a typical buck configuration. This is because the ground pin of the IC is
connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not
VIN to ground. Thus, the input voltage range of the TPS629210-Q1 in an IBB configuration becomes 3 V to 17 V
+ VOUT, where VOUT is a negative value.
The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the
output voltage for a TPS629210-Q1 in an IBB configuration may be set between –0.4 V and –5.5 V.
The maximum output current for the TPS629210-Q1 in an IBB topology is normally lower than a traditional buck
configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input
or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor
value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current
capability.
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When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage
rail, and in turn, the electrical characteristics of the TPS629210-Q1 device are referenced to this rail. During
power up, as there is no charge in the output capacitor, the IC GND pin (and VOUT) are effectively 0 V, thus
parameters such as the VIN UVLO and EN thresholds are the same as in a typical buck configuration. However,
after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally
continues to operate below what could appear to be the normal UVLO/EN falling thresholds relative to the
system ground. Thus, special care needs to be taken if the user is utilizing the dynamic mode change feature on
the MODE pin of the TPS629210-Q1 or driving the EN pin from an upstream microcontroller as the high and low
thresholds are relative to the negative rail and not the system ground.
More information on using a DCS regulator in an IBB configuration can be found in the Description
Compensating the Current Mode Boost Control Loop Application Note and Using the TPS6215x in an Inverting
Buck-Boost Topology Application Note.
TPS6292xx
2.2 µH
VIN
VIN
SW
22
F
10
F
EN
VOS
FB/
VSET
MODE/
S-CONF
PG
VOUT
-0.6V to -5.5V
GND
Figure 9-84. IBB Example with Adjustable Feedback
TPS6292xx
2.2 µH
VIN
VIN
SW
22
F
10
F
EN
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
VOUT
-0.4V to -5.5V
Figure 9-85. IBB Example with Internal Feedback
10 Power Supply Recommendations
The power supply to the TPS629210-Q1 needs to have a current rating according to the supply voltage, output
voltage, and output current of the TPS629210-Q1.
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11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more so at high switching
frequencies. Therefore, the PCB layout of the TPS629210-Q1 demands careful attention to make sure proper
operation and to get the performance specified. A poor layout can lead to issues like the following:
•
•
•
•
Poor regulation (both line and load)
Stability and accuracy weaknesses
Increased EMI radiation
Noise sensitivity
See Figure 11-1 for the recommended layout of the TPS629210-Q1, which is designed for common external
ground connections. The input capacitor should be placed as close as possible between the VIN and GND pin of
the TPS629210-Q1.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes)
for wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible
to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops that
conduct an alternating current should outline an area as small as possible, as this area is proportional to the
energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals
(for example, SW). As they carry information about the output voltage, they should be connected as close as
possible to the actual output voltage (at the output capacitor). The FB resistors, R1 and R2, should be kept
close to the IC and connect directly to those pins and the system ground plane. The same applies for the
S-CONFIG/MODE and VSET programming resistors.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread
the heat through the PCB.
In case any of the digital inputs (EN or S-CONF/MODE pins) need to be tied to the input supply voltage at VIN,
the connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in the TPS629210EVM-Q1 User's Guide.
11.2 Layout Example
GND
VOUT
GND
VIN
SW
VOS
PG
EN
FB
S-CONFIG
VIN
Figure 11-1. TPS629210-Q1 Layout
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11.2.1 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
The following are basic approaches for enhancing thermal performance:
•
•
Improving the power dissipation capability of the PCB design, for example, increasing copper thickness,
thermal vias, number of layers
Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs Application Note and Semiconductor and IC Package Thermal Metrics
Application Note.
The TPS629210-Q1 is designed for a maximum operating junction temperature (TJ) of 150°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given,
the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get an improved thermal behavior, it is recommended to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629210-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Note
•
•
•
•
•
•
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Note
Texas Instruments, TPS629210EVM-Q1 User's Guide
Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
Texas Instruments, Using the TPS6215x in an Inverting Buck-Boost Topology Application Note
Texas Instruments, Optimizing the TPS62130/40/50/60 Output Filter Application Note
Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters Application
Note
•
Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
DCS-Control™ is a trademark of Texas Instruments.
Copyright © 2021 Texas Instruments Incorporated
42
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Product Folder Links: TPS629210-Q1
TPS629210-Q1
SLVSFS6B – MAY 2021 – REVISED DECEMBER 2021
www.ti.com
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPS629210-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS629210QDRLRQ1
ACTIVE
SOT-5X3
DRL
8
4000 RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 150
T210
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS629210-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2021
Catalog : TPS629210
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS629210QDRLRQ1 SOT-5X3
DRL
8
4000
180.0
8.4
2.75
1.9
0.8
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-5X3 DRL
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS629210QDRLRQ1
8
4000
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/D 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/D 11/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/D 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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