首页 |元器件品牌

TPS63710DRRR [TI]

采用 3x3 WSON 封装的低噪声 1A 同步反相降压转换器 | DRR | 12 | -40 to 125;
TPS63710DRRR
型号： TPS63710DRRR
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

采用 3x3 WSON 封装的低噪声 1A 同步反相降压转换器 | DRR | 12 | -40 to 125

开关 光电二极管 转换器
文件： 总35页 (文件大小：2869K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Support &  
Community  
Product  
Folder  
Order  
Now  
Tools &  
Software  
Technical  
Documents  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
TPS63710 低噪声同步反相降压转换器  
1 特性  
3 说明  
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
输入电压范围为 3.1V 至 14V  
TPS63710 作为反相降压直流/直流转换器，可产生低  
输出电流为 1A  
至 -5.5V 的负输出电压。它提供高达 1A 的输出电流，  
具体值取决于输入电压与输出电压比。其经过滤波的参  
考系统提供高性能电信系统中所需的低 1/f 噪声。  
效率高达 91%  
输出电压精度为 ±1.5%  
同步整流  
TPS63710 采用固定频率的 PWM 控制拓扑。它具有  
内部电流限制和热关断功能。TPS63710 具有 3.1V 至  
14V 的输入电压范围，因此可用于需要从较高的正输  
入电压（绝对值）产生负输出电压的各种 应用 。  
低 1/f 噪声参考系统  
噪音：22µVRMS（10Hz 至 100kHz）  
输出电压：-1V 至 -5.5V  
|VOUT| < 0.7 x VIN  
同步整流提供高效率，特别是对于小输出电压（如  
-1.8V，此类电压通常用作高性能 DAC 和 ADC 的负电  
源电压）。该器件具有 1.5MHz 的固定开关频率，因  
此允许使用小型外部组件，并可实现较小的总体解决方  
案尺寸。  
1.5MHz 固定频率 PWM 模式  
热关断  
5μA 关断电流  
3mm × 3mm WSON 封装  
使用 TPS63710 并借助 WEBENCH® 电源设计器  
创建定制设计方案  
TPS63710 采用 3mm × 3mm WSON 封装，能够为高  
环境温度下运行的 应用 提供良好的散热性能。  
2 应用  
器件信息(1)  
•
•
•
•
•
通用负电压电源  
电信系统中的 ADC 和 DAC 电源  
GaN 晶体管偏压  
器件型号  
封装  
封装尺寸（标称值）  
TPS63710  
WSON  
3mm x 3mm  
光学模块激光二极管偏压  
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品  
附录。  
需要负电源电压 的  
噪声敏感型和空间受限型应用  
典型应用  
VOUT = -1.8V 时效率与输出电流间的关系  
TPS63710  
CCP  
CP  
100  
90  
80  
70  
60  
50  
VIN  
VIN  
CIN  
L
VOUT  
COUT  
SW  
EN  
VOUT  
VREF  
CAP  
R1  
CCAP  
FB  
R 2  
+V  
40  
VIN = 4.5 V  
VAUX  
30  
20  
10  
0
VIN = 5 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
CAUX  
R3  
PG  
GND  
Copyright © 2017, Texas Instruments Incorporated  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Output Current (A)  
1
D004  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SLVSD44  
 
 
 
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
目录  
7.4 Device Functional Modes........................................ 10  
Application and Implementation ........................ 12  
8.1 Application Information............................................ 12  
8.2 Typical Application ................................................. 12  
8.3 System Examples .................................................. 22  
Power Supply Recommendations...................... 24  
1
2
3
4
5
6
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ..................................... 4  
6.2 ESD Ratings ............................................................ 4  
6.3 Recommended Operating Conditions....................... 5  
6.4 Thermal Information ................................................. 5  
6.5 Electrical Characteristics........................................... 6  
6.6 Typical Characteristics.............................................. 7  
Detailed Description .............................................. 8  
7.1 Overview ................................................................... 8  
7.2 Functional Block Diagram ......................................... 8  
7.3 Feature Description................................................... 9  
8
9
10 Layout................................................................... 25  
10.1 Layout Guidelines ................................................. 25  
10.2 Layout Example .................................................... 25  
11 器件和文档支持 ..................................................... 26  
11.1 器件支持 ............................................................... 26  
11.2 社区资源................................................................ 26  
11.3 商标....................................................................... 26  
11.4 静电放电警告......................................................... 26  
11.5 术语表 ................................................................... 26  
12 机械、封装和可订购信息....................................... 26  
7
4 修订历史记录  
Changes from Original (September 2017) to Revision A  
Page  
•
•
•
•
新增特性：噪音：22µVRMS（10Hz 至 100kHz）.................................................................................................................... 1  
Changed 图 31 to 图 34 ....................................................................................................................................................... 18  
Added 图 35 and 图 36 ........................................................................................................................................................ 19  
Changed 图 41 .................................................................................................................................................................... 20  
2
Copyright © 2017–2018, Texas Instruments Incorporated  
 
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
5 Pin Configuration and Functions  
DRR Package  
12-Pin WSON  
Top View  
12  
10  
11  
9
8
7
Exposed Thermal Pad  
1
2
3
6
5
4
Table 1. Pin Functions  
Pin  
I/O  
Description  
Name  
No.  
VIN  
12  
I
Power supply Input. Connect the input capacitor from this pin to GND and place it as close as  
possible to the device pins.  
VAUX  
1
O
Connect the output capacitor of the internal voltage regulator from this pin to GND. VAUX can  
be loaded externally with up to 100uA. Do not use this pin for any pulsed load to not couple  
noise into the internal supply.  
GND  
CP  
10, 9  
Ground Connection. Voltages and signals are referenced to this pin.  
Connect a capacitor from this pin to SW.  
11  
8
O
O
I
SW  
Connect a capacitor from this pin to CP and the inductor from this pin to the output.  
Feedback pin for the voltage divider.  
FB  
5
VOUT  
CAP  
7
I
Output voltage sense pin.  
6
O
Reference system bypass capacitor connection. Do not tie anything other than a capacitor to  
GND to this pin. Keep any noise sources away from this pin. The capacitor connected to this  
pin forms a low-pass filter with an internal filter resistor and also defines the soft-start time.  
VREF  
EN  
4
2
O
I
Reference voltage output. Connect a voltage divider between this pin, FB and GND to set the  
output voltage. Do not connect any other circuitry to this pin.  
Enable pin. The device is enabled when the pin is connected to a logic high level e.g. VIN. The  
device is disabled when the pin is connected to a logic low level. The logic levels are  
referenced to the IC´s GND pin.  
PG  
3
-
O
-
Open drain power good output. Connect with a pull-up resistor to a positive voltage up to 5.5 V.  
If not used, leave open or connect to GND.  
Exposed  
Thermal Pad  
The thermal pad must be tied to GND. The pad must be soldered to a GND plane to achieve an  
appropriate thermal resistance and for mechanical reliability.  
Copyright © 2017–2018, Texas Instruments Incorporated  
3
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
6 Specifications  
6.1 Absolute Maximum Ratings(1)  
PIN  
MIN  
-0.3  
-0.5  
-3  
MAX  
15  
UNIT  
V
VIN, EN  
CP (DC)  
CP (AC, less than 10ns)(3)  
15  
V
17  
V
SW (DC)  
SW (AC, less than 10ns)(3)  
-16  
-20  
-0.3  
-3.6  
-6  
0.3  
1
V
Voltage(2)  
V
VAUX, PG  
FB  
5.5  
0.3  
0.3  
0.3  
5
V
V
VOUT  
V
VREF, CAP  
PG  
-5.5  
V
Sink Current  
mA  
°C  
°C  
Operating junction temperature, TJ  
Storage temperature, Tstg  
-40  
-65  
150  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to network GND pin.  
(3) While switching  
6.2 ESD Ratings  
VALUE  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
±2000  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification JESD22-  
C101(2)  
±500  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
4
Copyright © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
6.3 Recommended Operating Conditions  
MIN  
3.1  
NOM  
MAX  
14  
UNIT  
V
VIN  
Supply Voltage Range  
Supply voltage slew rate for a VIN step of less than 1V  
Supply voltage slew rate for a VIN step of greater or equal than 1V  
-1  
1
V/µs  
V/µs  
A
-0.1  
-1  
0.1  
0
IOUT  
L
Output Current  
duty cycle ≤ 70%  
Effective Inductance  
1.5  
2.2  
44  
44  
6.2  
100  
100  
µH  
µF  
COUT  
COUT  
CIN  
Effective Output Capacitance(1) for Tj = -20°C to 125°C  
Effective Output Capacitance(1) for Tj = -40°C to 125°C  
Effective Input Capacitance(1)  
15  
22  
µF  
2 x CCP  
µF  
Effective Capacitance on the CP pin required for full output current at ≤ 70% duty  
CCP  
4
4.7  
20(3)  
µF  
cycle(1) (2)  
CAUX  
CCAP  
R
Effective Capacitance from VAUX pin to GND(1)  
Effective Capacitance from CAP pin to GND(1)  
Total resistance for R1 + R2 from VREF to GND  
Operating Junction Temperature  
0.08  
0.01  
100  
-40  
0.22  
1
10  
µF  
µF  
kΩ  
°C  
500  
125  
TJ  
(1) The values given for all the capacitors are effective capacitance, which includes the dc bias effect. Especially the input capacitor CIN and  
the CCP capacitor, which are charged to the input voltage, are strongly effected. Their effective capacitance is much lower based on the  
dc voltage applied. Therefore, the nominal capacitor value needs to be larger than the minimum values given in the table. Please check  
the manufacturer´s dc bias curves for the effective capacitance vs dc voltage applied.  
(2) If a maximum output current below 1A is required, the capacitance can be reduced accordingly. See the application section for details.  
(3) The maximum value also includes dc bias at the nominal operating voltage. During start-up when the voltage is 0 V, the effective  
capacitance can be higher. Please see the application section for details.  
6.4 Thermal Information  
TPS63710  
THERMAL METRIC(1)  
DRR (WSON)  
12 PINS  
44.3  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
47.7  
18.9  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.4  
ψJB  
19.1  
RθJC(bot)  
5.8  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report, SPRA953.  
Copyright © 2017–2018, Texas Instruments Incorporated  
5
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
6.5 Electrical Characteristics  
TJ = –40°C to 125°C, over recommended input voltage range. Typical values are at VIN = 5 V and TJ = 25°C (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SUPPLY  
I(Q)  
Quiescent supply current  
IOUT = 0mA, EN = high  
EN = low, TJ = -40°C to 85°C  
15  
5
mA  
μA  
μA  
V
(1)  
(1)  
ISD  
Shutdown supply current  
25  
55  
ISD  
Shutdown supply current  
EN = low, TJ = -40°C to 125°C  
VIN falling, detected at VAUX  
VIN rising, detected at VAUX  
Junction temperature rising  
Junction temperature falling  
Undervoltage lockout threshold  
Undervoltage lockout hysteresis  
Thermal shutdown temperature  
Thermal shutdown hysteresis  
2.55  
250  
2.6  
2.7  
350  
VUVLO  
mV  
°C  
°C  
160  
20  
TSD  
CONTROL (EN, PG)  
VIH  
VIL  
IIN  
High level input voltage for EN  
1
14  
0.4  
0.1  
V
V
Low level input voltage for EN  
Input current for EN  
EN = high  
0.01  
400  
10  
μA  
kΩ  
µs  
V
RIN  
Input resistance for EN  
PG de-glitch time  
EN = low  
rising or falling  
IPG = 1 mA  
VOL_PG  
ILKG_PG  
VVAUX  
IVAUX  
PG output low voltage  
Input leakage current (PG)  
Voltage at VAUX  
0.07  
0.3  
VPG = 5 V  
100  
nA  
V
VIN ≥ 5 V, IVAUX = 100 µA  
4.6  
2.1  
Current drawn from VAUX  
0
100  
3
μA  
POWER SWITCH  
ILIM Switch current limit (LSD)  
ILIM  
4 V ≤ VIN < 14 V, duty cycle ≤ 70%  
3.1 V < VIN < 4 V, duty cycle ≤ 70%  
HSD switch, VIN ≥ 5 V  
1.4  
0.8  
A
A
Switch current limit (LSD)  
Switch on-resistance  
80  
120  
40  
130  
190  
80  
RDS(ON)  
LSD switch, VIN ≥ 5 V  
mΩ  
RECT switch, VIN ≥ 5 V  
at SW pin  
DMAX  
ton,min  
fS  
Maximum duty cycle  
Minimum on-time  
70%  
130  
1500  
ns  
Switching frequency  
1400  
-5.5  
1600  
-1  
kHz  
OUTPUT  
VOUT  
VFB  
Output voltage range  
FB regulation voltage  
Output voltage tolerance  
Output voltage tolerance  
|VOUT| < 0.7 x VIN  
V
V
-0.7(2)  
(3)  
(3)  
for VOUT ≤ –1.8 V  
for –1.8 V < VOUT ≤ –1 V  
VFB = –0.7 V  
-1.5%  
-2%  
1.5%  
1.5%  
100  
IFB  
Feedback input bias current  
2
nA  
Discharge resistance from pin VOUT  
to GND  
RDIS  
EN = low  
100  
Ω
Line regulation  
Load regulation  
0.05  
0.02  
%/A  
%/V  
Start-up delay time from EN = high to  
start switching  
tdelay  
with CCP = 10 µF  
5
ms  
Ramp time from start switching until  
device has reached 95% of its  
nominal output voltage  
CCAP = 47 nF, VOUT = -1.8 V, device  
not in current limit during start-up  
tramp  
Iramp  
1
ms  
µA  
Soft-start current into CCAP  
55  
100  
145  
(1) This specification applies after there has been a high to low transition on EN. If EN is low while the supply voltage is applied, the  
shutdown current can be up to 90µA.  
(2) Please see the application section for how to set the output voltage.  
(3) Tolerance of VFB voltage and error of gain stage - see also "Low Noise Reference System"  
6
Copyright © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
6.6 Typical Characteristics  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
25 °C  
85 °C  
125 °C  
–40 °C  
25 °C  
85 °C  
125 °C  
–40 °C  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
D018  
D020  
图 2. EN Threshold, rising VIN  
图 3. EN Threshold, falling VIN  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
140  
130  
120  
110  
100  
90  
25 °C  
85 °C  
125 °C  
80  
25 °C  
85 °C  
125 °C  
–40 °C  
70  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
D019  
D023  
图 4. EN Threshold Hysteresis  
图 5. Resistance of HSD  
180  
170  
160  
150  
140  
130  
120  
110  
100  
80  
75  
70  
65  
60  
55  
50  
45  
40  
25 °C  
85 °C  
125 °C  
25 °C  
85 °C  
125 °C  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
3
5
7
9
Input Voltage (V)  
11  
13  
15  
D024  
D025  
图 6. Resistance of LSD  
图 7. Resistance of RECT  
版权 © 2017–2018, Texas Instruments Incorporated  
7
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
7 Detailed Description  
7.1 Overview  
The TPS63710 is a dc-dc converter that generates a negative output voltage using an inverting buck topology. It  
operates with an input voltage range of 3.1 V to 14 V and generates a negative output voltage down to -5.5 V. As  
it is based on a step-down topology, the input voltage needs to be larger than the negative voltage, in absolute  
value, that is generated. The output is controlled by a fixed-frequency, pulse-width-modulated (PWM) regulator.  
As there is an inductor in the output path, similar to a step-down converter, the output current is continuous and  
the output voltage ripple is low. This makes this topology a perfect solution for noise sensitive applications.  
7.2 Functional Block Diagram  
SW  
CP  
VIN  
RECT  
HSD  
Current  
Sensor  
LSD  
Bias  
Regulator  
VAUX  
+
_
VREF  
FB  
-
Gate  
Control  
+
VBG  
UVLO  
_
100kΩ  
gm  
Modulator  
Oscillator  
+
Soft-Start  
CAP  
PG  
EN  
2.45kΩ  
Device  
Control  
VOUT  
+
100Ω  
gm  
_
22kΩ  
/EN  
Thermal  
Shutdown  
GND  
Copyright © 2017, Texas Instruments Incorporated  
图 8. Block Diagram  
8
版权 © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
7.3 Feature Description  
7.3.1 Low Noise Reference System  
The reference system in the TPS63710 uses an external filter capacitor on the CAP pin. This reduces the low-  
frequency (1/f) noise in a range from a lower limit up to around 100kHz. The lower limit is defined by the corner  
frequency of the RC filter from the internal 100-kΩ resistor and an external capacitor on the CAP pin. The corner  
frequency is defined by 公式 1.  
1
1
fc =  
=
2p ´
R
´
C
2p ´100
k
W´
C
CAP  
(1)  
In order to minimize the noise on the output voltage, the TPS63710 uses an architecture where the output  
voltage setting is done by changing the reference voltage which then is filtered. The gain stage therefore does  
not have to have a large gain in order to not increase the noise level. VBG is the internal bandgap reference  
voltage, optimized for low noise. Its output voltage is amplified and inverted and then filtered. The voltage on the  
CAP pin is the reference for the gain stage. The connection from CAP to the external capacitor should be as  
short as possible and be kept away from noisy traces. The gain stage has a small gain of 1/0.9. The voltage at  
VREF is negative and lower than the output voltage by the gain factor of the gain stage. Please also see Setting  
the Output Voltage. 图 9 shows the low noise architecture.  
VBG  
VREF  
CAP  
-
1
gain =  
+
0.9  
internal  
100kΩ  
SW  
L
CCAP  
R1  
COUT  
gain stage  
FB  
noise filter  
R2  
VOUT  
Copyright © 2017, Texas Instruments Incorporated  
GND  
图 9. Low Noise Architecture  
7.3.2 Duty Cycle  
The duty cycle referred to in this data sheet is the duty cycle at the SW pin. By definition, from the PWM  
operation, the CP pin has the inverse duty cycle of 1-D. As a first approximation, the duty cycle is defined as  
|VOUT| / VIN. However, the actual duty cycle is larger, due to losses, and must remain below 70% for a robust  
design.  
7.3.3 Enable  
The device is enabled when the EN pin is set to high. With EN set to low, the device shuts down. After EN is set  
high, the capacitor CCP (from CP to SW) is pre-charged with about 50mA. After the start-up delay time tdelay, the  
device starts switching and ramps the output voltage to its target value. See Soft-Start.  
The EN pin must be set externally to high or low. An internal pull-down resistor of about 400 kΩ is connected and  
keeps EN low, if a low is detected internally and afterwards the pin is floating. When a high level is detected, the  
internal resistor is disconnected. The logic levels are referenced to the IC´s GND pin.  
7.3.4 Undervoltage Lockout  
An undervoltage lockout circuit prevents the device from starting up and operating, if the supply voltage is too  
low. The device automatically shuts down the converter when the VAUX voltage falls below the VUVLO threshold.  
There is hysteresis to prevent oscillation with high impedance supply voltage sources. Once the threshold plus  
hysteresis is exceeded, the device enters soft-start. Undervoltage lockout is sensed on the VAUX voltage, as this  
is the internal supply for the control loop and logic.  
版权 © 2017–2018, Texas Instruments Incorporated  
9
 
 
 
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
Feature Description (接下页)  
When VIN ramps down to a voltage too low to maintain the desired output voltage, the absolute value of the  
output voltage drops and the power good output goes low. When the output voltage level reaches the voltage on  
CCAP, at about 90% of the target output voltage, the device shuts down and initiates a re-start cycle. The  
TPS63710 then stays in the start-up state, until the input voltage is high enough to reach the desired output  
voltage.  
7.3.5 Thermal Shutdown  
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds the  
thermal shutdown temperature TSD, the device turns off the internal power FETs, discharges the output capacitor  
and the power good output goes low. It starts operation again when the junction temperature has decreased by  
the thermal shutdown hysteresis.  
7.3.6 Power Good Output  
The TPS63710 has a built-in power good (PG) output to indicate whether or not the output voltage is in  
regulation. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain  
output that requires a pull-up resistor to any positive voltage up to 5.5 V. It can sink 1 mA of current and maintain  
its specified logic low level. PG is low when the device is turned off due to EN = low, undervoltage lockout, or  
thermal shutdown. There is a typical de-glitch time of 10 µs on the power good output. The minimum VIN to drive  
the PG pin properly is typically 2 V. If not used, the PG pin may be left floating or connected to GND.  
VAUX may be used to pull-up the PG pin, but the pull-up resistor must be chosen such that the maximum load of  
100 µA on VAUX is not exceeded.  
During start-up, the power good signal is gated by the soft-start circuit such that the output is held low as long as  
the soft-start is ongoing.  
表 2. Power Good Pin Logic Table  
EN  
X
device status  
VIN < 2 V  
PG state  
high impedance  
low  
low  
VIN ≥ 2 V  
2 V ≤ VIN < UVLO OR in thermal shutdown OR VOUT not in  
high  
high  
low  
regulation  
VOUT in regulation  
high impedance  
7.4 Device Functional Modes  
7.4.1 Soft-Start  
The discharge circuit keeps the output voltage at 0 V when the TPS63710 is disabled. The TPS63710 only  
begins the start-up cycle when the output voltage is between +300 mV to -300 mV to ensure a proper start-up.  
When the output voltage is not in this range, the device keeps the discharge switch on and waits until the voltage  
is within the window.  
When the device is enabled, the internal reference is powered up. After the startup delay time when the CCP  
capacitor is pre-charged, the device enters soft-start, starts switching and ramps down the output voltage. Soft-  
start is achieved by ramping the reference voltage, hence the output voltage, to its nominal value. This ramp time  
is defined by an external capacitor connected to the CAP pin. The capacitor is charged with typically 100 µA by  
an internal current source. The ramp time is defined in 公式 2.  
C
CAP´VREF  
CCAP´0.9´VOUT  
=
t
ramp =  
Iramp  
Iramp  
(2)  
7.4.2 VOUT Discharge  
The VOUT pin has a discharge circuit to connect the output to GND, once the device is disabled. This feature  
prevents residual voltages on the output capacitor. The discharge circuit becomes active when VIN drops below  
VUVLO, EN=low, or thermal shutdown occurs. The minimum supply voltage required to drive the discharge switch  
is typically 2 V.  
10  
版权 © 2017–2018, Texas Instruments Incorporated  
 
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
Device Functional Modes (接下页)  
7.4.3 Current Limit  
A current limit protects the device against short circuits at the output. The current limit is scaled down from its  
nominal value for input voltages below 4 V. The current limit monitors the peak current in the LSD during the ON-  
time. If this current is reached during the ON-time, the LSD is turned off and the HSD and RECT turned on to  
decrease the current. The next ON-time begins at the next switching cycle.  
A short circuit from VIN to GND during operation should be avoided as this leads to a high current discharging  
the CCP capacitor through the back-gate diode of the high side switch to GND. When there is an overload on the  
output and the output voltage drops below 0.9 times the target output voltage, the device re-starts.  
7.4.4 CCP Capacitor Precharge  
The CCP capacitor is pre-charged during the start-up delay phase by a current that increases up to 50 mA based  
on the voltage of VIN - VCP. When the voltage on CCP reaches approximately the VIN level, the device starts  
switching.  
7.4.5 PWM Operation  
The converter operates with a fixed-frequency, pulse-width-modulated control. In the OFF-time, the rectifier  
switch (RECT) and the high-side switch (HSD) are turned on to charge CCP to the input voltage. As well, the  
inductor current ramps down, continuing to charge the output capacitor. During the ON-time, the low-side switch  
(LSD) is closed and HSD and RECT are opened. CCP inverts the supply voltage onto SW, and the inductor  
current is ramped up. The LC output filter filters the SW voltage, just like in a step-down converter. Charging the  
CCP capacitor during the OFF-time limits the maximum duty cycle. The upper limit of the duty cycle is 70% to  
allow charging the CCP capacitor in the remaining 30%.  
Lower negative voltages require higher positive supply voltages. For an output voltage of -1.8 V, a minimum input  
voltage of 4.5 V is sufficient while for an output voltage of -3.3 V, the input voltage has to be above 6 V. See 图  
37 to 图 39 for the relation of input voltage, output voltage and temperature vs output current.  
For high input voltages and, in absolute value, small output voltages, the device operates with its minimum on-  
time (ton,min) to generate the duty cycle required for this VIN and VOUT ratio. This means that, for such cases, the  
switching frequency is lower than fS.  
版权 © 2017–2018, Texas Instruments Incorporated  
11  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
8 Application and Implementation  
注
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
8.1 Application Information  
The TPS63710 is intended for systems typically powered by a pre-regulated power supply but can also run on a  
battery with a supply voltage range between 3.1 V and 14 V.  
8.2 Typical Application  
The application covers the input voltage range from 4.5 V to 14 V at the full 1-A output current. The output  
capacitors are designed for an output voltage of -1.8 V. With output voltages below -1.8V (larger negative  
voltages), the output capacitance has to be increased as described in the Detailed Design Procedure. The  
minimum supply voltage is defined by the 70% duty cycle limit, output current and the output voltage. Please see  
图 37 to 图 39 for the recommended input voltage levels to generate a specific output voltage.  
3 x 10uF  
16V / 0805  
CCP  
2.2uF / 16V  
TPS63710  
0603  
CP  
VIN = 4.5V to 14V  
VIN  
EN  
CIN  
VOUT = -1.8V  
L
2 x 22uF  
16V  
SW  
4.7 uH  
2 x 22uF  
10V / 0805  
COUT  
VOUT  
VREF  
R 1  
R 2  
CAP  
CCAP  
1uF  
FB  
+V  
VAUX  
R3  
100kΩ  
CAUX  
PG  
220nF  
GND  
Copyright © 2017, Texas Instruments Incorporated  
图 10. Typical Application for an Input Voltage up to 14V  
8.2.1 Design Requirements  
The design of the inverter can be adapted to different output voltages and load currents. The following  
components cover an input voltage range up to 9 V. For CIN, a 0603 capacitor close to the device pins is  
required in addition to the larger capacitor. As the CCP capacitor has the same voltage across it, its dc bias effect  
is similar to CIN. 表 3 gives examples for the schematics optimized for different input and output voltage ranges.  
表 3. Bill of Materials  
(1)  
Reference  
Part Number  
Value  
Manufacturer  
IC  
TPS63710DRR  
Texas Instruments  
EMK107BB7225KA-T  
EMK316BB7226ML-T  
2.2 µF / 16 V +  
2 x 22 µF / 16 V  
CIN  
Taiyo Yuden  
CCP  
COUT  
L
EMK212BB7106MG-T  
C2012X7S1A226M125AC  
XFL4020-222  
3 x 10 µF / 16V  
2 x 22 µF / 10 V  
2.2 µH  
Taiyo Yuden  
TDK  
Coilcraft  
Würth  
CCAP  
CAUX  
R1  
885012206026  
1 µF / 10 V  
220 nF / 10 V  
196 kΩ  
885012206022  
Würth  
(1) See Third-party Products Disclaimer  
12  
版权 © 2017–2018, Texas Instruments Incorporated  
 
 
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
Typical Application (接下页)  
表 3. Bill of Materials (接下页)  
(1)  
Reference  
Part Number  
Value  
150 kΩ  
100 kΩ  
Manufacturer  
R2  
R3  
8.2.2 Detailed Design Procedure  
8.2.2.1 Custom Design With WEBENCH® Tools  
Click here to create a custom design using the TPS63710 device with the WEBENCH® Power Designer.  
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.  
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.  
3. Compare the generated design with other possible solutions from Texas Instruments.  
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time  
pricing and component availability.  
In most cases, these actions are available:  
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance  
Run thermal simulations to understand board thermal performance  
Export customized schematic and layout into popular CAD formats  
Print PDF reports for the design, and share the design with colleagues  
Get more information about WEBENCH tools at www.ti.com/WEBENCH.  
8.2.2.2 Setting the Output Voltage  
The output voltage of the TPS63710 converter is adjusted with an external resistor divider connected to the FB  
pin. The voltage at the feedback pin is negative and is regulated to -0.7 V. The gain stage adds a gain factor of  
1/0.9 such that the output voltage is -0.778 V for -0.7 V of FB voltage. See Low Noise Reference System for  
details.  
The value of the output voltage is set by the selection of the resistive divider using 公式 3 and VFB_SET = -0.778  
V. Both VOUT and VFB_SET are negative, so the ratio is positive again.  
V
OUT  
æ
ç
è
ö
÷
ø
R1  
= R2 ´  
-1  
VFB _ SET  
(3)  
It is recommended to choose resistor values such that R1 + R2 are in a range from 100 kΩ to 500 kΩ. For  
example, if an output voltage of -1.8 V is needed and a resistor of 150-kΩ has been chosen for R2, a 196-kΩ  
resistor on R1 is required to program the desired output voltage.  
表 4. Recommended Resistor Values  
Output Voltage  
-1 V  
R1  
R2  
51.1 kΩ  
196 kΩ  
287 kΩ  
130 kΩ  
180 kΩ  
150 kΩ  
130 kΩ  
24 kΩ  
-1.8 V  
-2.5 V  
-5 V  
For proper regulation, the minimum input voltage should remain at least above the output voltage, per 公式 4:  
1
VIN  
³
´|VOUT |  
0.7  
(4)  
13  
See 图 37 to 图 39 for the recommended input voltage levels to generate a specific output voltage.  
版权 © 2017–2018, Texas Instruments Incorporated  
 
 
 
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
8.2.2.3 Inductor Selection  
The basic parameters for choosing an appropriate inductor is saturation current, as well as the dc resistance of  
the inductor. The TPS63710 is designed such that it operates with an inductance as given in the recommended  
operating conditions. For best performance, a nominal inductance of 2.2 µH should be used for input voltages  
below 9 V. For input voltages above 9 V, a nominal inductance of 4.7 µH is preferred to keep the inductor current  
ripple at a reasonable level.  
Similar to a step-down converter, the inductor along with the output capacitor forms a LC filter. For noise-  
sensitive applications, larger values for the inductance and output capacitance are preferred to get the noise  
level at the output to very low values.  
The peak inductor current depends on the output load, the input voltage VIN, and the output voltage VOUT. The  
average inductor current equals the load current.  
The topology can be simplified to an inverter stage followed by a step-down converter. The equations for  
calculating the inductor current of a step-down converter therefore also apply. The worst case inductor ripple  
current occurs at 50% duty cycle which is when VIN = 2 x |VOUT|. The voltage across the inductor is VIN - |VOUT|,  
which is 0.5 x VIN at 50% duty cycle. With this, 公式 5 and dt = 0.5 x 1/fS, the peak to peak inductor ripple current  
is defined by 公式 6. The inductor´s saturation current must remain above its peak current which is calculated in  
公式 7. 表 5 shows a list of recommended inductors.  
dI  
V = L´  
dt  
(5)  
V
IN ´0.5  
1
|VOUT  
|
1
DIpp =  
´
´0.5 =  
´
´0.5  
L
f
S
L
f
S
(6)  
(7)  
1
I
Lpeak = IOUT + DIpp  
2
表 5. List of Inductors  
Input Voltage  
Vendor  
comment  
Suggested Inductor(1)  
3.1 V to 9 V  
Coilcraft  
XFL3012-222ME  
best performance for low  
input voltage  
3.1 V to 9 V  
Coilcraft  
XFL4020-222ME  
3.1 V to 9 V  
3.1 V to 14 V  
3.1 V to 14 V  
Toko  
Coilcraft  
Würth  
low cost; small size  
DFE252012F-2R2M  
XFL4020-472ME  
744 383 570 47  
(1) See Third-party Products Disclaimer  
8.2.2.4 Capacitor Selection  
8.2.2.4.1 CCP Capacitor  
The capacitance of CCP determines the maximum output current of TPS63710. Therefore it is selected at first. A  
minimum 4-uF of effective capacitance is required to support the full output current of 1 A. Only ceramic  
capacitors like X7R, X5R or equivalent are recommended. For applications that require a lower maximum output  
current, its value can be reduced linearly. As the voltage at the CCP capacitor is equal to the input voltage VIN,  
the dc bias effect has to be taken into account based on the maximum input voltage. 表 6 shows recommended  
CCP capacitors.  
表 6. CCP Capacitor Selection  
number of capacitors  
input voltage  
range; VIN  
required for 1A of output  
current based on dc bias  
effect  
nominal value  
voltage rating  
package size  
Suggested Capacitors(1)  
3.1 V to 6 V  
10 µF  
10 µF  
> VIN  
> VIN  
0805  
0805  
2
3
EMK212BB7106MG-T  
EMK212BB7106MG-T  
3.1 V to 14 V  
(1) See Third-party Products Disclaimer  
14  
版权 © 2017–2018, Texas Instruments Incorporated  
 
 
 
 
 
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
8.2.2.4.2 Input Capacitor  
The capacitance of the input capacitor should be at least twice the capacitance of CCP. At least a 22-μF ceramic  
input capacitor is recommended for a good transient behavior of the regulator and EMI behavior of the total  
power supply circuit. The capacitor must be located as close to the VIN and GND pins as possible. Only ceramic  
capacitors like X7R, X5R or equivalent are recommended. A 0603 size 2.2-µF ceramic capacitor in parallel to the  
main input capacitor is recommended to reduce high frequency noise. The input capacitance can be increased  
without limit. 表 7 shows recommended capacitors.  
表 7. Input Capacitor Selection  
number of capacitors  
input voltage  
range; VIN  
voltage  
rating  
required for 1A of  
output current based  
on dc bias effect  
nominal value  
package size  
Suggested Capacitors(1)  
3.1 V to 6 V  
2 x capacitance of CCP  
2 x capacitance of CCP  
> VIN  
> VIN  
1206  
1206  
2
3
EMK316BB7226ML-T  
EMK316BB7226ML-T  
3.1 V to 14 V  
(1) See Third-party Products Disclaimer  
8.2.2.4.3 Output Capacitor  
One of the major parameters necessary to define the capacitance value of the output capacitor is the maximum  
allowed output voltage ripple of the converter and device stability. Internal device compensation defines the limits  
for the capacitance on the output. Only ceramic capacitors like X7R, X5R or equivalent are recommended. Table  
表 8 gives the minimum amount of capacitors required for a given output voltage based on the dc bias effect. For  
lowest output voltage ripple, more capacitance can be added up to the maximum value as defined in the  
recommended operating conditions.  
表 8. Output Capacitor Selection  
number of capacitors  
required based on dc  
bias effect  
output voltage range;  
VOUT  
voltage  
rating  
(1)  
nominal value  
package size  
Suggested Capacitors  
-1 V to -3.3 V  
- 1 V to -5.5 V  
22 µF  
22 µF  
≥ 6.3 V  
≥ 10 V  
0805  
0805  
2
3
C2012X7S1A226M125AC  
C2012X7S1A226M125AC  
(1) See Third-party Products Disclaimer  
版权 © 2017–2018, Texas Instruments Incorporated  
15  
 
 
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
8.2.3 Application Curves  
8.2.3.1 Parameter Measurement Information  
The application curves have been taken using the schematic in 图 10 and BOM according 表 3. Based on the  
output voltage, the components given in 表 9 have been changed. The resistor divider is based on 表 4.  
表 9. Component Selection for VOUT Options  
VOUT  
CCP  
L
COUT  
-1 V and -1.8 V  
-3.3 V and -5 V  
2 x EMK212BB7106MG-T  
3 x EMK212BB7106MG-T  
XFL4020-222ME  
XFL4020-472ME  
2 x C2012X7S1A226M125AC  
3 x C2012X7S1A226M125AC  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 3.3 V  
VIN = 4.5 V  
VIN = 5 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
VIN = 4 V  
VIN = 5 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Output Current (A)  
1
Output Current (A)  
D003  
D004  
VOUT = -1 V  
IOUT = 0 A to 1 A  
TA = 25°C  
VOUT = -1.8 V  
IOUT = 0 A to 1 A  
TA = 25°C  
图 11. Efficiency vs Output Current  
图 12. Efficiency vs Output Current  
100  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 6 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
Output Current (A)  
Output Current (A)  
D013  
D006  
VOUT = -3.3 V  
IOUT = 0 A to 1 A  
TA = 25°C  
VOUT = -5 V  
IOUT = 0 A to 1 A  
TA = 25°C  
图 13. Efficiency vs Output Current  
图 14. Efficiency vs Output Current  
16  
版权 © 2017–2018, Texas Instruments Incorporated  
 
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
-0.99  
-0.992  
-0.994  
-0.996  
-0.998  
-1  
-1.78  
-1.785  
-1.79  
VIN = 3.3 V  
VIN = 4 V  
VIN = 5 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
VIN = 4.5 V  
VIN = 5 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
-1.795  
-1.8  
-1.002  
-1.004  
-1.006  
-1.008  
-1.805  
-1.81  
-1.815  
-1.82  
-1.01  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Output Current (A)  
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Output Current (A)  
1
D009  
D010  
VOUT = -1 V  
IOUT = 0 A to 1 A  
TA = 25°C  
VOUT = -1.8 V  
IOUT = 0 A to 1 A  
TA = 25°C  
图 15. Output Voltage vs Output Current  
图 16. Output Voltage vs Output Current  
-4.95  
-4.96  
-4.97  
-4.98  
-4.99  
-5  
-3.27  
-3.28  
-3.29  
-3.3  
-5.01  
-5.02  
-5.03  
-5.04  
-5.05  
-3.31  
-3.32  
VIN = 6 V  
VIN = 7 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
VIN = 9 V  
VIN = 12 V  
VIN = 14 V  
-3.33  
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
Output Current (A)  
D012  
Output Current (A)  
D017  
VOUT = -5 V  
IOUT = 0 A to 1 A  
TA = 25°C  
VOUT = -3.3 V  
IOUT = 0 A to 1 A  
TA = 25°C  
图 18. Output Voltage vs Output Current  
图 17. Output Voltage vs Output Current  
VIN = 5 V  
VOUT = -1.8 V  
IOUT = 100 mA to  
900 mA  
TA = 25°C  
VIN = 5 V  
VOUT = -1 V  
IOUT = 100 mA to  
900 mA  
TA = 25°C  
图 20. Load Transient Response  
图 19. Load Transient Response  
版权 © 2017–2018, Texas Instruments Incorporated  
17  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
VIN = 9 V  
VOUT = -3.3 V  
IOUT = 100 mA to  
900 mA  
TA = 25°C  
VIN = 9 V  
VOUT = -5 V  
IOUT = 100 mA to  
900 mA  
TA = 25°C  
图 21. Load Transient Response  
图 22. Load Transient Response  
VIN = 4 V to 6 V to 4 V  
VOUT = -1 V  
IOUT = 0.5 A  
TA = 25°C  
VIN = 4 V to 5 V to 4 V  
VOUT = -1.8 V  
IOUT = 0.5 A  
TA = 25°C  
图 23. Line Transient Response  
图 24. Line Transient Response  
VIN = 9 V to 12 V to 9 V  
VOUT = -3.3 V  
IOUT = 0.5 A  
TA = 25°C  
VIN = 9 V to 12 V to 9 V  
VOUT = -5 V  
IOUT = 0.5 A  
TA = 25°C  
图 25. Line Transient Response  
图 26. Line Transient Response  
18  
版权 © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
VIN = 5 V  
IOUT = 0.5 A  
TA = 25°C  
VIN = 5 V  
IOUT = 0.5 A  
TA = 25°C  
VOUT = -1 V  
VOUT = -1.8 V  
图 27. Start-Up Timing  
图 28. Start-Up Timing  
VIN = 9 V  
VOUT = -3.3 V  
IOUT = 0.5 A  
TA = 25°C  
VIN = 9 V  
VOUT = -5 V  
IOUT = 0.5 A  
TA = 25°C  
图 29. Start-Up Timing  
图 30. Start-Up Timing  
VIN = 5 V  
VOUT = -1.8 V  
IOUT = 1 A  
L = 2.2 µH  
TA = 25°C  
VIN = 5 V  
VOUT = -1 V  
IOUT = 1 A  
L = 2.2 µH  
TA = 25°C  
图 32. Output Voltage Ripple  
图 31. Output Voltage Ripple  
版权 © 2017–2018, Texas Instruments Incorporated  
19  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
VIN = 9 V  
VOUT = -3.3 V  
IOUT = 1 A  
L = 2.2 µH  
TA = 25°C  
VIN = 9 V  
VOUT = -5 V  
IOUT = 1 A  
L = 4.7 µH  
TA = 25°C  
图 33. Output Voltage Ripple  
图 34. Output Voltage Ripple  
VIN = 12 V  
VOUT = -5 V  
IOUT = 1 A  
L = 4.7 µH  
TA = 25°C  
VIN = 12 V  
VOUT = -1.8 V  
IOUT = 1 A  
L = 2.2 µH  
TA = 25°C  
图 36. Output Voltage Ripple  
图 35. Output Voltage Ripple  
1.2  
1.2  
1
1
0.8  
0.6  
0.4  
0.2  
0
0.8  
0.6  
0.4  
0.2  
0
VOUT = -5 V  
VOUT = -5 V  
VOUT = -3.3 V  
VOUT = -1 V  
VOUT = -3.3 V  
VOUT = -1.8 V  
VOUT = -1 V  
VOUT = -1.8 V  
3
5
7
9
11  
13  
15  
3
6
9
12  
15  
Input Voltage (V)  
Input Voltage (V)  
D014  
D015  
TA = 25°C  
TA = 85°C  
图 37. Maximum Output Current vs Input Voltage  
图 38. Maximum Output Current vs Input Voltage  
版权 © 2017–2018, Texas Instruments Incorporated  
20  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
1.2  
VOUT = -1 V  
VOUT = -1.8 V  
VOUT = -3.3 V  
VOUT = -5 V  
10µ  
1µ  
1
0.8  
0.6  
0.4  
0.2  
100n  
VOUT = -5 V  
VOUT = -3.3 V  
VOUT = -1 V  
VOUT = -1.8 V  
0
3
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
5
7
9
11  
13  
15  
Input Voltage (V)  
D021a  
D016  
IOUT = 0.2 A  
TA = 25°C  
TA = 125°C  
图 40. Output Noise Density  
图 39. Maximum Output Current vs Input Voltage  
10µ  
VOUT = -1 V  
VOUT = -1.8 V  
VOUT = -3.3 V  
VOUT = -5 V  
Vnoise = 22mVrms  
at Vout = -1.8V  
BW = 10Hz to 100kHz  
1µ  
100n  
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
D022a  
IOUT = 1 A  
TA = 25°C  
图 41. Output Noise Density  
版权 © 2017–2018, Texas Instruments Incorporated  
21  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
8.3 System Examples  
8.3.1 Typical Application for Powering the Negative Rail of a Gallium Nitride (GaN) Power Amplifier  
The TPS63710 requires a supply voltage in the range of 8.8 V to 14 V in order to generate an output voltage of  
-5 V. The circuit therefore was optimized for this input voltage range. The number of the input, output and CCP  
capacitors have been adjusted to compensate for the higher dc bias effect with large input and output voltages.  
In addition, the inductor has been changed to 4.7 µH for low inductor current ripple at an input voltage up to 14  
V.  
2.2uF / 16V  
3 x 10uF  
16V / 0805  
TPS63710  
0603  
CCP  
CP  
VIN = 8.8V to 14V  
VIN  
EN  
CIN  
VOUT = -5V  
L
2 x 22uF  
16V  
SW  
4.7uH  
3 x 22uF  
10V / 0805  
COUT  
VOUT  
VREF  
R1  
R2  
130kΩ  
CAP  
CCAP  
1uF  
FB  
24kΩ  
+V  
VAUX  
R3  
100kΩ  
CAUX  
PG  
220nF  
GND  
Copyright © 2017, Texas Instruments Incorporated  
图 42. Typical Application for an Output Voltage of -5 V  
8.3.2 Typical Application for Powering the Negative Rail of an ADC or DAC  
Typically, the input voltage to the inverter in applications powering the negative supply of an ADC or DAC is  
about 5 V. The circuit therefore was optimized for this input voltage range, because the size and amount of  
capacitors depends on the voltage applied to the capacitors. In order not to over-design, the input voltage range  
was set to the range required to set a limit for the dc bias of the capacitors. 图 43 shows a, for an input voltage of  
5-V, optimized design. The minimum input voltage to support the full output current is 4.5 V. The maximum input  
voltage is defined by the dc bias characteristic of the input and CCP capacitors. If a higher input voltage is  
required, these capacitors have to be adjusted accordingly.  
22  
版权 © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
System Examples (接下页)  
2 x 10uF  
16V / 0805  
CCP  
2.2uF / 16V  
0603  
TPS63710  
CP  
VIN = 4.5V to 6V  
VIN  
EN  
CIN  
22uF  
VOUT = -1.8V  
L
SW  
16V  
2.2 uH  
2 x 22uF  
10V / 0805  
COUT  
VOUT  
VREF  
196kΩ  
CAP  
CCAP  
FB  
1uF  
150kΩ  
+V  
VAUX  
R3  
100kΩ  
CAUX  
PG  
220nF  
GND  
Copyright © 2017, Texas Instruments Incorporated  
图 43. Typical Application for VIN ≈ 5 V  
8.3.3 Typical Application for Laser Diode Bias  
Laser diode bias typically requires a voltage of about -1 V from a 3.3 V supply. The TPS63710 was optimized for  
these operating conditions. The passive components have been chosen for a fixed supply voltage of 3.3 V. The  
number of the input, output and CCP capacitors have been adjusted for the input and output voltage in this  
application.  
10uF  
16V / 0805  
CCP  
2.2uF / 16V  
TPS63710  
0603  
CP  
VIN = 3.3V  
VIN  
EN  
CIN  
VOUT = -1V, 0.8A  
2 x 22uF  
10V / 0805  
COUT  
L
22uF  
10V / 0805  
SW  
2.2 uH  
VOUT  
VREF  
R1  
R2  
51.1kΩ  
CAP  
CCAP  
1uF  
FB  
180kΩ  
+V  
VAUX  
R3  
100kΩ  
CAUX  
PG  
220nF  
GND  
Copyright © 2017, Texas Instruments Incorporated  
图 44. Typical Application for an Output Voltage of -1 V  
版权 © 2017–2018, Texas Instruments Incorporated  
23  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
9 Power Supply Recommendations  
The power supply to the TPS63710 needs to have a current rating according to the input supply voltage, output  
voltage and output current of the TPS63710. The peak current requirement on the input depends on the duty  
cycle, as CCP is charged during the off-time. Worst case is for the maximum duty cycle of 70% when the OFF-  
time is at its shortest value of 30%. The peak current on the input can be up to 5 times of the average output  
current. A proper input capacitor needs to be placed directly at the VIN and GND pins to supply the peak current  
demand of the converter. Slew rates faster than 1 V/µs for a VIN step of less than 1 V and 0.1 V/µs for a VIN step  
over the full input voltage range up to 14 V should be avoided, as this leads to a large inrush current through the  
CCP capacitor and HSD.  
When the input supply of TPS63710 is shorted while the device is enabled, the charge stored on the CCP  
capacitor is transferred to the output. This may cause an output voltage undershoot. It is recommended to  
disable the TPS63710 by setting the EN pin to low while the supply voltage is within the recommended input  
voltage range. This ensures a proper shutdown.  
24  
版权 © 2017–2018, Texas Instruments Incorporated  
TPS63710  
www.ti.com.cn  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
10 Layout  
10.1 Layout Guidelines  
For all switching power supplies, the layout is an important step in the design, especially at high peak currents  
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as  
well as EMI problems. Therefore, use wide and short traces for the main current paths, and for the power-ground  
tracks. The input, output and CP capacitors should be placed as close as possible to the IC. Because CVAUX  
carries the peak currents of the gate control block, it should have a compact and direct routing to the VAUX and  
GND pin 10, staying away from sensitive signals. The CAP, FB, and VREF pins should all be routed close to the  
IC in order to keep them away from external noise. The total resistance of the voltage divider R1 + R2 must be  
kept in the range as defined in the Recommended Operating Conditions.  
The pinout of the device has been defined such that the external components can be placed directly at the pins  
to allow for a simplified external layout and good performance. Thermal and electrical vias should be used under  
the exposed thermal pad to the GND plane.  
10.2 Layout Example  
CCP  
PAC1001  
PAC1002  
L
PAC901  
PAC801  
PAC902  
PAC802  
VIN  
VOUT  
CIN  
PPP
COUT  
PAC1101  
PAC1102  
CCAP  
CAUX  
R3  
GND  
GND  
R2  
R1  
图 45. Recommended Layout  
版权 © 2017–2018, Texas Instruments Incorporated  
25  
TPS63710  
ZHCSGR8A –SEPTEMBER 2017–REVISED JULY 2018  
www.ti.com.cn  
11 器件和文档支持  
11.1 器件支持  
11.1.1 使用 WEBENCH® 工具创建定制设计  
单击此处，使用 TPS63710 器件并借助 WEBENCH® 电源设计器创建定制设计方案。  
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。  
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。  
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。  
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。  
在多数情况下，可执行以下操作：  
•
•
•
•
运行电气仿真，观察重要波形以及电路性能  
运行热性能仿真，了解电路板热性能  
将定制原理图和布局方案以常用 CAD 格式导出  
打印设计方案的 PDF 报告并与同事共享  
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。  
11.1.2 第三方产品免责声明  
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类  
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。  
11.2 社区资源  
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，  
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。  
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在  
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。  
设计支持  
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。  
11.3 商标  
E2E is a trademark of Texas Instruments.  
WEBENCH is a registered trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
11.4 静电放电警告  
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损  
伤。  
11.5 术语表  
SLYZ022 — TI 术语表。  
这份术语表列出并解释术语、缩写和定义。  
12 机械、封装和可订购信息  
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且  
不会对此文档进行修订。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。  
26  
版权 © 2017–2018, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS63710DRRR  
TPS63710DRRT  
ACTIVE  
ACTIVE  
WSON  
WSON  
DRR  
DRR  
12  
12  
3000 RoHS & Green  
250 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
63710  
63710  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2021  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS63710DRRR  
TPS63710DRRT  
WSON  
WSON  
DRR  
DRR  
12  
12  
3000  
250  
330.0  
180.0  
12.4  
12.4  
3.3  
3.3  
3.3  
3.3  
1.1  
1.1  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS63710DRRR  
TPS63710DRRT  
WSON  
WSON  
DRR  
DRR  
12  
12  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DRR0012C  
WSON - 0.8 mm max height  
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD  
3.1  
2.9  
A
B
PIN 1 INDEX AREA  
3.1  
2.9  
C
0.8 MAX  
SEATING PLANE  
0.08  
0.05  
0.00  
EXPOSED  
THERMAL PAD  
1.5±0.1  
(0.1) TYP  
10X 0.5  
6
7
2X  
13  
SYMM  
2.5±0.1  
2.5  
1
12  
0.3  
12X  
SYMM  
PIN 1 ID  
(OPTIONAL)  
0.2  
0.1  
0.05  
C A B  
0.5  
0.3  
12X  
4222932/A 05/2016  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DRR0012C  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(1.5)  
12X (0.6)  
(R0.05) TYP  
12  
SYMM  
1
12X (0.25)  
13  
SYMM  
(2.5)  
(1)  
10X (0.5)  
6
7
(0.5)  
(
0.2) VIA  
TYP  
(2.8)  
LAND PATTERN EXAMPLE  
SCALE:20X  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
METAL  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4222932/A 05/2016  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DRR0012C  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
12X (0.6)  
2X (1.38)  
1
12  
12X (0.25)  
2X (1.11)  
SYMM  
(0.66)  
10X (0.5)  
7
6
SYMM  
(2.8)  
13  
METAL  
TYP  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD 13  
81.7% PRINTED SOLDER COVERAGE BY AREA  
SCALE:20X  
4222932/A 05/2016  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
本、损失和债务，TI 对此概不负责。  
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE  
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2022，德州仪器 (TI) 公司  

相关型号：

TPS63710DRRT

 采用 3x3 WSON 封装的低噪声 1A 同步反相降压转换器 | DRR | 12 | -40 to 125

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63802

 采用 QFN/DFN 封装的 2A 高效 11µA 静态电流降压/升压转换器

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63802DLAR

 采用 QFN/DFN 封装的 2A 高效 11µA 静态电流降压/升压转换器 | DLA | 10 | -40 to 125

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63802DLAT

 采用 QFN/DFN 封装的 2A 高效 11µA 静态电流降压/升压转换器 | DLA | 10 | -40 to 125

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63805

 具有微型解决方案尺寸的 2A 高效 11µA 静态电流降压/升压转换器

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63805YFFR

 具有微型解决方案尺寸的 2A 高效 11µA 静态电流降压/升压转换器 | YFF | 15 | -40 to 125

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63805YFFT

 具有微型解决方案尺寸的 2A 高效 11µA 静态电流降压/升压转换器 | YFF | 15 | -40 to 125

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63805_V02

 TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63806

 TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63806YFFR

 TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63807

 TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

TPS63807YFFR

 TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明