TPS63805_V02 [TI]
TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size;
| 型号： | TPS63805_V02 |
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TEXAS INSTRUMENTS |
| 描述： | TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size |
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TPS63805, TPS63806, TPS63807
SLVSDS9E – JULY 2018 – REVISED AUGUST 2021
TPS6380x High-Efficiency, Low IQ Buck-Boost Converter with Small Solution Size
– Output discharge feature when EN is low
– 480-µs Tramp for small inrush current during
1 Features
•
Three pin-to-pin device options: TPS63805,
TPS63806, and TPS63807 with specific
application focus
start-up
2 Applications
•
Input voltage range: 1.3 V to 5.5 V
– Device input voltage > 1.8 V for start-up
Output voltage range: 1.8 V to 5.2 V (adjustable)
High efficiency over the entire load range
– Power save mode and mode selection for
forced PWM-mode
•
TPS63805
– System pre-regulator (smartphone, tablet, left
terminal, and telematics)
– Point-of-load regulation (wired sensor, port/
cable adapter, and dongle)
•
•
•
TPS63806
•
•
•
Peak current buck-boost mode architecture
– Defined transition points between buck, buck-
boost, and boost operation modes
– Forward and reverse current operation
– Start-up into pre-biased outputs
Safety and robust operation features
– Integrated soft start
– Overtemperature- and overvoltage-protection
– True shutdown function with load disconnect
– Forward and backward current limit
TPS63805
– Optimized for smallest solution size of 18.5
mm2 (works with a 22-µF minimum output
capacitor)
– 2-A output current for VI ≥ 2.3 V, VO = 3.3 V
– 11-µA operating quiescent current
TPS63806
– Optimized for best load step response (180-mV
load-step response at a 2 A current step)
– Up to 2.5-A transient output current
– 13-µA operating quiescent current
TPS63807
– Optimized for smallest solution size of 18.5
mm2 (works with a 22-µF minimum output
capacitor)
– Time-of-flight camera sensor (smartphone,
electronic smart lock, and ip network camera)
– Broadband network radio or SoC supply (IoT,
tracking, home automation, and EPOS)
– Thermoelectric device supply (TEC, optical
modules)
– General purpose voltage stabilizer
TPS63807
– Applications needing an output discharge
feature
•
3 Description
The TPS63805, TPS63806, and TPS63807 are high
efficiency, high output current buck-boost converters.
Depending on the input voltage, they automatically
operate in boost, buck, or in a novel 4-cycle buck-
boost mode when the input voltage is approximately
equal to the output voltage.
•
•
Device Information
PART NUMBER
TPS63805
PACKAGE(1)
BODY SIZE (NOM)
3 × 5 Balls WCSP
(0.4 mm pitch)
TPS63806
2.3 mm × 1.4 mm
TPS63807
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
– 2-A output current for VI ≥ 2.3 V, VO = 3.3 V
– 11-µA operating quiescent current
0.47 µH
100
90
80
70
60
50
40
L1
L2
VIN
1.3 V œ 5.5 V
VOUT
3.3 V
VIN
EN
VOUT
22 ꢀF
10 ꢀF
PG
FB
MODE
GND
30
VIN = 3.0 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
20
AGND
10
0
TPS63805
100m
1m
10m
Output Current (A)
100m
1
2
D
D001
01
Typical Application
Efficiency Versus Output Current (VO = 3.3 V)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS63805, TPS63806, TPS63807
SLVSDS9E – JULY 2018 – REVISED AUGUST 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................3
8 Specifications.................................................................. 4
8.1 Absolute Maximum Ratings........................................ 4
8.2 ESD Ratings............................................................... 4
8.3 Recommended Operating Conditions.........................4
8.4 Thermal Information....................................................4
8.5 Electrical Characteristics.............................................5
8.6 Typical Characteristics................................................7
9 Detailed Description........................................................8
9.1 Overview.....................................................................8
9.2 Functional Block Diagram...........................................8
9.3 Feature Description.....................................................9
9.4 Device Functional Modes..........................................11
10 Application and Implementation................................15
10.1 Application Information........................................... 15
10.2 Typical Application.................................................. 15
11 Power Supply Recommendations..............................31
12 Layout...........................................................................32
12.1 Layout Guidelines................................................... 32
12.2 Layout Example...................................................... 32
13 Device and Documentation Support..........................33
13.1 Device Support....................................................... 33
13.2 Receiving Notification of Documentation Updates..33
13.3 Support Resources................................................. 33
13.4 Trademarks.............................................................33
13.5 Electrostatic Discharge Caution..............................33
13.6 Glossary..................................................................33
14 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
Changes from Revision D (January 2021) to Revision E (August 2021)
Page
•
Added the TPS63807......................................................................................................................................... 1
Changes from Revision C (September 2019) to Revision D (January 2021)
Page
•
Updated the numbering format for tables, figures and cross-references throughout the document. .................1
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5 Description (continued)
The transitions between modes happen at defined thresholds and avoid unwanted toggling within the modes
to reduce output voltage ripple. The device output voltages are individually set by a resistive divider within
a wide output voltage range. The TPS63805 and TPS63807 achieve the lowest solution size with a tiny bill
of materials. An 11-μA quiescent current enables the highest efficiency for little to no-load conditions. The
TPS63805, TPS63806, and TPS63807 come in a 1.4-mm × 2.3-mm package. The device works with tiny
passive components to keep the overall solution size small.
The TPS63806 is optimized for applications where the load-step response under a heavy load profile is a
concern.
6 Device Comparison Table
PART
NUMBER
OUTPUT VOLTAGE
(VO)
VPP LOAD TRANSIENT
RESPONDS (TYP.)
I(Q;VIN) (TYP.)
C(O,EFF) (MIN.)
TPS63805/
TPS63807
Adjustable
Adjustable
11 µA
13 µA
7 µF
320 mV
180 mV
TPS63806
21 µF
7 Pin Configuration and Functions
A
B
C
D
E
3
2
1
VIN
VIN
EN
L1
GND
L2
VOUT
L1
GND
L2
VOUT
MODE
AGND
FB
PG
Not to scale
Figure 7-1. WCSP Package Top View
Table 7-1. Pin Functions
PIN
NAME
DESCRIPTION
NO
A2, A3
B2, B3
A1
VIN
Supply voltage
L1
Connection for inductor
EN
Device Enable input. Set HIGH to enable and LOW to disable. It must not be left floating.
Power ground
C2, C3
B1
GND
MODE
PFM/PWM mode selection. Set LOW for power save mode, set HIGH for forced PWM mode. It must not be
left floating.
C1
D2, D3
E2, E3
D1
AGND
L2
Analog ground
Connection for inductor
VOUT
FB
Power stage output
Voltage feedback sensing pin
Power good indicator, open drain output. If not used can be left floating.
E1
PG
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8 Specifications
8.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–3
MAX UNIT
VIN, L1, L2, EN, MODE, VOUT, FB, PG
6
9
V
V
Voltage(2)
L1, L2 (AC, less than 10 ns)
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground pin.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
1.3 (1)
1.8
4
NOM
MAX
5.5
UNIT
V
VI
VO
CI
L
Input voltage
Output voltage
5.2 (2)
V
Effective capacitance connected to VIN
Effective inductance
5
μF
μH
μF
µF
μF
µF
0.37
10
0.47
0.57
1.8 V ≤ VO ≤ 2.3 V
VO > 2.3 V
TPS63805/TPS63807 Effective capacitance
connected to VOUT
CO
7
8.2
27
1.8 V ≤ VO < 2.3 V
VO > 2.3 V
30
CO
TJ
TPS63806 Effective capacitance connected to VOUT
Operating junction temperature
21
Operating junction
temperature
–40
125
°C
(1) Minimum start-up voltage of VI > 1.8 V until power good
(2) VO margin for accuracy and load steps is considerd in absolut maximum ratings
8.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS6380x
THERMAL METRIC(1)
3x5 Ball WCSP
UNIT
15 PINS
78.8
0.6
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
19.5
0.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
19.5
N/A
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ= 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Minimum input voltage for full load,
once started
VIN;LOAD
IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C
2.3
11
V
TPS63805/TPS63807; TJ = 25°C, EN = VIN = 3.6 V, VOUT
3.3 V, not switching
=
IQ;VIN
Quiescent current into VIN
Quiescent current into VIN
μA
μA
TPS63806; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not
switching
IQ;VIN
ISD
13
Shutdown current into VIN
Undervoltage lockout threshold
Undervoltage lockout threshold
Thermal shutdown
EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 3.6 V, VOUT = 0 V
VIN falling, VOUT ≥ 1.8 V, once started
VIN rising
45
1.25
1.7
600
1.29
1.79
nA
V
1.2
1.6
UVLO
V
TSD
Temperature rising
150
20
°C
°C
TSD;HYST
Thermal shutdown hysteresis
SOFT-START, POWER GOOD
TPS63805/TPS63806 TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V,
IO = 3.5 A, time from first switching to power good
224
480
321
µs
µs
µs
Tramp
Soft-start, Current limit ramp time
TPS63807 TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5 A,
time from first switching to power good
Delay from EN-edge until rising
VOUT
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, Delay from EN-edge
until rising first switching
Tdelay
LOGIC SIGNALS EN, MODE
VTHR;EN Threshold Voltage rising for EN-Pin
1.07
0.97
1.2
1.1
1
1.13
1.03
V
V
Threshold Voltage falling for EN-
Pin
VTHF;EN
VIH
High-level input voltage
Low-level input voltage
V
V
VIL
0.4
VPG;rising
VPG;falling
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
95
90
%
%
Power Good threshold voltage
Power Good low-level output
voltage
VPG;Low
ISINK = 1 mA
VFB falling
0.4
0.2
V
tPG;delay
Ilkg
Power Good delay time
Input leakage current
14
µs
0.01
µA
OUTPUT
TPS63805/TPS63806 EN = low, -40°C ≤ TJ ≤ 85°C, VIN
3.6 V, VOUT = 3.3 V
=
ISD
Shutdown current into VOUT
±0.5
500
±600
nA
VFB
VFB
Feedback Regulation Voltage
Feedback Voltage accuracy
mV
%
V
PWM mode
VOUT rising
VIN rising
–1
5.5
5.5
1
5.9
5.9
5.7
5.7
Overvoltage Protection Threshold
V
Peak Inductor Current to enter
PFM-Mode
IPWM/PFM
IFB
VIN = 3.6 V; VOUT = 3.3 V
VFB = 500 mV
1.06
A
Feedback Input Bias Current
5
5
100
nA
A
Peak Current Limit, Boost Mode
4
5.75
Peak Current Limit, Buck-Boost
Mode
IPK
TPS63805/TPS63807; VIN ≥ 2.5 V
5
A
Peak Current Limit, Buck Mode
Peak Current Limit, Boost Mode
3.8
5.5
A
A
4.4
6.25
Peak Current Limit, Buck-Boost
Mode
IPK
TPS63806; VIN ≥ 2.5V
VI = 5 V, VO = 3.3 V
5.5
4
A
A
A
Peak Current Limit, Buck Mode
Peak Current Limit for Reverse
Operation
IPK;Reverse
–0.9
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VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ= 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 VIN = 3 V, VOUT = 3.3
High-side FET on-resistance
47
mΩ
A
V; IO = 0.5 A
Buck
RDS;ON
VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 VIN = 3 V, VOUT = 3.3
Low-side FET on-resistance
High-side FET on-resistance
Low-side FET on-resistance
30
43
mΩ
mΩ
A
V; IO = 0.5 A
VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 VIN = 3 V, VOUT = 3.3
A
V; IO = 0.5 A
Boost
RDS;ON
VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 VIN = 3 V, VOUT = 3.3
18
mΩ
A
V; IO = 0.5 A
Inductor Switching Frequency,
Boost Mode
VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
2.1
1.4
MHz
MHz
Inductor Switching Frequency,
Buck-Boost Mode
fSW
Inductor Switching Frequency,
Buck Mode
VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A
1.6
0.3
0.1
MHz
%
Line regulation
Load regulation
VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, forced-PWM
mode
%
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8.6 Typical Characteristics
16
20
16
12
8
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
12
8
4
4
0
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D006
D005
MODE = LOW
VO = 3.3 V
IO = 0 mA, not
switching
MODE = LOW
VO = 3.3 V
IO = 0 mA, not
switching
Figure 8-1. TPS63805/TPS63807 Quiescent Current
vs. Temperature
Figure 8-2. Quiescent Current vs. Temperature
1.4
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D004
EN = LOW
Figure 8-3. Shutdown Current vs. Temperature
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9 Detailed Description
9.1 Overview
The TPS63805, TPS63806, and TPS63807 buck-boost converter use four internal switches to maintain
synchronous power conversion at all possible operating conditions. This enables the device to keep high
efficiency over a wide input voltage and output load range. To regulate the output voltage at all possible
input voltage conditions, the device automatically transitions between buck, buck-boost, and boost operation as
required by the operating conditions. Therefore, it operates as a buck converter when the input voltage is higher
than the output voltage, and as a boost converter when the input voltage is lower than the output voltage. When
the input voltage is close to the output voltage, it operates in a 3-cycle buck-boost operation. In this mode, all
four switches are active (see Section 9.4.1.3). The RMS current through the switches and the inductor is kept at
a minimum to minimize switching and conduction losses. Controlling the switches this way allows the converter
to always keep high efficiency over the complete input voltage range. The device provides a seamless transition
between all modes.
9.2 Functional Block Diagram
L
L1
L2
VOUT
VIN
CIN
COUT
Current
Sensor
Gate
Gate
Driver
Driver
Device
Device
Control
Control
PG
VOUT
VIN
Device
Control
VMAX Switch
+
EN
Device Control
Ref
œ
+
Power Safe Mode
Protection
1.1 V
FB
+
œ
VIN
Ref
500 mV
Current Limit
œ
Buck/Boost Control
Off-time calculation
Soft-Start
Gate
Driver
MODE
GND
Power
Good
VOUT
AGND
L1, L2
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9.3 Feature Description
9.3.1 Control Loop Description
The TPS63805, TPS63806, and TPS63807 use a peak current mode control architecture. It has an inner current
loop where it measures the peak current of the boost high-side MOSFET and compares it to a reference current.
This current is the output of the outer voltage loop. It measures the output voltage via the FB-pin and compares
it with the internal voltage reference. That means, the outer voltage loop measures the voltage error (VREF-VFB),
and transforms it into the system current demand (IREF) for the inner current loop.
Figure 9-1 shows the simplified schematic of the control loop. The error amplifier and the type-2 compensation
represent the voltage loop. The voltage output is converted into the reference current IREF and fed into the
current comparator.
The scheme shows the skip-comparator handling the power-save mode (PFM) to achieve high efficiency at light
loads. See Section 9.4.2 for further details.
VIN
L1
IPK
œ
Gate
Driver
IREF
+
FB
VEA
+
Ref
500mV
œ
+
œ
ISKIP
Figure 9-1. Control Loop Architecture Scheme
9.3.2 Precise Device Enable: Threshold- or Delayed Enable
The enable-pin is a digital input to enable or disable the device by applying a high or low level. The device
enters shutdown when EN is set low. In addition, this input features a precise threshold and can be used as a
comparator that enables and disables the part at a defined threshold. This allows you to drive the state by a
slowly changing voltage and enables the use of an external RC network to achieve a precise power-up delay.
The enable pin can also be used with an external voltage divider to set a user-defined minimum supply voltage.
For proper operation, the EN pin must be terminated and must not be left floating.
VTHRESHOLD
VDELAY
R4
R5
R4
C5
EN
EN
Figure 9-2. Circuit Example for How to Use the Precise Device Enable Feature
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9.3.3 Mode Selection (PFM/PWM)
The mode-pin is a digital input to enable the automatic PWM/PFM mode that features the highest efficiency by
allowing pulse-frequency-modulation for lower output currents. This mode is enabled by applying a low level.
The device can be forced in PWM operation regardless of the output current to achieve minimum output ripple
by applying a high level. This pin must not be left floating.
9.3.4 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. It activates the
device once the input voltage (VI) has increased the UVLOrising value. Once active, the device allows operation
down to even smaller input voltages, which is determined by the UVLOfalling. This behavior requires VO to be
higher than the minimum value of 1.8 V.
UVLOrising
UVLOfalling
VIN
Device
active
Figure 9-3. Rising and Falling Undervoltage Lockout Behavior
9.3.5 Soft Start
To minimize inrush current and output voltage overshoot during start-up, the device features a controlled soft
start-up. After the device is enabled, the device starts all internal reference and control circuits within the enable
delay time, Tdelay. After that, the maximum switch current limit rises monotonically from 0 mA to the current limit.
The loop stops switching once VO is reached. This allows a quick output voltage ramp for small capacitors at
the output. The bigger the output capacitor, the longer it takes to settle Vo. A potential load during start-up will
lengthen the duration of the output voltage ramp as well. The gradual ramp of the current limit allows a small
inrush current for no-load conditions, as well as the possibility to start into high loads at start-up.
VIN
EN
Current Limit
Inductor
Current
0.95 x VOUT
VOUT
Power Good
Tdelay
Tramp
TStart-up
Figure 9-4. Device Start-up Scheme
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9.3.6 Adjustable Output Voltage
The device's output voltage is adjusted by applying an external resistive divider between VO, the FB-pin, and
GND. This allows you to program the output voltage in the recommended range. The divider must provide a
low-side resistor of less than 100 kΩ. The high-side resistor is chosen accordingly.
9.3.7 Overtemperature Protection - Thermal Shutdown
The device has a built-in temperature sensor which monitors the junction temperature. If the temperature
exceeds the threshold, the device stops operating. As soon as the IC temperature has decreased below the
programmed threshold, it starts operating again. There is a built-in hysteresis to avoid unstable operation at
junction temperatures at the overtemperature threshold.
9.3.8 Input Overvoltage - Reverse-Boost Protection (IVP)
The TPS63805, TPS63806, and TPS63807 can operate in reverse mode where the device transfers energy from
the output back to the input. If the source is not able to sink the revers current, the negative current builds up a
charge to the input capacitance and VIN rises. To protect the device and other components from that scenario,
the device features an input voltage protection (IVP) for reverse boost operation. Once the input voltage is above
the threshold, the converter forces PFM mode and the negative current operation is interrupted.
The PG signal goes low to indicate that behavior.
9.3.9 Output Overvoltage Protection (OVP)
In case of a broken feedback-path connection, the device can loose VO information and is not able to regulate.
To avoid an uncontrolled boosting of VO, the TPS63805, TPS63806, and TPS63807 feature output overvoltage
protection. It measures the voltage on the VOUT pin and stops switching when VO is greater than the threshold
to avoid harm to the converter and other components.
9.3.10 Power-Good Indicator
The power good goes high-impedance once the output is above 95% of the nominal voltage, and is driven low
once the output voltage falls below typically 90% of the nominal voltage. This feature also indicates overvoltage
and device shutdown cases as shown in Table 9-1. The PG pin is an open-drain output and is specified to sink
up to 1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The
PG signal can be used to sequence multiple rails by connecting it to the EN pin of other converters. Leave the
PG pin unconnected when not used.
Table 9-1. Power-Good Indicator Truth Table
LOGIC SIGNALS
PG LOGIC STATUS
EN
X
VO
VI
OVP
X
IVP
X
< 1.8 V
< UVLO_R
> UVLO_F
> 1.3V
Undefined
LOW
LOW
HIGH
HIGH
HIGH
HIGH
X
X
X
VO < 0.9 × target-VO
X
X
LOW
X
> UVLO_F
> UVLO_F
> UVLO_F
HIGH
X
X
LOW
X
HIGH
LOW
LOW
VO > 0.95 × target-VO
LOW
HIGH Z
9.4 Device Functional Modes
9.4.1 Peak-Current Mode Architecture
The TPS63805, TPS63806, and TPS63807 are based on a peak-current mode architecture. The error amplifier
provides a peak-current target (voltage that is translated into an equivalent current, see Figure 9-1), based on
the current demand from the voltage loop. This target is compared to the actual inductor current during the
ON-time. The ON-time is ended once the inductor current is equal to the current target and OFF-time is initiated.
The OFF-time is calculated by the control and a function of VI and VO.
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IPEAK
VEAmp
IIND
IPK-PK
TON
TOFF
0
Figure 9-5. Peak-Current Architecture Operation
9.4.1.1 Reverse Current Operation, Negative Current
When the TPS63805, TPS63806, and TPS63807 are forced to PWM operation (MODE = HIGH), the device
current can flow in reverse direction. This happens by the negative current capability of the TPS63805,
TPS63806, and TPS63807. The error amplifier provides a peak-current target (voltage that is translated into
an equivalent current, see Figure 9-1), even if the target has a negative value. The maximum average current is
even more negative than the peak current.
time
0
IPEAK
VEAmp
IAVG
IIND
IPK-PK
Figure 9-6. Peak-Current Operation, Reverse Current
9.4.1.2 Boost Operation
When VI is smaller than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63805, TPS63806, and TPS63807 operate in boost mode where the boost high-side and low-side switches
are active. The buck high-side switch is always turned on and the buck low-side switch is always turned off. This
lets the TPS63805, TPS63806, and TPS63807 operate as a classical boost converter.
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IPEAK
VEAmp
IIND
TON
TOFF
Figure 9-7. Peak-Current Boost Operation
9.4.1.3 Buck-Boost Operation
When VI is close to VO, the TPS63805, TPS63806, and TPS63807 operate in buck-boost mode where all
switches are active and the device repeats 3-cycles:
•
•
•
TON: Boost-charge phase where boost low-side and buck high-side are closed and the inductor current is built
up
TOFF: Buck discharge phase where boost high-side and buck low-side are closed and the inductor is
discharged
TCOM: VI connected to VO where all high-side switches are closed and the input is connected to the output
IPEAK
VEAmp
IIND
TON
TCOM
TOFF
TCOM
Figure 9-8. Peak-Current Buck-Boost Operation
9.4.1.4 Buck Operation
When VI is greater than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63805, TPS63806, and TPS63807 operate in buck mode where the buck high-side and low-side switches
are active. The boost high-side switch is always turned on and the boost low-side switch is always turned off.
This lets the TPS63805, TPS63806, and TPS63807 operate as a classical buck converter.
IPEAK
VEAmp
IIND
TON
TOFF
Figure 9-9. Peak-Current Buck Operation
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9.4.2 Power Save Mode Operation
Besides continuos conduction mode (PWM), the TPS63805, TPS63806, and TPS63807 feature power safe
mode (PFM) operation to achieve high efficiency at light load currents. This is implemented by pausing the
switching operation, depending on the load current.
The skip comparator manages the switching or pause operation. It compares the current demand signal from the
voltage loop, IREF, with the skip threshold, ISKIP, as shown in Figure 9-1. If the current demand is lower than the
skip value, the comparator pauses switching operation. If the current demand goes higher (due to falling VO), the
comparator activates the current loop and allows switching according to the loop behavior. Whenever the current
loop has risen VO by bringing charge to the output, the voltage loop output, IREF (respectively VEA), decreases.
When IREF falls below ISKIP-hysteresis, it automatically pauses again.
ICOIL
VO
ISKIP
VEA
Hysteresis
/ IREF
SKIP
Yes/No
Pause
Switching
Figure 9-10. Power Safe Mode Operation Curves
9.4.2.1 Current Limit Operation
To limit current and protect the device and application, the maximum peak inductor current is limited internally
on the IC. It is measured at the buck high-side switch which turns into an input current detection. To provide a
certain load current across all operation modes, the boost and buck-boost peak current limit is higher than in
buck mode. It limits the input current and allows no further increase of the delivered current. When using the
device in this mode, it behaves similar to a current source.
The current limit depends on the operation mode (buck, buck-boost, or boost mode).
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TPS63805, TPS63806, and TPS63807 are high efficiency, low quiescent current, non-inverting buck-boost
converters, suitable for applications that need a regulated output voltage from an input supply that can be higher
or lower than the output voltage.
10.2 Typical Application
L1
0.47µH
VIN
L1
L2
VIN
1.3V t 5.5V
VOUT = 3.3V
VIN
EN
VOUT
R3
100kQ
C2
C1
10 …F
22 …F
PG
FB
R1
511kQ
MODE
GND
R2
91kQ
AGND
TPS63805
Figure 10-1. TPS63805/TPS63807 3.3 VOUT Typical Application
L1
0.47µH
VIN
L1
L2
VIN
1.3V t 5.5V
VOUT = 3.3V
VIN
EN
VOUT
R3
100lQ
C2
C2
C1
10 …F
47 …F
47 …F
PG
FB
R1
511lQ
MODE
GND
R2
91lQ
AGND
TPS63806
Figure 10-2. TPS63806 3.3 VOUT Typical Application
10.2.1 Design Requirements
The design guideline provides a component selection to operate the device within Table 10-1.
Table 10-1 shows the list of components for the application characteristic curves.
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Table 10-1. Matrix of Output Capacitor and Inductor Combinations for the TPS63805/TPS63807
NOMINAL
INDUCTOR VALUE
[µH](1)
NOMINAL OUTPUT CAPACITOR VALUE [µF](2)
10
22
47
66
100
(3)
0.47
-
+
+
+
+
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(2) Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
(3) TPS63805/TPS63807 typical application. Other check marks indicate possible filter combinations.
Table 10-2. Matrix of Output Capacitor and Inductor Combinations for TPS63806
NOMINAL
INDUCTOR VALUE
[µH](1)
NOMINAL OUTPUT CAPACITOR VALUE [µF](2)
10
22
47
66
100
(1)
0.47
-
-
+
+
+
(1) TPS63806 typical application. Other check marks indicate possible filter combinations.
10.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, Section 8.1 outlines
minimum and maximum values for inductance and capacitance. Take tolerance and derating into account when
selecting nominal inductance and capacitance.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63805/TPS63807 device with the WEBENCH® Power
Designer. Click here to create a custom design using the TPS63806 device with the WEBENCH® Power
Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as the following:
•
•
•
•
Inductor ripple current
Output voltage ripple
Transition point into power save mode
Efficiency
See Table 10-3 for typical inductors.
For high efficiencies, the inductor must have a low DC resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced, mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady-state operation is calculated using Equation 2. Only the equation which defines the switch
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current in boost mode is shown because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
V
- V
IN
OUT
V
Duty Cycle Boost
D =
OUT
(1)
(2)
Iout
η ´ (1 - D)
Vin ´ D
IPEAK
=
+
2 ´ f ´ L
where
•
•
•
•
D = Duty Cycle in Boost mode
f = Converter switching frequency
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption)
Note
The calculation must be done for the minimum input voltage in boost mode.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated using Equation 2. Table 10-3 lists the possible inductors.
Table 10-3. List of Recommended Inductors
INDUCTOR
VALUE [µH]
SATURATION CURRENT
[A]
DCR [mΩ]
PART NUMBER
MANUFACTURER(1) SIZE (LxWxH mm)
0.47
0.47
5.4
5.5
7.6
26
XFL4015-471ME
DFE201612E
Coilcraft
Toko
4 x 4 x 2
2.0 x 1.6 x 1.2
(1) See Third-party Products Disclaimer.
10.2.2.3 Output Capacitor Selection
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and PGND pins of the IC. The recommended nominal output capacitor value is a single 22 µF for the
TPS63805/TPS63807 and 2x47 µF for the TPS63806 for all programmed output voltages ≤ 3.6 V. Above that
voltage, 2x22 µF for the TPS63805/TPS63807 and 3x47 µF for the TPS63806 capacitors are recommended.
It is important that the effective capacitance is given according to the recommended value in Section 8.3. In
general, consider DC bias effects resulting in less effective capacitance. The choice of the output capacitance
is mainly a trade-off between size and transient behavior since higher capacitance reduces transient response
overshoot and undershoot and increases transient response time. Table 10-4 lists possible output capacitors.
There is no upper limit for the output capacitance value.
Table 10-4. List of Recommended Capacitors(1)
CAPACITOR
[µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER
22
22
22
22
47
47
6.3
6.3
10
10
10
40
10
43
43
GRM188R60J226MEA0
GRM187R61A226ME15
GRM188R61A226ME15
GRM187R60J226ME15
GRM188R60J476ME15
GRM219R60J476ME44
Murata
Murata
Murata
Murata
Murata
Murata
0603 (1608)
0603 (1608)
0603 (1608)
0603 (1608)
0603 (1608)
0805 (2012)
10
6.3
6.3
(1) See Third-party Products Disclaimer.
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10.2.2.4 Input Capacitor Selection
A 10 µF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior
of the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN
and PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply
is located more than a few inches from the TPS63805, TPS63806, and TPS63807 converter, additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 µF is a typical choice.
Table 10-5. List of Recommended Capacitors(1)
CAPACITOR
[µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER
10
10
22
6.3
10
10
40
10
GRM188R60J106ME84
GRM188R61A106ME69
GRM188R60J226MEA0
Murata
Murata
Murata
0603 (1608)
0603 (1608)
0603 (1608)
6.3
10.2.2.5 Setting The Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is 500 mV nominal. The low-side resistor R2 (between FB and GND) must
not exceed 100 kΩ. The high-side resistor (between FB and VOUT) R1 is calculated by Equation 3.
æ
ç
è
ö
VOUT
VFB
R1 = R2 ×
- 1
÷
ø
(3)
where
VFB = 500 mV
•
Table 10-6. Resistor Selection for Typ. Voltages
VO [V]
R1 [kΩ]
R2 [kΩ]
91
2.5
3.3
3.6
5
365
511
562
806
91
91
91
10.2.3 Application Curves
Table 10-7. Components for Application Characteristic Curves (1)
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER COMMENT
0.47µH, 4 mm x 4 mm x 1.5 mm, 5.4 A,
7.6 mΩ
L1
XFL4015-471ME
Coilcraft
10 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
C1
C2
C2
C2
C2
GRM188R60J106ME84
GRM188R61A226ME15
GRM188R60J476ME15
GRM188R61A226ME15
GRM188R60J476ME15
Murata
TPS63805 1x 22 µF, 0603, Ceramic
Capacitor, ±20%, 10 V
TPS63805/TPS63807, VO
≤ 3.6 V
Murata
Murata
Murata
Murata
TPS63806 2x 47 µF, 0603, Ceramic
Capacitor, ±20%, 6.3 V
TPS63806, VO ≤ 3.6 V
TPS63805 2x 22 µF, 0603, Ceramic
Capacitor, ±20%, 10 V
TPS63805/TPS63807, VO
> 3.6 V
TPS63806 3x 47 µF, 0603, Ceramic
Capacitor, ±20%, 6.3 V
TPS63806, VO > 3.6 V
R1
R1
R1
R2
511 kΩ, 0603 Resistor, 1%, 100 mW
562 kΩ, 0603 Resistor, 1%, 100 mW
806 kΩ, 0603 Resistor, 1%, 100 mW
91 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
VO = 3.3 V
VO = 3.6 V
VO = 5 V
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Table 10-7. Components for Application Characteristic Curves (1) (continued)
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER COMMENT
R3
100 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
(1) See Third-party Products Disclaimer.
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Table 10-8. Typical Characteristics Curves
PARAMETER
Output Current Capability
CONDITIONS
FIGURE
Typical Output Current Capability versus Input Voltage
Typical Output Current Capability versus Input Voltage
Switching Frequency (TPS63805, TPS63806,TPS63807)
VO = 3.3 V, TPS63805/TPS63807
VO = 3.3 V, TPS63806
Figure 10-3
Figure 10-4
Typical Inductor Switching Frequency versus Input
Voltage
IO = 0 A, MODE = High
VO = 3.3 V
Figure 10-5
Figure 10-6
Typical Inductor Burst Frequency versus Output Current
Efficiency (TPS63805/TPS63807)
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus. Input Voltage (PFM/PWM)
Efficiency versus Input Voltage (PWM only)
Efficiency (TPS63806)
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE = Low
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE = High
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = Low
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
Figure 10-7
Figure 10-8
Figure 10-9
Figure 10-10
Figure 10-11
Figure 10-12
IO = 1 A, MODE = High
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus Input Voltage (PFM/PWM)
Efficiency versus Input Voltage (PWM only)
Regulation Accuracy (TPS63805/TPS63807)
Load Regulation, PWM Operation
VI = 2.5 V to 4.2, VO = 3.3 V, MODE = Low
VI = 2.5 V to 4.2 , VO = 3.3 V, MODE = High
VI = 1.8 V to 5, VO = 3.3 V, MODE = Low
VI = 2.5 V to 5, VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
Figure 10-13
Figure 10-14
Figure 10-15
Figure 10-18
Figure 10-17
Figure 10-18
IO = 1 A, MODE = High
VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
IO = 1 A, MODE = High
IO = 1 A, MODE = Low
Figure 10-19
Figure 10-20
Figure 10-21
Figure 10-22
Load Regulation, PFM/PWM Operation
Line Regulation, PWM Operation
Line Regulation, PFM/PWM Operation
Regulation Accuracy (TPS63806)
Load Regulation, PWM Operation
VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
IO = 1 A, MODE = High
IO = 1 A, MODE = Low
Figure 10-23
Figure 10-24
Figure 10-25
Figure 10-26
Load Regulation, PFM/PWM Operation
Line Regulation, PWM Operation
Line Regulation, PFM/PWM Operation
Switching Waveforms (TPS63805, TPS63806,TPS63807)
Switching Waveforms, PFM Boost Operation
Switching Waveforms, PFM Buck-Boost Operation
Switching Waveforms, PFM Buck Operation
Switching Waveforms, PWM Boost Operation
Switching Waveforms, PWM Buck-Boost Operation
Switching Waveforms, PWM Buck Operation
Transient Performance (TPS63805/TPS63807)
VI = 2.3 V, VO = 3.3 V, MODE = Low
VI = 3.3 V, VO = 3.3 V, MODE = Low
VI = 4.3 V, VO = 3.3 V, MODE = Low
VI = 2.3 V, VO = 3.3 V, MODE = High
VI = 3.3 V, VO = 3.3 V, MODE = High
VI = 4.3 V, VO = 3.3 V, MODE = High
Figure 10-27
Figure 10-28
Figure 10-29
Figure 10-30
Figure 10-31
Figure 10-32
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
Low
Load Transient, PFM/PWM Boost Operation
Load Transient, PFM/PWM Buck-Boost Operation
Load Transient, PFM/PWM Buck Operation
Load Transient, PWM Boost Operation
Figure 10-33
Figure 10-34
Figure 10-35
Figure 10-36
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
Low
VI = 4.2 V, VO = 3.3V, Load = 100 mA to 1A, MODE =
Low
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
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Table 10-8. Typical Characteristics Curves (continued)
PARAMETER
CONDITIONS
FIGURE
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
Load Transient, PWM Buck-Boost Operation
Load Transient, PWM Buck Operation
Line Transient, PWM Operation
Figure 10-37
VI = 4.2 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
Figure 10-38
Figure 10-39
Figure 10-40
Figure 10-41
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A , MODE =
Low
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
Line Transient, PWM Operation
Transient Performance (TPS63806)
Load Transient, PFM/PWM Boost Operation
VI = 2.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
Low
Figure 10-42
Figure 10-43
Figure 10-44
Figure 10-45
Figure 10-46
Figure 10-47
Figure 10-48
Figure 10-49
Figure 10-50
VI = 3.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
Low
Load Transient, PFM/PWM Buck-Boost Operation
Load Transient, PFM/PWM Buck Operation
Load Transient, PWM Boost Operation
Load Transient, PWM Buck-Boost Operation
Load Transient, PWM Buck Operation
Line Transient, PWM Operation
VI = 4.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
Low
VI = 2.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
High
VI = 3.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
High
VI = 4.3 V, VO = 3.3 V, Load = 25% to 75%, MODE =
High
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A , MODE =
Low
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
Line Transient, PWM Operation
VI = 2.8 V, VO = 3.3 V, Load = 50 mA to 5 A, with
1 MHz and 50% duty cycle, tr = 120 ns, tf = 60 ns,
MODE = High
Pulsed load, PWM Operation
Pulsed load, PWM Operation
Pulsed load, PWM Operation
Figure 10-51
Figure 10-52
Figure 10-53
VI = 3.3 V, VO = 3.3 V, Load = 50 mA to 5 A, with
1 MHz and 50% duty cycle, tr = 120 ns, tf = 60 ns,
MODE = High
VI = 4.2 V, VO = 3.3 V, Load = 50 mA to 5 A, with 1
MHz and 50% duty cycle, tr = 120 ns tf = 60 ns, MODE
= High
Start-up (TPS63805, TPS63806,TPS63807)
Start-up Behavior from Rising Enable, PFM Operation
Start-up Behavior from Rising Enable, PWM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA, MODE = Low
VI = 2.2 V, VO = 3.3 V, Load = 10 mA, MODE = High
Figure 10-54
Figure 10-55
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4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VO = 3.3 V
VO = 3.6 V
VO = 5 V
VO = 3.3 V
VO = 3.6 V
VO = 5 V
1.3
1.8
2.3
2.8
3.3
Input Voltage (V)
3.8
4.3
4.8
5.3
1.3
1.8
2.3
2.8
3.3
Input Voltage (V)
3.8
4.3
4.8
5.3
D002
D003
MODE = High
TPS63805
MODE = High
TPS63806
Figure 10-3. Typical Output Current Capability
versus Input Voltage
Figure 10-4. Typical Output Current Capability
versus Input Voltage
3.0
2.5
2.0
1.5
1M
100k
10k
VI = 2.5 V
VI = 3.6 V
VI = 4.8 V
1.0
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
1k
1m
0.5
2.5
10m
100m
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
Output Current (A)
D018
D007
VO = 3.6 V
MODE = Low
I O = 0 A
MODE = High
VI rising
Figure 10-6. Typical Inductor Burst Frequency
versus Output Current
Figure 10-5. Typical Inductor Switching Frequency
versus Input Voltage
100
100
90
80
70
60
50
40
30
90
80
70
20
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
10
0
60
100m
1m
10m
Output Current (A)
100m
1
2
1m
10m
100m
Output Current (A)
1
2
D019
D020
VO = 3.3 V
MODE = Low
TPS63805
VO = 3.3 V
MODE = High
TPS63805
Figure 10-7. Efficiency versus Output Current
(PFM/PWM)
Figure 10-8. Efficiency versus Output Current
(PWM Only)
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100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
1m
10m
100m
Output Current (A)
1
2
100m
1m
10m
Output Current (A)
100m
1
2
D022
D021
VO = 3.3 V
MODE = High
TPS63805
VO = 3.3 V
MODE = Low
TPS63805
Figure 10-10. Efficiency versus Input Voltage (PWM
Only)
Figure 10-9. Efficiency versus Output Current
(PFM/PWM)
100
100
90
90
80
80
70
IO = 100 mA
IO = 10 mA
IO = 100 mA
IO = 1 A
IO = 1.5 A
70
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
60
50
60
2.5
2.9
3.3
Input Voltage (V)
3.7
4.1
1.8
2.3
2.8
3.3 3.8
Input Voltage (V)
4.3
4.8
5.3
D023
D024
VO = 3.3 V
MODE = Low
TPS63805
IO = 1 A
MODE = Low
TPS63805
Figure 10-11. Efficiency versus Input Voltage (PFM/ Figure 10-12. Efficiency versus Input Voltage (PWM
PWM)
Only)
100
90
80
70
60
100
90
80
70
60
50
40
30
20
10
0
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
100m
1m
10m 100m
Output Current (A)
1
2.5
1m
10m
100m
Output Current (A)
1
2.5
D008
D013
VO = 3.3 V
MODE = High
TPS63806
VO = 3.3 V
MODE = Low
TPS63806
Figure 10-13. Efficiency versus Output Current
(PFM/PWM)
Figure 10-14. Efficiency versus Output Current
(PWM Only)
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100
90
80
70
60
100
90
80
70
60
50
40
30
20
10
0
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
100m
1m
10m 100m
Output Current (A)
1
2.5
1m
10m
100m
Output Current (A)
1
2.5
D009
D010
VO = 3.3 V
MODE = High
TPS63806
VO = 3.3 V
MODE = Low
TPS63806
Figure 10-15. Efficiency versus Output Current
(PFM/PWM)
Figure 10-16. Efficiency versus Input Voltage (PWM
Only)
100
100
90
90
80
80
70
IO = 100 mA
IO = 10 mA
IO = 100 mA
IO = 1 A
IO = 2 A
70
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
60
60
50
1.8
2.3
2.8
3.3 3.8
Input Voltage (V)
4.3
4.8
5.3
2.5
2.9
3.3
Input Voltage (V)
3.7
4.1
D012
D011
IO = 1 A
MODE = Low
TPS63806
VO = 3.3 V
MODE = High
TPS63806
Figure 10-18. Efficiency versus Input Voltage (PWM
Only)
Figure 10-17. Efficiency versus Input Voltage (PFM/
PWM)
0.2
1.5
1.0
0.5
0.0
0.1
0.0
-0.1
-0.5
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
-0.2
-0.3
-1.0
-1.5
0
0.5
1.0
Output Current (A)
1.5
2.0
0.5
1.0
Output Current (A)
1.5
2.0
D026
D027
VO = 3.3 V
MODE = High
TPS63805
VO = 3.3 V
MODE = Low
TPS63805
Figure 10-19. Load Regulation (PWM Only)
Figure 10-20. Load Regulation (PFM/PWM)
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0.3
0.2
0.1
0.2
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
D028
D029
IO = 1 A
MODE = Low
TPS63805
IO = 1 A
MODE = High
TPS63805
Figure 10-21. Line Regulation (PWM Only)
Figure 10-22. Line Regulation (PFM/PWM)
0.2
0.2
0.1
0.0
0.1
0.0
-0.1
-0.1
-0.2
-0.2
VI = 2.8 V
VI = 3.6 V
VI = 4.2 V
VI = 2.8 V
VI = 3.6 V
VI = 4.2 V
-0.3
-0.3
-0.4
-0.4
0
0.5
1.0 1.5
Output Current (A)
2.0
2.5
0
0.5
1.0 1.5
Output Current (A)
2.0 2.5
D014
D015
VO = 3.3 V
MODE = High
TPS63806
VO = 3.3 V
MODE = Low
TPS63806
Figure 10-23. Load Regulation (PWM Only)
Figure 10-24. Load Regulation (PFM/PWM)
0.2
0.2
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.1
0.0
0.1
0.0
-0.1
-0.1
-0.2
-0.2
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
D016
D017
IO = 1 A
MODE = Low
TPS63806
IO = 1 A
MODE = High
TPS63806
Figure 10-25. Line Regulation (PWM Only)
Figure 10-26. Line Regulation (PFM/PWM)
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VI = 2.3 V, VO = 3.3
MODE = Low
V
VI = 3.3 V, VO = 3.3
V
IO = 40 mA
MODE = Low
IO = 40 mA
Figure 10-27. Switching Waveforms, PFM Boost
Operation
Figure 10-28. Switching Waveforms, PFM Buck-
Boost Operation
VI = 4.2 V, VO = 3.3 V
MODE = Low
IO = 40 mA
VI = 2.3 V, VO = 3.3
MODE = Low
IO = 2 A
V
Figure 10-29. Switching Waveforms, PFM Buck
Operation
Figure 10-30. Switching Waveforms, PWM Boost
Operation
VI = 4.2 V, VO = 3.3
VI = 3.3 V, VO = 3.3
MODE = Low
IO = 2 A
MODE = Low
IO = 2 A
V
V
Figure 10-32. Switching Waveforms, PWM Buck
Operation
Figure 10-31. Switching Waveforms, PWM Buck-
Boost Operation
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IO from 100 mA
TPS63805
IO from 100 mA to
1 A tr = 1 µs, tf = 1
µs
VI = 2.5 V, VO = 3.3
TPS63805 MODE =
Low
VI = 3.3 V, VO = 3.3 V to 1 A tr = 1 µs, tf
MODE = Low
V
= 1 µs
Figure 10-34. Load Transient, PFM/PWM Buck-
Boost Operation
Figure 10-33. Load Transient, PFM/PWM Boost
Operation
IO from 100 mA
TPS63805
IO from 100 mA
TPS63805
VI = 5 V, VO = 3.3 V
to 1 A tr = 1 µs, tf
= 1 µs
VI = 2.5 V, VO = 3.3 V to 1 A tr = 1 µs, tf
MODE = Low
MODE = High
= 1 µs
Figure 10-35. Load Transient, PFM/PWM Buck
Operation
Figure 10-36. Load Transient, PWM Boost
Operation
IO from 100 mA
IO from 100 mA
TPS63805 MODE =
TPS63805
VI = 5 V, VO = 3.3 V to 1 A tr = 1 µs, tf
VI = 3.3 V, VO = 3.3 V to 1 A tr = 1 µs, tf
High
MODE = High
= 1 µs
= 1 µs
Figure 10-38. Load Transient, PWM Buck Operation
Figure 10-37. Load Transient, PWM Buck-Boost
Operation
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VI from 2.2 V to
VI from 2.2 V to
4.2 V tr = 1 µs, tf
= 1 µs
TPS63805
TPS63805
MODE = High
IO = 0.5 A
4.2 V tr =1 µs, tf =
1 µs
IO = 1 A
MODE = High
Figure 10-39. Line Transient, PWM Operation
Figure 10-40. Line Transient, PWM Operation
VI from 3 V to 3.6
TPS63805
IO from 100 mA
VI = 2.8 V, VO = 3.3
V
TPS63806 MODE =
Low
IO = 0.5 A
V tr = 1 µs, tf = 1
µs
to 2 A tr = 1 µs, tf
= 1 µs
MODE = High
Figure 10-41. Line Transient, PWM Operation
Figure 10-42. Load Transient, PFM/PWM Boost
Operation
IO from 100 mA
VI = 4.2 V, VO = 3.3 V
IO from 100 mA
to 2 A tr = 1 µs, tf
= 1 µs
TPS63806
VI = 3.3 V, VO = 3.3
V
TPS63806 MODE =
Low
to 2 A tr = 1 µs, tf
= 1 µs
MODE = Low
Figure 10-43. Load Transient, PFM/PWM Buck-
Boost Operation
Figure 10-44. Load Transient, PFM/PWM Buck
Operation
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IO 100 mA to 2 A
tr = tf = 1 µs
TPS63806
VI = 2.8 V, VO = 3.3 V
IO from 100 mA
to 2 A tr = 1 µs, tf
= 1 µs
TPS63806
VI = 3.3 V, VO = 3.3 V
MODE = High
MODE = High
Figure 10-46. Load Transient, PWM Buck-Boost
Operation
Figure 10-45. Load Transient, PWM Boost
Operation
VI = 4.2 V, VO = 3.3 IO 100 mA to 2 A TPS63806 MODE =
VI 2.2 V to 4.2 V
tr = tf = 1 µs
TPS63806
IO = 1 A
V
tr = tf = 1 µs
High
MODE = High
Figure 10-47. Load Transient, PWM Buck Operation
Figure 10-48. Line Transient, PWM Operation
VI 2.2 V to 4.2 V
tr = tf = 1 µs
TPS63806
VI 3.0 V to 3.6 V
tr = tf = 1 µs
TPS63806
IO = 2 A
IO = 1 A
MODE = High
MODE = High
Figure 10-49. Line Transient, PWM Operation
Figure 10-50. Line Transient, PWM Operation
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IO 50 mA to 5 A
VI = 3.3 V, VO = 3.3 V
IO 50 mA to 5 A
with 1 MHz and
50% duty cycle tr
= 120 ns, tf = 60
ns
TPS63806
MODE = High
with 1 MHz and
TPS63806
VI = 2.8 V, VO = 3.3 V 50% duty cycle tr
MODE = High
= 120 ns, tf = 60
ns
Figure 10-51. Pulsed Load, PWM Operation
Figure 10-52. Pulsed Load, PWM Operation
IO 50 mA to 5 A
VI = 4.2 V, VO = 3.3
V
100 mΩ resistive
load
MODE = Low
with 1 MHz and
TPS63806
VI = 4.2 V, VO = 3.3 V 50% duty cycle tr
MODE = High
Figure 10-54. Start-up Behavior from Rising
Enable, PFM Operation
= 120 ns, tf = 60
ns
Figure 10-53. Pulsed Load, PWM Operation
VI = 4.2 V, VO = 3.3 V
MODE = High
100 mΩ resistive load
Figure 10-55. Start-up Behavior from Rising Enable, PWM Operation
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11 Power Supply Recommendations
The TPS63805, TPS63806, and TPS63807 device families have no special requirements for its input power
supply. The input power supply output current needs to be rated according to the supply voltage, output voltage,
and output current of the TPS63805, TPS63806, and TPS63807.
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12 Layout
12.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS63805, TPS63806, and
TPS63807 device.
1. Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route
wide and direct traces to the input and output capacitor results in low trace resistance and low parasitic
inductance.
2. Use a common ground node for power ground and a different one for control ground to minimize the effects
of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
3. Use separate traces for the supply voltage of the power stage and the supply voltage of the analog stage.
4. The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.
12.2 Layout Example
Figure 12-1. TPS63805, TPS63806, and TPS63807 Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
QFN/SON Package FAQs
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63805/TPS63807 device with the WEBENCH® Power
Designer. Click here to create a custom design using the TPS63806 device with the WEBENCH® Power
Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS63805YFFR
TPS63805YFFT
TPS63806YFFR
TPS63807YFFR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
15
15
15
15
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS63805
SNAGCU
SNAGCU
SNAGCU
TPS63805
TPS63806
TPS63807
3000 RoHS & Green
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS63805YFFR
TPS63805YFFT
TPS63806YFFR
TPS63807YFFR
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
15
15
15
15
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
1.5
1.5
1.5
1.5
2.42
2.42
2.42
2.42
0.75
0.75
0.75
0.75
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS63805YFFR
TPS63805YFFT
TPS63806YFFR
TPS63807YFFR
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
15
15
15
15
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
3000
3000
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0015
DSBGA - 0.625 mm max height
S
C
A
L
E
6
.
0
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.8 TYP
SYMM
E
D
C
1.6
D: Max = 2.285 mm, Min =2.225 mm
E: Max = 1.374 mm, Min =1.314 mm
TYP
SYMM
B
A
0.4 TYP
0.3
3
1
2
15X
0.2
0.015
C A B
0.4
TYP
4219378/B 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
15X ( 0.23)
(0.4) TYP
2
3
1
A
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219378/B 05/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
3
15X ( 0.25)
1
2
A
B
(0.4) TYP
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219378/B 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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