TPS63802DLAT [TI]
采用 QFN/DFN 封装的 2A 高效 11µA 静态电流降压/升压转换器 | DLA | 10 | -40 to 125;
| 型号： | TPS63802DLAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 QFN/DFN 封装的 2A 高效 11µA 静态电流降压/升压转换器 | DLA | 10 | -40 to 125 升压转换器 开关 光电二极管 输出元件 |
| 文件： | 总38页 (文件大小：2938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS63802
ZHCSJ11D –NOVEMBER 2018 –REVISED JANUARY 2021
采用DFN 封装的TPS63802 2A、高效率、低IQ 降压/升压转换器
1 特性
2 应用
• 输入电压范围：1.3V 至5.5V
• 系统前置稳压器（跟踪和远程信息处理、便携式
POS、家庭自动化、IP 网络摄像头）
• 负载点调节（有线传感器、端口/电缆适配器和加密
狗、电子智能锁、物联网）
• 蓄电池备用电源（电表、数据集中器、电能质量监
测仪）
– 器件启动时输入电压大于1.8V
• 输出电压范围：1.8V 至5.2V（可调节）
• VI ≥2.3V、VO = 3.3V 时，输出电流为2A
• 在整个负载范围内具有高效率
– 11µA 工作静态电流
• 热电器件电源（TEC、光纤模块）
• 通用电压稳定器和转换器
– 具有省电模式和强制PWM 模式
• 峰值电流降压/升压模式架构
– 可在降压、降压/升压和升压操作模式之间定义
切换点
– 正向和反向电流运行
– 启动至预偏置输出
3 说明
TPS63802 是一款高效率、高输出电流降压/升压转换
器。根据输入电压不同，当输入电压近似等于输出电压
时，它会自动以升压、降压或全新的 4 周期降压/升压
模式运行。在定义的阈值内进行模式切换，避免不必要
的模式内切换，以减少输出电压纹波。这类器件的输出
电压可在较宽输出电压范围内通过电阻式分压器进行单
独调整。静态电流为11μA，可在超小甚至空载条件下
实现出色效率。
• 安全、可靠运行的特性
– 集成软启动
– 过热和过压保护
– 带负载断开功能的真正关断功能
– 正向和反向电流限制
• 21.5mm2 的小解决方案尺寸
– 小型SON/DFN 封装（类似于QFN）
– 小型0.47µH 电感器
– 与22µF 最小输出电容器配合使用
• 使用TPS63802 并借助WEBENCH® Power
Designer 创建定制设计方案
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS63802
10 引脚VSON-HR
（0.5mm 间隔）
3.0mm × 2.0mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
0.47 µH
100
90
80
70
60
50
40
L1
L2
VOUT
3.3 V
VIN
1.3 V œ 5.5 V
VIN
EN
VOUT
22 ꢀF
10 ꢀF
PG
FB
TPS63802
MODE
GND
30
AGND
VIN = 3.0 V
VIN = 3.3 V
20
VIN = 3.6 V
VIN = 4.2 V
10
0
典型应用
100m
1m
10m
Output Current (A)
100m
1
2
D
D001
01
效率与输出电流间的关系(VO = 3.3V)
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEU9
TPS63802
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ZHCSJ11D –NOVEMBER 2018 –REVISED JANUARY 2021
Table of Contents
9.4 Device Functional Modes..........................................13
10 Application and Implementation................................17
10.1 Application Information........................................... 17
10.2 Typical Application.................................................. 17
11 Power Supply Recommendations..............................27
12 Layout...........................................................................28
12.1 Layout Guidelines................................................... 28
12.2 Layout Example...................................................... 28
13 Device and Documentation Support..........................29
13.1 Device Support....................................................... 29
13.2 Documentation Support.......................................... 29
13.3 接收文档更新通知................................................... 29
13.4 支持资源..................................................................29
13.5 Trademarks.............................................................30
13.6 静电放电警告.......................................................... 30
13.7 术语表..................................................................... 30
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings........................................ 5
8.2 ESD Ratings............................................................... 5
8.3 Recommended Operating Conditions.........................5
8.4 Thermal Information....................................................5
8.5 Electrical Characteristics.............................................6
8.6 Typical Characteristics................................................8
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description...................................................10
Information.................................................................... 30
4 Revision History
Changes from Revision C (June 2020) to Revision D (January 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
Changes from Revision B (September 2019) to Revision C (June 2020)
Page
• Added device comparison ................................................................................................................................. 3
• Changed 1x 22 µF to 2x 22 µF.........................................................................................................................19
• Changed Part Number from TPS63802RMW to TPS63802DLA .....................................................................20
• Change MODE from High to Low in Application Curves ................................................................................. 20
• Deleted layout guideline to separate AGND and PGND ..................................................................................28
• Changed Use a common-power GND, but connect AGND and PGND through via at a different layer. to Use a
common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. ..............28
Changes from Revision A (January 2019) to Revision B (September 2019)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
• 更改了封装组名称...............................................................................................................................................1
• Added related documentation ..........................................................................................................................29
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5 Description (continued)
The TPS63802 comes in a 1.4 mm x 2.3 mm thermally enhanced HotRod™ dual flat no-lead (DFN) package.
With the tiny bill-off material, the solution size can be small.
6 Device Comparison Table
PART
NUMBER
SWITCH CURRENT LIMIT BOOST
(MIN.)
OUTPUT VOLTAGE I(Q;VIN) (TYP.)
C(O,EFF) (MIN.)
PACKAGE
TPS63802
SIMILAR TI PARTS
TPS63805
Adjustable
11 µA
7 µF
4 A
VSON
Adjustable
11 µA
15 µA
7 µF
4 A
WCSP
WCSP
TPS63810
fixed: 3.3 V/3.45 V
16 µF
5.2 A
TPS63811
or I2C programmable
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7 Pin Configuration and Functions
EN
MODE
AGND
FB
1
2
3
4
5
10
9
VIN
L1
8
GND
L2
7
6
PG
VOUT
Not to scale
图7-1. 10-Pin DLA Package (Top View)
表7-1. Pin Functions
DESCRIPTION
PIN
NAME
EN
NO.
1
Device Enable input. Set HIGH to enable and LOW to disable. It must not be left floating.
MODE
2
PFM/PWM mode selection. Set LOW for power save mode, set HIGH for forced PWM mode. It must not be
left floating.
AGND
FB
3
4
Analog ground
Voltage feedback sensing pin
Power good indicator, open-drain output
Power stage output
PG
5
VOUT
L2
6
7
Connection for inductor
Power ground
GND
L1
8
9
Connection for inductor
Supply voltage input
VIN
10
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8 Specifications
8.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–3
MAX UNIT
VIN, L1, L2, EN, MODE, VOUT, FB, PG
6
9
V
V
Voltage(2)
L1, L2 (AC, less than 10 ns)
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground pin.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
1.3 (1)
1.8
NOM
MAX
5.5
UNIT
V
VI
VO
CI
L
Input voltage
Output voltage
5.2 (2)
V
Effective capacitance connected to VIN
Effective inductance
4
5
μF
μH
μF
µF
0.37
10
0.47
0.57
125
1.8 V ≤VO ≤2.3 V
CO
TJ
TPS63802 Effective capacitance connected to VOUT
Operating junction temperature
VO > 2.3 V
7
8.2
Operating junction
temperature
°C
–40
(1) Minimum startup voltage of VI > 1.8 V until power good
(2) VO margin for accuracy and load steps is considerd in absolut maximum ratings
8.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)(1)
TPS63802
THERMAL METRIC
VSON
10 PINS
81.0
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
36.4
23.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ΨJT
23.5
ΨJB
RΘJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Minimum input voltage for full load,
once started
VIN;LOAD
IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C
2.3
11
V
TPS63802; TJ = 25°C, EN = VIN = 3.6 V, VOUT = 3.3 V, not
switching
IQ;VIN
ISD
Quiescent current into VIN
μA
Shutdown current into VIN
Undervoltage lockout threshold
Undervoltage lockout threshold
Thermal shutdown
45
1.25
1.7
600
1.29
1.79
nA
V
EN = low, -40°C ≤TJ ≤85°C, VIN = 3.6 V, VOUT = 0 V
VIN falling, VOUT ≥1.8 V, once started
VIN rising
1.2
1.6
UVLO
V
TSD
Temperature rising
150
20
°C
°C
TSD;HYST
Thermal shutdown hysteresis
SOFT-START, POWER GOOD
Tramp Soft-start, Current limit ramp time
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5 A, time from
first switching to power good
224
321
µs
µs
TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, Delay from EN-edge
until rising
first switching
Delay from EN-edge until rising
VOUT
Tdelay
LOGIC SIGNALS EN, MODE
VTHR;EN Threshold Voltage rising for EN-Pin
1.07
0.97
1.2
1.1
1
1.13
1.03
V
V
Threshold Voltage falling for EN-
Pin
VTHF;EN
VIH
High-level input voltage
Low-level input voltage
V
V
VIL
0.4
0.4
VPG;rising
VPG;falling
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
95
90
%
%
Power Good threshold voltage
Power Good low-level output
voltage
VPG;Low
ISINK = 1 mA
VFB falling
V
tPG;delay
Ilkg
Power Good delay time
Input leakage current
14
µs
0.01
0.2
µA
OUTPUT
ISD
Shutdown current into VOUT
Feedback Regulation Voltage
Feedback Voltage accuracy
±0.5
500
±600
nA
mV
%
EN = low, -40°C ≤TJ ≤85°C, VIN = 3.6 V, VOUT = 3.3 V
VFB
VFB
PWM mode
VOUT rising
VIN rising
1
5.9
5.9
–1
5.5
5.5
5.7
5.7
V
Overvoltage Protection Threshold
V
Peak Inductor Current to enter
PFM-Mode
IPWM/PFM
IFB
VIN = 3.6 V; VOUT = 3.3 V
VFB = 500 mV
1.06
A
Feedback Input Bias Current
5
5
100
nA
A
Peak Current Limit, Boost Mode
4
5.75
Peak Current Limit, Buck-Boost
Mode
IPK
5
3.8
A
A
A
TPS63802; VIN ≥2.5 V
Peak Current Limit, Buck Mode
Peak Current Limit for Reverse
Operation
IPK;Reverse
VI = 5 V, VO = 3.3 V
–0.9
VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 VIN = 3 V, VOUT = 3.3
High-side FET on-resistance
Low-side FET on-resistance
High-side FET on-resistance
Low-side FET on-resistance
47
30
43
18
mΩ
mΩ
mΩ
mΩ
A
V; IO = 0.5 A
Buck
RDS;ON
VIN = 3 V, VOUT = 3.3 V; I(L2) = 0.19 VIN = 3 V, VOUT = 3.3
A
V; IO = 0.5 A
VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 VIN = 3 V, VOUT = 3.3
A
V; IO = 0.5 A
Boost
RDS;ON
VIN = 3 V, VOUT = 3.3 V; I(L1) = 0.19 VIN = 3 V, VOUT = 3.3
A
V; IO = 0.5 A
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VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5.2 V , TJ= –40°C to +125°C, typical values are at VIN= 3.6 V, VOUT = 3.3 V and TJ=
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Inductor Switching Frequency,
Boost Mode
VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
2.1
MHz
Inductor Switching Frequency,
Buck-Boost Mode
fSW
VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
1.4
MHz
Inductor Switching Frequency,
Buck Mode
VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C
VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A
1.6
0.3
0.1
MHz
%
Line regulation
Load regulation
VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, forced-PWM
mode
%
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8.6 Typical Characteristics
16
1.4
1.2
1
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
VI = 1.8 V
VI = 3.6 V
VI = 5.5 V
12
8
0.8
0.6
0.4
0.2
0
4
-0.2
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D004
D006
EN = LOW
MODE = LOW
VO = 3.3 V
IO = 0 mA, not
switching
图8-2. Shutdown Current vs. Temperature
图8-1. Quiescent Current vs. Temperature
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9 Detailed Description
9.1 Overview
The TPS63802 buck-boost converter uses four internal switches to maintain synchronous power conversion at
all possible operating conditions. This enables the device to keep high efficiency over a wide input voltage and
output load range. To regulate the output voltage at all possible input voltage conditions, the device automatically
transitions between buck, buck-boost, and boost operation as required by the operating conditions. Therefore, it
operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter
when the input voltage is lower than the output voltage. When the input voltage is close to the output voltage, it
operates in a 3-cycle buck-boost operation. In this mode, all four switches are active (see 节 9.4.1.3). The RMS
current through the switches and the inductor is kept at a minimum to minimize switching and conduction losses.
Controlling the switches this way allows the converter to always keep high efficiency over the complete input
voltage range. The device provides a seamless transition between all modes.
9.2 Functional Block Diagram
L
L1
L2
VOUT
VIN
CIN
COUT
Current
Sensor
Gate
Gate
Driver
Driver
Device
Device
Control
Control
PG
VOUT
VIN
Device
Control
VMAX Switch
+
EN
Device Control
Ref
œ
+
Power Safe Mode
Protection
1.1 V
FB
+
œ
VIN
Ref
500 mV
Current Limit
œ
Buck/Boost Control
Off-time calculation
Soft-Start
Gate
Driver
MODE
GND
Power
Good
VOUT
AGND
L1, L2
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9.3 Feature Description
9.3.1 Control Loop Description
The TPS63802 uses a peak current mode control architecture. It has an inner current loop where it measures
the peak current of the boost high-side MOSFET and compares it to a reference current. This current is the
output of the outer voltage loop. It measures the output voltage via the FB-pin and compares it with the internal
voltage reference. That means, the outer voltage loop measures the voltage error (VREF-VFB), and transforms it
into the system current demand (IREF) for the inner current loop.
图 9-1 shows the simplified schematic of the control loop. The error amplifier and the type-2 compensation
represent the voltage loop. The voltage output is converted into the reference current IREF and fed into the
current comparator.
The scheme shows the skip-comparator handling the power-save mode (PFM) to achieve high efficiency at light
loads. See 节9.4.2 for further details.
VIN
L1
IPK
œ
Gate
Driver
IREF
+
FB
VEA
+
Ref
500mV
œ
+
œ
ISKIP
图9-1. Control Loop Architecture Scheme
9.3.2 Precise Device Enable: Threshold- or Delayed Enable
The enable-pin is a digital input to enable or disable the device by applying a high or low level. The device enters
shutdown when EN is set low. In addition, this input features a precise threshold and can be used as a
comparator that enables and disables the part at a defined threshold. This allows you to drive the state by a
slowly changing voltage and enables the use of an external RC network to achieve a precise power-up delay.
The enable pin can also be used with an external voltage divider to set a user-defined minimum supply voltage.
For proper operation, the EN pin must be terminated and must not be left floating.
VTHRESHOLD
VDELAY
R4
R5
R4
C5
EN
EN
图9-2. Circuit Example for How to Use the Precise Device Enable Feature
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9.3.3 Mode Selection (PFM/PWM)
The mode-pin is a digital input to enable the automatic PWM/PFM mode that features the highest efficiency by
allowing pulse-frequency-modulation for lower output currents. This mode is enabled by applying a low level.
The device can be forced in PWM operation regardless of the output current to achieve minimum output ripple
by applying a high level. This pin must not be left floating.
9.3.4 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. It activates the
device once the input voltage (VI) has increased the UVLOrising value. Once active, the device allows operation
down to even smaller input voltages, which is determined by the UVLOfalling. This behavior requires VO to be
higher than the minimum value of 1.8 V.
UVLOrising
UVLOfalling
VIN
Device
active
图9-3. Rising and Falling Undervoltage Lockout Behavior
9.3.5 Soft Start
To minimize inrush current and output voltage overshoot during start-up, the device features a controlled soft
start-up. After the device is enabled, the device starts all internal reference and control circuits within the enable
delay time, Tdelay. After that, the maximum switch current limit rises monotonically from 0 mA to the current limit.
The loop stops switching once VO is reached. This allows a quick output voltage ramp for small capacitors at the
output. The bigger the output capacitor, the longer it takes to settle Vo. A potential load during start-up will
lengthen the duration of the output voltage ramp as well. The gradual ramp of the current limit allows a small
inrush current for no-load conditions, as well as the possibility to start into high loads at start-up.
The converter can start-up into pre-biased loads by a forced operation in PFM during the soft-start until the first
switching cycle request from the output voltage control loop.
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VIN
EN
Current Limit
Inductor
Current
0.95 x VOUT
VOUT
Power Good
Tdelay
Tramp
TStart-up
图9-4. Device Start-up Scheme
9.3.6 Adjustable Output Voltage
The device's output voltage is adjusted by applying an external resistive divider between VO, the FB-pin, and
GND. This allows you to program the output voltage in the recommended range. The divider must provide a low-
side resistor of less than 100 kΩ. The high-side resistor is chosen accordingly.
9.3.7 Overtemperature Protection - Thermal Shutdown
The device has a built-in temperature sensor which monitors the junction temperature. If the temperature
exceeds the threshold, the device stops operating. As soon as the IC temperature has decreased below the
programmed threshold, it starts operating again. There is a built-in hysteresis to avoid unstable operation at
junction temperatures at the overtemperature threshold.
9.3.8 Input Overvoltage - Reverse-Boost Protection (IVP)
The TPS63802 can operate in reverse mode where the device transfers energy from the output back to the
input. If the source is not able to sink the revers current, the negative current builds up a charge to the input
capacitance and VIN rises. To protect the device and other components from that scenario, the device features
an input voltage protection (IVP) for reverse boost operation. Once the input voltage is above the threshold, the
converter forces PFM mode and the negative current operation is interrupted.
The PG signal goes low to indicate that behavior.
9.3.9 Output Overvoltage Protection (OVP)
In case of a broken feedback-path connection, the device can loose VO information and is not able to regulate.
To avoid an uncontrolled boosting of VO, the TPS63802 features output overvoltage protection. It measures the
voltage on the VOUT pin and stops switching when VO is greater than the threshold to avoid harm to the
converter and other components.
9.3.10 Power-Good Indicator
The power good goes high-impedance once the output is above 95% of the nominal voltage, and is driven low
once the output voltage falls below typically 90% of the nominal voltage. This feature also indicates overvoltage
and device shutdown cases as shown in 表9-1. The PG pin is an open-drain output and is specified to sink up to
1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG
signal can be used to sequence multiple rails by connecting it to the EN pin of other converters. Leave the PG
pin unconnected when not used.
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表9-1. Power-Good Indicator Truth Table
LOGIC SIGNALS
PG LOGIC STATUS
Undefined
EN
X
VO
VI
OVP
X
IVP
X
< 1.8 V
< UVLO_R
> UVLO_F
> 1.3V
LOW
HIGH
HIGH
HIGH
HIGH
X
X
X
LOW
LOW
LOW
LOW
HIGH Z
VO < 0.9 × target-VO
X
X
X
> UVLO_F
> UVLO_F
> UVLO_F
HIGH
X
X
X
HIGH
LOW
VO > 0.95 × target-VO
LOW
9.4 Device Functional Modes
9.4.1 Peak-Current Mode Architecture
The TPS63802 is based on a peak-current mode architecture. The error amplifier provides a peak-current target
(voltage that is translated into an equivalent current, see 图 9-1), based on the current demand from the voltage
loop. This target is compared to the actual inductor current during the ON-time. The ON-time is ended once the
inductor current is equal to the current target and OFF-time is initiated. The OFF-time is calculated by the control
and a function of VI and VO.
IPEAK
VEAmp
IIND
IPK-PK
TON
TOFF
0
图9-5. Peak-Current Architecture Operation
9.4.1.1 Reverse Current Operation, Negative Current
When the TPS63802 is forced to PWM operation (MODE = HIGH), the device current can flow in reverse
direction. This happens by the negative current capability of the TPS63802 . The error amplifier provides a peak-
current target (voltage that is translated into an equivalent current, see 图 9-1), even if the target has a negative
value. The maximum average current is even more negative than the peak current.
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time
0
IPEAK
VEAmp
IAVG
IIND
IPK-PK
图9-6. Peak-Current Operation, Reverse Current
9.4.1.2 Boost Operation
When VI is smaller than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63802 operates in boost mode where the boost high-side and low-side switches are active. The buck high-
side switch is always turned on and the buck low-side switch is always turned off. This lets the TPS63802
operate as a classical boost converter.
IPEAK
VEAmp
IIND
TON
TOFF
图9-7. Peak-Current Boost Operation
9.4.1.3 Buck-Boost Operation
When VI is close to VO, the TPS63802 operates in buck-boost mode where all switches are active and the
device repeats 3-cycles:
• TON: Boost-charge phase where boost low-side and buck high-side are closed and the inductor current is built
up
• TOFF: Buck discharge phase where boost high-side and buck low-side are closed and the inductor is
discharged
• TCOM: VI connected to VO where all high-side switches are closed and the input is connected to the output
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IPEAK
VEAmp
IIND
TON
TCOM
TOFF
TCOM
图9-8. Peak-Current Buck-Boost Operation
9.4.1.4 Buck Operation
When VI is greater than VO (and the voltages are not close enough to trigger buck-boost operation), the
TPS63802 operates in buck mode where the buck high-side and low-side switches are active. The boost high-
side switch is always turned on and the boost low-side switch is always turned off. This lets the TPS63802
operate as a classical buck converter.
IPEAK
VEAmp
IIND
TON
TOFF
图9-9. Peak-Current Buck Operation
9.4.2 Power Save Mode Operation
Besides continuos conduction mode (PWM), the TPS63802 features power safe mode (PFM) operation to
achieve high efficiency at light load currents. This is implemented by pausing the switching operation, depending
on the load current.
The skip comparator manages the switching or pause operation. It compares the current demand signal from the
voltage loop, IREF, with the skip threshold, ISKIP, as shown in 图 9-1. If the current demand is lower than the skip
value, the comparator pauses switching operation. If the current demand goes higher (due to falling VO), the
comparator activates the current loop and allows switching according to the loop behavior. Whenever the current
loop has risen VO by bringing charge to the output, the voltage loop output, IREF (respectively VEA), decreases.
When IREF falls below ISKIP-hysteresis, it automatically pauses again.
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ICOIL
VO
ISKIP
VEA
Hysteresis
/ IREF
SKIP
Yes/No
Pause
Switching
图9-10. Power Safe Mode Operation Curves
9.4.2.1 Current Limit Operation
To limit current and protect the device and application, the maximum peak inductor current is limited internally on
the IC. It is measured at the buck high-side switch which turns into an input current detection. To provide a
certain load current across all operation modes, the boost and buck-boost peak current limit is higher than in
buck mode. It limits the input current and allows no further increase of the delivered current. When using the
device in this mode, it behaves similar to a current source.
The current limit depends on the operation mode (buck, buck-boost, or boost mode).
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TPS63802 is a high efficiency, low quiescent current, non-inverting buck-boost converter, suitable for
applications that need a regulated output voltage from an input supply that can be higher or lower than the
output voltage.
10.2 Typical Application
L1
0.47 µH
VIN
L1
L2
VIN
1.3V t 5.5V
VOUT = 3.3V
VIN
EN
VOUT
R3
100lQ
C2
C1
22 …F
10 …F
PG
FB
R1
511lQ
MODE
GND
R2
91lQ
AGND
TPS63802
图10-1. 3.3 VOUT Typical Application
10.2.1 Design Requirements
The design guideline provides a component selection to operate the device within 表10-1.
表10-1 shows the list of components for the application characteristic curves.
表10-1. Matrix of Output Capacitor and Inductor Combinations
NOMINAL
INDUCTOR VALUE
[µH](1)
NOMINAL OUTPUT CAPACITOR VALUE [µF](2)
10
22
47
66
100
(3)
0.47
-
+
+
+
+
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(2) Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
(3) TPS63802 typical application. Other check marks indicate possible filter combinations.
10.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, 节 8.1 outlines minimum
and maximum values for inductance and capacitance. Take tolerance and derating into account when selecting
nominal inductance and capacitance.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63802 device with the WEBENCH® Power Designer.
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1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as the following:
• Inductor ripple current
• Output voltage ripple
• Transition point into power save mode
• Efficiency
See 表10-2 for typical inductors.
For high efficiencies, the inductor must have a low DC resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced, mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady-state operation is calculated using 方程式 2. Only the equation which defines the switch
current in boost mode is shown because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
V
- V
IN
OUT
V
Duty Cycle Boost
D =
OUT
(1)
(2)
Iout
η ´ (1 - D)
Vin ´ D
IPEAK
=
+
2 ´ f ´ L
where
• D = Duty Cycle in Boost mode
• f = Converter switching frequency
• L = Inductor value
• η= Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption)
Note
The calculation must be done for the minimum input voltage in boost mode.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated using 方程式2. 表10-2 lists the possible inductors.
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表10-2. List of Recommended Inductors
INDUCTOR
VALUE [µH]
SATURATION CURRENT
[A]
PART NUMBER
MANUFACTURER(1) SIZE (LxWxH mm)
DCR [mΩ]
0.47
0.47
5.4
5.5
7.6
26
XFL4015-471ME
DFE201612E
Coilcraft
Toko
4 x 4 x 2
2.0 x 1.6 x 1.2
(1) See Third-party Products Disclaimer.
10.2.2.3 Output Capacitor Selection
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and PGND pins of the IC. The recommended nominal output capacitor value is a single 22 µF for all
programmed output voltages ≤3.6 V. Above that voltage, 2x 22 µF capacitors are recommended.
It is important that the effective capacitance is given according to the recommended value in 节 8.3. In general,
consider DC bias effects resulting in less effective capacitance. The choice of the output capacitance is mainly a
trade-off between size and transient behavior since higher capacitance reduces transient response overshoot
and undershoot and increases transient response time. 表10-3 lists possible output capacitors.
There is no upper limit for the output capacitance value.
表10-3. List of Recommended Capacitors(1)
CAPACITOR
[µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
PART NUMBER
MANUFACTURER
ESR [mΩ]
22
22
22
22
47
47
6.3
6.3
10
10
10
40
10
43
43
GRM188R60J226MEA0
GRM187R61A226ME15
GRM188R61A226ME15
GRM187R60J226ME15
GRM188R60J476ME15
GRM219R60J476ME44
Murata
Murata
Murata
Murata
Murata
Murata
0603 (1608)
0603 (1608)
0603 (1608)
0603 (1608)
0603 (1608)
0805 (2012)
10
6.3
6.3
(1) See Third-party Products Disclaimer.
10.2.2.4 Input Capacitor Selection
A 10 µF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior of
the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and
PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply is
located more than a few inches from the TPS63802 converter, additional bulk capacitance can be required in
addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 µF is a typical
choice.
表10-4. List of Recommended Capacitors(1)
CAPACITOR
[µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
PART NUMBER
MANUFACTURER
ESR [mΩ]
10
10
22
6.3
10
10
40
10
GRM188R60J106ME84
GRM188R61A106ME69
GRM188R60J226MEA0
Murata
Murata
Murata
0603 (1608)
0603 (1608)
0603 (1608)
6.3
10.2.2.5 Setting The Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is 500 mV nominal. The low-side resistor R2 (between FB and GND) must
not exceed 100 kΩ. The high-side resistor (between FB and VOUT) R1 is calculated by 方程式3.
æ
ç
è
ö
VOUT
VFB
R1 = R2 ×
- 1
÷
ø
(3)
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where
• VFB = 500 mV
表10-5. Resistor Selection for Typ. Voltages
VO [V]
2.5
3.3
3.6
5
R1 [kΩ]
R2 [kΩ]
91
365
511
91
562
91
806
91
10.2.3 Application Curves
表10-6. Components for Application Characteristic Curves (1)
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER COMMENT
TPS63802 2 A Buck-Boost Converter (2
mm x 3 mm QFN)
TPS63802DLA
Texas Instruments
0.47 µH, 4 mm x 4 mm x 1.5 mm, 5.4 A,
7.6 mΩ
L1
XFL4015-471ME
Coilcraft
Murata
10 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
C1
C2
C2
GRM188R60J106ME84
GRM188R60J226MEA0
GRM188R60J226MEA0
1x 22 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
Murata
Murata
VO ≤3.6 V
2x 22 µF, 0603, Ceramic Capacitor, ±20%,
6.3 V
VO > 3.6 V
R1
R1
R1
R2
R3
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
VO = 3.3 V
VO = 3.6 V
VO = 5 V
511 kΩ, 0603 Resistor, 1%, 100 mW
562 kΩ, 0603 Resistor, 1%, 100 mW
806 kΩ, 0603 Resistor, 1%, 100 mW
91 kΩ, 0603 Resistor, 1%, 100 mW
100 kΩ, 0603 Resistor, 1%, 100 mW
(1) See Third-party Products Disclaimer.
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表10-7. Typical Characteristics Curves
PARAMETER
CONDITIONS
FIGURE
Output Current Capability
Typical Output Current Capability versus Input Voltage
Switching Frequency
VO = 3.3 V
图10-2
Typical Inductor Switching Frequency versus Input
Voltage
IO = 0 A, MODE = High
VO = 3.3 V
图10-3
图10-4
Typical Inductor Burst Frequency versus Output Current
Efficiency
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus Output Current (PFM/PWM)
Efficiency versus Output Current (PWM only)
Efficiency versus. Input Voltage (PFM/PWM)
Efficiency versus Input Voltage (PWM only)
Regulation Accuracy
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE = Low
VI = 2.5 V to 4.2 V, VO = 3.3 V, MODE = High
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = Low
VI = 1.8 V to 5 V, VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
图10-5
图10-6
图10-7
图10-8
图10-9
图10-10
IO = 1 A, MODE = High
Load Regulation, PWM Operation
VO = 3.3 V, MODE = High
VO = 3.3 V, MODE = Low
IO = 1 A, MODE = High
IO = 1 A, MODE = Low
图10-11
图10-12
图10-13
图10-14
Load Regulation, PFM/PWM Operation
Line Regulation, PWM Operation
Line Regulation, PFM/PWM Operation
Switching Waveforms
Switching Waveforms, PFM Boost Operation
Switching Waveforms, PFM Buck-Boost Operation
Switching Waveforms, PFM Buck Operation
Switching Waveforms, PWM Boost Operation
Switching Waveforms, PWM Buck-Boost Operation
Switching Waveforms, PWM Buck Operation
Transient Performance
VI = 2.3 V, VO = 3.3 V, MODE = Low
VI = 3.3 V, VO = 3.3 V, MODE = Low
VI = 4.3 V, VO = 3.3 V, MODE = Low
VI = 2.3 V, VO = 3.3 V, MODE = High
VI = 3.3 V, VO = 3.3 V, MODE = High
VI = 4.3 V, VO = 3.3 V, MODE = High
图10-15
图10-16
图10-17
图10-18
图10-19
图10-20
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
Low
Load Transient, PFM/PWM Boost Operation
Load Transient, PFM/PWM Buck-Boost Operation
Load Transient, PFM/PWM Buck Operation
Load Transient, PWM Boost Operation
Load Transient, PWM Buck-Boost Operation
Load Transient, PWM Buck Operation
Line Transient, PWM Operation
图10-21
图10-22
图10-23
图10-24
图10-25
图10-26
图10-27
图10-28
图10-29
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
Low
VI = 4.2 V, VO = 3.3V, Load = 100 mA to 1A, MODE =
Low
VI = 2.5 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
VI = 3.3 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
VI = 4.2 V, VO = 3.3 V, Load = 100 mA to 1A, MODE =
High
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
VI = 2.3 V to 4.3 V, VO = 3.3 V, Load = 1 A , MODE =
Low
Line Transient, PWM Operation
VI = 3 V to 3.6 V, VO = 3.3 V, Load = 0.5 A , MODE =
Low
Line Transient, PWM Operation
Start-up
Start-up Behavior from Rising Enable, PFM Operation
Start-up Behavior from Rising Enable, PWM Operation
VI = 2.2 V, VO = 3.3 V, Load = 10 mA, MODE = Low
VI = 2.2 V, VO = 3.3 V, Load = 10 mA, MODE = High
图10-30
图10-31
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4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 3.3 V
VO = 3.6 V
VO = 5 V
0.5
0.0
1.3
1.8
2.3
2.8
3.3
Input Voltage (V)
3.8
4.3
4.8
5.3
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
D002
D007
MODE = High
I O = 0 A
MODE = High
VI rising
图10-2. Typical Output Current Capability versus
图10-3. Typical Inductor Switching Frequency
Input Voltage
versus Input Voltage
1M
100k
10k
100
90
80
70
VI = 2.5 V
VI = 3.6 V
VI = 4.8 V
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
1k
1m
60
100m
10m
100m
1m
10m
Output Current (A)
100m
1
2
Output Current (A)
D018
D019
VO = 3.6 V
MODE = Low
VO = 3.3 V
MODE = Low
图10-4. Typical Inductor Burst Frequency versus
图10-5. Efficiency versus Output Current (PFM/
Output Current
PWM)
100
90
80
70
60
50
40
30
100
90
80
70
20
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
10
0
60
100m
1m
10m
100m
Output Current (A)
1
2
1m
10m
Output Current (A)
100m
1
2
D020
D021
VO = 3.3 V
MODE = High
VO = 3.3 V
MODE = Low
图10-6. Efficiency versus Output Current (PWM
图10-7. Efficiency versus Output Current (PFM/
Only)
PWM)
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100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
IO = 100 mA
IO = 10 mA
IO = 100 mA
IO = 1 A
VI = 1.8 V
VI = 3.3 V
VI = 5.0 V
IO = 1.5 A
0
1m
10m
100m
Output Current (A)
1
2
2.5
2.9
3.3
Input Voltage (V)
3.7
4.1
D022
D023
VO = 3.3 V
MODE = High
VO = 3.3 V
MODE = Low
图10-8. Efficiency versus Input Voltage (PWM
图10-9. Efficiency versus Input Voltage (PFM/
Only)
PWM)
100
90
0.2
0.1
0.0
80
-0.1
70
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
-0.3
60
0
0.5
1.0
Output Current (A)
1.5
2.0
1.8
2.3
2.8
3.3 3.8
Input Voltage (V)
4.3
4.8
5.3
D026
D024
VO = 3.3 V
MODE = High
IO = 1 A
MODE = Low
图10-11. Load Regulation (PWM Only)
图10-10. Efficiency versus Input Voltage (PWM
Only)
1.5
1.0
0.5
0.0
0.3
0.2
0.1
0.0
-0.5
-0.1
-0.2
-0.3
VI = 2.5 V
VI = 3.6 V
VI = 4.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-1.0
-1.5
0.5
1.0
Output Current (A)
1.5
2.0
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
D027
D028
VO = 3.3 V
MODE = Low
IO = 1 A
MODE = Low
图10-12. Load Regulation (PFM/PWM)
图10-13. Line Regulation (PWM Only)
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0.2
0.1
0.0
-0.1
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
-0.2
2.5
2.7
2.9
3.1
3.3 3.5
Input Voltage (V)
3.7
3.9
4.1
4.3
VI = 2.3 V, VO = 3.3
V
MODE = Low
IO = 40 mA
D029
IO = 1 A
MODE = High
图10-15. Switching Waveforms, PFM Boost
图10-14. Line Regulation (PFM/PWM)
Operation
VI = 3.3 V, VO = 3.3
VI = 4.2 V, VO = 3.3 V
MODE = Low
IO = 40 mA
MODE = Low
IO = 40 mA
V
图10-17. Switching Waveforms, PFM Buck
图10-16. Switching Waveforms, PFM Buck-Boost
Operation
Operation
VI = 3.3 V, VO = 3.3
VI = 2.3 V, VO = 3.3
MODE = Low
IO = 2 A
MODE = Low
IO = 2 A
V
V
图10-19. Switching Waveforms, PWM Buck-Boost
图10-18. Switching Waveforms, PWM Boost
Operation
Operation
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VI = 4.2 V, VO = 3.3
IO from 100 mA to
MODE = Low
IO = 2 A
VI = 2.5 V, VO = 3.3
V
V
1 A tr = 1 µs, tf = 1
µs
MODE = Low
图10-20. Switching Waveforms, PWM Buck
Operation
图10-21. Load Transient, PFM/PWM Boost
Operation
IO from 100 mA
IO from 100 mA
VI = 3.3 V, VO = 3.3 V to 1 A tr = 1 µs, tf
= 1 µs
MODE = Low
VI = 5 V, VO = 3.3 V
to 1 A tr = 1 µs, tf
= 1 µs
MODE = Low
图10-22. Load Transient, PFM/PWM Buck-Boost
图10-23. Load Transient, PFM/PWM Buck
Operation
Operation
IO from 100 mA
IO from 100 mA
VI = 2.5 V, VO = 3.3 V to 1 A tr = 1 µs, tf
= 1 µs
MODE = High
VI = 3.3 V, VO = 3.3 V to 1 A tr = 1 µs, tf
= 1 µs
MODE = High
图10-24. Load Transient, PWM Boost Operation
图10-25. Load Transient, PWM Buck-Boost
Operation
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VI from 2.2 V to
IO from 100 mA
IO = 0.5 A
4.2 V tr =1 µs, tf = MODE = High
1 µs
VI = 5 V, VO = 3.3 V to 1 A tr = 1 µs, tf
= 1 µs
MODE = High
图10-27. Line Transient, PWM Operation
图10-26. Load Transient, PWM Buck Operation
VI from 3 V to 3.6
VI from 2.2 V to
IO = 0.5 A
V tr = 1 µs, tf = 1
µs
MODE = High
IO = 1 A
4.2 V tr = 1 µs, tf
= 1 µs
MODE = High
图10-29. Line Transient, PWM Operation
图10-28. Line Transient, PWM Operation
VI = 4.2 V, VO = 3.3
V
VI = 4.2 V, VO
3.3 V
=
100 mΩresistive
100 mΩ
MODE = Low
MODE = High
load
resistive load
图10-30. Start-up Behavior from Rising Enable,
图10-31. Start-up Behavior from Rising Enable,
PFM Operation
PWM Operation
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11 Power Supply Recommendations
The TPS63802 device family has no special requirements for its input power supply. The input power supply
output current needs to be rated according to the supply voltage, output voltage, and output current of the
TPS63802.
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12 Layout
12.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS63802 device.
1. Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route wide
and direct traces to the input and output capacitor results in low trace resistance and low parasitic
inductance.
2. Use a common ground node for power ground and a different one for control ground to minimize the effects
of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
3. Use separate traces for the supply voltage of the power stage and the supply voltage of the analog stage.
4. The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.
12.2 Layout Example
L1
C1
C2
R2
R1
图12-1. TPS63802 Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.1.2 Development Support
QFN/SON Package FAQs
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63802 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Selecting a DC/DC Converter for Maximum Battery Life in Pulsed-Load Applications
Application Report
• Texas Instruments, Selecting the Right DC/DC Converter for Maximum Battery Life Application Report
• Texas Instruments, Supercapacitor Backup Power Supply with TPS63802 Application Report
• Texas Instruments, Extend Battery Lifetime in Wireless Network Cameras and Video Doorbells Application
Note
• Texas Instruments, Prevent Battery Overdischarge with Precise Threshold Enable Pin Application Note
• Texas Instruments, Using Non-Inverting Buck-Boost Converter for Voltage Stabilization Application Report
• Texas Instruments, Precise Delayed Start-up with Precise Threshold Enable-pin Application Note
• Texas Instruments, Buck-Boost Converters Solving Power Challenges in Optical Modules Application Note
• Texas Instruments, Improving Load Transient Response for Controlled Loads Application Report
• Texas Instruments, TPS63802EVM User's Guide
• Texas Instruments, HotRod QFN Package PCB Attachment Application Report
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS63802DLAR
TPS63802DLAT
ACTIVE
ACTIVE
VSON-HR
VSON-HR
DLA
DLA
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
63802
63802
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS63802DLAR
TPS63802DLAT
VSON-
HR
DLA
DLA
10
10
3000
250
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
VSON-
HR
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS63802DLAR
TPS63802DLAT
VSON-HR
VSON-HR
DLA
DLA
10
10
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
DLA0010A
2.1
1.9
A
B
3.1
2.9
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
(0.1) TYP
SYMM
0.5
0.3
5X
0.3
0.2
5X
5
6
8X 0.5
SYMM
2
10
1
0.3
0.2
5X
0.8
0.6
0.1
C A B
C
4X
1.2
0.05
1
4223750/D 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
DLA0010A
PKG
5X (0.9)
4X (0.75)
(0.55)
5X (0.6)
5X (0.25)
10
1
8X
(0.5)
(0.25)
(2)
PKG
(R0.05) TYP
5
6
4X (0.25)
4X (0.9)
(1.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223750/D 03/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
DLA0010A
PKG
5X (0.9)
(0.175)
4X (0.75)
5X (0.6)
5X (0.25)
10
1
8X
(0.5)
2X
(0.25)
PKG
(2)
(R0.05) TYP
(0.5)
5
6
4X (0.25)
2X (0.55)
(0.75)
4X (0.9)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 8: 83%
SCALE: 30X
4223750/D 03/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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