TPS65022_16 [TI]
Power Management IC for Li-Ion Powered Systems;
| 型号： | TPS65022_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Power Management IC for Li-Ion Powered Systems |
| 文件： | 总45页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65022
www.ti.com
SLVS667–JULY 2006
POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
FEATURES
DESCRIPTION
•
•
•
•
1.2 A, 97% Efficient Step-Down Converter for
System Voltage (VDCDC1)
The TPS65022 is an integrated Power Management
IC for applications powered by one Li-Ion or
Li-Polymer cell, and which require multiple power
rails. The TPS65022 provides three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a
processor based system. All three step-down
converters enter a low-power mode at light load for
maximum efficiency across the widest possible range
of load currents. The TPS65022 also integrates two
general-purpose 200 mA LDO voltage regulators,
which are enabled with an external input pin. Each
LDO operates with an input voltage range between
1.5 V and 6.5 V, allowing them to be supplied from
one of the step-down converters or directly from the
battery. The default output voltage of the LDOs can
be digitally set to 4 different voltage combinations
using the DEFLDO1 and DEFLDO2 pins. The serial
interface can be used for dynamic voltage scaling,
masking interrupts, or for dis/enabling and setting the
LDO output voltages. The interface is compatible
with the Fast/Standard mode I2C specification,
allowing transfers at up to 400 kHz. The TPS65022
is available in a 40-pin (RHA) QFN package, and
operates over a free-air temperature of -40°C to
85°C.
1 A, Up to 95% Efficient Step-Down Converter
for Memory Voltage (VDCDC2)
900 mA, 90% Efficient Step-Down Converter
for Processor Core (VDCDC3)
30 mA LDO/Switch for Real Time Clock
(VRTC)
•
•
2 x 200 mA General-Purpose LDO
Dynamic Voltage Management for Processor
Core
•
Preselectable LDO Voltage Using Two Digital
Input Pins
•
•
•
Externally Adjustable Reset Delay Time
Battery Backup Functionality
Separate Enable Pins for Inductive
Converters
I2C™ Compatible Serial Interface
•
•
•
•
•
85-µA Quiescent Current
Low Ripple PFM Mode
Thermal Shutdown Protection
40-Pin 6 mm x 6 mm QFN Package
APPLICATIONS
•
•
•
•
•
•
PDA
Cellular/Smart Phone
Internet Audio Player
Digital Still Camera
Digital Radio Player
Split Supply TMS320™ DSP Family and µP
Solutions:
OMAP™1610, OMAP1710, OMAP330, XScale
Bulverde, Samsung ARM-Based Processors,
etc.
•
Intel® PXA270, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320, OMAP, PowerPAD are trademarks of Texas Instruments.
Intel is a registered trademark of Intel Corporation.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS65022
www.ti.com
SLVS667–JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE(1)
PART NUMBER(2)
–40°C to 85°C
40 pin QFN (RHA)
TPS65022RHA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) The RHA package is available in tape and reel. Add the R suffix (TPS65022RHAR) to order quantities of 2500 parts per reel. Add the T
suffix (TPS65022RHAT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 7
2000
UNIT
V
VI
Input voltage range on all pins except AGND and PGND pins with respect to AGND
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3
Peak current at all other pins
mA
mA
1000
Continuous total power dissipation
See Dissipation Rating Table
TA Operating free-air temperature
TJ Maximum junction temperature
Tstg Storage temperature
–40 to 85
125
°C
°C
°C
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
RHA(1)(2)
2.85 W
28 mW/°C
1.57 W
1.14 W
(1) The thermal resistance junction to ambient of the RHA package is 35°C/W measured on a high K board.
(2) The thermal resistance junction to case (exposed pad) of the RHA package is 5°C/W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
Input voltage range step-down convertors
(VINDCDC1, VINDCDC2, VINDCDC3)
VCC
2.5
6
V
Output voltage range for VDCDC1 step-down convertor(1)
Output voltage range for VDCDC2 (mem) step-down convertor(1)
Output voltage range for VDCDC3 (core) step-down convertor(1)
Input voltage range for LDOs (VINLDO1, VINLDO2)
Output voltage range for LDOs (VLDO1, VLDO2)
Output current at L1
0.6
0.6
0.6
1.5
1
VINDCDC1
VINDCDC2
VINDCDC3
6.5
VO
V
VI
V
VO
VINLDO1-2
1200
V
IO(DCDC2)
mA
µH
µF
µF
mA
µH
Inductor at L1(2)
2.2
10
10
3.3
22
(2)
CI(DCDC1)
CO(DCDC1)
IO(DCDC2)
Input capacitor at VINDCDC1
(2)
Output capacitor at VDCDC1
Output current at L2
1000
(2)
Inductor at L2
2.2
3.3
(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
(2) See applications section for more information.
2
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SLVS667–JULY 2006
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
22
MAX UNIT
(2)
CI(DCDC2)
CO(DCDC2)
IO(DCDC3)
Input capacitor at VINDCDC2
Output capacitor at VDCDC2
Output current at L3
µF
µF
(2)
10
900
mA
µH
µF
µF
µF
µF
µF
mA
µF
°C
°C
Ω
(2)
Inductor at L3
2.2
10
10
1
3.3
22
CI(DCDC3)
CO(DCDC3)
CI(VCC)
Input capacitor at VINDCDC3(2)
(2)
Output capacitor at VDCDC3
(2)
Input capacitor at VCC
(2)
Ci(VINLDO)
CO(VLDO1-2)
IO(VLDO1-2)
CO(VRTC)
TA
Input capacitor at VINLDO
1
(2)
Output capacitor at VLDO1, VLDO2
2.2
Output current at VLDO1, VLDO2
200
(3)
Output capacitor at VRTC
4.7
-40
-40
Operating ambient temperature
Operating junction temperature
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(4)
85
125
10
TJ
1
(3) See applications section for more information.
(4) Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted
accordingly.
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
Rpullup at SCLK and SDAT = 4.7 kΩ,
pulled to VRTC
VIH
High level input voltage
1.3
0
VCC
V
Rpullup at SCLK and SDAT = 4.7 kΩ,
pulled to VRTC
VIL
IH
Low level input voltage
Input bias current
0.4
0.1
V
0.01
µA
CONTROL SIGNALS : HOT_RESET
VIH
VIL
High level input voltage
Low level input voltage
Input bias current
1.3
0
VCC
0.4
0.1
35
V
V
IIB
0.01
30
µA
ms
tglitch
Deglitch time at HOT_RESET
25
0
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH
VOL
High level output voltage
Low level output voltage
Duration of low pulse at RESPWRON
Resetpwron threshold
6
V
V
IIL = 5 mA
0.3
External capacitor 1 nF
VRTC falling
100
2.4
ms
V
–3%
–3%
3%
3%
Resetpwron threshold
VRTC rising
2.52
V
3
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SLVS667–JULY 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
All 3 DCDC converters enabled,
TEST CONDITIONS
MIN TYP MAX UNIT
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
zero load and no switching, LDOs
enabled
85 100
All 3 DCDC converters enabled,
zero load and no switching, LDOs
off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
78
57
90
70
Operating quiescent
current, PFM
I(q)
µA
DCDC1 and DCDC2 converters
enabled, zero load and no
switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
DCDC1 converter enabled, zero
load and no switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
43
2
55
3
All 3 DCDC converters enabled
and running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
DCDC1 and DCDC2 converters
enabled and running in PWM,
LDOs off
Current into VCC;
PWM
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
II
1.5
2.5
mA
DCDC1 converter enabled and
running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
0.85
23
2
33
5
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
µA
µA
µA
VCC = 2.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
I(q)
Quiescent current
All converters disabled, LDOs off
3.5
VCC = 3.6 V, VBACKUP = 0 V;
V(VSYSIN) = 0 V
43
4
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SLVS667–JULY 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP
I(q)
Operating quiescent current
Operating quiescent current
20
33
3
µA
µA
VBACKUP < V_VBACKUP, current into
VBACKUP
I(SD)
2
3
VRTC LDO output voltage
Output current for VRTC
VSYSIN = VBACKUP = 0 V, IO = 0 mA
VSYSIN < 2.57 V and VBACKUP < 2.57 V
VRTC = GND; VSYSIN = VBACKUP = 0 V
V
IO
30
mA
mA
VRTC short-circuit current limit
100
Maximum output current at VRTC for VRTC > 2.6 V, VCC = 3 V;
30
mA
RESPWRON = 1
VSYSIN = VBACKUP = 0 V
VO
Output voltage accuracy for VRTC
Line regulation for VRTC
VSYSIN = VBACKUP = 0 V; IO = 0 mA
VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA
-1%
-1%
1%
1%
IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V
Load regulation VRTC
-3%
1%
Regulation time for VRTC
Input leakage current at VSYSIN
rDS(on) of VSYSIN switch
rDS(on) of VBACKUP switch
Input voltage range at VBACKUP(1)
Input voltage range at VSYSIN(1)
VSYSIN threshold
Load change from 10% to 90%
VSYSIN < V_VSYSIN
10
µs
µA
Ω
Ω
V
Ilkg
2
12.5
12.5
3.75
3.75
3%
2.73
2.73
–3%
–3%
–3%
–3%
V
VSYSIN falling
VSYSIN rising
2.55
2.65
2.55
2.65
V
VSYSIN threshold
3%
V
VBACKUP threshold
VBACKUP falling
VBACKUP falling
3%
V
VBACKUP threshold
3%
V
SUPPLY PIN: VINLDO
I(q)
Operating quiescent current
Current per LDO into VINLDO
16
30
1
µA
µA
Total current for both LDOs into VINLDO,
VLDO = 0 V
I(SD)
Shutdown current
0.1
(1) Based on the requirements for the Intel PXA270 processor.
5
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SLVS667–JULY 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDCDC1 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC1
Maximum output current
2.5
6
V
mA
µA
IO
1200
I(SD)
rDS(on)
Ilkg
Shutdown supply current in VINDCDC1
P-channel MOSFET on-resistance
P-channel leakage current
DCDC1_EN = GND
0.1
1
261
2
VINDCDC1 = V(GS) = 3.6 V
VINDCDC1 = 6 V
125
mΩ
µA
rDS(on)
Ilkg
N-channel MOSFET on-resistance
N-channel leakage current
VINDCDC1 = V(GS) = 3.6 V
V(DS) = 6 V
130
7
260
10
mΩ
µA
Forward current limit (P- and N-channel)
Oscillator frequency
2.5 V < VI(MAIN) < 6 V
1.55
1.3
1.75
1.5
1.95
1.7
A
fS
MHz
VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
3 V
–2%
–2%
–1%
–1%
–2%
–1%
2%
2%
1%
1%
2%
1%
Fixed output voltage
FPWMDCDC1=0
VINDCDC1 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
3.3 V
VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
3 V
Fixed output voltage
FPWMDCDC1=1
VINDCDC1 = 3.6 V to 6 V;
0 mA ≤ IO ≤ 1.2 A
3.3 V
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=0
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=1
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Line Regulation
0
0.25
750
%/V
%/A
µs
Load Regulation
Soft start ramp time
IO = 10 mA to 1200 mA
VDCDC1 ramping from 5% to 95% of target
value
Internal resistance from L1 to GND
VDCDC1 discharge resistance
1
MΩ
DCDC1 discharge = 1
300
Ω
6
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SLVS667–JULY 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDCDC2 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC2
Maximum output current
2.5
6
V
mA
µA
IO
1000
I(SD)
rDS(on)
Ilkg
Shutdown supply current in VINDCDC2
P-channel MOSFET on-resistance
P-channel leakage current
DCDC2_EN = GND
0.1
1
300
2
VINDCDC2 = V(GS) = 3.6 V
VINDCDC2 = 6 V
140
mΩ
µA
rDS(on)
Ilkg
ILIMF
fS
N-channel MOSFET on-resistance
N-channel leakage current
VINDCDC2 = V(GS) = 3.6 V
V(DS) = 6 V
150
7
297
10
mΩ
µA
Forward current limit (P- and N-channel)
Oscillator frequency
2.5 V < VINDCDC2 < 6 V
1.4
1.3
1.55
1.5
1.7
1.7
A
MHz
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
1.8 V
–2%
–2%
–2%
–1%
–2%
–1%
2%
2%
2%
1%
2%
1%
Fixed output voltage
FPWMDCDC2=0
VINDCDC2 = 2.8 V to 6 V;
0 mA ≤ IO ≤ 1 A
2.5 V
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1 A
1.8 V
Fixed output voltage
FPWMDCDC2=1
VINDCDC2 = 2.8 V to 6 V;
0 mA ≤ IO ≤ 1 A
2.5 V
Adjustable output voltage with resistor
divider at DEFDCDC2 FPWMDCDC2=0
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1 A
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=1
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1 A
VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Line Regulation
0
0.25
750
%/V
%/A
µs
Load Regulation
Soft start ramp time
IO = 10 mA to 1 mA
VDCDC2 ramping from 5% to 95% of target
value
Internal resistance from L2 to GND
VDCDC2 discharge resistance
1
MΩ
DCDC2 discharge =1
300
Ω
7
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDCDC3 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC3
Maximum output current
2.5
6
V
mA
µA
IO
900
I(SD)
rDS(on)
Ilkg
Shutdown supply current in VINDCDC3
P-channel MOSFET on-resistance
P-channel leakage current
DCDC3_EN = GND
0.1
310
0.1
220
7
1
698
2
VINDCDC3 = V(GS) = 3.6 V
VINDCDC3 = 6 V
mΩ
µA
rDS(on)
Ilkg
N-channel MOSFET on-resistance
N-channel leakage current
VINDCDC3 = V(GS) = 3.6 V
V(DS) = 6 V
503
10
mΩ
µA
Forward current limit (P- and N-channel)
Oscillator frequency
2.5 V < VINDCDC3 < 6 V
1.15
1.3
1.34
1.5
1.52
1.7
A
fS
MHz
Fixed output voltage
FPWMDCDC3=0
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA
–2%
–1%
–2%
–1%
2%
1%
2%
1%
All VDCDC3
Fixed output voltage
FPWMDCDC3=1
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA
Adjustable output voltage with resistor
divider at DEFDCDC3 FPWMDCDC3=0
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 800 mA
Adjustable output voltage with resistor
divider at DEFDCDC3; FPWMDCDC3=1
VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 800 mA
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
Line Regulation
0
0.25
750
%/V
%/A
µs
Load Regulation
Soft start ramp time
IO = 10 mA to 400 mA
VDCDC3 ramping from 5% to 95% of target
value
Internal resistance from L3 to GND
VDCDC3 discharge resistance
1
MΩ
DCDC3 discharge =1
300
Ω
8
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SLVS667–JULY 2006
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
VI
Input voltage range for LDO1, 2
LDO1 output voltage range
LDO2 output voltage range
1.5
1
6.5
3.3
3.3
V
V
V
VO
VO
1
VI = 1.8 V, VO = 1.3 V
200
Maximum output current for LDO1,
LDO2
IO
mA
mA
VI = 1.5 V, VO = 1.3 V
120
65
LDO1 and LDO2 short circuit
current limit
I(SC)
V(LDO1) = GND, V(LDO2) = GND
400
IO = 50 mA, VINLDO = 1.8 V
IO = 50 mA, VINLDO = 1.5 V
IO = 200 mA, VINLDO = 1.8 V
120
150
300
Minimum voltage drop at LDO1,
LDO2
mV
Output voltage accuracy for LDO1,
LDO2
IO = 10 mA
–2%
1%
VINLDO1,2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA
Line regulation for LDO1, LDO2
–1%
–1%
1%
1%
Load regulation for LDO1, LDO2
Regulation time for LDO1, LDO2
IO = 0 mA to 50 mA
Load change from 10% to 90%
10
µs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
VIL
High level input voltage
Low level input voltage
Input bias current
1.3
0
VCC
0.1
V
V
0.001
0.05
µA
THERMAL SHUTDOWN
T(SD) Thermal shutdown
Thermal shutdown hysteresis
INTERNAL UNDERVOLTAGE LOCK OUT
Increasing junction temperature
Decreasing junction temperature
160
20
°C
°C
UVLO
Internal UVLO
VCC falling
–2%
2.35
120
2%
1%
V
Internal UVLO comparator
hysteresis
V(UVLO_HYST)
mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)
Falling threshold
25 mV overdrive
–1%
40
1
V
Hysteresis
50
60
10
mV
Propagation delay
µs
POWER GOOD
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, decreasing
V(PGOODF)
–12%
–7%
–10%
–5%
–8%
–3%
VDCDC1, VDCDC2, VDCDC3, VLDO1,
VLDO2, increasing
V(PGOODR)
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PIN ASSIGNMENT
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
30
29
28
27
SCLK
1
2
DEFDCDC3
VDCDC3
PGND3
SDAT
INT
3
4
5
6
7
8
9
RESPWRON
TRESPWRON
DCDC1_EN
DCDC2_EN
DCDC3_EN
LDO_EN
LOWBAT
L3
26
25
VINDCDC3
VINDCDC1
L1
24
23
22
21
PGND1
VDCDC1
DEFDCDC1
10
11 12 13 14 15 16 17 18 19 20
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
NO.
SWITCHING REGULATOR SECTION
AGND1
40
17
–
Analog ground connection. All analog ground pins are connected internally on the chip.
Analog ground connection. All analog ground pins are connected internally on the chip.
Connect the power pad to analog ground.
AGND2
PowerPAD™
Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply
as VINDCDC2, VINDCDC3, and VCC.
VINDCDC1
6
I
I
I
I
I
I
L1
7
9
8
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
VDCDC1 feedback voltage sense input, connect directly to VDCDC1
Power ground for VDCDC1 converter
VDCDC1
PGND1
Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply
as VINDCDC1, VINDCDC3, and VCC.
VINDCDC2
36
L2
35
33
34
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
VDCDC2 feedback voltage sense input, connect directly to VDCDC2
Power ground for VDCDC2 converter
VDCDC2
PGND2
Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply
as VINDCDC1, VINDCDC2, and VCC.
VINDCDC3
5
L3
4
2
3
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
VDCDC3 feedback voltage sense input, connect directly to VDCDC3
Power ground for VDCDC3 converter
VDCDC3
PGND3
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.
This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
Also supplies serial interface block
VCC
37
I
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V. This pin can also be connected
to a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set
in a range from 0.6 V to VINDCDC1 V.
DEFDCDC1
DEFDCDC2
DEFDCDC3
10
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V. This pin can also be connected
to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set
in a range from 0.6 V to VINDCDC2 V.
32
1
I
I
Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V. This pin can also be
connected to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3
converter is set in a range from 0.6 V to VINDCDC3 V.
DCDC1_EN
DCDC2_EN
DCDC3_EN
25
24
23
I
I
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO
VLDO1
19
20
18
22
15
16
14
12
13
I
O
O
I
I Input voltage for LDO1 and LDO2
Output voltage of LDO1
VLDO2
Output voltage of LDO2
LDO_EN
VBACKUP
VRTC
Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs
Connect the backup battery to this input pin.
I
O
I
Output voltage of the LDO/switch for the real time clock
Input of system voltage for VRTC switch
VSYSIN
DEFLD01
DEFLD02
I
Digital input, used to set default output voltage of LDO1 and LDO2
Digital input, used to set default output voltage of LDO1 and LDO2
I
CONTROL AND I2C SECTION
HOT_RESET
TRESPWRON
RESPWRON
PWRFAIL
LOW_BAT
INT
11
26
27
31
21
28
30
29
38
39
I
I
Push button input used to reboot or wake-up processor via RESPWRON output pin
Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms
Open drain System reset output
O
O
O
O
I
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
Open drain output of LOW_BAT comparator
Open drain output
SCLK
Serial interface clock line
SDAT
I/O
I
Serial interface data/address
PWRFAIL_SNS
LOWBAT_SNS
Input for the comparator driving the PWRFAIL output.
Input for the comparator driving the LOW_BAT output.
I
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FUNCTIONAL BLOCK DIAGRAM
VSYSIN
THERMAL
SHUTDOWN
VCC
VBACKUP
VRTC
BBAT
SWITCH
VINDCDC1
L1
DCDC1
VDCDC1
DEFDCDC1
STEP-DOWN
CONVER TER
SCLK
SDAT
PGND1
Serial Interface
VINDCDC2
DCDC1_EN
DCDC2_EN
DCDC3_EN
LDO_EN
L2
DCDC2
VDCDC2
DEFDCDC2
STEP-DOWN
CONVERTER
HOT_RESET
RESPWRON
CONTROL
PGND2
VCC
INT
AGND1
VINDCDC3
L3
LOWBAT_SNS
PWRFAIL_SNS
DCDC3
UVLO
VREF
OSC
VDCDC3
DEFDCDC3
PGND3
LOW_BATT
STEP-DOWN
CONVERTER
PWRFAIL
TRESPWRON
DEFLDO1
DEFLDO2
VLDO1
VLDO1
200-mA LDO
AGND2
VINLDO
VLDO2
VLDO2
200-mA LDO
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TYPICAL CHARACTERISTICS
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER
VDCDC1
INDUCTOR
VLCF4020-2R2
OUTPUT CAPACITOR
C2012X5R0J106M
C2012X5R0J106M
C2012X5R0J106M
OUTPUT CAPACITOR VALUE
2 × 10 µF
2 × 10 µF
2 × 10 µF
VDCDC2
VLCF4020-2R2
VDCDC3
VLF4012AT-2R2M1R5
Table 1. Table of Graphs
FIGURE
η
Efficiency
vs Output current
1, 2, 3, 4, 5, 6, 7
Line transient response
8, 9, 10
11, 12, 13
14
Load transient response
VDCDC2 PFM operation
VDCDC2 low ripple PFM operation
VDCDC2 PWM operation
15
16
Startup VDCDC1, VDCDC2 and VDCDC3
Startup LDO1 and LDO2
17
18
Line transient response
19, 20, 21
22, 23, 24
Load transient response
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
V = 3.8 V
I
V = 4.2 V
V = 4.2 V
I
I
V = 5 V
I
V = 3.8 V
I
V = 5 V
I
= 25oC
T
= 25oC
T
A
A
V
= 3.3 V
V
= 3.3 V
O
PFM / PWM Mode
O
PWM Mode
0.01
0.1
1
10
100
1 k
10 k
0.01
0.1
1
10
100
1 k
10 k
I
- Output Current - mA
I
- Output Current - mA
O
O
Figure 1.
Figure 2.
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DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
V = 2.5 V
I
V = 3.8 V
I
V = 3.8 V
I
V = 4.2 V
I
V = 2.5 V
I
V = 4.2 V
I
V = 5 V
I
V = 5 V
I
= 25oC
= 1.8 V
T
= 25oC
T
A
A
V
= 1.8 V
V
O
PWM Mode
O
PWM / PFM Mode
0.01
0.1
1
10
100
1 k
10 k
0.01
0.1
1
10
100
1 k
10 k
I
- Output Current - mA
I
- Output Current - mA
O
O
Figure 3.
Figure 4.
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
= 25oC
V = 3 V
T
I
A
V
= 1.55 V
O
PWM Mode
V = 2.5 V
I
V = 3.8 V
I
V = 3.8 V
I
V = 3 V
I
V = 4.2 V
I
V = 2.5 V
V = 4.2 V
I
I
V = 5 V
I
T
= 25oC
A
V = 5 V
I
V
= 1.55 V
O
PWM / PFM Mode
0.01
0.1
I
1
10
100
1 k
0.01
0.1
1
10
100
1 k
I
- Output Current - mA
- Output Current - mA
O
O
Figure 5.
Figure 6.
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DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
VDCDC1 LINE TRANSIENT RESPONSE
Ch1 = V
Ch2 = V
V = 3 V
I
I
C1 High
4.74 V
O
V = 3.8 V
C1 Low
3.08 V
I
V = 2.5 V
I
V = 4.2 V
I
C2 PK-PK
85 mV
V = 5 V
I
C2 Mean
3.2957 V
I
= 100 mA
O
V = 3.6 V to 4.7 V
T
= 25oC
= 1.3 V
I
A
V
= 3 V
O
PWM Mode
V
O
Low Ripple PFM Mode
0.01
0.1
1
10
I
- Output Current - mA
O
Figure 7.
Figure 8.
VDCDC3 LINE TRANSIENT RESPONSE
VDCDC2 LINE TRANSIENT RESPONSE
Ch1 = V
Ch2 = V
I
Ch1 = V
Ch2 = V
I
C1 High
4.05 V
C1 High
4.04 V
O
O
C1 Low
2.95 V
C1 Low
2.94 V
C2 PK-PK
46.0 mV
C2 PK-PK
49.9 mV
C2 Mean
1.79419 V
C2 Mean
1.59798 V
I
= 100 mA
I = 100 mA
O
O
V = 3 V to 4 V
V = 3 V to 4 V
I
I
V
= 1.8 V
V = 1.6 V
O
PWM Mode
O
PWM Mode
Figure 9.
Figure 10.
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VDCDC1 LOAD TRANSIENT RESPONSE
VDCDC2 LOAD TRANSIENT RESPONSE
Ch2 = V
Ch4 = I
O
O
C4 High
830 mA
C4 High
1.09 A
C4 Low
90 mA
Ch2 = V
Ch4 = I
C4 Low
120 mA
O
O
C2 PK-PK
80 mV
C2 PK-PK
188 mV
C2 Mean
3.3051 V
C2 Mean
1.7946 V
I
= 100 mA to 800 mA
I
= 120 mA to 1080 mA
O
V = 3.8 V
O
V = 3.8 V
I
I
V
= 1.8 V
PWM Mode
PWM Mode
V
= 3.3 V
O
O
Figure 11.
VDCDC3 LOAD TRANSIENT RESPONSE
Figure 12.
VDCDC2 OUTPUT VOLTAGE RIPPLE
I
= 1 mA
T
= 25oC
A
Ch2 = V
Ch4 = I
O
V = 3.8 V
O
I
V
= 1.8 V
O
O
C4 High
730 mA
PFM Mode
C4 Low
80 mA
C2 PK-PK
17.0 mV
C2 PK-PK
80 mV
C2 Mean
1.80522 V
C2 Mean
1.5931 V
I
= 80 mA to 720 mA
O
V = 3.8 V
T
= 25oC
A
PWM Mode
I
V
= 1.6 V
O
Figure 13.
Figure 14.
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VDCDC2 OUTPUT VOLTAGE RIPPLE
= 1.8 V
VDCDC2 OUTPUT VOLTAGE RIPPLE
V
V = 3.8 V
O
I
V = 3.8 V
V
I
= 1.8 V
I
O
I
= 1 mA
= 25oC
= 1 mA
= 25oC
O
O
T
T
A
A
Low Ripple PFM Mode
PWM Mode
C2 PK-PK
7.7 mV
C2 Mean
1.79955 mV
Figure 15.
Figure 16.
STARTUP LDO1 AND LDO2
STARTUP VDCDC1, VDCDC2, AND VDCDC3
ENABLE
ENABLE
VDCDC1
LDO1
VDCDC2
VDCDC3
LDO2
Figure 17.
Figure 18.
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LDO1 LINE TRANSIENT RESPONSE
LDO2 LINE TRANSIENT RESPONSE
I
= 25 mA
= 1.1 V
I
= 25 mA
= 3.3 V
O
O
Ch1 = V
I
Ch1 = V
Ch2 = V
I
V
T
V
T
C1 High
4.51 V
C1 High
3.83 V
O
O
Ch2 = V
O
= 25oC
O
= 25oC
A
A
C1 Low
3.99 V
C1 Low
3.29 V
C2 PK-PK
6.1 mV
C2 PK-PK
6.2 mV
C2 Mean
1.09702 V
C2 Mean
3.29828 V
Figure 19.
Figure 20.
VRTC LINE TRANSIENT RESPONSE
LDO1 LOAD TRANSIENT RESPONSE
I
= 10 mA
= 3 V
O
Ch1 = V
I
V
T
C1 High
3.82 V
O
Ch2 = V
O
C4 High
48.9 mA
= 25oC
A
C1 Low
3.28 V
C4 Low
2.1 mA
C2 PK-PK
22.8 mV
C2 PK-PK
42.5 mV
C2 Mean
1.09664 V
C2 Mean
2.98454 V
V = 3.3 V
I
V
T
= 1.1 V
= 25oC
O
Ch2 = V
Ch4 = I
O
A
O
Figure 21.
Figure 22.
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LDO2 LOAD TRANSIENT RESPONSE
VRTC LOAD TRANSIENT RESPONSE
C4 High
47.8 mA
C4 High
21.4 mA
C4 Low
-2.9 mA
C4 Low
-1.4 mA
C2 PK-PK
40.4 mV
C2 PK-PK
76 mV
C2 Mean
3.29821 V
C2 Mean
2.9762 V
V = 4 V
I
V = 3.8 V
I
V
T
= 3.3 V
= 25oC
Ch2 = V
Ch4 = I
O
Ch2 = V
Ch4 = I
O
V
T
= 3 V
= 25oC
O
O
A
O
O
A
Figure 23.
Figure 24.
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DETAILED DESCRIPTION
VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY
The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. This is the
VCC_BATT rail of the Intel® PXA270 Bulverde processor for example.
In applications using a backup battery, the backup voltage can be either directly connected to the TPS65022
VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g. TPS61070) if a single NiMH battery is used.
The voltage applied to the VBACKUP pin is fed through a PMOS switch to the VRTC pin. The TPS65022
asserts the RESPWRON signal if VRTC drops below 2.4 V. This, together with 375 mV at 30 mA drop out for
the PMOS switch means that the voltage applied at VBACKUP must be greater than 2.775 V for normal system
operation.
When the voltage at the VSYSIN pin exceeds 2.65 V, the path from VBACKUP to VRTC is cut, and VRTC is
supplied by a similar PMOS switch from the voltage source connected to the VSYSIN input. Typically this is the
VDCDC1 converter but can be any voltage source within the appropriate range.
In systems where no backup battery is used, the VBACKUP pin is connected to GND. In this case, a low power
LDO is enabled, supplied from VCC and capable of delivering 30 mA to the 3 V output. This LDO is disabled if
the voltage at the VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to
this pin as previously described.
Inside TPS65022 there is a switch (Vmax switch) which selects the higher voltage between VCC and
VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output
of the Vmax switch are:
•
•
•
•
•
•
•
•
•
INT output
RESPWRON output
HOT_RESET input
LOW_BATT output
PWRFAIL output
Enable pins for dc-dc converters, LDO1 and LDO2
Undervoltage lockout comparator (UVLO)
Reference system with low frequency timing oscillators
LOW_BATT and PWRFAIL comparators
The main 1.5-MHz oscillator, and the I2C™ interface are only powered from VCC
.
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DETAILED DESCRIPTION (continued)
V
VSYSIN
CC
VBACKUP
V
V
ref
ref
V_VSYSIN
V_VBACKUP
V_VSYSIN
EN
VRTC
LDO
V_VBACKUP
priority
#1
priority
#2
priority
#3
VRTC
RESPWRON
V
ref
A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
Figure 25.
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3
The TPS65022 incorporates three synchronous step-down converters operating typically at 1.5 MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the
converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation
(PFM). The VDCDC1 converter is capable of delivering 1.2 A output current, the VDCDC2 converter is capable
of delivering 1 A and the VDCDC3 converter is capable of delivering up to 900 mA.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The
pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The
VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is
tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected
to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application
information section for more details.
The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If
DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If
DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The
core voltage can be reprogrammed via the serial interface in the range of 0.8 V to 1.6 V with a programmable
slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway,
whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to
program the output voltage and slew rate during voltage transitions.
The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs
of which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged
via on-chip 300-Ω resistors when the dc-dc converters are disabled.
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DETAILED DESCRIPTION (continued)
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for
a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the
VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three
converters can be changed using the CON_CTRL register.
POWER SAVE MODE OPERATION
As the load current decreases, the converters enter the power save mode operation. During PSM, the
converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for
one burst cycle. However, the frequency between different burst cycles depends on the actual load current and
is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
VINDCDC1
I
=
PFMDCDC1 enter
24 W
VINDCDC2
I
I
=
=
PFMDCDC2 enter
26 W
VINDCDC3
PFMDCDC3 enter
39 W
(1)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
VINDCDC1
I
=
PFMDCDC1 leave
18 W
VINDCDC2
I
I
=
PFMDCDC2 leave
20 W
VINDCDC3
=
PFMDCDC3 leave
29 W
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output
voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to
PWM mode if either of the following conditions are met:
1. the output voltage drops 2% below the nominal VO due to increasing load current
2. the PFM burst time exceeds 16 × 1/fs (10.67 µs typical).
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DETAILED DESCRIPTION (continued)
These control methods reduce the quiescent current to typically 14 µA per converter, and the switching activity
to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM
mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The
soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft
start time is typically 750 µs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 µs between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65022 converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load
current and output voltage. It is calculated as:
ǒr
max ) R Ǔ
Vin
+ Vout
) Iout
max
min
min
DS(on)
L
(3)
with:
Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
Voutmin = nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or
OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is
individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the
VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as
the converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An
interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when
the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
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DETAILED DESCRIPTION (continued)
LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS65022 step-down and LDO voltage
regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the
junction temperature rises above 160°C.
POWER GOOD MONITORING
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any
voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the
relevant PGOODZ register bits indicate that power is good.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the five regulators on the TPS65022 prevents the device from malfunctioning
at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The
UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note
that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA
when all three converters are running in PWM mode. This current needs to be taken into consideration if an
external RC filter is used at the VCC pin to remove switching noise from the TPS65022 internal analog circuitry
supply.
POWER-UP SEQUENCING
The TPS65022 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by
providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The
relevant control pins are described in Table 2.
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
INPUT
FUNCTION
OUTPUT
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to
1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V.
DEFDCDC3
DEFDCDC2
DEFDCDC1
I
I
I
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to
1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V,
DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V.
DCDC3_EN
DCDC2_EN
DCDC1_EN
I
I
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65022 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of
VDCDC3 to its default value defined with the DEFDCDC3 pin. HOT_RESET is internally de-bounced by
the TPS65022.
HOT_RESET
I
RESPWRON is held low when power is initially applied to the TPS65022. The VRTC voltage is monitored:
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at
the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
RESPWRON
O
I
TRESPWRON
Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms.
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SYSTEM RESET + CONTROL SIGNALS
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for
tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by
an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by
the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the
voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before
VDCDC1 was disabled.
DEFLDO1 and DEFLDO2
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3.
DEFLDO2
DEFLDO1
VLDO1
1.1 V
VLDO2
1.3 V
1.3 V
2.8 V
3.3 V
0
0
1
1
0
1
0
1
1.5 V
2.6 V
3.15 V
Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read via the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO
interrupts since this provides the POWER_OK function.
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TIMING DIAGRAMS
HOT_RESET
tDEGLITCH
tNRESPWRON
RESPWRON
V
DCDC3
default voltage
O
any voltage set
with I2C interface
Figure 26. HOT_RESET Timing
2.35 V
1.9 V
1.2 V
2.47 V
1.9 V
0.8 V
V
CC
UVLO*
VRTC
2.52 V
2.4 V
3 V
RESPWRON
DCDCx_EN
tNRESPWRON
Ramp
Within
800 ms
1.8 V
V DCDCx
O
slope depending on load
LDO_EN
V LDOx
O
1.5 V
VSYSIN = VBACKUP = GND;
VINLDO = V
*... Internal Signal
CC
Figure 27. Power-Up and Power-Down Timing
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V
CC
t
NRESPWRON
RESPWRON
DCDC1_EN
DCDC2_EN
3.3 V or 3 V
Ramp Within 800 ms
V DCDC1
O
Ramp Within
800 ms
V DCDC2
O
2.5 V or 1.8 V
Ramp Within 800 ms
DEFCORE
register
Default Value
Set Higher Output Voltage for DCDC3
GO bit in
CON_CTRL2
Automatically Set
to Default Value
Cleared Automatically
DCDC3_EN
V DCDC3
O
1.3 V or 1.55 V
1.3 V or 1.55 V
Slope Depending
On Load
Programmed
Slew Rate
Ramp Within
800 ms
Ramp Within 800 ms
Figure 28. DVS Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed
to new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65022 has a 7-bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
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whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a
start condition and terminated with a stop condition. When addressed, the TPS65022 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65022 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end
of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In
this case, the slave TPS65022 device must leave the data line high to enable the master to generate the stop
condition
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 29. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 30. START and STOP Conditions
SCLK
SDAT
A6
A5
A4
A0
ACK
0
R7
R6
R5
R0 ACK
0
D7
D6
D5
D0 ACK
R/W
0
0
Register Address
Stop
Start
Slave Address
Data
Note: SLAVE = TPS65020
Figure 31. Serial i/f WRITE to TPS65022 Device
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SCLK
SDAT
A6
A0
R/W ACK
R7
R0 ACK
0
A6
A0
R/W ACK
D7
D0 ACK
0
0
1
0
Slave
Drives
the Data
Stop
Register
Address
Master
Drives
ACK and Stop
Start
Slave Address
Slave Address
Repeated
Start
Note: SLAVE = TPS65020
Figure 32. Serial i/f READ from TPS65022: Protocol A
SCLK
SDA
A6
A0
R/W ACK
R7
R0 ACK
A6
A0
R/W ACK D7
D0
ACK
0
0
0
1
0
Stop Start
Stop
Slave
Drives
the Data
Register
Address
Master
Drives
ACK and Stop
Start
Slave Address
Slave Address
Note: SLAVE = TPS65020
Figure 33. Serial i/f READ from TPS65022: Protocol B
DATA
t
(BUF)
t
h(STA)
t
(LOW)
t
r
t
f
CLK
t
t
t
(HIGH)
su(STA)
t
su(STO)
h(STA)
t
t
su(DATA)
h(DATA)
STO
STA
STA
STO
Figure 34. Serial i/f Timing Diagram
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MIN
MAX
UNIT
kHz
ns
fMAX
Clock frequency
400
twH(HIGH)
twL(LOW)
tR
Clock high time
600
Clock low time
1300
ns
DATA and CLK rise time
300
300
ns
tF
DATA and CLK fall time
ns
th(STA)
th(DATA)
th(DATA)
tsu(DATA)
tsu(STO)
t(BUF)
Hold time (repeated) START condition (after this period the first clock pulse is generated)
600
600
0
ns
Setup time for repeated START condition
Data input hold time
ns
ns
Data input setup time
100
600
1300
ns
STOP condition setup time
Bus free time
ns
ns
VERSION. Register Address: 00h (read only)
VERSION
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
0
0
1
0
0
0
1
0
Read/Write
R
R
R
R
R
R
R
R
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PGOODZ. Register Address: 01h (read only)
PGOODZ
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
LOWBATTZ
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
PWRFAILZ
LOWBATT
LOWBATTZ
R
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
Set by signal
PWRFAIL
Default value
loaded by:
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
PWRFAILZ
R
Read/Write
R
R
R
R
R
R
Bit 7 PWRFAILZ:
0 = indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.
1 = indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.
Bit 6 LOWBATTZ:
0 = indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.
1 = indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.
Bit 5 PGOODZ VDCDC1:
0 = indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if
the VDCDC1 converter is disabled.
1 = indicates that the VDCDC1 converter output voltage is below its target regulation voltage
Bit 4 PGOODZ VDCDC2:
0 = indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if
the VDCDC2 converter is disabled.
1 = indicates that the VDCDC2 converter output voltage is below its target regulation voltage
Bit 3 PGOODZ VDCDC3: .
0 = indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if
the VDCDC3 converter is disabled and during a DVM controlled output voltage transition
1 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage
Bit 2 PGOODZ LDO2:
0 = indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is
disabled.
1 = indicates that LDO2 output voltage is below its target regulation voltage
Bit 1 PGOODZ LDO1
0 = indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is
disabled.
1 = indicates that the LDO1 output voltage is below its target regulation voltage
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MASK. Register Address: 02h (read/write)
Default Value: C0h
MASK
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
MASK
MASK
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
PWRFAILZ LOWBATTZ
Default
1
1
0
0
0
0
0
0
Default value
loaded by:
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
Read/Write
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
REG_CTRL. Register Address: 03h (read/write)
Default Value: FFh
The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of
the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition
resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The
REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.
REG_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
VDCDC1
ENABLE
VDCDC2
ENABLE
VDCDC3
ENABLE
LDO2
ENABLE
LDO1
ENABLE
Default
1
1
1
1
1
1
1
1
Set by signal
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ LDO_ENZ
LDO_ENZ
Default value
loaded by:
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
Read/Write
Bit 5 VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when
DCDC1_EN returns high.
Bit 4 VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when
DCDC2_EN returns high.
Bit 3 VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when
DCDC3_EN returns high.
Bit 2 LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1 LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.
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CON_CTRL. Register Address: 04h (read/write)
Default Value: B1h
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
Default
1
0
1
1
0
0
0
1
Default value
loaded by:
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
UVLO
R/W
Read/Write
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to
minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is
taken as the reference and consequently has a fixed zero phase shift.
DCDC2 CONVERTER
DELAYED BY
DCDC3 CONVERTER
DELAYED BY
CON_CTRL<7:6>
CON_CTRL<5:4>
00
01
10
11
zero
00
01
10
11
zero
1/4 cycle
1/2 cycle
3/4 cycle
1/4 cycle
1/2 cycle
3/4 cycle
Bit 3 LOW RIPPLE:
0 =
1 =
PFM mode operation optimized for high efficiency for all converters
PFM mode operation optimized for low output voltage ripple for all converters
Bit 2 FPWM DCDC2:
0 =
1 =
DCDC2 converter operates in PWM / PFM mode
DCDC2 converter is forced into fixed frequency PWM mode
Bit 1 FPWM DCDC1:
0 =
1 =
DCDC1 converter operates in PWM / PFM mode
DCDC1 converter is forced into fixed frequency PWM mode
Bit 0 FPWM DCDC3:
0 =
1 =
DCDC3 converter operates in PWM / PFM mode
DCDC3 converter is forced into fixed frequency PWM mode
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CON_CTRL2. Register Address: 05h (read/write)
Default Value: 40h
CON_CTRL2
B7
GO
0
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
Core adj
allowed
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
Default
1
0
0
0
0
0
0
Default value
loaded by:
UVLO +
DONE
RESET(1)
UVLO
R/W
UVLO
R/W
UVLO
R/W
Read/Write
R/W
R/W
The CON_CTRL2 register can be used to take control the inductive converters.
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
•
•
•
•
•
undervoltage lockout (UVLO)
DCDC1_EN and DCDC3_EN pulled low
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
Bit 7
GO:
0 = no change in the output voltage for the DCDC3 converter
1 = the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC3 output voltage is actually in regulation at the
desired voltage.
Bit 6
CORE ADJ Allowed:
0 = the output voltage is set with the I2C register
1 = DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up
Bit 2– 0 0 = the output capacitor of the associated converter is not actively discharged when the converter
is disabled
1 = the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load
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DEFCORE. Register Address: 06h (read/write
Default Value: 14h/1Eh
DEFCORE
B7
B6
B5
B4
CORE4
1
B3
B2
CORE2
1
B1
B0
Bit name and function
Default
CORE3
DEFDCDC3
RESET(1)
R/W
CORE1
DEFDCDC3
RESET(1)
R/W
CORE0
0
0
0
0
Default value loaded by:
Read/Write
RESET(2)
R/W
RESET(1)
R/W
RESET(2)
R/W
RESET(1): DEFCORE[3:1] are reset to the default
value by one of these events:
RESET(2): DEFCORE[4] and DEFCORE[0] are reset
to the default value by one of these events:
•
•
•
•
•
undervoltage lockout (UVLO)
DCDC1_EN and DCDC3_EN pulled low
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
•
•
•
•
•
undervoltage lockout (UVLO)
DCDC1_EN pulled low
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
CORE4 CORE3 CORE2 CORE1 CORE0
VDCDC3
CORE4
CORE3
CORE2
CORE1 CORE0
VDCDC3
1.2 V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.8 V
0.825 V
0.85 V
0.875 V
0.9 V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225 V
1.25 V
1.275 V
1.3 V
0.925 V
0.95 V
0.975 V
1 V
1.325 V
1.35 V
1.375 V
1.4 V
1.025 V
1.05 V
1.075 V
1.1 V
1.425 V
1.45 V
1.475 V
1.5 V
1.125 V
1.15 V
1.175 V
1.525 V
1.55 V
1.6 V
DEFSLEW. Register Address: 07h (read/write)
Default Value: 06h
DEFSLEW
B7
B6
B5
B4
B3
B2
B1
B0
SLEW0
0
Bit name and function
Default
SLEW2
1
SLEW1
1
Default value loaded by:
Read/Write
UVLO
R/W
UVLO
R/W
UVLO
R/W
SLEW2
SLEW1
SLEW0
VDCDC3 SLEW RATE
0.15 mV/µs
0.3 mV/µs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.6 mV/µs
1.2 mV/µs
2.4 mV/µs
4.8 mV/µs
9.6 mV/µs
Immediate
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LDO_CTRL. Register Address: 08h (read/write)
Default Value: set with DEFLDO1 and DEFLDO2
LDO_CTRL
B7
B6
LDO2_2
DEFLDOx
UVLO
B5
LDO2_1
DEFLDOx
UVLO
B4
LDO2_0
DEFLDOx
UVLO
B3
B2
LDO1_2
DEFLDOx
UVLO
B1
LDO1_1
DEFLDOx
UVLO
B0
LDO1_0
DEFLDOx
UVLO
Bit name and
function
Default
Default value
loaded by:
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2.
The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.
LDO1 OUTPUT
VOLTAGE
LDO2 OUTPUT
VOLTAGE
LDO1_2
LDO1_1
LDO1_0
LDO2_2
LDO2_1
LDO2_0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.05 V
1.2 V
1.3 V
1.8 V
2.5 V
2.8 V
3 V
1.1 V
1.35 V
1.5 V
2.2 V
2.6 V
2.85 V
3.15 V
3.3 V
DESIGN PROCEDURE
Inductor Selection for the DC-DC Converters
Each of the converters in the TPS65022 typically use a 3.3 µH output inductor. Larger or smaller inductor values
are used to optimize the performance of the device for specific operation conditions. The selected inductor has
to be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly
the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest
efficiency.
For a fast transient response, a 2.2-µH inductor in combination with a 22-µF output capacitor is recommended.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
needed because during heavy load transient the inductor current rises above the value calculated under
Equation 4.
Vout
Vin
1 *
DI + Vout
L
L ƒ
(4)
(5)
DI
L
I
+ I
)
outmax
Lmax
2
with:
f = Switching Frequency (1.5 MHz typical)
L = Inductor Value
∆IL = Peak-to-Peak inductor ripple current
ILMAX = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
36
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A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65022 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core
material from inductor to inductor differs and has an impact on the efficiency especially at high switching
frequencies.
See Table 4 and the typical applications for possible inductors.
Table 4. Tested Inductors
DEVICE
INDUCTOR
VALUE
TYPE
COMPONENT SUPPLIER
3.3 µH
3.3 µH
3.3 µH
2.2 µH
3.3 µH
3.3 µH
2.2 µH
3.3 µH
3.3 µH
3.3 µH
2.2 µH
CDRH2D14NP-3R3
LPS3010-332
Sumida
Coilcraft
TDK
DCDC3 converter
VLF4012AT-3R3M1R3
VLF4012AT-2R2M1R5
CDRH2D18/HPNP-3R3
VLF4012AT-3R3M1R3
VLCF4020-2R2
TDK
Sumida
TDK
DCDC2 converter
DCDC1 converter
TDK
CDRH3D14/HPNP-3R2
CDRH4D28C-3R2
MSS5131-332
Sumida
Sumida
Coilcraft
TDK
VLCF4020-2R2
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the
TPS65022 allow the use of small ceramic capacitors with a typical value of 10 µF for each converter without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended
components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness, the RMS ripple current is calculated as:
V
out
1 -
V
1
in
x
I
= V
x
RMSCout
out
L x ¦
2 x Ö3
(6)
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
out
1 -
V
in
1
DV
= V
x
x
+ ESR
out
out
L x ¦
8 x C
x ¦
out
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output
capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output voltage ripple is less than 1% of the nominal output voltage.
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Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. Each dc-dc converter requires a 10-µF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the
input for the dc-dc converters. A filter resistor of up to 10R and a 1-µF capacitor is used for decoupling the VCC
pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow
via this resistor into the VCC pin when all converters are running in PWM mode.
Table 5. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
1206
COMPONENT SUPPLIER
TDK C3216X5R0J226M
COMMENTS
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
22 µF
22 µF
22 µF
22µF
1206
Taiyo Yuden JMK316BJ226ML
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK C2012X5R0J106M
0805
0805
10 µF
10 µF
0805
0805
Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 6 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 35.
The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3
does not change the voltage set with the register.
Table 6.
PIN
LEVEL
VCC
GND
VCC
GND
VCC
GND
DEFAULT OUTPUT VOLTAGE
3.3 V
3 V
DEFDCDC1
2.5 V
1.8 V
1.55 V
1.3 V
DEFDCDC2
DEFDCDC3
Using an external resistor divider at DEFDCDCx:
10 R
V
V
(bat)
CC
1 mF
VDCDC3
L3
V
O
VINDCDC3
DCDC3_EN
L
C
I
C
O
R1
R2
DEFDCDC3
AGND PGND
Figure 35. External Resistor Divider
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When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to
maintain a high efficiency at light load.
V(DEFDCDCx) = 0.6 V
V
OUT
R1 + R2
V
= V
x
- R2
R1 = R2 x
OUT
DEFDCDCx
V
R2
DEFDCDCx
(8)
VRTC Output
The VRTC output is typically connected to the Vcc_Batt pin of a Intel® PXA270 processor. During power-up of
the processor, the TPS65022 internally switches from the LDO or the backup battery to the system voltage
connected at the VSYSIN pin (see Figure 25). It is recommended that a 4.7-µF (minimum) capacitor be added to
the VRTC pin.
LDO1 and LDO2
The LDOs in the TPS65022 are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2 µF. The LDOs output voltage can be changed to different voltages
between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in
applications powering processors different from PXA270. The supply voltage for the LDOs needs to be
connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and
provides the highest efficiency.
TRESPWRON
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2 µA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
(1 V - 0.25 V) x C(reset)
t(reset) = 2 x 128 x
2 mA
(9)
Where:
t(reset) is the reset delay time
C(reset) is the capacitor connected to the TRESPWRON pin
VCC-Filter
An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and
other analog circuitry. A typical value of 10 R and 1 µF is used to filter the switching spikes, generated by the
dc-dc converters. A larger resistor than 10 R should not be used because the current into VCC of up to 3 mA
causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to
switch off too early.
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APPLICATION INFORMATION
TYPICAL CONFIGURATION FOR THE Intel® PXA270 BULVERDE PROCESSOR
V
CC
10 R
PWRFAIL
nBatt_Fault
GPIO
V
CC
1 mF
10 mF
10 mF
10 mF
LOW_BATT
VINDCDC1
VINDCDC2
VINDCDC3
VRTC
Vcc_Batt
SYS_EN
3 V
4.7 mF
DCDC2_EN
DCDC1_EN
VDCDC1
Vcc_IO
3 V; 3.3 V
V
L1
Vcc_LCD
Vcc_BB
1.8 V; 2.5 V; 3 V; 3.3 V
1.8 V; 2.5 V; 3 V; 3.3 V
TPS65021
CC
2.2 mH
22 mF
22 mF
VDCDC2
L2
PWRFAIL_SNS
LOWBAT_SNS
Vcc_MEM 1.8 V; 2.5 V; 3 V; 3.3 V
Vcc_USIM 1.8 V; 3 V
2.2 mH
VIN_LDO
1 MR
DCDC3_EN
LDO_EN
HOT_RESET
PWR_EN
TRESPWRON
DEFLDO1
LDO2
LDO1
L3
Vcc_PLL
1.3 V
1 nF
2.2 mF
2.2 mF
GND
GND
Vcc_SRAM 1.1 V
DEFLDO2
VSYSIN
Variable 0.85 V to 1.4 V
Vcc_CORE
2.2 mH
VDCDC1
22 mF
V
VDCDC3
INT
CC
DEFDCDC1
DEFDCDC2
nVcc_Fault
nRESET
RESPWRON
DEFDCDC3
VBACKUP
SCLK
SDAT
SCLK
SDAT
3 V
Backup
Battery
4.7 kW
4.7 kW
VRTC
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2006
PACKAGING INFORMATION
Orderable Device
TPS65022RHAR
TPS65022RHARG4
TPS65022RHAT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHA
40
40
40
40
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
QFN
QFN
RHA
RHA
RHA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TPS65022RHATG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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