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TPS650860

SWCS128A –MARCH 2015–REVISED DECEMBER 2015

TPS650860 Configurable Multirail PMU for Multicore Processors

1 Device Overview

1.1 Features

1

• Wide V_INRange From 5.6 V to 21 V

• Three Load Switches With Slew Rate Control

• Three Variable-Output Voltage Synchronous

Step-Down Controllers With DCAP2™ Topology

– Up to 300 mA of Output Current With Voltage

Drop Less Than 1.5% of Nominal Input Voltage

– Scalable Output Current Using External FETs

With Selectable Current Limit

– I²C DVS Control From 0.41 V to 1.67 V in 10-

mV Steps or 1 V to 3.575 V in 25-mV Steps

– R_DSON< 96 mΩ at Input Voltage of 1.8 V

• 5-V Fixed-Output Voltage LDO (LDO5)

– Power Supply for Gate Drivers of SMPS and for

LDOA1

• Three Variable-Output Voltage Synchronous Step-

Down Converters With DCS-Control Topology

– Automatic Switch to External 5-V Buck for

Higher Efficiency

– V_INRange From 4.5 V to 5.5 V

– Up to 3 A of Output Current

• Built-in Flexibility and Configurability by Factory

OTP Programming

– I²C DVS Control From 0.41 V to 1.67 V in 10-

mV Steps or 0.425 V to 3.575 V in 25-mV Steps

– Six GPI Pins Configurable to Enable (CTL1 to

CTL6) or Sleep Mode Entry (CTL3 and CTL6) of

Any Selected Rails

– Four GPO Pins Configurable to Power Good of

Any Selected Rails

• Three LDO Regulators With Adjustable Output

Voltage

– LDOA1: I²C-Selectable Output Voltage From

1.35 V to 3.3 V for up to 200 mA of Output

Current

– Open-Drain Interrupt Output Pin

• I²C Interface Supports:

– LDOA2 and LDOA3: I²C-Selectable Output

Voltage From 0.7 V to 1.5 V for up to 600 mA of

Output Current

– Standard Mode (100 kHz)

– Fast Mode (400 kHz)

– Fast Mode Plus (1 MHz)

• VTT LDO for DDR Memory Termination

1.2 Applications

•

Residential Gateway

POS Terminals

•

Programmable Logic Controllers

Embedded PCs

Test and Measurement

Human to Machine Interfaces

1.3 Description

The TPS650860 device is a single-chip power-management IC designed for multicore processors, FPGAs,

and other System-on-Chips (SoCs). The TPS650860 offers an input range of 5.6 V to 21 V, enabling a

wide range of applications. The device is well suited for NVDC and non-NVDC power architecture using

2S, 3S, or 4S Li-Ion battery packs. See the Application Section for 5-V input supplies. The D-CAP2™ and

DCS-Control high-frequency voltage regulators use small inductors and capacitors to achieve a small

solution size. The D-CAP2 and DCS-Control topologies have excellent transient response performance,

which is great for processor core and system memory rails that have fast load switching. An I²C interface

allows simple control either by an embedded controller (EC) or by an SoC. The PMIC comes in an

8-mm × 8-mm, single-row VQFN package with thermal pad for good thermal dissipation and ease of board

routing.

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS650860

VQFN (64)

8.00 mm × 8.00 mm

(1) For more information, see the Mechanical Packaging and Orderable Information section.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS650860

SWCS128A –MARCH 2015–REVISED DECEMBER 2015

www.ti.com

1.4 Functional Block Diagram

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

System Enable or LDO3P3

SW1

CTL2

V1

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

DRVL1

EN

/Ç[3ꢁ{[t9b.1

/Ç[4

EN

FBVOUT1

Control

Inputs

PGNDSNS1

/Ç[ꢀ

ILIM1

/Ç[6ꢁ{[t9b.2

VPULL

VIN

BOOT2

DRVH2

/[Y

I²C CTL

SW2

5!Ç!

SoC

V2

V5ANA

VSET

EN

VPULL

DRVL2

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

Control

Outputs

FBVOUT2

PGNDSNS2

Lwv.

Dt01

Dth2

Dth3

Dth4

FBGND2

ILIM2

Internal

Interrupt

events

V5ANA

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

REGISTERS

3 A

<tDb5_.Ü/Y3>

V5ANA

PVIN4

LX4

BUCK4

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

ë{ò{

VSYS

Digital Core

VSET

EN

V4

V5

ëw9C

FB4

[5hꢀt0

[5h3t3

ëꢀ!b!

3 A

<tDb5_.Ü/Y4>

LDO5V

REFSYS

PVIN5

LX5

BUCK5

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

FB5

3 A

<tDb5_.Ü/Yꢀ>

V5ANA

VIN

Thermal

monitoring

BOOT6

DRVH6

AGND

Thermal shutdown

SW6

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL6

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

VTT_LDO

VDDQ/2

µ 0.5 A

EN

VTT

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

Figure 1-1. PMIC Functional Block Diagram

2

Device Overview

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

Table of Contents

Device Overview ......................................... 1

1

5

Detailed Description ................................... 19

5.1 Overview ............................................ 19

5.2 Functional Block Diagram........................... 20

5.3 SMPS Voltage Regulators .......................... 21

5.4 LDOs and Load Switches ........................... 28

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 2

Revision History ......................................... 3

Pin Configuration and Functions..................... 4

Specifications ............................................ 8

4.1 Absolute Maximum Ratings .......................... 8

4.2 ESD Ratings.......................................... 8

4.3 Recommended Operating Conditions ................ 9

4.4 Thermal Information .................................. 9

2

3

4

5.5

Power Goods (PGOOD or PG) and GPOs ......... 29

5.6 Power Sequencing and VR Control ................. 31

5.7 Device Functional Modes ........................... 35

5.8 I²C Interface ......................................... 35

5.9 Register Maps....................................... 39

Application and Implementation .................... 71

6.1 Application Information .............................. 71

6.2 VIN 5-V Application ................................. 80

6.3 Do's and Don'ts ..................................... 83

Power Supply Coupling and Bulk Capacitors.... 83

Layout .................................................... 83

8.1 Layout Guidelines ................................... 83

8.2 Layout Example ..................................... 84

Device and Documentation Support ............... 85

9.1 Device Support ..................................... 85

9.2 Documentation Support ............................. 85

9.3 Community Resources.............................. 85

9.4 Trademarks.......................................... 85

9.5 Electrostatic Discharge Caution..................... 85

9.6 Glossary ............................................. 85

6

4.5

Electrical Characteristics: Total Current

Consumption.......................................... 9

Electrical Characteristics: Reference and Monitoring

System .............................................. 10

4.6

7

8

4.7

4.8

Electrical Characteristics: Buck Controllers......... 11

Electrical Characteristics: Synchronous Buck

Converters........................................... 12

9

4.9 Electrical Characteristics: LDOs .................... 13

4.10 Electrical Characteristics: Load Switches........... 15

4.11 Digital Signals: I²C Interface ........................ 16

4.12 Digital Input Signals (CTLx)......................... 16

4.13 Digital Output Signals (IRQB, GPOx) ............... 16

4.14 Timing Requirements ............................... 16

4.15 Switching Characteristics ........................... 17

4.16 Typical Characteristics .............................. 18

10 Mechanical, Packaging, and Orderable

Information .............................................. 86

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2015) to Revision A

Page

•

Changed device status from: PRODUCT PREVIEW to: PRODUCTION DATA ............................................. 1

Revision History

3

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

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3 Pin Configuration and Functions

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

FBGND2

FBVOUT2

DRVH2

1

2

3

4

5

6

7

8

9

48 VTTFB

47 VTT

46 PVINVTT

45 ILIM6

SW2

BOOT2

44 FBVOUT6

43 DRVH6

42 SW6

PGNDSNS2

DRVL2

DRV5V_2_A1

LDOA1

41 BOOT6

40 PGNDSNS6

39 DRVL6

38 DRV5V_1_6

37 DRVL1

36 PGNDSNS1

35 BOOT1

34 SW1

TOP VIEW

PGND/Thermal Pad

LX3 10

PVIN3 11

FB3 12

CTL1 13

CTL6/SLPENB2 14

IRQB 15

GPO1 16

33 DRVH1

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

The thermal pad must be connected to the system power ground plane.

Figure 3-1. RSK (VQFN) Pin Map Diagram

4

Pin Configuration and Functions

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

Pin Functions

NO.

NAME

I/O

DESCRIPTION

SMPS REGULATORS

Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output

capacitor.

1

2

FBGND2

I

Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output

capacitor.

FBVOUT2

3

4

DRVH2

SW2

O

I

High-side gate driver output for BUCK2 controller.

Switch node connection for BUCK2 controller.

Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and

SW2 pin.

5

BOOT2

I

6

7

PGNDSNS2

DRVL2

I

Power GND connection for BUCK2. Connect to ground terminal of external low-side FET.

Low-side gate driver output for BUCK2 controller.

O

5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (TYP) ceramic

capacitor. Shorted on board to LDO5P0 pin typically.

8

DRV5V_2_A1

I

10

11

12

20

21

22

23

24

25

29

LX3

O

I

Switch node connection for BUCK3 converter.

PVIN3

FB3

Power input to BUCK3 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.

Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.

Switch node connection for BUCK5 converter.

I

LX5

O

I

PVIN5

FB5

Power input to BUCK5 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.

Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.

Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.

Power input to BUCK4 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor.

Switch node connection for BUCK4 converter.

I

FB4

I

PVIN4

LX4

I

O

I

FBVOUT1

Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor.

Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current

limit of external low-side FET.

30

ILIM1

I

33

34

DRVH1

SW1

O

I

High-side gate driver output for BUCK1 controller.

Switch node connection for BUCK1 controller.

Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and

SW1 pin.

35

BOOT1

I

36

37

PGNDSNS1

DRVL1

I

Power GND connection for BUCK1. Connect to ground terminal of external low-side FET.

Low-side gate driver output for BUCK1 controller.

O

5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (TYP) ceramic

capacitor. Shorted on board to LDO5P0 pin typically.

38

DRV5V_1_6

I

39

40

DRVL6

O

I

Low-side gate driver output for BUCK6 controller.

PGNDSNS6

Power GND connection for BUCK6. Connect to ground terminal of external low-side FET.

Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and

SW6 pin.

41

42

BOOT6

SW6

I

Switch node connection for BUCK6 controller.

Pin Configuration and Functions

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Pin Functions (continued)

NO.

NAME

I/O

DESCRIPTION

SMPS REGULATORS (continued)

43

44

DRVH6

O

I

High-side gate driver output for BUCK6 controller.

FBVOUT6

Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor.

Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current

limit of external low-side FET.

45

64

ILIM6

ILIM2

I

Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current

limit of external low-side FET.

LDO and LOAD SWITCHES

LDOA1 output. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating when

not in use.

9

LDOA1

O

I

Output of load switch B1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave

floating when not in use.

17

18

19

31

32

SWB1

Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (TYP) ceramic capacitor

to improve transient performance. Connect to ground when not in use.

PVINSWB1_B2

SWB2

Output of load switch B2. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave

floating when not in use.

O

I

Output of load switch A1. Bypass to ground with a 0.1-µF (TYP) ceramic capacitor. Leave

floating when not in use.

SWA1

Power supply to load switch A1. Bypass to ground with a 1-µF (TYP) ceramic capacitor to

improve transient performance. Connect to ground when not in use.

PVINSWA1

46

47

48

PVINVTT

VTT

I

O

I

Power supply to VTT LDO. Bypass to ground with a 10-µF (MIN) ceramic capacitor.

Output of load VTT LDO. Bypass to ground with 2× 22-µF (MIN) ceramic capacitors.

Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor.

VTTFB

Output of LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating

when not in use.

49

50

LDOA3

O

I

Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.

Connect to ground when not in use.

PVINLDOA2_A3

Output of LDOA2. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor. Leave floating

when not in use.

51

54

56

LDOA2

O

LDO3P3

LDO5P0

Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (TYP) ceramic capacitor.

Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to

ground with a 4.7-µF (TYP) ceramic capacitor.

External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass

this pin with an optional ceramic capacitor to improve transient performance.

57

V5ANA

I

6

Pin Configuration and Functions

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

Pin Functions (continued)

NO.

NAME

I/O

DESCRIPTION

INTERFACE

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin.

13

CTL1

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a

group of VRs chosen can be entered into (L) or out of (H) sleep state where their output

voltages may be different from those in normal state.

14

15

16

CTL6/SLPENB2

IRQB

I

O

Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be

used as an enable signal to an external VR.

GPO1

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be

used as an enable signal to an external VR.

26

GPO2

O

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

of VRs of any choice or to be controlled by an I²C register bit by the user, which then can be

used as an enable signal to an external VR.

27

28

GPO3

GPO4

O

Open-drain output that can be configured to reflect power good status of VRs of any choice or

to be controlled by an I²C register bit by the user, which then can be used as an enable signal

to an external VR.

58

59

CLK

I

I²C clock

I²C data

DATA

I/O

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin.

60

CTL2

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a

group of VRs chosen can be entered into (L) or out of (H) sleep state where their output

voltages may be different from those in normal state.

61

CTL3/SLPENB1

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin.

62

63

CTL4

CTL5

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin.

REFERENCE

Band-gap reference output. Stabilize it by connecting a 100-nF (TYP) ceramic capacitor

between this pin and quiet ground.

53

52

55

VREF

O

—

I

Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of

VREF capacitor.

AGND

VSYS

System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a

1-µF (TYP) ceramic capacitor.

THERMAL PAD

Thermal pad

—

Connect to PCB ground plane using multiple vias for good thermal and electrical performance.

Pin Configuration and Functions

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4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

ANALOG

VSYS

Input voltage from battery

–0.3

–2⁽²⁾

–1⁽³⁾

–0.3

28

7

V

PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6

V5ANA

6

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

SW1, SW2, SW6

0.3

34

28

7

LX3, LX4, LX5

BOOTx to SWx

Differential voltage

5.5

VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT,

VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1

–0.3

3.6

3.3

V

PVINLDOA2_A3, LDOA2, LDOA3

DIGITAL IOs

DATA, CLK, GPO1-GPO3

CTL1-CTL6, GPO4, IRQB

–0.3

–40

3.6

7

V

T_stg

Storage temperature

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient for less than 5 ns.

(3) Transient for less than 20 ns.

4.2 ESD Ratings

VALUE

UNIT

Human Body Model (HBM),

±1000

V

per ANSI/ESDA/JEDEC JS001⁽¹⁾

Electrostatic discharge (ESD)

performance

V_ESD

Charged Device Model (CDM),

per JESD22-C101⁽²⁾

All pins

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8

Specifications

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

13

MAX UNIT

ANALOG

VSYS

5.6

–0.3

–1

21

V

v

VREF

1.3

PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

DRVL1, DRVL2, DRVL6

5

5.5

0.3

26.5

5.5

V

SW1, SW2, SW6

21

LX3, LX4, LX5

–1

5.5

FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5

LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1

PVINVTT

–0.3

3.6

3.3

FBVOUT6

FBVOUT6 / 2

3.6

1.2 / 1.35

3.3

VTT, VTTFB

PVINSWA1, SWA1

PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2

LDOA2, LDOA3

1.8

1.5

DIGITAL IOs

DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB

CHIP

–0.3

3.3

V

T_A

T_J

Operating ambient temperature range

Operating junction temperature range

–40

27

85

°C

125

4.4 Thermal Information

TPS650860

THERMAL METRIC⁽¹⁾

RSK (VQFN)

64 PINS

25.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

11.3

4.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

4.4

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

4.5 Electrical Characteristics: Total Current Consumption

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PMIC shutdown current that includes I_Qfor

References, LDO5, LDO3P3, and digital core

V_SYS= 13 V, all functional output rails

are disabled

I_SD

65

µA

Specifications

9

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4.6 Electrical Characteristics: Reference and Monitoring System

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE

Bandgap reference Voltage

Accuracy

1.25

V

V_REF

–0.5%

0.047

5.24

0.5%

0.22

5.56

C_VREF

Bandgap output capacitor

VSYS UVLO threshold for LDO5

0.1

5.4

µF

V

V_{SYS_UVLO_5V}

V_SYSfalling

VSYS UVLO threshold hysteresis for V_SYSrising above

V_{SYS_UVLO_5V_HYS}

V_{SYS_UVLO_3V}

200

3.6

mV

V

LDO5

V_{SYS_UVLO_5V}

VSYS UVLO threshold for LDO3P3

V_SYSfalling

3.45

3.75

VSYS UVLO threshold hysteresis for V_SYSrising above

V_{SYS_UVLO_3V_HYS}

150

mV

LDO3P3

V_{SYS_UVLO_3V}

T_CRIT

Critical threshold of die temperature

Hysteresis of T_CRIT

T_Jrising

130

110

145

10

160

120

°C

T_{CRIT_HYS}

T_HOT

T_Jfalling

T_Jrising

Hot threshold of die temperature

Hysteresis of T_HOT

115

10

T_{HOT_HYS}

LDO5

V_IN

T_Jfalling

Input voltage at V_SYSpin

DC output voltage

5.6

4.9

13

5

21

5.1

V

V_OUT

I_OUT= 10 mA

I_OUT

DC output current

100

180

mA

Measured with output shorted to

ground

I_OCP

Overcurrent protection

200

mA

Power Good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTrising

94%

V_{TH_PG_HYS}

I_Q

Power Good deassertion hysteresis

Quiescent current

V_OUTrising or falling

V_IN= 13 V, I_OUT= 0 A

4%

20

µA

µF

C_OUT

External output capacitance

2.7

4.7

10

1

V5ANA-to-LDO5P0 LOAD SWITCH

V_IN= 5 V, measured from

V5ANA pin to LDO5P0 pin at

I_OUT= 200 mA

R_DSON

On resistance

Ω

Power Good threshold for external 5-

V supply

V_{TH_PG}

V_{TH_HYS_PG}

I_LKG

V_V5ANArising

V_V5ANAfalling

4.7

V

Power Good threshold hysteresis for

external 5-V supply

100

mV

µA

Switch disabled,

V_V5ANA= 5 V, V_LDO5= 0 V

Leakage current

10

21

LDO3P3

V_IN

Input voltage at V_SYSpin

DC output voltage

5.6

13

V

I_OUT= 10 mA

3.3

V_OUT

V_IN= 13 V,

I_OUT= 10 mA

Accuracy

–3%

3%

40

I_OUT

I_OCP

DC output current

Overcurrent protection

mA

Measured with output shorted to

ground

70

Power Good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_{TH_PG_HYS}

I_Q

V_OUTrising

V_OUTfalling

92%

3%

20

Power Good deassertion hysteresis

V_IN= 13 V,

I_OUT= 0 A

Quiescent current

µA

µF

C_OUT

External output capacitance

2.2

4.7

10

Specifications

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

4.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, T_A= –40°C to 85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK1, BUCK2, BUCK6

Power input voltage for

external HSD FET

V_IN

5.6

0.41

1⁽¹⁾

13

21

1.67

V

VID step size = 10 mV, BUCKx_VID[6:0]

progresses from 0000001 to 1111111

DC output voltage VID

range and options

VID step size = 25 mV, BUCKx_VID[6:0]

progresses from 0000001 to 1111111

3.575

Set by BUCK1_VID[6:0], 10 mV step size

selected

BUCK1 output voltage

BUCK2 output voltage

BUCK6 output voltage

1.05

3.3

Set by BUCK2_VID[6:0], 25 mV step size

selected

V_OUT

Set by BUCK6_VID[6:0], 10 mV step size

selected

1.5

DC output voltage

accuracy

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 100 mA to 7 A

–2%

2%

40

Total output voltage

accuracy (DC + ripple) in I_OUT= 10 mA, V_OUT≤ 1 V

DCM

–30

2.5

mV

SR(V_OUT

)

Output DVS slew rate

3.125

mV/µs

Low-side output valley

current limit accuracy

(programmed by external

I_{LIM_LSD}

–15%

15%

resistor R_LIM

)

Source current out of

ILIM1 pin

I_LIMREF

V_LIM

T = 25°C

45

0.2

50

55

2.25

µA

V

Voltage at ILIM1 pin

V_LIM= R_LIM× I_LIMREF

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 7 A

ΔV_OUT/ΔV_IN

Line regulation

–0.5%

0.5%

V_IN= 13 V, V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5,

3.3 V, I_OUT= 0 A to 7 A,

ΔV_OUT/ΔI_OUT

Load regulation

0%

1%

referenced to V_OUTat I_OUT= I_{OUT_MAX}

Power Good deassertion V_OUTrising

threshold in percentage

of target V_OUT

105.5%

89.5%

108%

92%

110.5%

94.5%

V_{TH_PG}

V_OUTfalling

Source, IDRVH = –50 mA

3

2

Ω

R_{DSON_DRVH}

Driver DRVH resistance

Driver DRVL resistance

Sink, IDRVH = 50 mA

Source, IDRVL = –50 mA

Sink, IDRVL = 50 mA

BUCK1_DIS[1:0] = 01

BUCK1_DIS[1:0] = 10

BUCK1_DIS[1:0] = 11

3

Ω

R_{DSON_DRVL}

0.4

100

200

500

100

Ω

Output auto-discharge

resistance

R_DIS

Ω

C_BOOT

Bootstrap capacitance

nF

Bootstrap switch ON

resistance

R_{ON_BOOT}

20

Ω

(1) BUCKx_VID[6:0] = 0000001 – 0011000

Specifications

11

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4.8 Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, T_A= –40°C to 85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

BUCK3, BUCK4, BUCK5

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Power input voltage

4.5

5

5.5

V

VID step size = 10 mV,

BUCKx_VID[6:0] progresses from

0000001 to 1111111

0.41

1.67

VID step size = 12.5 mV,

BUCKx_VID[6:0] progresses from

0000001 to 1111111

DC output voltage VID range

and options

0.4125

0.425

1.9875

3.575

V

VID step size = 25 mV,

BUCKx_VID[6:0] progresses from

0000001 to 1111111

Set by BUCK3_VID[6:0], 25-mV step

size selected

BUCK3 output voltage

BUCK4 output voltage

BUCK5 output voltage

1.05

3.3

V_OUT

Set by BUCK4_VID[6:0], 25-mV step

size selected

Set by BUCK5_VID[6:0], 25-mV step

size selected

1.5

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 1.5 A

–2%

2%

2.5%

40

DC output voltage accuracy

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 100 mA

–2.5%

Total output voltage accuracy

(DC + ripple) in DCM

I_OUT= 10 mA, V_OUT≤ 1 V

–30

2.5

mV

SR(V_OUT

)

Output DVS slew rate

Continuous DC output current

HSD FET current limit

Quiescent current

3.125

35

mV/µs

I_OUT

3

7

A

I_{IND_LIM}

I_Q

4.3

–0.5%

–0.2%

V_IN= 5 V, V_OUT= 1 V

µA

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 1.5 A

ΔV_OUT/ΔV_IN

Line regulation

0.5%

2%

V_IN= 5 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8, 2.5, 3.3 V,

I_OUT= 0 A to 3 A, referenced to

V_OUTat I_OUT= 1.5 A

ΔV_OUT/ΔI_OUT

Load regulation

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Power Good reassertion

hysteresis entering back into

V_{TH_PG}

V_{TH_HYS_PG}

V_OUTrising or falling

3%

BUCK3_DIS[1:0] = 01

BUCK3_DIS[1:0] = 10

BUCK3_DIS[1:0] = 11

100

200

500

Output auto-discharge

resistance

R_DIS

Ω

12

Specifications

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

4.9 Electrical Characteristics: LDOs

over recommended input voltage range, T_A= –40°C to 85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDOA1

V_IN

Input voltage

4.5

5

5.5

V

DC output voltage

Accuracy

Set by LDOAx_VID[3:0]

3.3

V_OUT

I_OUT= 0 to 200 mA

–2%

2%

200

V

I_OUT

DC output current

Line regulation

mA

ΔV_OUT/ΔV_IN

I_OUT= 40 mA

–0.5%

–2%

0.5%

2%

ΔV_OUT/ΔI_OUTLoad regulation

I_OUT= 10 mA to 200 mA

V_IN= 5 V, Measured with output

shorted to ground

I_OCP

Overcurrent protection

500

mA

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Measured from EN = H to reach 95%

of final value,

t_STARTUP

Start-up time

500

µs

C_OUT= 4.7 µF

I_Q

Quiescent current

External output capacitance

ESR

I_OUT= 0 A

23

µA

µF

mΩ

Ω

2.7

4.7

10

C_OUT

100

LDOA1_DIS[1:0] = 01

LDOA1_DIS[1:0] = 10

LDOA1_DIS[1:0] = 11

100

190

450

Output auto-discharge

resistance

R_DIS

Ω

LDOA2 and LDOA3

(1)

V_IN

Power input voltage

V_OUT+ V_DROP

1.8

0.7

1.2

1.98

V

LDOA2 DC output voltage

LDOA3 DC output voltage

DC output voltage accuracy

DC output current

Set by LDOAx_VID[3:0]

I_OUT= 0 to 600 mA

V_OUT

–2%

3%

I_OUT

600

mA

mV

V_OUT= 0.99 × V_{OUT_NOM}

I_OUT= 600 mA

,

V_DROP

Dropout voltage

350

ΔV_OUT/ΔV_IN

Line regulation

I_OUT= 300 mA

–0.5%

–2%

0.5%

2%

ΔV_OUT/ΔI_OUTLoad regulation

I_OUT= 10 mA to 600 mA

Measured with output shorted to

ground

I_OCP

Overcurrent protection

0.65

1.25

A

Power Good assertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Measured from EN = H to reach 95%

of final value, C_OUT= 4.7 µF

t_STARTUP

I_Q

Start-up time

500

µs

Quiescent current

I_OUT= 0 A

20

µA

(1) It must be equal to or greater than 1.62 V.

Specifications

13

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Electrical Characteristics: LDOs (continued)

over recommended input voltage range, T_A= –40°C to 85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDOA2 and LDOA3 (continued)

f = 1 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

C_OUT= 2.2 µF – 4.7 µF

48

dB

PSRR

Power supply rejection ratio

f = 10 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

30

C_OUT= 2.2 µF – 4.7 µF

External output capacitance

ESR

2.2

4.7

10

µF

C_OUT

100

mΩ

LDOA2_DIS[1:0] = 01

LDOA2_DIS[1:0] = 10

LDOA2_DIS[1:0] = 11

80

180

475

Output auto-discharge

resistance

R_DIS

Ω

VTT LDO

V_IN

Power input voltage

DC output voltage

1.2

3.3

10

V

V_IN= 1.2 V, Measured at VTTFB pin

V_IN/ 2

Relative to V_IN/ 2, I_OUT≤ 10 mA,

1.1 V ≤ V_IN≤ 1.35 V

–10

V_OUT

DC output voltage accuracy

DC output current

mV

mA

Relative to V_IN/ 2, I_OUT≤ 500 mA,

1.1 V ≤ V_IN≤ 1.35 V

–25

–500

–4%

25

500

4%

I_OUT

sink(–) and source(+)

1.1 V ≤ V_IN≤ 1.35 V,

I_OUT= –500 mA to 500 mA

ΔV_OUT/ΔI_OUTLoad regulation

Measured with output shorted to

ground

I_OCP

Overcurrent protection

0.95

A

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

110%

95%

V_{TH_PG}

Power Good reassertion

hysteresis entering back into

V_{TH_PG}

V_{TH_HYS_PG}

5%

I_Q

Total ground current

V_IN= 1.2 V, I_OUT= 0 A

V_IN= 1.2 V, disabled

240

1

µA

µF

kΩ

Ω

I_LKG

C_IN

C_OUT

OFF leakage current

External input capacitance

External output capacitance

10

35

VTT_DIS = 0

VTT_DIS = 1

1000

60

Output auto-discharge

resistance

R_DIS

80

100

14

Specifications

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

4.10 Electrical Characteristics: Load Switches

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SWA1

V_IN

Input voltage range

DC output current

0.5

1.8

3.3

V

I_OUT

300

mA

V_IN= 1.8 V, measured from PVINSWA1 pin to

SWA1 pin at I_OUT= I_OUT,MAX

60

93

R_DSON

ON resistance

mΩ

V_IN= 3.3 V, measured from PVINSWA1 pin to

SWA1 pin at I_OUT= I_OUT,MAX

100

165

V_OUTrising

V_OUTfalling

108%

92%

Power Good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power Good reassertion hysteresis entering

back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turnon

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

10

mA

µA

10.5

9

I_Q

Quiescent current

V_IN= 1.8 V, I_OUT= 0 A

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

370

900

I_LKG

Leakage current

nA

µF

10

C_OUT

External output capacitance

0.1

100

200

500

SWA1_DIS[1:0] = 01

SWA1_DIS[1:0] = 10

SWA1_DIS[1:0] = 11

R_DIS

Output auto-discharge resistance

Ω

SWB1_2

V_IN

Input voltage range

0.5

1.8

3.3

V

I_OUT

DC current per output

400

mA

V_IN= 1.8 V, measured from PVINSWB1_B2 pin to

SWB1/SWB2 pin at I_OUT= I_OUT,MAX

68

75

92

mΩ

R_DSON

ON resistance

V_IN= 3.3 V, measured from PVINSWB1_B2 pin to

SWB1/SWB2 pin at I_OUT= I_OUT,MAX

125

V_OUTrising

V_OUTfalling

108%

92%

Power Good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power Good reassertion hysteresis entering

back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turning on

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

10

mA

µA

10.5

9

I_Q

Quiescent current

V_IN= 1.8 V, I_OUT= 0 A

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

460

I_LKG

Leakage current

nA

µF

10

1150

C_OUT

External output capacitance

0.1

100

200

500

SWBx_DIS[1:0] = 01

SWBx_DIS[1:0] = 10

SWBx_DIS[1:0] = 11

R_DIS

Output auto-discharge resistance

Ω

Specifications

15

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4.11 Digital Signals: I²C Interface

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

High-level input voltage

Low-level input voltage

Leakage current

TEST CONDITIONS

V_{PULL_UP}= 1.8 V

MIN

TYP

MAX UNIT

V_OL

V_IH

V_IL

0.4

V

1.2

0.4

0.3

8.5

2.5

1

V

I_LKG

V_{PULL_UP}= 1.8 V

Standard mode

Fast mode

0.01

µA

R_PULL-UPPullup resistance

kΩ

Fast mode plus

C_OUT

Total load capacitance per pin

50

pF

4.12 Digital Input Signals (CTLx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

High-level input voltage

Low-level input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

0.85

V

0.4

V

4.13 Digital Output Signals (IRQB, GPOx)

Over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

Leakage current

TEST CONDITIONS

I_OL< 2 mA

V_{PULL_UP}= 1.8 V

MIN

TYP

MAX UNIT

V_OL

I_LKG

0.4

V

0.35

µA

4.14 Timing Requirements

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

MIN

NOM

MAX

UNIT

I²C INTERFACE

Clock frequency (standard mode)

100

400

kHz

ns

f_CLK

Clock frequency (fast mode)

Clock frequency (fast mode plus)

Rise time (standard mode)

Rise time (fast mode)

1000

300

t_r

ns

Rise time (fast mode plus)

Rise time (standard mode)

Rise time (fast mode)

120

ns

300

ns

t_f

300

ns

Rise time (fast mode plus)

120

ns

16

Specifications

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

4.15 Switching Characteristics

over operating free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK CONTROLLERS

Measured from enable going high to when output reaches

90% of target value.

t_PG

Total turnon time

550

50

850

µs

ns

Minimum on-time of

DRVH

T_ON,MIN

DRVH off to DRVL on

DRVL off to DRVH on

15

30

ns

T_DEAD

f_SW

Driver dead-time

Continuous-conduction mode,

V_IN= 13 V, V_OUT≥ 1 V

Switching frequency

1000

kHz

BUCK CONVERTERS

t_PGTotal turnon time

Measured from enable going high to when output reaches

90% of target value.

250

1000

µs

Continuous-conduction mode, V_OUT= 1 V, I_OUT= 1 A

Continuous-conduction mode, V_OUT= 1.05 V, I_OUT= 1 A

Continuous-conduction mode, V_OUT= 1.8 V, I_OUT= 1 A

1.7

1.9

2.5

MHz

f_SW

Switching frequency

LDOAx

Measured from enable going high to when output reaches

95% of final value,

V_OUT= 1.2 V, C_OUT= 4.7 µF

t_STARTUP

Start-up time

180

22

µs

VTT LDO

t_STARTUP

SWA1

Measured from enable going high to PG assertion,

V_OUT= 0.675 V, C_OUT= 40 µF

Measured from enable going high to reach 95% of final

value,

0.85

0.63

ms

V_IN= 3.3 V, C_OUT= 0.1 µF

t_TURN-ON

SWB1_2

t_TURN-ON

Turnon time

Measured from enable going high to reach 95% of final

value,

V_IN= 1.8 V, C_OUT= 0.1 µF

Measured from enable going high to reach 95% of final

value,

V_IN= 3.3 V, C_OUT= 0.1 µF

1.1

ms

Turnon time

Measured from enable going high to reach 95% of final

value,

0.82

V_IN= 1.8 V, C_OUT= 0.1 µF

Specifications

17

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4.16 Typical Characteristics

Measurements done at 25°C.

Figure 4-1. BUCK2 Controller Start Up

Figure 4-2. BUCK3 Converter Start Up

100%

95%

90%

85%

80%

75%

70%

65%

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

Vout = 1 V

60%

55%

50%

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

0.1

0.2 0.3 0.40.5 0.7

1

2

3

4

5 6 7

0.1

0.2 0.3 0.40.5 0.7

1

2

3

4 5 6 7

Iout (A)

D011

D012

Figure 4-3. BUCK1 Efficiency at V_IN= 13 V

Figure 4-4. BUCK1 Efficiency at V_IN= 18 V

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

Vout = 1 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

0.1

0.2

0.3 0.4 0.5 0.7

Iout (A)

1

2

3

D009

Figure 4-5. BUCK3 Efficiency at V_IN= 5 V

18

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5 Detailed Description

5.1 Overview

The TPS650860 power-management integrated circuit (PMIC) provides a highly flexible and configurable

power solution that can power a wide array of processors along with DDR3/DDR4 memory and other

peripherals. Integrated in the PMIC are three step-down controllers (BUCK1, BUCK2, and BUCK6), three

step-down converters (BUCK3, BUCK4, and BUCK5), a sink or source LDO (VTT LDO), three low-voltage

V_INLDOs (LDOA1–LDOA3), and three load switches (SWA1, SWB1, and SWB2). With on-chip one-time

programmable (OTP) memory, configuration of each rail for default output value, power-up sequence, fault

handling, and power good mapping into a GPO pin are all conveniently flexible. All VRs have a built-in

discharge resistor, and the value can be changed using the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL

registers. When enabling a VR, the PMIC automatically disconnects the discharge resistor for that rail

without any I²C command. Table 5-1 summarizes the key characteristics of the voltage rails.

Table 5-1. Summary of Voltage Regulators

INPUT VOLTAGE (V)

OUTPUT VOLTAGE RANGE (V)

CURRENT

(mA)

RAIL

BUCK1

TYPE

Step-down

MIN

MAX

MIN

TYP

MAX

OTP-

programmable

4.5

21

0.41

0.7

3.575

3.3

scalable

3000

Controller

Step-down

Controller

OTP-

programmable

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

LDOA1

LDOA2

LDOA3

4.5

21

5.5

21

Step-down

Converter

OTP-

programmable

Step-down

Converter

OTP-

programmable

4.5

3000

Step-down

Converter

OTP-

programmable

4.5

3000

Step-down

Controller

OTP-

programmable

4.5

scalable

200⁽¹⁾

600

OTP-

programmable

LDO

4.5

5.5

1.98

OTP-

programmable

1.62

0.7

1.5

OTP-

programmable

0.7

1.5

600

SWA1

Load Switch

0.5

3.3

300

SWB1/SWB2

Sink and Source

LDO

VTT

BUCK6 output

V_BUCK6/ 2

500

(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max I_OUTof LDO5.

Detailed Description

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5.2 Functional Block Diagram

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

System Enable or LDO3P3

SW1

CTL2

V1

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

DRVL1

EN

/Ç[3ꢁ{[t9b.1

/Ç[4

EN

FBVOUT1

Control

Inputs

PGNDSNS1

/Ç[ꢀ

ILIM1

/Ç[6ꢁ{[t9b.2

VPULL

VIN

BOOT2

DRVH2

/[Y

I²C CTL

SW2

5!Ç!

SoC

V2

V5ANA

VSET

EN

VPULL

DRVL2

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

Control

Outputs

FBVOUT2

PGNDSNS2

Lwv.

Dt01

Dth2

Dth3

Dth4

FBGND2

ILIM2

Internal

Interrupt

events

V5ANA

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

REGISTERS

3 A

<tDb5_.Ü/Y3>

V5ANA

PVIN4

LX4

BUCK4

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

ë{ò{

VSYS

Digital Core

VSET

EN

V4

V5

ëw9C

FB4

[5hꢀt0

[5h3t3

ëꢀ!b!

3 A

<tDb5_.Ü/Y4>

LDO5V

REFSYS

PVIN5

LX5

BUCK5

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

FB5

3 A

<tDb5_.Ü/Yꢀ>

V5ANA

VIN

Thermal

monitoring

BOOT6

DRVH6

AGND

Thermal shutdown

SW6

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL6

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

VTT_LDO

VDDQ/2

µ 0.5 A

EN

VTT

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

Figure 5-1. PMIC Functional Block Diagram

20

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5.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set

by an external resistor at ILIMx pin), which allows for optimal selection of external passive components

based on the desired system load. The buck converters include integrated power stage and require a

minimum number of pins for power input, inductor, and output voltage feedback input. Combined with

high-frequency switching, all these features allow use of inductors in small form factor, thus reducing total-

system cost and size.

BUCK1–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the

BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM

depending on the output load to maximize efficiency.

All controllers and converters can be set to default V_OUTor dynamically voltage changing at any time. This

means that the rails can be programmed for any V_OUTby the factory, so the device starts up with the

default voltage, or during operation the rail can be programmed to another operating V_OUTwhile the rail is

enable or disabled. There are two step sizes or ranges available for V_OUTselection: 10-mV and 25-mV

steps. The step-size range must be selected prior to use and must be programmed by the factory. It is not

subject to programming or change during operation.

For the 10-mV step-size range V_OUToptions, refer to the Table 5-2. For the 25-mV step-size range V_OUT

options, refer to the Table 5-3.

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Table 5-2. 10-mV Step-Size V_OUTRange

VID Bits

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

V_OUT

0

VID Bits

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

V_OUT

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

1.25

VID Bits

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

V_OUT

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

1.38

1.39

1.40

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

1.56

1.57

1.58

1.59

1.60

1.61

1.62

1.63

1.64

1.65

1.66

1.67

0.41

0.42

0.43

0.44

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

22

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Table 5-3. 25-mV Step-Size V_OUTRange

V_OUT

(Converters)

V_OUT

(Controllers)

VID Bits

V_OUT

VID Bits

V_OUT

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

2.025

2.050

2.075

2.100

2.125

2.150

2.175

2.200

2.225

2.250

2.275

2.300

2.325

2.350

2.375

2.400

2.425

2.450

2.475

2.500

2.525

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

2.550

2.575

2.600

2.625

2.650

2.675

2.700

2.725

2.750

2.775

2.800

2.825

2.850

2.875

2.900

2.925

2.950

2.975

3.000

3.025

3.050

3.075

3.100

3.125

3.150

3.175

3.200

3.225

3.250

3.275

3.300

3.325

3.350

3.375

3.400

3.425

3.450

3.475

3.500

3.525

3.550

3.575

0.425

0.450

0.475

0.500

0.525

0.550

0.575

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

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5.3.1 Controller Overview

The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two

external N-MOSFETs. They are D-CAP2 controller scheme that optimizes transient responses at high load

currents for such applications as CORE and DDR supplies. The output voltage is compared with internal

reference voltage after divider resistors. The PWM comparator determines the timing to turn on the high-

side MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage.

Because the device does not have a dedicated oscillator for control loop on board, switching cycle is

controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency

by feed-forwarding the input and output voltage into the on-time one-shot timer.

The D-CAP2 control scheme has an injected ripple from the SW node that is added on to the reference

voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP™

mode control. Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used

with the controllers.

TPS65086x

Controllers

VDD

V_REFœ V_{TH_PG}

+

UV

PGOOD

FAULT

EN

PGOOD

+

DCHG

VFB

OV

V_REF+V_{TH_PG}

+

Control Logic

PWM

Ramp Generator

+

BOOT

REF

SS Ramp Comp

DRVH

SW

HS

VSYS

XCON

OC

+

VDRV

50 µA

ILIM

+

LS

DRVL

PGND

NOC

+

One-Shot

GND

+

ZC

UDG-12093

Figure 5-2. Controller Block Diagram

24

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5.3.2 Converter Overview

The PMIC synchronous step-down DCDC converters include a unique hysteretic PWM controller scheme

which enables a high switching frequency converter, excellent transient and AC load regulation as well as

operation with cost-competitive external components. The controller topology supports forced PWM mode

as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent

current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In

forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows

filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage

options featuring smallest solution size by using only three external components per converter.

A significant advantage of PMIC compared to other hysteretic PWM controller topologies is its excellent

AC load transient regulation capability. When the output voltage falls below the threshold of the error

comparator, a switch pulse is initiated, and the high-side switch is turned on. It remains turned on until a

minimum ON-time of t_ONminexpires and the output voltage trips the threshold of the error comparator or

the inductor current reaches the high-side switch current limit. When the high-side switch turns off, the

low-side switch rectifier is turned on and the inductor current ramps down until the high-side switch turns

on again or the inductor current reaches zero. In forced PWM mode operation, negative inductor current is

allowed to enable continuous conduction mode even at no load condition.

VIN

VREF

0.40 V

Current

Limit Comparator

Bandgap

Limit

High Side

MODE

Softstart

MODE

NMOS

VIN

FB

Gate Driver

Anti

Shoot-Through

Min. On Time

Control

Logic

SW

EN

FB

Min. OFF Time

VREF

Limit

Low Side

Integrated

Feed Back

Network

Error

Comparator

Zero/Negative

Current Limit Comparator

GND

Figure 5-3. Converter Block Diagram

Detailed Description

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5.3.3 DVS

BUCK1–BUCK6 support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs

can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID) defined in

Section 4.7 and Section 4.8. DVS slew rate is minimum 2.5 mV/µs. In order to meet the minimum slew

rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV or at 6-µs interval per 25-mV

steps. When DVS is active, the VR is forced into PWM mode, unless BUCKx_DECAY = 1, to ensure the

output keeps track of VID code with minimal delay. Additionally, PGOOD is masked when DVS is in

progress. An example of slew down and up from one VID to another (step size of 10 mV) is depicted in

Figure 5-4.

VID

Number of Steps x 3 µs

V_OUT

Figure 5-4. DVS Timing Diagram I (BUCKx_DECAY = 0)

As illustrated in Figure 5-5, if a BUCKx_VID[6:0] is set to 7b000 0000, its output voltage will slew down to

0.5 V first, and then will drift down to 0 V as the SMPS stops switching. Subsequently, if a

BUCKx_VID[6:0] is set to a value (neither 7b000 0000 nor 7b000 0001) when its output voltage is less

than 0.5 V, the VR will ramp up to 0.5 V first with soft-start kicking in, then will slew up to target voltage in

the slew rate aforementioned. It must be noted that a fixed 200 µs of soft-start time is reserved for V_OUTto

reach 0.5 V. In this case, however, the SMPS is not forced into PWM mode as it otherwise could cause

V_OUTto droop momentarily if V_OUTmight have been drifting above 0.5 V for any reason.

VID

Number of Steps x 3 µs

V_OUT

200 µs

load and time dependent

Figure 5-5. DVS Timing Diagram II (BUCKx_DECAY = 0)

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5.3.4 Decay

In addition to DVS, BUCK1–BUCK6 can decay down to a lower voltage when BUCKx_DECAY bit in

BUCKxCTRL register is set to 1. Decay mode is only used in a downward direction of VID. The VR does

not control slew rate. As both high-side and low-side FETs stop switching, the output voltage ramps down

naturally, dictated by current drawn from the load and output filtering capacitance. When the VR is in the

middle of decay down its PGOOD is masked until V_OUTfalls below the over-voltage (OV) threshold of the

set VID value. Shown in Figure 5-6 are two cases that differ from each other as to whether V_OUThas

reached the target voltage corresponding to a new VID when the VR is commanded to slew back up to a

higher voltage. In case that V_OUThas not decayed down below VID as denoted case 2, the VR will wait for

VID to catch up, and then V_OUTwill start ramping up to keep up with the VID ramp.

VID

V_OUT

case 2

case 1

Figure 5-6. Decay Down to a Lower V_OUTand Slew Up

VID

V_OUT

case 2

200 us

case 1

Figure 5-7. Decay Down to 0 V and Slew Up

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5.3.5 Current Limit

The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the

current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for

a desired resistor value, depending on specific application conditions. I_LIMREFis the current source out of

the ILIMx pin that is typically 50 µA, and R_DSONis the maximum channel resistance of the low-side FET.

the scaling factor is 1.3 to take into account all errors and temperature variations of R_DSON, I_LIMREF, and

R_ILIM. Finally, 8 is another scaling factor associated with I_LIMREF

.

I_ripple,min

R_DSONì8ì1.3ì(I_LIM

-

)

2

R_ILIM

=

I_LIMREF

where

•

I_LIMis the target current limit. An appropriate margin must be allowed when determining I_LIMfrom maximum

output DC load current.

•

I_ripple,minis the minimum peak-to-peak inductor ripple current for a given V_OUT

.

(1)

V_out(v_in,min- V_out

)

I_ripple,min

=

L_maxì V_in,minì ƒ_sw,max

where

•

L_maxis maximum inductance

f_sw,maxis maximum switching frequency

V_in,minminimum input voltage to the external power stage

(2)

The buck converter limit inductor peak current cycle-by-cycle to I_{IND_LIM}is specified in Section 4.8.

5.4 LDOs and Load Switches

5.4.1 VTT LDO

Powered from the BUCK6 output , VTT LDO tracks V_BUCK6by regulating its output to a half of its input.

The LDO is capable of sinking and sourcing current up to 500 mA, and it is designed specifically to power

DDR memory. The LDO core is a transconductance amplifier with large gain, and it drives a current output

stage that either sources or sinks current depending on the deviation of VTTFB pin voltage from the target

regulation voltage.

5.4.2 LDOA1–LDOA3

The TPS65086x device integrates three general purpose LDOs. LDOA1 is powered from a 5-V supply

through the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail as long as a valid

power supply is available at VSYS. See Table 5-4 for LDOA1 output voltage options. LDOA2 and LDOA3

share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to

LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See Table 5-5 for LDOA2 and LDOA3 output voltage

options. LDOA1 is controlled by LDOA1CTRL register.

Table 5-4. LDOA1 Output Voltage Options

VID Bits

0000

V_OUT

1.35

1.5

VID Bits

0100

V_OUT

1.8

VID Bits

1000

V_OUT

2.3

VID Bits

1100

V_OUT

2.85

0001

0101

1.9

1001

2.4

1101

3.0

0010

1.6

0110

2.0

1010

2.5

1110

3.3

0011

1.7

0111

2.1

1011

2.6

1111

Not Used

28

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Table 5-5. LDOA2 and LDOA3 Output Voltage Options

VID Bits

0000

V_OUT

0.70

0.75

0.80

0.85

VID Bits

0100

V_OUT

0.90

0.95

1.00

1.05

VID Bits

1000

V_OUT

1.10

1.15

1.20

1.25

VID Bits

1100

V_OUT

1.30

1.35

1.40

1.50

0001

0101

1001

1101

0010

0110

1010

1110

0011

0111

1011

1111

5.4.3 Load Switches

The PMIC features three general purpose load switches. SWA1 has its own power input pin (PVINSWA1),

while SWB1 and SWB2 share one power input pin (PVINSWB1_B2). All switches have built-in slew rate

control during startup to limit the inrush current.

5.5 Power Goods (PGOOD or PG) and GPOs

The device provides information on status of VRs through four GPO pins along with Power-Good Status

registers defined in Section 5.9.49 and Section 5.9.50. Power-good information of any individual VR and

load switch can be assigned to be part of the PGOOD tree as defined from Section 5.9.39 to

Section 5.9.46. PGOOD assertion delays are programmable from 0 ms to 15 ms for GPO1 and 0 ms to

100 ms for GPO2–GPO4, respectively, as are defined in Section 5.9.20 and Section 5.9.33.

Detailed Description

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.Ü/Y1_tD

.Ü/Y1_tD_a!{Y

.Ü/Y2_tD

.Ü/Y2_tD_a!{Y

.Ü/Y3_tD

.Ü/Y3_tD_a!{Y

.Ü/Y4_tD

.Ü/Y4_tD_a!{Y

.Ü/Y5_tD

.Ü/Y5_tD_a!{Y

.Ü/Y6_tD

.Ü/Y6_tD_a!{Y

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{í!1_tD_a!{Y

[ꢀh!2_tD

[ꢀh!2_tD_a!{Y

selecꢂꢃꢄle ms

wising

9dge

[ꢀh!3_tD

{ò{Ç9a tD

[ꢀh!3_tD_a!{Y

ꢀelꢃy

{í.1_tD

{í.1_tD_a!{Y

{í.2_tD

{í.2_tD_a!{Y

ëÇÇ_tD

ëÇÇ_tD_a!{Y

/Çw[1

/Çw[1_a!{Y

/Çw[2

/Çw[2_a!{Y

/Çw[3ꢁ{[t9b.1

/Çw[3_a!{Y

/Çw[4

/Çw[4_a!{Y

/Çw[5

/Çw[5_a!{Y

/Çw[6ꢁ{[t9b.2

/Çw[6_a!{Y

Figure 5-8. Power Good Tree

Alternatively, the GPOs can be used as general purpose outputs controlled by the user via I²C. Refer to

the I2C_RAIL_EN2/GPOCTRL Register Description for details on controlling the GPOs in I²C control

mode.

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5.6 Power Sequencing and VR Control

The device has 3 different ways of sequencing the rails during power up and power down:

•

Rail enabled by CTLx pin

Rail enabled by power good, (PG), of prior enabled rail

Rail enabled by I²C software command

A delay can be added from any CTLx pin or PG to the enable of the subjected enabled rail. This creates a

very flexible device capable of many sequence options. If a rail cannot be sequenced automatically, any

rail can be enabled or disabled via I²C command.

5.6.1 CTLx Sequencing

The device has six control-input pins (CTL1–CTL6) to control six SMPS regulators, three LDO regulators,

and three load switches. This allows the user to define up to six distinctive groups, to which each VR can

be assigned for highly flexible power sequencing. Of the six CTLx pins, CTL3 and CTL6 can be configured

alternatively to active-low sleep enable pins. For instance, if a system level SLEEP state is defined such

that BUCK1 output regulation voltage is lower than in the normal mode, then BUCK2 SLEEP state can be

assigned to CTL3 or CTL6. By being pulled low, either CTL3 or CTL6 can be used to put BUCK1 into

SLEEP state, and BUCK1 will regulate its output at a voltage defined by BUCK1_SLP_VID[6:0] in

Section 5.9.22. In the example Section 5.6.4, see how the BUCK1 is enabled from CTL1 pin for a

demonstration of this feature.

5.6.2 PG Sequencing

Any rail can be sequenced by the power good of a prior rail. This can be combined with the CTLx method

to allow for further sequence control and create more distinctive groups of enables than the 6 from CTLx.

This also allows some of the CTLx pins to be freed up for other purposes such as logic input gates. In the

example Section 5.6.4, see how the BUCK5 is enabled from the BUCK4 PG for a demonstration of this

feature.

5.6.3 Enable Delay

A delay can be added to the enable of any rail after the desired CTLx & PGs are met. This allows for the

option to create additional timing groups from either CTLx pins or internal PGs. In the example

Section 5.6.4, see how the BUCK2 and BUCK6 are enabled after BUCK1 from CTL1 pin for a

demonstration of this feature.

5.6.4 Power Up Sequence

When a valid power supply is detected at the VSYS pin as V_SYScrosses above V_{SYS_UVLO_5V}

+

V_{SYS_UVLO+5V_HYS}, the power-up sequence is initiated by driving one of the control input pins high, followed

by the rest of pins in order. Illustrated in Figure 5-9 is an example where CTL1–CTL4 are defined to

control four groups of VRs, while GPO1–GPO4 are defined to provide a PGOOD status of each group.

The control input pins do not necessarily have to be pulled up in a staggered manner. For instance, if

CTL2 is pulled up from the preceding group of VRs before PGOOD has been asserted at GPO1, the

BUCK4 enable will be delayed until the PGOOD is asserted.

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5.6 V

VSYS

LDO5/LDO3P3

LDOA1/GPO1

I²C Available

CTL1

BUCK1

BUCK2

BUCK6

CTL2

2 ms

4 ms

BUCK3

BUCK4

BUCK5

GPO4

CTL4

PG of all BUCKs

LDOA2

LDOA3

GPO3

CTL5

16 ms

PG of BUCKs and LDOs

SWA1

SWB1

SWB2

CTL6

2 ms

8 ms

VTT

Figure 5-9. TPS650860 Power Up Sequence Example

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5.6.5 Power Down Sequence

The power down sequence can follow the CTLx pins, or be controlled with the I²C commands. If the

internal PGs are used for sequencing or if some rails need to ramp down before others a delay can be

added to the de-assertion low of the internal enable of the subjected rail. This delay can be independent of

the power up delay option. Thus, power up and power down sequences can be different of each other or

relatively similar to match most applications' sequences.

Refer to Figure 5-10 for an example of a power down sequence demonstrating the delay disable of

BUCK1 and BUCK2.

CTL6

VTT

CTL5

CTL4

LDOA1

LDOA2

SWA1

SWB1

SWB2

CTL2

BUCK3

BUCK4

BUCK5

CTL1

BUCK6

2 ms

BUCK2

4 ms

BUCK1

Figure 5-10. TPS650860 Power Down Sequence Example

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5.6.6 Sleep State Entry and Exit

Normal State

Sleep State

Normal State

1.8 V

CTL6

0 V

1.8 V

CTL1-CTL4

1.8V

GPO1-GPO4

BUCK1_VID

BUCK1_DECAY = 1

BUCK1

BUCK1_SLP_VID

BUCK1_DECAY = 0

Figure 5-11. Connected Standby Entry and Exit Sequence

Section 5.6.6 illustrates an example where BUCK1 is defined to enter Sleep State in response to CTL6

going low.

NOTE

All PGOODs from GPO1–GPO4 stay asserted during the entry and the exit. Depending on

status of the BUCK1_DECAY bit defined in the BUCK1CTRL register, BUCK1 output will

either decay or slew down to a new voltage defined in BUCK1_SLP_VID[6:0].

5.6.7 Emergency Shutdown

5.4 V

VSYS

GPOx

444 ns (nominal with +/- 1-% variation

BUCKx

LDOAx

SWx

VTT

Figure 5-12. Emergency Shutdown Sequence

When V_SYScrosses below V_{SYS_UVLO_5V}, all power good pins will be deasserted, and after 444 ns (nom) of

delay all VRs will shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure

timely decay of all VR outputs. Other conditions that will cause emergency shutdown are the die

temperature rising above the critical temperature threshold (T_CRIT), and de-assertion of power good of any

rail (configurable).

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5.7 Device Functional Modes

5.7.1 Off Mode

When power supply at the VSYS pin is less than V_{SYS_UVLO_5V}(5.4-V nominal) + V_{SYS_UVLO_5V_HYS}(0.2-V

nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than

V_{SYS_UVLO_3V}(3.6-V nominal) + V_{SYS_UVLO_3V_HYS}(0.15-V nominal) while it is still less than V_{SYS_UVLO_5V}

+

V_{SYS_UVLO_5V_HYS}, then the internal bandgap reference (VREF pin) along with LDO3P3 are enabled and

regulated at target values.

5.7.2 Standby Mode

When power supply at the VSYS pin rises above V_{SYS_UVLO_5V}+ V_{SYS_UVLO_5V_HYS}, the device enters

standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and

I²C interface and CTL pins are ready to respond. All default registers defined in Section 5.9 should have

been loaded from one-time programmable (OTP) memory by now. Quiescent current consumption in

standby mode is specified in Section 4.5.

5.7.3 Active Mode

The device proceeds to active mode when any output rail is enabled either via an input pin as discussed

in Section 5.6 or by writing to EN bits via I²C. Output regulation voltage can also be changed by writing to

VID bits defined in Section 5.9.

5.8 I²C Interface

The I²C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see

I²C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA)

and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled

high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, DATA and CLK. A

master device, usually a microcontroller or a digital signal processor, controls the bus. The master is

responsible for generating the SCL signal and device addresses. The master also generates specific

conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits

data on the bus under control of the master device.

The TPS650860 device works as a slave and supports the following data transfer modes, as defined in

the I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode

(1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents

are loaded when V_SYShigher than V_{SYS_UVLO_5V}is applied to the TPS650860 device. The I²C interface is

running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred

to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it

is referred to as H/S-mode.

The TPS650860 device supports 7-bit addressing; however, 10-bit addressing and general call address

are not supported. The default device address is 0x5E.

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5.8.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high (see Figure 5-13). All I²C-compatible devices should

recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse (see

Figure 5-14). All devices recognize the address sent by the master and compare it to their internal fixed

addresses. Only the slave device with a matching address generates an acknowledge (see Figure 5-15),

by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this

acknowledge, the master knows that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data

from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the

transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on

which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can

continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from

low to high while the SCL line is high (see Figure 5-13). This releases the bus and stops the

communication link with the addressed slave. All I²C-compatible devices must recognize the stop

condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for

a start condition followed by a matching address.

SDA

SCL

S

P

START

STOP

Condition

Figure 5-13. START and STOP Conditions

SDA

SCL

Data valid

Change of data allowed

Figure 5-14. Bit Transfer on the I²C Bus

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Data Output at

Transmitter

Not ACK

ACK

Data Output at

Receiver

SCL from

Master

1

2

8

9

S

START

Condition

Clock pulse for ACK

Figure 5-15. Acknowledge on the I²C Bus

Generate ACK signal

SDA

MSB

ACK signal from slave

Address

R/W

SCL

1

2

7

8

9

1

2

3-8

9

ACK

Byte complete, interrupt

within slave

Clock line held low while

interrupts are serviced

S or Sr

P or Sr

START or

STOP or

Repeated START Condition

Figure 5-16. I²C Bus Protocol

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SCL

SDA

A6 A5 A4

A0 R/W ACK

R7 R6 R5

R0 ACK

0

D7 D6 D5

D0 ACK

0

START

Slave Address

Register Address

Data

STOP

Figure 5-17. I²C Interface WRITE to TPS650860 in F/S Mode

SCL

SDA

A6

A0 R/W ACK

R7

R0 ACK

0

A6

A0 R/W ACK D7

D0 ACK

0

1

0

Master

drives ACK

and Stop

Slave drives

the Data

Slave Address

START

Slave Address

Register Address

STOP

Repeated

START

Figure 5-18. I²C Interface READ from TPS650860 in F/S Mode

(Only Repeated START is Supported)

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5.9 Register Maps

5.9.1 Register Map Summary

Table 5-6. Register Map Summary

Address Hex Value

Name

DEVICEID

Short Description

Device ID code indicating revision

1h

2h

IRQ

Interrupt statuses

3h

IRQ_MASK

Interrupt masking

4h

PMIC_STAT

SHUTDNSRC

BUCK1CTRL

BUCK2CTRL

BUCK3DECAY

BUCK3VID

PMIC temperature indicator

Shutdown root cause indicator bits

BUCK1 decay control and voltage select

BUCK2 decay control and voltage select

BUCK3 decay control

5h

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

40h

41h

42h

BUCK3 voltage select

BUCK3SLPCTRL

BUCK4CTRL

BUCK5CTRL

BUCK6CTRL

LDOA2CTRL

LDOA3CTRL

DISCHCTRL1

DISCHCTRL2

DISCHCTRL3

BUCK3 voltage select for sleep state

BUCK4 control

BUCK5 control

BUCK6 control

LDOA2 control

LDOA3 control

Discharge resistors for each rail control

System power good on GPO3 (if GPO3 is programmed to

be system PG)

43h

PG_DELAY1

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

FORCESHUTDN

BUCK1SLPCTRL

BUCK2SLPCTRL

BUCK4VID

Software force shutdown

BUCK1 voltage select for sleep state

BUCK2 voltage select for sleep state

BUCK4 voltage select

BUCK4SLPVID

BUCK5VID

BUCK4 voltage select for sleep state

BUCK5 voltage select

BUCK5SLPVID

BUCK6VID

BUCK5 voltage select for sleep state

BUCK6 voltage select

BUCK6SLPVID

LDOA2VID

BUCK6 voltage select for sleep state

LDOA2 voltage select

LDOA3VID

LDOA3 voltage select

BUCK123CTRL

BUCK1, 2, and 3 disable and PFM/PWM mode control

System power good on GPO1, 2, and 4 (if GPOs is

programmed to be system PG)

9Dh

PG_DELAY2

9Fh

A0h

SWVTT_DIS

SWs & VTT I²C disable bits

I²C Enable control of individual rails

I2C_RAIL_EN1

I²C Enable control of individual rails and I²C controlled

GPOs, high or low

A1h

I2C_RAIL_EN2/GPOCTRL

A2h

A3h

A4h

A5h

A6h

A7h

A8h

PWR_FAULT_MASK1

PWR_FAULT_MASK2

GPO1PG_CTRL1

GPO1PG_CTRL2

GPO4PG_CTRL1

GPO4PG_CTRL2

GPO2PG_CTRL1

Power fault masking for individual rails

Power good tree control for GPO1

Power good tree control for GPO4

Power good tree control for GPO2

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Table 5-6. Register Map Summary (continued)

Address Hex Value

Name

Short Description

Power good tree control for GPO2

Power good tree control for GPO3

A9h

AAh

ABh

ACh

GPO2PG_CTRL2

GPO3PG_CTRL1

GPO3PG_CTRL2

MISCSYSPG

Power good tree control with CTL3 and CTL6 for GPO

LDOA1 control for discharge, voltage selection, and

enable

AEh

LDOA1CTRL

B0h

B1h

B2h

B3h

B4h

B5h

PGSTATUS1

PGSTATUS2

Power good statuses for individual rails

Power fault statuses for individual rails

Critical temperature indicators

PWR_FAULT_STATUS1

PWR_FAULT_STATUS2

TEMPCRIT

TEMPHOT

Hot temperature indicators

The user must not attempt to write a RESERVED R/W bit to the opposite value.

5.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = OTP-

Programmable]

Figure 5-19. DEVICEID Register

Bit

7

6

5

4

3

2

1

0

OTP_

PART_

NUMBER[2]

PART_

NUMBER[1]

PART_

NUMBER[0]

Bit Name

REVID[1]

REVID[0]

VERSION[1] VERSION[0] NUMBER[3]

TPS650860

Access

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-7. DEVICEID Register Descriptions

Bit

7-6

5-4

Field

Type Reset

Description

REVID[1:0]

OTP_VERSION[1:0]

R

OTP-Programmable

Silicon revision ID

OTP variation ID

00: A

01: B

10: C

11: D

3-0

PART_NUMBER[3:0]

R

OTP-Programmable

Device part number ID

0000: TPS650860

0001: TPS650861

...

1111: TPS65086F

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5.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0000 0000]

Figure 5-20. IRQ Register

Bit

7

FAULT

0

6

5

4

3

SHUTDN

0

2

1

0

DIETEMP

0

Bit Name

TPS650860

Access

RESERVED

0

R/W

R

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-8. IRQ Register Descriptions

Bit

Field

Type Reset

Description

7

FAULT

R/W

0

Fault interrupt. Asserted when either condition occurs: power fault of any rail, or

die temperature crosses over the critical temperature threshold (T_CRIT). The

user can read Reg. 0xB2–0xB6 to determine what has caused the interrupt.

0: Not asserted

1: Asserted. Host to write 1 to clear.

3

0

SHUTDN

DIETEMP

R/W

0

Asserted when PMIC shuts down. To clear indicator, SHUTDNSRC must be

cleared first, see Section 5.9.6

0: Not asserted.

1: Asserted. Host to write 1 to clear.

Die temp interrupt. Asserted when PMIC die temperature crosses above the hot

temperature threshold (T_HOT).

0: Not asserted.

1: Asserted. Host to write 1 to clear.

5.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = 1111 1111]

Figure 5-21. IRQ_MASK Register

Bit

7

MFAULT

1

6

5

4

3

MSHUTDN

1

2

1

0

MDIETEMP

1

Bit Name

TPS650860

Access

RESERVED

1

R/W

R

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-9. IRQ_MASK Register Descriptions

Bit

Field

Type Reset

Description

7

MFAULT

R/W

1

FAULT interrupt mask.

0: Not masked.

1: Masked.

3

0

MSHUTDN

MDIETEMP

PMIC shutdown event interrupt mask

0: Not masked.

1: Masked.

Die temp interrupt mask.

0: Not masked.

1: Masked.

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5.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0000 0000]

Figure 5-22. PMICSTAT Register

Bit

7

6

5

4

3

2

1

0

Bit Name

TPS650860

Access

RESERVED

SDIETEMP

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-10. PMICSTAT Register Descriptions

Bit

Field

Type Reset

Description

0

SDIETEMP

R

0

PMIC die temperature status.

0: PMIC die temperature is below T_HOT

.

1: PMIC die temperature is above T_HOT

.

5.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0000 0000]

Figure 5-23. SHUTDNSRC Register

Bit

7

6

5

4

3

COLDOFF

0

2

UVLO

0

1

0

CRITTEMP

0

Bit Name

TPS650860

Access

RESERVED

OCP

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-11. SHUTDNSRC Register Descriptions

Bit

Field

Type Reset

Description

3

COLDOFF

R/W

0

Set by PMIC cleared by host. Host to write 1 to clear. This bit is always 0 for

TPS650860.

0 = Cleared

1= PMIC was shut down by pulling down CTL1 pin.

2

1

UVLO

OCP

Set by PMIC cleared by host. Host to write 1 to clear.

0 = Cleared

1= PMIC was shut down due to a UVLO event (V_SYScrosses below 5.4 V).

Assertion of this bit sets the SHUTDN bit in Section 5.9.3.

Set by PMIC cleared by host. Host to write 1 to clear.

0 = Cleared

1= PMIC was shut down due to an overcurrent event from BUCK1, BUCK2,

BUCK6, or VTT LDO. Assertion of this bit sets the SHUTDN bit in

Section 5.9.3.

0

CRITTEMP

R/W

0

Set by PMIC cleared by host. Host to write 1 to clear.

0 = Cleared

1= PMIC was shut down due to the rise of PMIC die temperature above critical

temperature threshold (T_CRIT). Assertion of this bit sets the SHUTDN bit in

Section 5.9.3.

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5.9.7 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = OTP-Programmable]

Figure 5-24. BUCK1CTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK1_

VID[6]

BUCK1_

VID[5]

BUCK1_

VID[4]

BUCK1_

VID[3]

BUCK1_

VID[2]

BUCK1_

VID[1]

BUCK1_

VID[0]

BUCK1_

DECAY

Bit Name

TPS650860

Access

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-12. BUCK1CTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK1_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK1 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

0

BUCK1_DECAY

R/W OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

5.9.8 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = OTP-Programmable]

Figure 5-25. BUCK2CTRL Register (offset = 21h) [reset = OTP-Programmable]

Bit

7

6

5

4

3

2

1

0

BUCK2_

VID[6]

BUCK2_

VID[5]

BUCK2_

VID[4]

BUCK2_

VID[3]

BUCK2_

VID[2]

BUCK2_

VID[1]

BUCK2_

VID[0]

BUCK2_

DECAY

Bit Name

TPS650860

Access

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-13. BUCK2CTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK2_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK2 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK2_DECAY

R/W OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

Detailed Description

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5.9.9 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = OTP-

Programmable]

Figure 5-26. BUCK3DECAY Register

Bit

7

6

5

4

3

2

1

0

BUCK3_

DECAY

Bit Name

RESERVED

TPS650860

Access

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-14. BUCK3DECAY Register Descriptions

Bit

Field

Type Reset

Description

7:1

RESERVED

R/W

0

Reserved

X: Reserved bit are do not care, can be 1 or 0.

0

BUCK3_DECAY

R/W

OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

5.9.10 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = OTP-Programmable]

Figure 5-27. BUCK3VID Register

Bit

7

6

5

4

3

2

1

0

BUCK3_

VID[6]

BUCK3_

VID[5]

BUCK3_

VID[4]

BUCK3_

VID[3]

BUCK3_

VID[2]

BUCK3_

VID[1]

BUCK3_

VID[0]

Bit Name

RESERVED

TPS650860

Access

1

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-15. BUCK3VID Register Descriptions

Bit

Field

Type Reset

R/W OTP-Programmable

Description

7:1

BUCK3_VID[6:0]

This field sets the BUCK3 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

44

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5.9.11 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = OTP-

Programmable]

Figure 5-28. BUCK3SLPCTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP

Bit Name

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

_ EN

TPS650860

Access

1

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-16. BUCK3SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK3_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK3 regulator output regulation voltage in

sleep mode. BUCK3_SLP_VID bits are copied to BUCK3_VID

bits upon enters sleep mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

0

BUCK3_SLP_EN

R/W OTP-Programmable

BUCK3 sleep mode enable. For this bit to be effective, BUCK3

must be factory configured to enter sleep mode either by

CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0: Disable.

1: Enable.

5.9.12 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP-Programmable]

Figure 5-29. BUCK4CTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK4_

MODE

Bit Name

RESERVED

BUCK4_DIS

TPS650860

Access

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-17. BUCK4CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:2

RESERVED

R/W

1111

Reserved bits: Do not write to 0. These bits must stay 1 for sleep

control reasons.

1

0

BUCK4_MODE

BUCK4_DIS

R/W

OTP-Programmable

This field sets the BUCK4 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

R/W

OTP-Programmable

BUCK4 Disable Bit. Writing 0 to this bit forces BUCK4 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

Detailed Description

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5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]

Figure 5-30. BUCK5CTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK5_

MODE

Bit Name

RESERVED

BUCK5_DIS

TPS650860

Access

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-18. BUCK5CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:2

RESERVED

R/W

1111

Reserved bits: Do not write to 0. These bits must stay 1 for sleep

control reasons.

1

0

BUCK5_MODE

BUCK5_DIS

R/W

OTP-Programmable

This field sets the BUCK5 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

R/W

OTP-Programmable

BUCK5 Disable Bit. Writing 0 to this bit forces BUCK5 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]

Figure 5-31. BUCK6CTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK6_

MODE

Bit Name

RESERVED

BUCK6_DIS

TPS650860

Access

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-19. BUCK6CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:2

RESERVED

R/W

1111

Reserved bits: Do not write to 0. These bits must stay 1 for sleep

control reasons.

1

0

BUCK6_MODE

BUCK6_DIS

R/W

OTP-Programmable

This field sets the BUCK6 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

R/W

OTP-Programmable

BUCK6 Disable Bit. Writing 0 to this bit forces BUCK6 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

46

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SWCS128A –MARCH 2015–REVISED DECEMBER 2015

5.9.15 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = OTP-Programmable]

Figure 5-32. LDOA2CTRL Register

Bit

7

6

5

4

3

2

1

0

Bit Name

TPS650860

Access

RESERVED

LDOA2_DIS

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-20. LDOA2CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:2

RESERVED

R/W

1111

Reserved bits: Do not write to 0. These bits must stay 1 for sleep

control reasons.

0

LDOA2_DIS

R/W

OTP-Programmable

LDOA2 Disable Bit. Writing 0 to this bit forces LDOA2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

5.9.16 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = OTP-Programmable]

Figure 5-33. LDOA3CTRL Register

Bit

7

6

5

4

3

2

1

0

Bit Name

TPS650860

Access

RESERVED

LDOA3_DIS

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-21. LDOA3CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:2

RESERVED

R/W

1111

Reserved bits: Do not write to 0. These bits must stay 1 for sleep

control reasons.

0

LDOA3_DIS

R/W

OTP-Programmable

LDOA3 Disable Bit. Writing 0 to this bit forces LDOA3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

5.9.17 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-34. DISCHCTRL1 Register

Bit

7

6

5

4

3

2

1

0

BUCK4_

DISCHG[1]

BUCK4_

DISCHG[0]

BUCK3_

DISCHG[1]

BUCK3_

DISCHG[0]

BUCK2_

DISCHG[1]

BUCK2_

DISCHG[0]

BUCK1_

DISCHG[1]

BUCK1_

DISCHG[0]

Bit Name

TPS650860

Access

0

1

0

1

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Detailed Description

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Table 5-22. DISCHCTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7-6

BUCK4_DISCHG[1:0]

R/W

OTP-Programmable

BUCK4 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5-4

3-2

1-0

BUCK3_DISCHG[1:0]

BUCK2_DISCHG[1:0]

BUCK1_DISCHG[1:0]

OTP-Programmable

BUCK3 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5.9.18 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-35. DISCHCTRL2 Register

Bit

7

6

5

4

3

2

1

0

LDOA2_

DISCHG[1]

LDOA2_

DISCHG[0]

SWA1_

DISCHG[1]

SWA1_

DISCHG[0]

BUCK6_

DISCHG[1]

BUCK6_

DISCHG[0]

BUCK5_

DISCHG[1]

BUCK5_

DISCHG[0]

Bit Name

TPS650860

Access

0

1

0

1

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-23. DISCHCTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7-6

LDOA2_DISCHG[1:0]

R/W

OTP-Programmable

LDOA2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5-4

3-2

1-0

SWA1_DISCHG[1:0]

BUCK6_DISCHG[1:0]

BUCK5_DISCHG[1:0]

OTP-Programmable

SWA1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK6 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK5 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

48

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5.9.19 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-36. DISCHCTRL3 Register

Bit

7

6

5

4

3

2

1

0

SWB2_

DISCHG[1]

SWB2_

DISCHG[0]

SWB1_

DISCHG[1]

SWB1_

DISCHG[0]

LDOA3_

DISCHG[1]

LDOA3_

DISCHG[0]

Bit Name

RESERVED

TPS650860

Access

0

1

0

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-24. DISCHCTRL3 Register Descriptions

Bit

Field

Type Reset

Description

5-4

SWB2_DISCHG[1:0]

R/W

OTP-Programmable

SWB2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

3-2

1-0

SWB1_DISCHG[1:0]

LDOA3_DISCHG[1:0]

OTP-Programmable

SWB1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

LDOA3 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5.9.20 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = OTP-Programmable]

Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to

GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC

can be programmed for system PG, level shifter or I²C controller GPO.

Figure 5-37. PG_DELAY1 Register

Bit

7

6

5

4

3

2

1

0

GPO3_PG_

DELAY[2]

GPO3_PG_

DELAY[1]

GPO3_PG_

DELAY[0]

Bit Name

RESERVED

TPS650860

Access

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-25. PG_DELAY1 Register Descriptions

Bit

Field

Type Reset

R/W OTP-Programmable

Description

2-0

GPO3_PG_DELAY[2:0]

Programmable delay power good or level shifter for GPO3 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10 % variation

000 = 2.5 ms

001 = 5.0 ms

010 = 10 ms

011 = 15 ms

100 = 20 ms

101 = 50 ms

110 = 75 ms

111 = 100 ms

XXX = Register not used

Detailed Description

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5.9.21 FORCESHUTDN: Force Emergency Shutdown Control Register

(offset = 91h) [reset = 0000 0000]

Figure 5-38. FORCESHUTDN Register

Bit

7

6

5

4

3

2

1

0

SDWN

0

Bit Name

TPS650860

Access

RESERVED

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-26. FORCESHUTDN Register Descriptions

Bit

Field

Type Reset

R/W

Description

0

SDWN

0

Forces reset of the PMIC and reset of all registers. The bit is self-clearing.

0 = No action.

1 = PMIC is forced to shut down.

5.9.22 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = OTP-

Programmable]

Figure 5-39. BUCK1SLPCTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK1_

SLP_ EN

Bit Name

SLP_ VID[6] SLP_ VID[5] SLP_ VID[4] SLP_ VID[3] SLP_ VID[2] SLP_ VID[1] SLP_ VID[0]

TPS650860

Access

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-27. BUCK1SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK1_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK1 regulator output regulation voltage in

sleep mode. Mapping between bits and output voltage is defined

as in Section 5.9.7.

0

BUCK1_SLP_EN

R/W OTP-Programmable

BUCK1 sleep mode enable. For this bit to be effective, BUCK1

must be factory configured to enter sleep mode either by

CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0: Disable.

1: Enable.

50

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5.9.23 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = OTP-

Programmable]

Figure 5-40. BUCK2SLPCTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP

Bit Name

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

_ EN

TPS650860

Access

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-28. BUCK2SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK2_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK2 regulator output regulation voltage in

sleep mode. Mapping between bits and output voltage is defined

as in Section 5.9.8.

0

BUCK2_SLP_EN

R/W OTP-Programmable

BUCK2 sleep mode enable. For this bit to be effective, BUCK2

must be factory configured to enter sleep mode either by

CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0: Disable.

1: Enable.

5.9.24 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = OTP-Programmable]

Figure 5-41. BUCK4VID Register

Bit

7

6

5

4

3

2

1

0

BUCK4_

VID[6]

BUCK4_

VID[5]

BUCK4_

VID[4]

BUCK4_

VID[3]

BUCK4_

VID[2]

BUCK4_

VID[1]

BUCK4_

VID[0]

BUCK4_

DECAY

Bit Name

TPS650860

Access

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-29. BUCK4VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK4_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK4 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

0

BUCK4_DECAY

R/W OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

Detailed Description

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5.9.25 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = OTP-Programmable]

Figure 5-42. BUCK4SLPVID Register

Bit

7

6

5

4

3

2

1

0

BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP

Bit Name

RESERVED

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS650860

Access

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-30. BUCK4SLPVID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK4_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK4 regulator output regulation voltage in

sleep mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

5.9.26 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = OTP-Programmable]

Figure 5-43. BUCK5VID Register

Bit

7

6

5

4

3

2

1

0

BUCK5_

VID[6]

BUCK5_

VID[5]

BUCK5_

VID[4]

BUCK5_

VID[3]

BUCK5_

VID[2]

BUCK5_

VID[1]

BUCK5_

VID[0]

BUCK5_

DECAY

Bit Name

TPS650860

Access

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-31. BUCK5VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK5_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK5 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

0

BUCK5_DECAY

R/W OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

52

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5.9.27 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = OTP-Programmable]

Figure 5-44. BUCK5SLPVID Register

Bit

7

6

5

4

3

2

1

0

BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP

Bit Name

RESERVED

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS650860

Access

0

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-32. BUCK5SLPVID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK5_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK5 regulator output regulation voltage in

sleep mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

5.9.28 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP-Programmable]

Figure 5-45. BUCK6VID Register

Bit

7

6

5

4

3

2

1

0

BUCK6_

VID[6]

BUCK6_

VID[5]

BUCK6_

VID[4]

BUCK6_

VID[3]

BUCK6_

VID[2]

BUCK6_

VID[1]

BUCK6_

VID[0]

BUCK6_

DECAY

Bit Name

TPS650860

Access

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-33. BUCK6VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK6_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK6 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK6_DECAY

R/W OTP-Programmable

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

Detailed Description

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5.9.29 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = OTP-Programmable]

Figure 5-46. BUCK6SLPVID Register

Bit

7

6

5

4

3

2

1

0

BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP

Bit Name

RESERVED

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS650860

Access

1

0

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-34. BUCK6SLPVID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK6_SLP_VID[6:0]

R/W OTP-Programmable

This field sets the BUCK6 regulator output regulation voltage in

normal mode.

See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges

for V_OUToptions.

5.9.30 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP-Programmable]

Figure 5-47. LDOA2VID Register

Bit

7

6

5

4

3

2

1

0

LDOA2_SLP LDOA2_SLP LDOA2_SLP LDOA2_SLP

LDOA2_

VID[3]

LDOA2_

VID[3]

LDOA2_

VID[1]

LDOA2_

VID[0]

Bit Name

_

VID[3]

VID[2]

VID[1]

VID[0]

TPS650860

Access

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-35. LDOA2VID Register Descriptions

Bit

Field

Type Reset

Description

7-4

LDOA2_SLP_VID[3:0]

R/W OTP-Programmable

This field sets the LDOA2 regulator output regulation voltage in

sleep mode.

See Table 5-5 for V_outoptions.

3-0

LDOA2_VID[3:0]

R/W OTP-Programmable

This field sets the LDOA2 regulator output regulation voltage in

normal mode.

See Table 5-5 for V_outoptions.

54

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5.9.31 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP-Programmable]

Figure 5-48. LDOA3VID Register

Bit

7

6

5

4

3

2

1

0

LDOA3_SLP LDOA3_SLP LDOA3_SLP LDOA3_SLP

LDOA3_

VID[3]

LDOA3_

VID[3]

LDOA3_

VID[1]

LDOA3_

VID[0]

Bit Name

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS650860

Access

1

0

1

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-36. LDOA3VID Register Descriptions

Bit

Field

Type Reset

Description

7-4

LDOA3_SLP_VID[3:0]

R/W OTP-Programmable

This field sets the LDOA3 regulator output regulation voltage in

sleep mode.

See Table 5-5 for V_outoptions.

3-0

LDOA3_VID[3:0]

R/W OTP-Programmable

This field sets the LDOA3 regulator output regulation voltage in

normal mode.

See Table 5-5 for V_outoptions.

5.9.32 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP-Programmable]

Figure 5-49. BUCK123CTRL Register

Bit

7

6

5

4

3

2

1

0

BUCK3

_MODE

BUCK2

_MODE

BUCK1

_MODE

BUCK3

_DIS

BUCK2

_DIS

BUCK1

_DIS

Bit Name

RESERVED

TPS650860

Access

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-37. BUCK123CTRL Register Descriptions

Bit

Field

Type Reset

Description

5

BUCK3_MODE

R/W

OTP-Programmable

This field sets the BUCK3 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

4

3

2

BUCK2_MODE

BUCK1_MODE

BUCK3_DIS

OTP-Programmable

This field sets the BUCK2 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

This field sets the BUCK1 regulator operating mode.

0 = Automatic mode

1 = Forced PWM mode

BUCK3 Disable Bit. Writing 0 to this bit forces BUCK3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

1

0

BUCK2_DIS

BUCK1_DIS

R/W

OTP-Programmable

BUCK2 Disable Bit. Writing 0 to this bit forces BUCK2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

BUCK1 Disable Bit. Writing 0 to this bit forces BUCK1 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

Detailed Description

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5.9.33 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = OTP-Programmable]

Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to

GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC

can be programmed for system PG, level shifter or I²C controller GPO.

Figure 5-50. PG_DELAY2 Register

Bit

7

6

5

4

3

2

1

0

GPO2_PG_

DELAY[2]

GPO2_PG_

DELAY[1]

GPO2_PG_

DELAY[0]

GPO4_PG_

DELAY[2]

GPO4_PG_

DELAY[1]

GPO4_PG_

DELAY[0]

GPO1_PG_

DELAY[1]

GPO1_PG_

DELAY[0]

Bit Name

TPS650860

Access

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-38. PG_DELAY2 Register Descriptions

Bit

Field

Type Reset

Description

7-5

GPO2_PG_DELAY[2:0]

R/W OTP-Programmable

Programmable delay power good or level shifter for GPO2 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10 % variation

000 = 2.5 ms

001 = 5.0 ms

010 = 10 ms

011 = 15 ms

100 = 20 ms

101 = 50 ms

110 = 75 ms

111 = 100 ms

4-2

GPO4_PG_DELAY[2:0]

Programmable delay power good or level shifter for GPO4 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10 % variation

000 = 2.5 ms

001 = 5.0 ms

010 = 10 ms

011 = 15 ms

100 = 20 ms

101 = 50 ms

110 = 75 ms

111 = 100 ms

1-0

GPO1_PG_DELAY[1:0]

Programmable delay power good or level shifter for GPO1 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10 % variation

00 = 0 ms

01 = 5.0 ms

10 = 10 ms

11 = 15 ms

5.9.34 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = OTP-Programmable]

Figure 5-51. SWVTT_DIS Register

Bit

7

SWB2_DIS

1

6

SWB1_DIS

1

5

SWA1_DIS

1

4

VTT_DIS

1

3

Reserved

0

2

Reserved

0

1

Reserved

0

Reserved

0

Bit Name

TPS650860

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 5-39. SWVTT_DIS Register Descriptions

Bit

Field

Type Reset

Description

7

SWB2_DIS

SWB1_DIS

SWA1_DIS

VTT_DIS

R/W

OTP-Programmable

SWB2 Disable Bit. Writing 0 to this bit forces SWB2 to

turn off regardless of any control input pin (CTL1–CTL6)

status.

0: Disable.

1: Enable.

6

5

4

OTP-Programmable

SWB1 Disable Bit. Writing 0 to this bit forces SWB1 to

turn off regardless of any control input pin (CTL1–CTL6)

status.

0: Disable.

1: Enable.

SWA1 Disable Bit. Writing 0 to this bit forces SWA1 to

turn off regardless of any control input pin (CTL1–CTL6)

status.

0: Disable.

1: Enable.

VTT Disable Bit. Writing 0 to this bit forces VTT to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

3

2

1

0

Reserved

R/W

0

Reserved, Keep bit 0 at all times. Do not write to 1.

5.9.35 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = OTP-

Programmable]

Figure 5-52. I2C_RAIL_EN1 Register

Bit

7

LDOA2_EN

0

6

SWA1_EN

0

5

BUCK6_EN

0

4

BUCK5_EN

0

3

BUCK4_EN

0

2

BUCK3_EN

0

1

BUCK2_EN

0

BUCK1_EN

0

Bit Name

TPS650860

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-40. I2C_RAIL_EN1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_EN

R/W

OTP-Programmable

LDOA2 I²C Enable

0: LDOA2 is enabled or disabled by one of the control input pins

or internal PG signal.

1: LDOA2 is forced on unless LDOA2_DIS = 0.

SWA1 I²C Enable

0: SWA1 is enabled or disabled by one of the control input pins

or internal PG signal.

1: SWA1 is forced on unless SWA1_DIS = 0.

BUCK6 I²C Enable

0: BUCK6 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK6 is forced on unless BUCK6_DIS = 0.

BUCK5 I²C Enable

0: BUCK5 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK5 is forced on unless BUCK5_DIS = 0.

6

5

4

3

SWA1_EN

BUCK6_EN

BUCK5_EN

BUCK4_EN

OTP-Programmable

BUCK4 I²C Enable

0: BUCK4 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK4 is forced on unless BUCK4_DIS = 0.

Detailed Description

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Table 5-40. I2C_RAIL_EN1 Register Descriptions (continued)

Bit

Field

Type Reset

Description

2

BUCK3_EN

R/W

OTP-Programmable

BUCK3 I²C Enable

0: BUCK3 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK3 is forced on unless BUCK3_DIS = 0.

BUCK2 I²C Enable

0: BUCK2 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK2 is forced on unless BUCK2_DIS = 0.

BUCK1 I²C Enable

1

0

BUCK2_EN

BUCK1_EN

OTP-Programmable

0: BUCK1 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK1 is forced on unless BUCK1_DIS = 0.

5.9.36 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset =

A1h) [reset = OTP-Programmable]

Figure 5-53. I2C_RAIL_EN2/GPOCTRL Register

Bit

7

GPO4_LVL

X

6

GPO3_LVL

X

5

GPO2_LVL

0

4

GPO1_LVL

1

3

VTT_EN

0

2

SWB2_EN

0

1

SWB1_EN

0

LDOA3_EN

0

Bit Name

TPS650860

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-41. I2C_RAIL_EN2/GPOCTRL Register Descriptions

Bit

Field

Type Reset

Description

7

GPO4_LVL

R/W

OTP-Programmable

The field is to set GPO4 pin output if the pin is factory-

configured as an open-drain general-purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

X: Bit not used or is do not care for this version.

6

GPO3_LVL

R/W

OTP-Programmable

The field is to set GPO3 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

X: Bit not used or is do not care for this version.

5

4

GPO2_LVL

GPO1_LVL

R/W

OTP-Programmable

The field is to set GPO2 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

The field is to set GPO1 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

3

2

1

VTT_EN

R/W

OTP-Programmable

VTT LDO I²C Enable

0: VTT LDO is enabled or disabled by one of the control input

pins or internal PG signals.

1: VTT LDO is forced on unless VTT_DIS = 0.

SWB2 I²C Enable

0: SWB2 is enabled or disabled by one of the control input pins

or internal PG signals.

1: SWB2 is forced on unless SWB2_DIS = 0.

SWB1 I²C Enable

SWB2_EN

SWB1_EN

0: SWB1 is enabled or disabled by one of the control input pins

or internal PG signals.

1: SWB1 is forced on unless SWB1_DIS = 0.

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Table 5-41. I2C_RAIL_EN2/GPOCTRL Register Descriptions (continued)

Bit

Field

LDOA3_EN

Type Reset

R/W OTP-Programmable

Description

LDOA3 I²C Enable

0

0: LDOA3 is enabled or disabled by one of the control input pins

or internal PG signals.

1: LDOA3 is forced on unless LDOA3_DIS = 0.

5.9.37 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = OTP-

Programmable]

Figure 5-54. PWR_FAULT_MASK1 Register

Bit

7

6

5

4

3

2

1

0

LDOA2_

FLTMSK

SWA1_

FLTMSK

BUCK6_

FLTMSK

BUCK5_

FLTMSK

BUCK4_

FLTMSK

BUCK3_

FLTMSK

BUCK2_

FLTMSK

BUCK1_

FLTMSK

Bit Name

TPS650860

Access

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-42. PWR_FAULT_MASK1 Register Descriptions

Bit

Field

Type Reset

OTP-Programmable

Description

7

LDOA2_FLTMSK

R/W

LDOA2 Power Fault Mask. When masked, power fault from

LDOA2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

6

5

4

3

2

1

0

SWA1_FLTMSK

BUCK6_FLTMSK

BUCK5_FLTMSK

BUCK4_FLTMSK

BUCK3_FLTMSK

BUCK2_FLTMSK

BUCK1_FLTMSK

OTP-Programmable

SWA1 Power Fault Mask. When masked, power fault from SWA1

does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK6 Power Fault Mask. When masked, power fault from

BUCK6 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK5 Power Fault Mask. When masked, power fault from

BUCK5 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK4 Power Fault Mask. When masked, power fault from

BUCK4 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK3 Power Fault Mask. When masked, power fault from

BUCK3 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK2 Power Fault Mask. When masked, power fault from

BUCK2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK1 Power Fault Mask. When masked, power fault from

BUCK1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

Detailed Description

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5.9.38 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = OTP-

Programmable]

Figure 5-55. PWR_FAULT_MASK2 Register

Bit

7

6

5

4

3

2

1

0

LDOA1_

FLTMSK

VTT_

FLTMSK

SWB2_

FLTMSK

SWB1_

FLTMSK

LDOA3_

FLTMSK

Bit Name

RESERVED

TPS650860

Access

0

1

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-43. PWR_FAULT_MASK2 Register Descriptions

Bit

Field

Type Reset

Description

4

LDOA1_FLTMSK

R/W

OTP-Programmable

LDOA1 Power Fault Mask. When masked, power fault from

LDOA1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

3

2

1

0

VTT_FLTMSK

OTP-Programmable

VTT LDO Power Fault Mask. When masked, power fault from

VTT LDO does not cause PMIC to shutdown.

0: Not Masked

1: Masked

SWB2_FLTMSK

SWB1_FLTMSK

LDOA3_FLTMSK

SWB2 Power Fault Mask. When masked, power fault from

SWB2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

SWB1 Power Fault Mask. When masked, power fault from

SWB1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

LDOA3 Power Fault Mask. When masked, power fault from

LDOA3 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

5.9.39 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = OTP-

Programmable]

Figure 5-56. GPO1PG_CTRL1 Register

Bit

7

6

5

4

3

2

1

0

LDOA2

_MSK

BUCK6

_MSK

BUCK5

_MSK

BUCK4

_MSK

BUCK3

_MSK

BUCK2

_MSK

BUCK1

_MSK

Bit Name

RESERVED

TPS650860

Access

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-44. GPO1PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_MSK

R/W OTP-Programmable

0: LDOA2 PG is part of Power Good tree of GPO1 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

5

4

BUCK6_MSK

BUCK5_MSK

R/W OTP-Programmable

0: BUCK6 PG is part of Power Good tree of GPO1 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK5 PG is part of Power Good tree of GPO1 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

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Table 5-44. GPO1PG_CTRL1 Register Descriptions (continued)

Bit

Field

Type Reset

Description

3

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W OTP-Programmable

0: BUCK4 PG is part of Power Good tree of GPO1 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

2

1

0

R/W OTP-Programmable

0: BUCK3 PG is part of Power Good tree of GPO1 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK2 PG is part of Power Good tree of GPO1 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK1 PG is part of Power Good tree of GPO1 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

5.9.40 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = OTP-

Programmable]

Figure 5-57. GPO1PG_CTRL2 Register

Bit

7

CTL5_MSK

1

6

CTL4_MSK

1

5

CTL2_MSK

1

4

CTL1_MSK

1

3

VTT_MSK

1

2

1

0

Bit Name

TPS650860

Access

RESERVED

RESERVED LDOA3_MSK

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-45. GPO1PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_MSK

R/W OTP-Programmable

0: CTL5 pin status is part of Power Good tree of GPO1 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

6

5

4

3

0

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W OTP-Programmable

0: CTL4 pin status is part of Power Good tree of GPO1 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO1 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO1 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO1 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO1 pin

and is ignored.

LDOA3_MSK

0: LDOA3 PG is part of Power Good tree of GPO1 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

5.9.41 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = OTP-

Programmable]

Figure 5-58. GPO4PG_CTRL1 Register

Bit

7

6

5

4

3

2

1

0

Bit Name

TPS650860

Access

LDOA2_MSK RESERVED BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 5-46. GPO4PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_MSK

R/W OTP-Programmable

0: LDOA2 PG is part of Power Good tree of GPO4 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

5

4

3

2

1

0

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W OTP-Programmable

0: BUCK6 PG is part of Power Good tree of GPO4 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK5 PG is part of Power Good tree of GPO4 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK4 PG is part of Power Good tree of GPO4 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK3 PG is part of Power Good tree of GPO4 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK2 PG is part of Power Good tree of GPO4 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK1 PG is part of Power Good tree of GPO4 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

5.9.42 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = OTP-

Programmable]

Figure 5-59. GPO4PG_CTRL2 Register

Bit

7

CTL5_MSK

1

6

CTL4_MSK

1

5

CTL2_MSK

0

4

CTL1_MSK

0

3

VTT_MSK

1

2

1

0

Bit Name

TPS650860

Access

RESERVED

RESERVED LDOA3_MSK

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-47. GPO4PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_MSK

R/W OTP-Programmable

0: CTL5 pin status is part of Power Good tree of GPO4 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

6

5

4

3

0

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W OTP-Programmable

0: CTL4 pin status is part of Power Good tree of GPO4 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO4 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO4 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO4 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

LDOA3_MSK

0: LDOA3 PG is part of Power Good tree of GPO4 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO4 pin and

is ignored.

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5.9.43 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = OTP-

Programmable]

Figure 5-60. GPO2PG_CTRL1 Register

Bit

7

6

5

4

3

2

1

0

Bit Name

TPS650860

Access

LDOA2_MSK RESERVED BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-48. GPO2PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_MSK

R/W OTP-Programmable

0: LDOA2 PG is part of Power Good tree of GPO2 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin

and is ignored.

5

4

3

2

1

0

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W OTP-Programmable

0: BUCK6 PG is part of Power Good tree of GPO2 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK5 PG is part of Power Good tree of GPO2 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK4 PG is part of Power Good tree of GPO2 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK3 PG is part of Power Good tree of GPO2 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK2 PG is part of Power Good tree of GPO2 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK1 PG is part of Power Good tree of GPO2 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

5.9.44 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = OTP-

Programmable]

Figure 5-61. GPO2PG_CTRL2 Register

Bit

7

6

5

4

3

2

1

0

LDOA3_

MSK

Bit Name

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

RESERVED

TPS650860

Access

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-49. GPO2PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_MSK

R/W OTP-Programmable

0: CTL5 pin status is part of Power Good tree of GPO2 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO2

pin and is ignored.

6

5

CTL4_MSK

CTL2_MSK

R/W OTP-Programmable

0: CTL4 pin status is part of Power Good tree of GPO2 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO2

pin and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO2 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO2

pin and is ignored.

Detailed Description

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Table 5-49. GPO2PG_CTRL2 Register Descriptions (continued)

Bit

Field

Type Reset

Description

4

CTL1_MSK

R/W OTP-Programmable

0: CTL1 pin status is part of Power Good tree of GPO2 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO2

pin and is ignored.

3

0

VTT_MSK

R/W OTP-Programmable

0: VTT LDO PG is part of Power Good tree of GPO2 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

LDOA3_MSK

0: LDOA3 PG is part of Power Good tree of GPO2 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

5.9.45 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = OTP-

Programmable]

Figure 5-62. GPO3PG_CTRL1 Register

Bit

7

6

5

4

3

2

1

0

LDOA2

_MSK

BUCK6

_MSK

BUCK5

_MSK

BUCK4

_MSK

BUCK3

_MSK

BUCK2

_MSK

BUCK1

_MSK

Bit Name

RESERVED

TPS650860

Access

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-50. GPO3PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_MSK

R/W OTP-Programmable

0: LDOA2 PG is part of Power Good tree of GPO3 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

5

4

3

2

1

0

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W OTP-Programmable

0: BUCK6 PG is part of Power Good tree of GPO3 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK5 PG is part of Power Good tree of GPO3 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK4 PG is part of Power Good tree of GPO3 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK3 PG is part of Power Good tree of GPO3 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK2 PG is part of Power Good tree of GPO3 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK1 PG is part of Power Good tree of GPO3 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

5.9.46 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = OTP-

Programmable]

Figure 5-63. GPO3PG_CTRL2 Register

Bit

7

CTL5_MSK

1

6

CTL4_MSK

0

5

CTL2_MSK

0

4

CTL1_MSK

0

3

VTT_MSK

1

2

1

0

Bit Name

TPS650860

Access

RESERVED

RESERVED LDOA3_MSK

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 5-51. GPO3PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W OTP-Programmable

0: CTL5 pin status is part of Power Good tree of GPO3 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

6

5

4

3

0

R/W OTP-Programmable

0: CTL4 pin status is part of Power Good tree of GPO3 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO3 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO3 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO3 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO3 pin

and is ignored.

LDOA3_MSK

0: LDOA3 PG is part of Power Good tree of GPO3 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

5.9.47 MISCSYSPG Register (offset = ACh) [reset = OTP-Programmable]

Figure 5-64. MISCSYSPG Register

Bit

7

6

5

4

3

2

1

0

GPO1_

CTL3_MSK

GPO1_

CTL6_MSK

GPO4_

CTL3_MSK

GPO4_

CTL6_MSK

GPO2_

CTL3_MSK

GPO2_

CTL6_MSK

GPO3_

CTL3_MSK

GPO3_

CTL6_MSK

Bit Name

TPS650860

Access

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-52. MISCSYSPG Register Descriptions

Bit

Field

Type Reset

Description

7

GPO1_CTL3_MSK

R/W OTP-Programmable

0: CTL3 pin status is part of Power Good tree of GPO1 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO1 pin.

6

5

4

3

2

1

GPO1_CTL6_MSK

GPO4_CTL3_MSK

GPO4_CTL6_MSK

GPO2_CTL3_MSK

GPO2_CTL6_MSK

GPO3_CTL3_MSK

0: CTL6 pin status is part of Power Good tree of GPO1 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO1 pin.

0: CTL3 pin status is part of Power Good tree of GPO4 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO4 pin.

0: CTL6 pin status is part of Power Good tree of GPO4 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO4 pin.

0: CTL3 pin status is part of Power Good tree of GPO2 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO2 pin.

0: CTL6 pin status is part of Power Good tree of GPO2 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO2 pin.

0: CTL3 pin status is part of Power Good tree of GPO3 pin.

1: CTL3 pin status is NOT part of Power Good tree of

GPO13pin.

0

GPO3_CTL6_MSK

R/W OTP-Programmable

0: CTL6 pin status is part of Power Good tree of GPO3 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO3 pin.

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5.9.48 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP-Programmable]

Figure 5-65. LDOA1CTRL Register

Bit

7

6

5

4

3

2

1

0

LDOA1_

DISCHG[1]

LDOA1_

DISCHG[0]

LDOA1_SDWN

_CONFIG

LDOA1_

VID[3]

LDOA1_

VID[2]

LDOA1_

VID[1]

LDOA1_

VID[0]

LDOA1_

EN

Bit Name

TPS650860

Access

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-53. LDOA1CTRL Register Descriptions

Bit

Field

Type Reset

Description

7-6

LDOA1_DISCHG[1:0]

R/W OTP-Programmable

LDOA1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5

LDOA1_SDWN_CONFIG

R/W OTP-Programmable

Control for Disabling LDOA1 during Emergency Shutdown

0: LDOA1 will turn off during Emergency Shutdown for factory-

programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.

1: LDOA1 is controlled by LDOA1_EN bit only.

4-1

0

LDOA1_VID[3:0]

LDOA1_EN

R/W OTP-Programmable

This field sets the LDOA1 regulator output regulation voltage.

See Table 5-4 for V_OUToptions.

LDOA1 Enable Bit.

0: Disable.

1: Enable.

5.9.49 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]

Figure 5-66. PG_STATUS1 Register

Bit

7

6

5

4

3

2

1

0

LDOA2_

PGOOD

BUCK6_

PGOOD

BUCK5_

PGOOD

BUCK4_

PGOOD

BUCK3_

PGOOD

BUCK2_

PGOOD

BUCK1_

PGOOD

Bit Name

RESERVED

TPS650860

Access

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-54. PG_STATUS1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_PGOOD

R

0

LDOA2 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

5

4

3

2

1

BUCK6_PGOOD

BUCK5_PGOOD

BUCK4_PGOOD

BUCK3_PGOOD

BUCK2_PGOOD

BUCK6 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK5 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK4 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK3 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK2 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

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Table 5-54. PG_STATUS1 Register Descriptions (continued)

Bit

Field

BUCK1_PGOOD

Type Reset

Description

0

R

0

BUCK1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

5.9.50 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]

Figure 5-67. PG_STATUS2 Register

Bit

7

6

5

4

3

2

1

0

LDO5

_PGOOD

LDOA1

_PGOOD

VTT

_PGOOD

LDOA3

_PGOOD

Bit Name

RESERVED

TPS650860

Access

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-55. PG_STATUS2 Register Descriptions

Bit

Field

Type Reset

Description

5

LDO5_PGOOD

R

0

LDO5 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

4

3

0

LDOA1_PGOOD

VTT_PGOOD

LDOA1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

VTT LDO Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

LDOA3_PGOOD

LDOA3 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

5.9.51 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]

Figure 5-68. PWR_FAULT_STATUS1 Register

Bit

7

6

5

4

3

2

1

0

LDOA2_

PWRFLT

BUCK6_

PWRFLT

BUCK5_

PWRFLT

BUCK4_

PWRFLT

BUCK3_

PWRFLT

BUCK2_

PWRFLT

BUCK1_

PWRFLT

Bit Name

RESERVED

TPS650860

Access

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-56. PWR_FAULT_STATUS1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_PWRFLT

R

0

This fields indicates that LDOA2 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

5

4

3

BUCK6_PWRFLT

BUCK5_PWRFLT

BUCK4_PWRFLT

This fields indicates that BUCK6 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK5 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK4 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

Detailed Description

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Table 5-56. PWR_FAULT_STATUS1 Register Descriptions (continued)

Bit

Field

Type Reset

Description

2

BUCK3_PWRFLT

R

0

This fields indicates that BUCK3 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

1

0

BUCK2_PWRFLT

BUCK1_PWRFLT

This fields indicates that BUCK2 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

5.9.52 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]

Figure 5-69. PWR_FAULT_STATUS2 Register

Bit

7

6

5

4

3

2

1

0

LDOA1_

PWRFLT

VTT_

PWRFLT

LDOA3_

PWRFLT

Bit Name

RESERVED

TPS650860

Access

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-57. PWR_FAULT_STATUS2 Register Descriptions

Bit

Field

Type Reset

Description

4

LDOA1_PWRFLT

R/W

0

This fields indicates that LDOA1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

3

0

VTT_PWRFLT

This fields indicates that VTT LDO has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

LDOA3_PWRFLT

This fields indicates that LDOA3 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

5.9.53 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL

temperature threshold (T_CRIT). There are 5 temperature sensors across the die.

Figure 5-70. TEMPCRIT Register

Bit

7

6

5

4

3

2

1

0

Top-Right

_CRIT

Top-Left

_CRIT

Bottom-Right

_CRIT

Bit Name

RESERVED

DIE_CRIT

VTT_CRIT

TPS650860

Access

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 5-58. TEMPCRIT Register Descriptions

Bit

Field

Type Reset

Description

4

DIE_CRIT

R/W

0

Temperature of rest of die has exceeded T_CRIT

0: Not asserted.

1: Asserted. The host to write 1 to clear.

.

3

2

VTT_CRIT

Temperature of VTT LDO has exceeded T_CRIT

.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

Top-Right_CRIT

Temperature of die Top-Right has exceeded T_CRIT. Top-Right corner of die

from top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

Top-Left_CRIT

R/W

0

Temperature of die Top-Left has exceeded T_CRIT.Top-Left corner of die from

top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

Bottom-Right_CRIT

Temperature of die Bottom-Right has exceeded T_CRIT. Bottom-Right corner of

die from top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

5.9.54 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature

threshold (T_HOT). There are 5 temperature sensors across the die.

Figure 5-71. TEMPHOT Register

Bit

7

6

5

4

3

2

1

0

Top-Right

_HOT

Top-Left

_HOT

Bottom-Right

_HOT

Bit Name

RESERVED

DIE_HOT

VTT_HOT

TPS650860

Access

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-59. TEMPHOT Register Descriptions

Bit

Field

Type Reset

Description

4

DIE_HOT

R/W

0

Temperature of rest of die has exceeded T_HOT

0: Not asserted.

1: Asserted. The host to write 1 to clear.

.

3

2

VTT_HOT

Temperature of VTT LDO has exceeded T_HOT

.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

Top-Right_HOT

Temperature of Top-Right has exceeded T_HOT. Top-Right corner of die from top

view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

Top-Left_HOT

R/W

0

Temperature of Top-Left has exceeded THOT. Top-Left corner of die from top

view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

Bottom-Right_HOT

Temperature of Bottom-Right has exceeded T_HOT. Bottom-Right corner of die

from top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

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5.9.55 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]

Asserted when overcurrent condition is detected from a LSD FET.

Figure 5-72. OC_STATUS Register

Bit

7

6

5

4

3

2

1

0

BUCK6

_OC

BUCK2

_OC

BUCK1

_OC

Bit Name

RESERVED

TPS650860

Access

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-60. OC_STATUS Register Descriptions

Bit

Field

Type Reset

Description

2

BUCK6_OC

R/W

0

BUCK6 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

BUCK2_OC

BUCK1_OC

BUCK2 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

BUCK1 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

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6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Typical Application

For a detailed description about application usage, refer to the TPS65086x Design Guide (SLVUAJ9) and

to the TPS65086x Schematic and Layout Checklist (SLVA734). The TPS650860 can be used in several

different applications from computing, industrial interfacing and much more. This section describes the

general application information and provides a more detailed description on the TPS650860 device that

powers a generic multicore-processor application. An example system block diagram for the device

powering an SoC and the rest of platform is shown in Figure 6-1. The functional block diagram from

Figure 5-1 outlines the typical external components necessary for proper device functionality.

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Example

SoC

PMIC

PLATFORM

V_IN

EXT FET

BUCK1

VCORE

V_IN

EXT FET

BUCK2

VGPU

VCCIO

5V Supply

BUCK3 3.5A

BUCK4 3A

VCPU1

Note: An LDO or

Buck can supply

the VPP rail if

BUCK5 3A

VCPU2

needed for DDR.

V_IN

EXT FET

BUCK6

VDDQ, VDD1&2

VTT LDO µ0.5A

VREF, VTT

DDR

LDO5V or

5V Supply

VSUPP1

VSUPP2

VSUPP3

VSUPP4

VSUPP5

VSUPP6

LDOA1 0.2A

LDOA2 0.6A

LDOA3 0.6A

SWA1 0.3A

SWB1 0.3A

SWB2 0.3A

1.8V

Input up to 3.3V

LDO5V

V_SYS

LDO5

V_IN

5V Supply

PG_5V

LDO3P3

IRQB

GPO1 œ GPO4

SDA

CTL1 œ CTL6

SCL

Figure 6-1. Typical Application Example

72

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6.1.1.1 Design Requirements

The TPS650860 requires decoupling caps on the supply pins. Follow the values for recommended

capacitance on these supplies given in the Specifications section. The controllers, converter, LDOs, and

some other features can be adjusted to meet specific application needs. Section 6.1.1.2 describes how to

design and adjust the external components to achieve desired performance.

6.1.1.2 Detailed Design Procedure

6.1.1.2.1 Controller Design Procedure

Designing the controller can be broken down into the following steps:

1. Design the output filter

2. Select the FETs

3. Select the bootstrap capacitor

4. Select the input capacitors

5. Set the current limits

Controllers BUCK1, BUCK2, and BUCK6 require a 5-V supply and capacitors at their corresponding

DRV5V_x_x pins. For most applications, the DRV5V_x_x input must come from the LDO5P0 pin to ensure

uninterrupted supply voltage; a 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for decoupling.

ë_{ò{

/

Lb

5wëIx

.hhÇ1

[

hÜÇ

[5hꢂë

2ꢁ2 µC

5wëꢂë_x_x

0ꢁ1 µC

ë_hÜÇ

{íx

/ontroller

/

hÜÇ

5wë[x

ꢀDb5{b{x

/ontrol

from {h/

C.ëhÜÇx

L[Lax

<C.Db52>

w_{L[L a}

<C.Db52> only present for .Ü/Y2

Figure 6-2. Controller Diagram

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6.1.1.2.1.1 Selecting the Inductor

Placement of an inductor is required between the external FETs and the output capacitors. Together, the

inductor and output capacitors make the double-pole that contributes to stability. In addition, the inductor

is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used

increases, the ripple current decreases, which typically results in an increased efficiency. However, with

an increase in inductance used, the transient performance decreases. Finally, the inductor selected must

be rated for appropriate saturation current, core losses, and DC resistance (DCR).

Equation 3 shows the calculation for the recommended inductance for the controller.

V_OUT× (V_INœ V_OUT

)

L =

V_IN× f_SW× Iout_MAX× K_IND

where

•

V_OUTis the typical output voltage

V_INis the typical input voltage

f_SWis the typical switching frequency

Iout_MAXis the maximum load current

K_INDis the ratio of I_Lrippleto the I_out(max). For this application, TI recommends that K_INDis set to a value from 0.2

to 0.4. (3)

With the chosen inductance value, the peak current for the inductor in steady state operation, I_L(max), can

be calculated using Equation 4. The rated saturation current of the inductor must be higher than the I_L(max)

current.

(V_INœ V_OUT) × V_OUT

I_LMAX= Iout_MAX

+

2 × V_IN× f_SW× L

(4)

Following the previous equations, the preferred inductor selected for the controllers are listed Table 6-1.

Table 6-1. Recommended Inductors

MANUFACTURER

Cyntec

PART NUMBER

PIME031B

PIMB041B

PIMB051B

PIME051E

PIMB051H

PIME061B

PIME061E

PIMB061H

PIMB062D

VALUE

SIZE

HEIGHT

1.2 mm

1.5 mm

1.8 mm

1.2 mm

1.5 mm

1.8 mm

2.4 mm

0.47 µH–1 µH

0.33 µH–2.2 µH

1 µH–3.3 µH

3.3 mm × 3.7 mm

4.45 mm × 4.75 mm

5.4 mm × 5.75 mm

6.8 mm × 7.3 mm

Cyntec

0.33 µH–4.7 µH

0.47 µH–4.7 µH

0.56 µH–3.3 µH

0.33 µH–4.7 µH

0.1 µH–4.7 µH

0.1 µH–6.8 µH

Cyntec

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6.1.1.2.1.2 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple.

The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from

their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on

the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize

the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage

ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of

ceramic capacitors drops with increasing DC bias voltage.

TI recommends the use of small ceramic capacitors placed between the inductor and load with many vias

to the PGND plane for the output capacitors of the BUCK controllers. This solution typically provides the

smallest and lowest cost solution available for DCAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. Equation 5

provides a rough estimate of the minimum required capacitance to ensure proper transient response.

Because the transient response is significantly affected by the board layout, some experimentation is

expected in order to confirm that values derived in this section are applicable to any particular use case.

Equation 5 is not meant to be an absolute requirement, but rather a rough starting point. Alternatively,

some known combination values from which to begin are provided in Table 6-2.

I_TRAN(max)²× L

C_OUT

>

(V_INœ V_OUT) × V_OVER

where

•

I_TRAN(max)is the maximum load current step

L is the chosen inductance

V_OUTis the minimum programmed output voltage

V_INis the maximum input voltage

V_OVERis the maximum allowable overshoot from programmed voltage

(5)

In cases where the transient current change is very low, the DC stability may become important.

Equation 6 approximates the amount of capacitance necessary to maintain DC stability. Again, this is

provided as a starting point; actual values will vary on a board-to-board case.

V_OUT× 50 µs

C_OUT

>

V_IN× f_SW× L

where

•

V_OUTis the maximum programmed output voltage

50 µs is based on internal ramp setup

V_INis the minimum input voltage

f_SWis the typical switching frequency

L is the chosen inductance

(6)

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It is necessary to choose the maximum valuable between Equation 5 and Equation 6.

Table 6-2. Known LC Combinations

I_{TRAN(max) (A)}

L (µH)

0.47

0.33

0.22

V_OUT(V)

V_OVER(V)

0.05

C_OUT(µF)

3.5

4

1

220

440

640

550

0.05

5

1.35

1

0.068

0.06

8

20

1

0.16

6.1.1.2.1.3 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower R_DSONvalues are better for

improving the overall efficiency of the controller, however higher gate charge thresholds will result in lower

efficiency so the two need to be balanced for optimal performance. As the R_DSONfor the low-side FET

decreases, the minimum current limit increases; therefore, ensure selection of the appropriate values for

the FETs, inductor, output capacitors, and current limit resistor. The Texas Instruments' CSD87331Q3D,

CSD87381P and CSD87588N devices are recommended for the controllers, depending on the required

maximum current.

6.1.1.2.1.4 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a

capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends

placing ceramic capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,

10-V capacitor is used for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and

turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common

practice for controller design.

6.1.1.2.1.5 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

6.1.1.2.1.6 Selecting the Input Capacitors

Due to the nature of the switching controller with a pulsating input current, a low ESR input capacitor is

required for best input-voltage filtering and also for minimizing the interference with other circuits caused

by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x

pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is

recommended for most applications. To achieve the low ESR requirement, a ceramic capacitor is

recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be

considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS

and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata

GRM21BR61E226ME44: 22-µF, 0805, 25-V, ±20%, or similar capacitors.

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6.1.1.2.2 Converter Design Procedure

Designing the converter has only two steps: design the output filter and select the input capacitors.

The converter must be supplied by a 5-V source. Figure 6-3 shows a diagram of the converter.

[

hÜÇ

ꢀëLbx

ë_hÜÇ

.Ü/Yꢁë

C_IN

[óx

C.x

C_OUT

/onverter

/ontrol

from {h/

Figure 6-3. Converter Diagram

6.1.1.2.2.1 Selecting the Inductor

It is required that an inductor be placed between the external FETs and the output capacitors. Together,

the inductor and output capacitors form a double pole in the control loop that contributes to stability. In

addition, the inductor is directly responsible for the output ripple, efficiency, and transient performance. As

the inductance used increases, the ripple current decreases, which typically results in an increase in

efficiency. However, with an increase in inductance used, the transient performance decreases. Finally,

the inductor selected must be rated for appropriate saturation current, core losses, and DC resistance

(DCR).

NOTE

Internal parameters for the converters are optimized for a 0.47 µH inductor, however it is

possible to use other inductor values as long as they are chosen carefully and thoroughly

tested.

Equation 7 shows the calculation for the recommended inductance for the converter.

V_OUT× (V_INœ V_OUT

)

L =

V_IN× f_SW× Iout_MAX× K_IND

where

•

V_OUTis the typical output voltage

V_INis the typical input voltage

f_SWis the typical switching frequency

Iout_MAXis the maximum load current

K_INDis the ratio of I_Lrippleto the I_out(max). For this application, TI recommends that K_INDis set to a value from 0.2

to 0.4.

(7)

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With the chosen inductance value and the peak current for the inductor in steady state operation, I_L(MAX)

can be calculated using Equation 8. The rated saturation current of the inductor must be higher than the

I_L(MAX)current.

(V_INœ V_OUT) × V_OUT

I_LMAX= Iout_MAX

+

2 × V_IN× f_SW× L

(8)

Following these equations, the preferred inductor selected for the converters is listed in Table 6-3.

Table 6-3. Recommended Inductors

MANUFACTURER

PART NUMBER

VALUE

SIZE

HEIGHT

Cyntec

PIFE32251B-R47MS

0.47 µH

3.2 mm × 2.5 mm

1.2 mm

6.1.1.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values are recommended because they provide the lowest output

voltage ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside

from the wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on

the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize

the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage

ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of

ceramic capacitors drops with increasing DC-bias voltage.

For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors

between the inductor and load with many vias to the PGND plane. This solution typically provides the

smallest and lowest-cost solution available for DCAP2 controllers.

The output capacitance must equal or exceed the minimum capacitance listed for BUCK3, BUCK4, and

BUCK5 (assuming quality layout techniques are followed).

6.1.1.2.2.3 Selecting the Input Capacitors

Due to the nature of the switching converter with a pulsating input current, a low ESR input capacitor is

required for best input-voltage filtering and for minimizing the interference with other circuits caused by

high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for

most applications. A ceramic capacitor is recommended to achieve the low ESR requirement. However,

the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. The input

capacitor can be increased without any limit for better input-voltage filtering.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V,

±20%, or similar capacitor.

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6.1.1.2.3 LDO Design Procedure

The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, it is

recommended to use ceramic capacitors to maintain a high amount of capacitance with low ESR on the

VTT LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the

GRM188R60J226MEA0 from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred

input capacitor for the VTT LDO is the CL05A106MP5NUNC from Samsung (10-µF, 0402, 10-V, ±20%, or

similar capacitor).

The remaining LDOs must have input and output capacitors chosen based on the values in Section 4.9.

6.1.1.3 Application Curves

Figure 6-4. BUCK2 Controller Load Transient

Figure 6-5. BUCK3 Controller Load Transient

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6.2 VIN 5-V Application

The PMIC can be operated by a 5-V input voltage to the system because the power path of the controller

does not go through the device itself. The concept is simple: supply the controller VINs with the 5-V input,

and supply the VSYS with a 5.8-V step-up of the 5 V with a boost or charge pump. The 5.8 V is

recommended because the UVLO of the internal LDO5 is at 5.6 V and the device measures the voltage at

VSYS and determines the optimum internal compensation and controller settings thus, it is ideal the VSYS

be close to the VIN of the controllers.

Example

SoC

PMIC

PLATFORM

V_IN

EXT FET

BUCK1

VCORE

V_IN

EXT FET

BUCK2

BUCK3 3.5A

BUCK4 3A

BUCK5 3A

BUCK6

VGPU

VCCIO

5V Supply

VCPU1

Note: An LDO or

Buck can supply

the VPP rail if

VCPU2

needed for DDR.

V_IN

EXT FET

VDDQ, VDD1&2

VTT LDO µ0.5A

VREF, VTT

DDR

VREF, VTT

DDR

LDO5V or

5V Supply

LDOA1 0.2A

LDOA2 0.6A

LDOA3 0.6A

SWA1 0.3A

SWB1 0.3A

SWB2 0.3A

VSUPP1

VSUPP2

VSUPP3

VSUPP4

VSUPP5

VSUPP6

1.8V

Input up to 3.3V

Supply diode needed if

pre-bias is not supported

Charge Pump

or Boost

VSYS = Vout - Vf

40 mA œ 440 mA

LDO5V

V_SYS

V_IN

LDO5

5V

PG_5V

LDO3P3

CTL1

IRQB

GPO1

GPO2

GPO3

GPO4

DATA

SCLK

CTL2

CTL3

CTL4

CTL5

CTL6

Figure 6-6. VIN 5-V Application

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6.2.1 Design Requirements

The PMIC requires a step-up voltage from the 5-V input to 5.8 V for the VSYS supply. TI recommends

keeping the VSYS near 5.8 V for optimization of the controllers.

Depending on the application use cases, the supply current to the VSYS can require from 40 mA with the

drivers being supplied by the 5-V input to 440 mA with the drivers being supplied by the LDO5 and the

LDOA1 being operated at max loading. This means that a charge pump may be used in some applications

like the 5-V input but in others, a small boost may be required.

A Schottky diode from the 5-V input to the VSYS is recommended to ensure the VSYS is biased and the

internal reference LDOs are on before the step-up regulator is enabled or fully ramped up. If the step-up

cannot tolerate pre-bias condition then, 2 diodes may be needed to prevent the initial 5-V supply biasing

the output of the step-up.

6.2.2 Design Procedure

To design a 5-V input application, first provide a step-up voltage from the 5-V input to the VSYS. Design

the step-up to output a voltage near 5.8 V. Next, route the 5-V input to the controller and converter VINs.

Thus, all power paths (all high currents) are routed through the controllers or directly to the converters.

None of the high currents are required from the step-up supply. After the input stage is complete, the rest

of the system can be designed as normal following the typical application procedure. Only the controller

design is affected by the input voltage change.

6.2.2.1 Controller Design Procedure

Designing the controller can be broken down into the following steps:

1. Design the output filter.

2. Select the FETs.

3. Select the bootstrap capacitor, same procedure as Section 6.1.1.2.1.4

4. Select the input capacitors.

5. Set the current limits. Will be very different values but, same procedure as Section 6.1.1.2.1.5

Controllers BUCK1, BUCK2, and BUCK6 require a 5-V supply and capacitors at their corresponding

DRV5V_x_x pins. For most applications, the DRV5V_x_x input must come from the LDO5P0 pin to ensure

uninterrupted supply voltage; a 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for decoupling.

ë_Lb

/

Lb

5wëIx

.hhÇ1

[

hÜÇ

[5hꢂë or ëꢂ!b!

5wëꢂë_x_x

0ꢁ1 µC

ë_hÜÇ

{íx

2ꢁ2 µC

/ontroller

/

hÜÇ

5wë[x

ꢀDb5{b{x

C.ëhÜÇx

L[Lax

<C.Db52>

w_L[La

<C.Db52> only present for .Ü/Y2

Figure 6-7. 5-V Input Controller Diagram

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6.2.2.1.1 Selecting the LC Output Filter

Selecting the inductor is the same as the typical application. Refer to Section 6.1.1.2.1.1 for desired

inductor calculations.

Selection of the output capacitance is also the same as the typical design procedure, but due to the

reduced V_IN, the likely required minimum C_OUTwill be larger. This is because the V_L, or V_IN– V_OUT, is

much smaller. Refer to Section 6.1.1.2.1.2 for output capacitance selection calculations.

6.2.2.1.2 Selecting the FETs

For lower current and lower input voltage applications, smaller lower-cost FETs can be selected with the

trade off of R_DSONand max VDS because the output power is reduced. The CSD85301Q2 is

recommended for lower current applications. The CSD87381P is recommended for mid-range current

applications.

6.2.2.1.3 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

6.2.2.1.4 Selecting the Input Capacitors

Due to the nature of the switching controller with a pulsating input current, a low ESR input capacitor is

required for best input-voltage filtering and also for minimizing the interference with other circuits caused

by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x

pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is

recommended for most applications. To achieve the low ESR requirement, a ceramic capacitor is

recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be

considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VIN

and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata

GRM188R61A226ME15 (22-µF, 0603, 10-V, ±20%) or similar capacitors.

6.2.3 Application Curve

100%

95%

90%

85%

80%

75%

70%

65%

Vout = 1 V

Vout = 1.8 V

60%

Vout = 2.5 V

Vout = 3.3 V

55%

50%

0.1

0.2 0.3 0.40.5 0.7

1

2

3

4 5 6 7

Iout (A)

D010

Figure 6-8. BUCK1 Efficiency at V_IN= 5 V

82

Application and Implementation

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6.3 Do's and Don'ts

•

Connect the LDO5V output to the DRV5V_x_x inputs for situations where an external 5-V supply is not

initially available or is not available the entire time PMIC is on. If the external 5-V supply is always

present, then DRV5V_x_x can be directly connected to remove the V5ANA-to-LDO5P0 load switch

R_DSON

.

•

Ensure that none of the control pins are potentially floating.

Include 0-Ω resistors on the DRVH and BOOT pins of controllers on prototype boards, which allows for

slowing the controllers if the system is unable to handle the noise generated by the large switching or if

switching voltage is too large due to layout.

•

Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here

causes reference circuits to regulate incorrectly.

Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may

turn on the HS FET passing the input to the output until VSYS is biased.

7 Power Supply Coupling and Bulk Capacitors

This device is designed to work with several different input voltages. The minimum voltage on the VSYS

pin is 5.6 V for the device to start up; however, this is a low power rail. The input to the FETs must be

between 4.5 V to 21 V as long as the proper BOM choices are made. Input to the converters must be 5 V.

For the device to output maximum power, the input power must be sufficient. For the controllers, VIN must

be able to supply sufficient input current for the application's output power. For the converters, PVINx must

be able to supply 2 A typically.

A best practice here is to determine power usage by the system and back-calculate the necessary power

input based on expected efficiency values.

8 Layout

8.1 Layout Guidelines

For a detailed description regarding layout recommendations, refer to the TPS65086x Design Guide

(SLVUAJ9) and to the TPS650860 Schematic and Layout Check List (SLVA734). For all switching power

supplies, the layout is an important step in the design, especially at high peak currents and high switching

frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI issues.

Therefore, use wide and short traces for the main current path and for the power ground tracks. The input

capacitors, output capacitors, and inductors must be placed as close as possible to the IC. Use a

common-ground node for power ground and use a different, isolated node for control ground to minimize

the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two vias. Use

of the design guide is highly encouraged in addition to the following list of other basic requirements:

•

Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.

To ensure proper sensing based on FET R_DSON, PGNDSNSx must not connect to PGND until very

close to the PGND pin of the FET.

•

All inductors, input/output caps, and FETs for the converters and controller must be on the same board

layer as the IC.

To achieve the best regulation performance, place feedback connection points near the output

capacitors and minimize the control feedback loop as much as possible.

•

Bootstrap capacitors must be placed close to the IC.

The internal reference regulators must have their input and output caps placed close to the IC pins.

Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with

DRVLx, which provides optimal driver loops.

Layout

83

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8.2 Layout Example

.Ü/Y2

ëw9C /ap

ëÇÇ

.Ü/Y6

.Ü/Y3

.Ü/Y5

.Ü/Y4

.Ü/Y1

Figure 8-1. EVM Layout Example With All Components on the Top Layer

84

Layout

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES

NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR

SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR

SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Development Support

SLVA734

TPS65086x Schematic and Layout Checklist

SLVUAJ9 TPS650860 Design Guide

9.2 Documentation Support

9.2.1 Related Documentation

SLVUAH2 TPS65086x Evaluation Module

SLYY077

Power management integrated buck controllers for distant point-of-load applications

9.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools

and contact information for technical support.

9.4 Trademarks

D-CAP2, D-CAP, E2E are trademarks of Texas Instruments.

NXP is a trademark of NXP Semiconductors.

All other trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

9.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Device and Documentation Support

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

86

Mechanical, Packaging, and Orderable Information

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS650860A0RSKR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 2 节和 3 节锂离子电池供电器件或非电池供电器件的可配置多电轨 PMIC \| RSK \| 64 \| -40 to 85 电池集成电源管理电路
文件：	总94页 (文件大小：1355K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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