TPS65261-1RHBR [TI]

4.5V 至 18V 输入电压、3A/2A/2A 输出电流三路同步 | RHB | 32 | -40 to 85;


型号：	TPS65261-1RHBR
厂家：	TEXAS INSTRUMENTS
描述：	4.5V 至 18V 输入电压、3A/2A/2A 输出电流三路同步 \| RHB \| 32 \| -40 to 85 开关
文件：	总48页 (文件大小：3293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

TPS6526x 4.5V 至18V 输入电压、3A/2A/2A 输出电流

三路同步降压转换器

1 特性

3 说明

• 工作输入电源电压范围

TPS65261、TPS65261-1 是一款具有 3A/2A/2A 输出

（4.5V 至18V）

电流的单片三路同步降压转换器。4.5V 至 18V 的宽输

入电源电压范围包括大多数运行自 5V、9V、12V 或

15V 电源总线的中间总线电压。该转换器具有恒定频

率峰值电流模式，专用于简化应用，同时方便设计人员

根据目标应用来优化系统。可使用一个外部电阻器在

250 kHz 至 2 MHz 之间调整此转换器的开关频率。

Buck1 和 Buck 2，3 之间的 180°异相运行（Buck2 和

3 同相运行）最大限度地减少了对输入滤波器的要求。

• 反馈基准电压为0.6V ±1%

• 最大连续输出电流：3A/2A/2A

• 可调节时钟频率范围为250 kHz 至2 MHz

• 针对每次降压的专用使能引脚和软启动引脚

• 自动加电/断电序列

• 轻载条件下的的脉冲跳跃模式(PSM)（仅限

TPS65261）

• 输出电压电源正常状态指示器

• 输入电压电源故障指示器

• 热过载保护

在将 MODE 引脚接至 V7V 并且配置 EN1/2/3 引脚

时，TPS65261，TPS65261-1 特有一个自动上电时

序。此器件还特有一个开漏RESET 信号来监视断电。

2 应用

轻负载时， TPS65261 自动运行在脉冲跳跃模式

(PSM)，而 TPS65261-1 运行在强制持续电流模式

(FCC)。PSM 模式通过减少轻负载时的开关损耗来提

供高效率，而 FCC 模式降低噪声灵敏性和射频 (RF)

干扰。

• 数字电视(DTV)

• 机顶盒

• 家庭网关和接入点网络

• 无线路由器

• 安全监控

• POS 机

此器件特有过压保护、过流和短路保护以及过热保护。

电源正常引脚在任何输出电压超出稳压范围时被置为有

效。

器件信息⁽¹⁾

器件型号

TPS65261

TPS65261-1

模式

PSM

封装

RHB（VQFN，32）

FCCM

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Vout1

Vin

PVINx

VIN

LX1

TPS65261

TPS65261-1

FB1

LX2

VDIV

Vout2

Vout3

RESET

PGOOD

ENx

FB2

LX3

MODE

SSx

ROSC

AGND

FB3

PGND

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSCD3

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................24

8 Application and Implementation..................................26

8.1 Application Information............................................. 26

8.2 Typical Application.................................................... 26

8.3 Power Supply Recommendations.............................36

8.4 Layout....................................................................... 36

9 Device and Documentation Support............................39

9.1 Documentation Support............................................ 39

9.2 接收文档更新通知..................................................... 39

9.3 支持资源....................................................................39

9.4 Trademarks...............................................................39

9.5 静电放电警告............................................................ 39

9.6 术语表....................................................................... 39

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................7

6.6 Typical Characteristics................................................9

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................14

Information.................................................................... 39

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (May 2014) to Revision C (May 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 通篇去除了图像的颜色........................................................................................................................................1

• Changed the description of V7V pin in 表5-1.....................................................................................................3

• Moved the storage temperature row in the ESD Ratings table to the Absolute Maximum Ratings table...........5

• Renamed Handling Ratings to ESD Ratings ..................................................................................................... 5

• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator

and Bootstrap................................................................................................................................................... 21

• Changed the recommended value of C5 in 图8-1 .......................................................................................... 26

Changes from Revision A (December 2013) to Revision B (May 2014)

Page

• 更改了所有文本、表格和图形以符合新的数据表模板.........................................................................................1

• Changed 图8-37 ............................................................................................................................................. 38

English Data Sheet: SLVSCD3

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5 Pin Configuration and Functions

32 31 30 29 28 27 26 25

EN3

SS1

COMP1

FB1

PGOOD

RESET

MODE

V7V

AGND

ROSC

FB3

Thermal Pad

FB2

COMP2

SS2

COMP3

SS3

10 11 12 13 14 15 16

(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal

performance.)

图5-1. RHB Package 8-Pin VQFN (Top View)

表5-1. Pin Functions

DESCRIPTION

NO.

NAME

Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck3 with a resistor

divider.

EN3

An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown,

overcurrent, undervoltage or ENx shut down.

PGOOD

RESET Open drain power failure output signal.

When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3

MODE

pins.

V7V

FB2

Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground

Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.

Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate

the control loop of buck2 with peak current PWM mode.

COMP2

SS2

Soft-start and tracking input for buck2. An internal 5-µA pullup current source is connected to this pin. The soft-start

time can be programmed by connecting a capacitor between this pin and ground.

Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from

BST2 pin to LX2 pin.

BST2

Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a

diode voltage below the ground up to PVIN2 voltage.

LX2

Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input

ceramic capacitor.

PGND2

PVIN2

PVIN3

PGND3

Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 10µF).

Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 10µF).

Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input

ceramic capacitor.

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English Data Sheet: SLVSCD3

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

DESCRIPTION

NO.

NAME

Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a

diode voltage below the ground up to PVIN3 voltage.

LX3

Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) from

BST3 pin to LX3 pin.

BST3

SS3

Soft-start and tracking input for buck3. An internal 5-µA pullup current source is connected to this pin. The soft-start

time can be programmed by connecting a capacitor between this pin and ground.

Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate

the control loop of buck3 with peak current PWM mode.

COMP3

FB3

Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.

Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.

ROSC

Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current

power grounds to the (–) terminal of bypass capacitor of input voltage VIN.

AGND

FB1

Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.

Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate

the control loop of buck1 with peak current PWM mode.

COMP1

Soft-start and tracking input for buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start

time can be programmed by connecting a capacitor between this pin and ground.

SS1

BST1

LX1

Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) from

BST1 pin to LX1 pin.

Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a

diode voltage below the ground up to PVIN1 voltage.

Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input

ceramic capacitor.

PGND1

PVIN1

Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 10µF).

VIN

Buck controller power supply.

VDIV

Input voltage threshold for power failure detection of input voltage.

Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck1 with a resistor

divider.

EN1

EN2

PAD

Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor

divider.

There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for

optimal thermal performance.

English Data Sheet: SLVSCD3

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ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

–1.0

–0.3

–40

MAX

UNIT

PVIN1, PVIN2, PVIN3,VIN

LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV

FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC

AGND, PGND1, PGND2, PGND3

3.6

0.3

125

150

Operating junction temperature, T_J

°C

Storage temperature range, T_stg

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

MIN

MAX

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

2000

–2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

500

–500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

UNIT

PVIN1, PVIN2, PVIN3,VIN

LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV

FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC

Operating junction temperature

–0.8

–0.1

–40

6.8

6.3

T_A

T_J

°C

Operating junction temperature

125

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English Data Sheet: SLVSCD3

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

www.ti.com.cn

UNIT

6.4 Thermal Information

TPS65261

THERMAL METRIC⁽¹⁾

RHB (32 PINS)

R_θJA

Junction-to-ambient thermal resistance

31.6

23.4

6.1

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JT

6.1

ψ_JB

R_θJC(bot)

0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

English Data Sheet: SLVSCD3

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6.5 Electrical Characteristics

T_A= 25°C, V_IN= 12 V, f_SW= 600 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY VOLTAGE

VIN

Input voltage range

4.5

VIN rising

VIN falling

4.25

3.75

500

9.2

UVLO

VIN undervoltage lockout

Shutdown supply current

3.5

Hysteresis

µA

IDD_SDN

EN1=EN2=EN3=MODE=0 V

EN1=EN2=EN3=5 V,

FB1=FB2=FB3=0.8 V

IDD_{Q_NSW}

605

µA

Input quiescent current without

buck1/2/3 switching

IDD_{Q_NSW1}

IDD_{Q_NSW2}

IDD_{Q_NSW3}

V_7V

EN1=5V, EN2=EN3=0 V, FB1=0.8V

EN2=5 V, EN1=EN3=0V, FB2=0.8 V

EN3=5V, EN1=EN2=0V, FB3=0.8V

V_7Vload current = 0 A

330

6.3

µA

V7V LDO output voltage

V7V LDO current limit

6.6

I_{OCP_V7V}

175

FEEDBACK VOLTAGE REFERENCE

V_COMP= 1.2 V, T_J= 25°C

0.596

0.594

0.6 0.605

0.6 0.606

V_FB

Feedback voltage

V_COMP= 1.2 V, T_J= -40°C to 125°C

I_OUT1= 1.5 A, I_OUT2= 1 A, I_OUT3= 1 A

5 V < PVINx < 18 V

V_{LINEREG_BUCK}

V_{LOADREG_BUCK}

Line regulation-DC

Load regulation-DC

0.002

%/V

%/A

0.02

I_OUTx= (10–100%) × I_{OUTx_max}

Buck1, Buck2, Buck3

V_ENXH

V_ENXL

I_ENX1

EN1/2/3 high level input voltage

1.2

1.15

3.6

6.6

1.26

EN1/2/3 low level input voltage

EN1/2/3 pullup current

Hysteresis current

1.1

4.3

ENx = 1 V

µA

µS

I_ENX2

ENx = 1.5 V

I_ENhys

I_SSX

T_{ON_MIN}

G_{m_EA}

Soft start charging current

Minimum on time

100

Error amplifier trans-conductance

300

–2 µA < I_COMPX< 2 µA

COMP1/2/3 voltage to inductor current

G_{m_PS1/2/3}

I_LX= 0.5 A

7.4

A/V

I_LIMIT1

Buck1 peak inductor current limit

Buck1 low side source current limit

Buck1 low side sink current limit

Buck2/3 peak inductor current limit

Buck2/3 low side source current limit

Buck2/3 low side sink current limit

Overcurrent wait time

4.33

2.6

5.1

4.3

1.3

3.1

2.7

6.02

3.73

I_LIMITSOURCE1

I_LIMITSINK1

I_LIMIT2/3

I_{LIMITSOURCE2/3}

I_LIMITSINK2/3

T_{Hiccup_wait}

T_{Hiccup_re}

256

8192

100

cycles

mΩ

Hiccup time before re-start

Rdson_HS1

Rdson_LS1

Rdson_HS2

Rdson_LS2

Rdson_HS3

Rdson_LS3

Buck1 High-side switch resistance

Buck1 low-side switch resistance

Buck2 High-side switch resistance

Buck2 low-side switch resistance

Buck3 High-side switch resistance

Buck3 low-side switch resistance

VIN = 12 V

140

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English Data Sheet: SLVSCD3

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

www.ti.com.cn

6.5 Electrical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, f_SW= 600 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER GOOD, MODE, POWER SEQUENCE

FBx undervoltage Falling

92.5

%V_REF

cycles

µA

FBx undervoltage Rising

FBx overvoltage Rising

FBx overvoltage Falling

V_{th_PG}

Feedback voltage threshold

107.5

105

T_{DEGLITCH(PG)_F}PGOOD falling edge deglitch time

T_{RDEGLITCH(PG)_R}PGOOD rising edge deglitch time

128

512

I_PG

PGOOD pin leakage

0.05

0.4

V_{LOW_PG}

V_MODEH

V_MODEL

I_MODE1

I_MODE2

PGOOD pin low voltage

MODE high level input voltage

MODE low level input voltage

MODE pullup current

I_SINK= 1 mA

1.2

1.15

3.6

1.26

1.1

MODE = 1 V

µA

MODE pullup current

MODE = 1.5 V

6.6

µA

Delay time between bucks at automatic

power sequencing mode

T_psdelay

MODE = 1.5 V

1024

cycles

POWER FAILURE DETECTOR

VDIV_th

VDIV threshold

1.18

1.23

1.26

µA

VDIV = 1 V

I_VDIV

VDIV pullup current

VDIV = 1.5 V

µA

I_VDIVhys

VDIV hysteresis current

µA

T_{deglitch_R}

T_{deglitch_F}

OSCILLATOR

F_SW

RESET deglitch on the rising edge

RESET deglitch on the falling edge

534

cycles

16 cycles

560

250

600

640

2000

kHz

ROSC = 73.2 kΩ

Switching frequency

F_{SW_range}

THERMAL PROTECTION

T_{TRIP_OTP}

Temperature rising

Hysteresis

160

°C

Thermal protection trip point

T_{HYST_OTP}

English Data Sheet: SLVSCD3

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6.6 Typical Characteristics

T_A= 25°C, V_IN= 12 V, V_OUT1= 1.2 V, V_OUT2= 3.3 V, V_OUT3= 1.8 V, f_SW= 600 kHz (unless otherwise noted)

100

PSM Mode, Vout = 1.2V

PSM Mode, V_O= 1.2 V

PSM Mode, Vout = 1.8V

PSM Mode, V_O= 1.8 V

PSM M VO = 3.3V

PSM Mode, V_O= 3.3 V

PSM M Vout = .3V

PSM Mode, V_O= 3.3 V

PSM M VO = 5.0V

PSM Mode, V_O= 5.0 V

VO = 1.2V

PSM M Vout = 5.0V

PSM Mode, V_O= 5.0 V

M Vout = 1.8V

FCC Mode, V_O= 1.8 V

F M

FCC Mode, V_O= 1.2 V

F M VO = 3.3V

FCC Mode, V_O= 3.3 V

F M Vout = .3V

FCC Mode, V_O= 3.3 V

FFCCCC MMooddee,, VVO==55..00VV

FFCCCC MMooddee,, VVou=t =5.50.0VV

0.01

0.1

0.01

0.1

Output Load (A)

C002

C003

图6-1. BUCK 1 Efficiency

图6-2. BUCK 2 Efficiency

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

3.33

3.32

3.31

3.30

3.29

3.28

3.27

VIN=5V

_IN= 5 V

VIN=5V

_IN= 5 V

VVIN==1122VV

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Output Load (A)

C004

C005

V_OUT= 1.2 V

图6-3. BUCK1, PSM Mode, Load Regulation

V_OUT= 3.3 V

图6-4. BUCK2, PSM Mode, Load Regulation

1.820

1.210

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

1.206

1.202

1.198

1.194

1.190

IOUT= A

I_OUT= 0.1 A

VIN=5V

V_IN= 5 V

IOUT= A

I_OUT= 1.5 A

VVIN==1122VV

IIOUT==3.0AA

OUT

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Output Load (A)

Input Voltage (V)

C006

C007

V_OUT= 1.8 V

V_OUT= 1.2 V

图6-6. BUCK1, PSM Mode, Line Regulation

图6-5. BUCK3, PSM Mode, Load Regulation

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English Data Sheet: SLVSCD3

TPS65261, TPS65261-1

ZHCSBX0C –DECEMBER 2013 –REVISED MAY 2023

www.ti.com.cn

6.6 Typical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, V_OUT1= 1.2 V, V_OUT2= 3.3 V, V_OUT3= 1.8 V, f_SW= 600 kHz (unless otherwise noted)

3.300

3.298

3.296

3.294

3.292

3.290

1.810

1.806

1.802

1.798

1.794

1.790

IOUT=

I_OUT= 0.1 A

IOUT=

I_OUT= 0.1 A

IOUT= A

I_OUT= 1.0 A

IOUT= A

I_OUT= 1.0 A

IIOUT==2A.0 A

OUT

IIOUT==2A.0 A

OUT

Input Voltage (V)

C008

C009

V_OUT= 3.3 V

图6-7. BUCK2, PSM MODE, LINE REGULATION

V_OUT= 1.8 V

图6-8. BUCK3, PSM Mode, Line Regulation

640

620

600

580

560

0.606

0.604

0.602

0.600

0.598

0.596

0.594

100

125

œ50

œ25

100

125

-50

-25

Junction Temperature (°C)

C011

Junction Temperature (°C)

C012

图6-9. Voltage Reference vs Temperature

ROSC = 73.2 kΩ

图6-10. Oscillator Frequency vs Temperature

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

100

125

100

125

œ50

œ25

œ50

œ25

Junction Temperature (°C)

C013

C014

V_IN= 12 V

EN = 1 V

图6-11. Shutdown Quiescent vs Temperature

图6-12. EN Pin Pull-Up Current vs Temperature, EN=1.0V

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6.6 Typical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, V_OUT1= 1.2 V, V_OUT2= 3.3 V, V_OUT3= 1.8 V, f_SW= 600 kHz (unless otherwise noted)

7.4

7.2

7.0

6.8

6.6

6.4

6.2

6.0

1.28

1.24

1.20

1.16

1.12

100

125

100

125

œ50

œ25

œ50

œ25

Junction Temperature (°C)

C015

C016

V_IN= 12 V

EN = 1.5 V

V_IN= 12 V

图6-13. EN Pin Pullup Current vs Temperature, EN = 1.5 V

图6-14. EN Pin Threshold Raising vs Temperature

1.23

5.4

1.19

1.15

1.11

1.07

5.2

5.0

4.8

4.6

100

125

100

125

œ50

œ25

œ50

œ25

Junction Temperature (°C)

C017

C018

V_IN= 12 V

图6-15. EN Pin Threshold Falling vs Temperature

图6-16. SS Pin Charge Current vs Temperature

5.5

3.5

5.3

5.1

4.9

4.7

3.3

3.1

2.9

2.7

100

125

100

125

œ50

œ25

œ50

œ25

Junction Temperature (°C)

C019

C020

V_IN= 12 V

图6-17. Buck1 High-Side Current Limit vs Temperature

图6-18. Buck2 High-Side Current Limit vs Temperature

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6.6 Typical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, V_OUT1= 1.2 V, V_OUT2= 3.3 V, V_OUT3= 1.8 V, f_SW= 600 kHz (unless otherwise noted)

3.5

3.3

3.1

2.9

2.7

1.25

1.24

1.23

1.22

1.21

100

125

100

125

œ50

œ25

œ50

œ25

Junction Temperature (°C)

C021

C022

图6-20. VDIV Pin Threshold vs Temperature

V_IN= 12 V

图6-19. Buck3 High-Side Current Limit vs Temperature

English Data Sheet: SLVSCD3

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7 Detailed Description

7.1 Overview

The TPS65261, TPS65261-1 is a monolithic triple synchronous step-down (buck) converter with 3A/2A/2A

output currents. A wide 4.5V to 18V input supply voltage range encompasses the most intermediate bus

voltages operating off 5V, 9V, 12V or 15V power bus. The feedback voltage reference for each buck is 0.6V.

Each buck is independent with dedicated enable, soft-start and loop compensation pins.

The TPS65261, TPS65261-1 implements a constant frequency, peak current mode control that simplifies

external loop compensation. The wide switching frequency of 250kHz to 2MHz allows optimizing system

efficiency, filtering size and bandwidth. The switching frequency can be adjusted with an external resistor

connected between ROSC pin and ground. The switching clock of buck1 is 180° out-of-phase operation from the

clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size and power supply

induced noise.

The TPS65261, TPS65261-1 has been designed for safe monotonic startup into pre-biased loads. The default

start up is when VIN is typically 4.5V. The ENx pin also can be used to adjust the input voltage under voltage

lockout (UVLO) with an external resistor divider. In addition, the ENx pin has an internal 3.6uA current source, so

the EN pin can be floating to automatically power up the converters.

The TPS65261, TPS65261-1 reduces the external component count by integrating a bootstrap circuit. The bias

voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pin. A UVLO

circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When V_BST-VLXvoltage drops to the

threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65261, TPS65261-1 can operate at

100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is

typically 2.1V.

The TPS65261, TPS65261-1 features a PGOOD pin to supervise each output voltage of the buck converters.

The TPS65261, TPS65261-1 has power good comparators with hysteresis, which monitor the output voltages

through feedback voltages. When all bucks are in regulation range and power sequence is done, PGOOD is

asserted to high.

The SS (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during

power up. A small value capacitor or resistor divider is connected to the pin for soft start or voltage tracking.

At light loading, TPS65261 will automatically operate in pulse skipping mode (PSM) to save power.

The TPS65261, TPS65261-1 is protected from overload and over temperature fault conditions. The converter

minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the

output is overvoltage, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105%

of the 0.6V reference voltage. The TPS65261, TPS65261-1 implements both high-side MOSFET overload

protection and bidirectional low-side MOSFET overload protection to avoid inductor current runaway. If the

overcurrent condition has lasted for more than the OC wait time (256 clock cycles), the converter will shut down

and re-start after the hiccup time (8192 clock cycles). The TPS65261, TPS65261-1 shuts down if the junction

temperature is higher than the thermal shutdown trip point. When the junction temperature drops 20°C typically

below the thermal shutdown trip point, the TPS65261, TPS65261-1 will be restarted under control of the soft

start circuit automatically.

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7.2 Functional Block Diagram

ROSC

VIN

V3V

OSC/Phase Shift

V7V LDO

Bias

V7V

VIN

clk

enable

PVIN2

BST2

LX2

V7V

VIN

clk

en_buck2

VIN

PVIN1

enable

en_buck1

BST

BST1

LX1

BUCK2

BST

MODE

BUCK1

PGND2

MODE

PGND

Comp

vfb

PGND1

5 µA

PGND

SS2

FB2

Comp

vfb

5 µA

SS1

FB1

COMP1

1 µA

COMP2

1 µA

VIN

1.23 V

Power

Failure

deglitch

VDIV

RESET

PGOOD

clk

V7V

VIN

PVIN3

BST3

LX3

en_buck3

MODE

enable

VIN

Power

Good

BST

3 µA

3.6 µA

FB1

FB2

FB3

BUCK3

MODE

EN1

PGND3

PGND

Comp

vfb

5 µA

1.2 V

2 K

6.3 V

3.6 µA

SS3

FB3

3 µA

en_buck1

1.2 V

6.3 V

3.6 µA

2 K

State

Machine

en_buck2

en_buck3

3 µA

EN2

COMP3

AGND

1.2 V

6.3 V

3.6 µA

Over

Temp

3 µA

EN3

1.2 V

6.3 V

7.3 Feature Description

7.3.1 Adjusting the Output Voltage

The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. It is

recommended to use 1% tolerance or better resistors.

Vout

COMP

0.6 V

图7-1. Voltage Divider Circuit

0.6

R₂= R₁´

V_out- 0.6

(1)

English Data Sheet: SLVSCD3

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To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator

is more sensitive to noise. The recommended resistor values are shown in 表7-1.

表7-1. Output Resistor Divider Selection

OUTPUT VOLTAGE

(V)

(kΩ)

1.2

1.5

1.8

2.5

3.3

31.6

45.3

22.6

73.2

36.5

4.99

7.3.2 Power Failure Detector

The power failure detector monitors the voltage on VDIV, and sets open-drain output RESET low when VDIV is

below 1.23V. There is deglitch on the rising edge, 534 frequency cycles. 图 7-2 shows the power failure detector

timing diagram.

1 µA

VIN

V7V

Threshold_r

VIN

Threshold_f

1 µA

1.23 V

V7V

Power

Failure

VDIV

RESET

Delay Time

534 Cycles

图7-2. Power Failure Detector Timing Diagram

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The thresholds can be calculated using 方程式2 and 方程式3.

Threshold^_= Vref 1+

-I_p´R1

(2)

(3)

Threshold^_= Vref 1+

- I +I ´R1

(

)

The divider resisters can be calculated using 方程式4 and 方程式5.

Threshold^_- Threshold_

R1=

I_h

(4)

(5)

Vref

Threshold_ - Vref

R2 =

´I_h+ I_p

Threshold^_- Threshold^_

Where I_h= 1µA, I_p= 1µA.

7.3.3 Enable and Adjusting Undervoltage Lockout

The EN1/2/3 pin provides electrical on/off control of the device. After the EN1/2/3 pin voltage exceeds the

threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the

regulator stops switching and enters low Iq state.

The EN pin has an internal pull-up current source, allowing the user to float the EN pin to enable the device. If an

application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.

The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage

falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500mV. If an

application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVINx in split

rail applications, then the ENx pin can be configured as shown in 图 7-3, 图 7-4 and 图 7-5. When using the

external UVLO function, it is recommended to set the hysteresis to be greater than 500mV.

The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external

components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO

function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be

calculated using 方程式6 and 方程式7.

V_ENFALLING

- V

STOP

_STARTç

V_ENRISING

R₁=

V_ENFALLING

+ I

_Pç

V_ENRISING

(6)

(7)

R₁´ V_ENFALLING

V_STOP- V_ENFALLILNG+ R I + I

R₂=

₁(_h)

Where I_h= 3µA, I_P= 3.6uA, V_ENSRISING= 1.2V, V_ENFALLING= 1.15V.

English Data Sheet: SLVSCD3

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VIN

PVIN

图7-3. Adjustable VIN Undervoltage Lockout

图7-4. Adjustable PVIN Undervoltage Lockout,

VIN>4.5V

PVIN

VIN

图7-5. Adjustable VIN and PVIN Undervoltage Lockout

7.3.4 Soft-Start Time

The voltage on the respective SS pin controls the start-up of the buck output. When the voltage on the SS pin is

less than the internal 0.6V reference, the TPS65261, TPS65261-1 regulates the internal feedback voltage to the

voltage on the SS pin instead of 0.6V. The SS pin can be used to program an external soft-start function or to

allow output of the buck to track another supply during start-up. The device has an internal pull-up current source

of 5µA (typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the SS pin.

The TPS65261, TPS65261-1 regulates the internal feedback voltage to the voltage on the SS pin, allowing

VOUT to rise smoothly from 0V to its regulated voltage without inrush current. The soft-start time can be

calculated approximately by 方程式8.

Css(nF)´ Vref(V)

Tss ms =

( )

Iss(µA)

(8)

Many of the common power supply sequencing methods can be implemented using the SSx and ENx pins. 图

7-6 shows the method implementing ratio-metric sequencing by connecting the SSx pins of three buck channels

together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start

time, the pull-up current source must be tripled in 方程式8.

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EN threshold=1.2 V

EN1

EN2

EN3

Vout3 = 3.3 V

SS1

Vout2 1.8 V

Vout1 1.2 V

SS2

SS3

PGOOD

Css

PGOOD Deglitch Time

Tss = Css*0.6 V/15 µA

图7-6. Ratio Metric Power Up Using SSx Pins

English Data Sheet: SLVSCD3

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Simultaneous power supply sequencing can be implemented by connecting capacitor to SSx pin, shown in 图

7-7. The capacitors can be calculated using 方程式8 and 方程式9.

Css1

Css2

Css3

Vout1 Vout2 Vout3

(9)

EN threshold = 1.2 V

EN1

EN2

EN3

Vout3 = 3.3 V

SS1

SS2

SS3

Css1

Vout2 1.8 V

Vout1 1.2 V

Css2

PGOOD

Css3

PGOOD Deglitch Time

Tss = Css3*0.6 V/5 µA

图7-7. Simultaneous Startup Sequence Using SSx Pins

7.3.5 Power Up Sequencing

TPS65261, TPS65261-1 features a comprehensive sequencing circuit for the 3 bucks. If the MODE pin ties high

to V7V, three buck start up and shutdown is in sequence according to different buck enable pin setup. If the

MODE pin ties low to ground, three buck on/off is separately controlled by three enable pins.

7.3.5.1 External Power Sequencing

The TPS65261, TPS65261-1 has a dedicated enable pin and soft-start pin for each converter. The converter

enable pins are biased by a current source that allows for easy sequencing with the addition of an external

capacitor. Disabling the converter with an active pull-down transistor on the ENs pin allows for a predictable

power-down timing operation. 图 7-8 shows the timing diagram of a typical buck power-up sequence by

connecting a capacitor at ENx pin.

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VIN

V7V

EN Threshold

Threshold

ENx Rise Time

Charge C^EN

Dictated by C^EN

with 6.6 µA

ENx

Soft Start Rise Time

Pre-Bias Startup

Dictated by Css

VOUTx

PGOOD Deglitch Time

t = C^SS× 0.6 V / 5 µA

t = C^EN× (1.2 - 0.4) V / 3.6 µA

t = C^EN× 0.4 V / 1.4 µA

PGOOD

图7-8. Startup Power Sequence

7.3.5.2 Automatic Power Sequencing

The TPS65261, TPS65261-1 starts with a pre-defined power-up and power-down sequence when the MODE pin

ties high to V7V. As shown in 表 7-2, the sequence is dictated by the different combinations of EN1 and EN2

status. EN3 is used to start/stop the converters. Buck2 and buck3 are identical converters and can be swapped

in the system operation to allow for additional sequencing stages. 图 7-9 shows the power sequencing when

EN1 and EN2 are pulled up high.

表7-2. Power Sequencing

MODE

High

EN1

High

Low

High

Low

EN2

High

Low

EN3

Start Sequencing

Shutdown Sequencing

Buck1→Buck2→Buck3 Buck3→Buck2→Buck1

Buck2→Buck1→Buck3 Buck3→Buck1→Buck2

Buck2→Buck3→Buck1 Buck1→Buck3→Buck2

Used to start/stop

bucks in sequence

Automatic Power

Sequencing

Reserved

Externally

controlled

sequencing

Used to start/stop Used to start/stop Used to start/stop

buck1 buck2 buck3

Low

English Data Sheet: SLVSCD3

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VIN

V7V

MODE

EN1

EN2

EN3

Buck1

Buck2

Buck3

PGOOD

t1 t2

= t1 = t2 = t3 = t4 = 1024*(1/fsw)

psdelay

图7-9. Automatic Power Sequencing

7.3.6 V7V Low Dropout Regulator and Bootstrap

Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V

pin. The internal built-in low dropout linear regulator (LDO) supplies 6.3V (typical) from VIN to V7V. A 10µF

ceramic capacitor must be connected from V7V pin to power ground.

If the input voltage, VIN, decreases to UVLO threshold voltage, the UVLO comparator detects the V7V pin

voltage and forces the converter off.

Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in 图 7-10, which is

normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side

MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less

than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47nF. A

ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended

because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered

from the V7V pin directly.

To improve drop out, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage

is greater than the BST-LX UVLO threshold, which is typically 2.1V. When the voltage between BST and LX

drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is

turned on allowing the boot capacitor to be recharged.

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VIN

LDO

(VBSTx –VLXx)

nBootUV

–

2.1 V

PVINx

V7V

BSTx

C^BIAS

10 µF

High-side

MOSFET

nBootUV

PWM

UVLO Bias Buck

Controller

Gate

Driver

C^B

LXx

Low-side

MOSFET

nBootUV

PWM

Gate

Driver

BootUV

Protection

CLK

图7-10. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram

7.3.7 Out-of-Phase Operation

To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.

This enables the system, having less input current ripple, to reduce the input capacitors’size, cost and EMI.

7.3.8 Output Overvoltage Protection (OVP)

The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.

When the output is overloaded, the error amplifier compares the actual output voltage to the internal reference

voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of

the error amplifier demands maximum output current. After the condition is removed, the regulator output rises

and the error amplifier output transitions to the steady state voltage. In some applications with small output

capacitance, the load can respond faster than the error amplifier. This leads to the possibility of an output

overshoot. Each buck compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than

the OVP threshold, the high-side MOSFET is turned off preventing current from flowing to the output and

minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET

turns on at the next clock cycle.

7.3.9 Slope Compensation

To prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the device

adds built-in slope compensation, which is a compensating ramp to the switch current signal.

7.3.10 Overcurrent Protection

The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side

MOSFET and the low-side MOSFET.

7.3.10.1 High-side MOSFET Overcurrent Protection

The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-

side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch

current and the current reference generated by the COMP pin voltage are compared, when the peak switch

current intersects the current reference, the high-side switch is turned off.

English Data Sheet: SLVSCD3

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7.3.10.2 Low-side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During

normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-

side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side

sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the

next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing

current limit at the start of a cycle.

The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than

the hiccup wait time which is programmed for 256 switching cycles shown in 图 7-11, the device will shut down

itself and restart after the hiccup time of 8192 cycles. The hiccup mode helps reduce the device power

dissipation under severe overcurrent condition.

OCP peak inductor current threshold

OC limiting (waiting) time

256 cycles

hiccup time

8192 cycles

soft start time

t = Css × 0.6 V / 5 µA

Output over loading

Inductor Current

Soft-start is reset after OC waiting time

About 2.1 V

0.6 V

OC fault removed, soft-start, and output recovery

SS Pin Voltage

Output hard short circuit

Vout

Output Voltage

图7-11. Overcurrent Protection

7.3.11 Power Good

The PGOOD pin is an open drain output. After feedback voltage of each buck is between 95% (rising) and 105%

(falling) of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is

recommended to use a pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V

or less. The PGOOD is in a defined state after the VIN input voltage is greater than 1V, but with reduced current

sinking capability. The PGOOD achieves full current sinking capability after the VIN input voltage is above UVLO

threshold, which is 4.25V.

The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) or greater than

107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low if the input voltage is

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undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start

period.

7.3.12 Adjustable Switching Frequency

The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching

frequency of the device is adjustable from 250KHz to 2MHz.

To determine the ROSC resistance for a given switching frequency, use 方程式 10 or the curve in 图 7-12. To

reduce the solution size, set the switching frequency as high as possible, but tradeoffs of the supply efficiency

and minimum controllable on time must be considered.

ƒ_osckHz = 39557´R(kW)^-0.975

(

)

(10)

200

175

150

125

100

200 400 600 800 1000 1200 1400 1600 1800 2000

Switching Frequency (kHz)

C010

图7-12. ROSC versus Switching Frequency

7.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 140°C

typically.

7.4 Device Functional Modes

7.4.1 Pulse Skipping MODE (PSM)

The TPS65261 can enter high efficiency pulse skipping mode (PSM) operation at light load current.

When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 230mA

current typically. Because the integrated current comparator catches the peak inductor current only, the average

load current entering PSM varies with applications and external output filters. In PSM, the sensed peak inductor

current is clamped at 230mA.

When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current

comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing

and going negative.

Due to the delay in the circuit and current comparator tdly (typical 50ns at V_IN= 12V), the real peak inductor

current threshold to turn off high-side power MOSFET, can shift higher depending on inductor inductance and

input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be

calculated by 方程式11.

Vin - Vout

IL_PEAK= 230 mA +

´ tdly

(11)

English Data Sheet: SLVSCD3

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After the charge accumulated on the Vout capacitor is more than loading need, COMP pin voltage drops to low

voltage driven by the error amplifier. There is an internal comparator at the COMP pin. If COMP voltage is lower

than 0.35V, the power stage stops switching to save power.

230 mA

Turn off

high-side Power MOSFET

Inductor

Current Peak

Current

Current Comparator

Delay: tdly

Sensing

IL_Peak

Inductor Peak Current

图7-13. PSM Current Comparator

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The devices are triple synchronous step down dc/dc converters. They are typically used to convert a higher dc

voltage to lower dc voltages with continuous available output current of 3A/2A/2A. The following design

procedure can be used to select component values for the TPS65261 and TPS65261-1. This section presents a

simplified discussion of the design process.

8.2 Typical Application

C15

22 pF

C26

22 pF

R263

20 K

R153

19.5 K

R152 39 K

R262 20 K

C17

C24

10 nF

C231

C181

10 nF

3.3 nF

2.2 nF

R20

73.2 K

C232

22 pF

R23

20 K

R18

30 K

C182

22 pF

R25

16 R16

Vout1

+1.2 V

Max. 3 A

Vout3

+ 1.8 V

Max. 2 A

BST1

LX1

BST3

C25

C16

47 nF

LX3

PGND3

PVIN3

PVIN2

PGND2

LX2

4.7 uH

C151

22 uF

C152

22 uF

C261

22 uF

C262

22 uF

PGND1

PVIN1

VIN

C28

10 uF

C13

10 uF

Vin

TPS65261

TPS65261-1

C29

1 uF

C12

R29

10 uF

146 K

VDIV

EN1

C101

22 uF

C102

22 uF

R30

20 K

4.7 uH

47nF

Vout2

+ 3.3 V

Max. 2 A

EN2

BST2

30 K

C72

22 pF

10 uF

10 nF

C71

2.2 nF

100 K

R10239 K

100 K

R103

8.67 K

C10

22 pF

图8-1. Typical Application Schematic

English Data Sheet: SLVSCD3

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8.2.1 Design Requirements

This example details the design of triple synchronous step-down converter. A few parameters must be known in

order to start the design process. These parameters are typically determined at the system level. For this

example, we start with the following known parameters:

表8-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Vout1

1.2 V

Iout1

3 A

Vout2

Iout2

3.3 V

2 A

Vout3

1.8 V

Iout3

2 A

Transient Response 1A Load Step

Input Voltage

±5%

12 V normal, 4.5 V to 18 V

±1%

Output Voltage Ripple

Switching Frequency

600 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use 方程式 12. LIR is a coefficient that represents the amount of

inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In

general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for

the majority of applications.

- V_out

V_out

inmax

L =

I_o´LIR

_max´ ƒ_sw

(12)

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.

The RMS and peak inductor current can be found from 方程式14 and 方程式15.

- V_out

V_out

V_inmax´ ƒ_sw

inmax

I_ripple

(13)

V_out´ V

- V_out

(

)

inmax

V_inmax´L ´ ƒ_sw

I_Lrms

I_O²+

(14)

(15)

I_ripple

I_Lpeak= I_out

The current flowing through the inductor is the inductor ripple current plus the output current. During power up,

faults or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of

the device. For this reason, the most conservative approach is to specify an inductor with a saturation current

rating equal to or greater than the switch current limit rather than the peak inductor current.

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8.2.2.2 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in

load current. The output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to

supply the load with current when the regulator cannot. This situation can occur if there are desired hold-up

times for the regulator where the output capacitor must hold the output voltage above a certain level for a

specified amount of time after the input power is removed. The regulator is also temporarily not able to supply

sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from

no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change

in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be

sized to supply the extra current to the load until the control loop responds to the load change. The output

capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a

tolerable amount of drop in the output voltage. 方程式 16 shows the minimum output capacitance necessary to

accomplish this.

2´ DI_out

C_o=

ƒ_sw´ DV_out

(16)

Where ΔI_outis the change in output current, f_swis the regulators switching frequency and ΔV_outis the allowable

change in the output voltage.

方程式 17 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where f_swis the switching frequency, V_orippleis the maximum allowable output voltage ripple, and I_orippleis the

inductor ripple current.

C_o>

V_oripple

8´ ƒ_sw

I_oripple

(17)

方程式 18 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification.

V_oripple

R_esr

I_oripple

(18)

Additional capacitance de-ratings for aging, temperature and DC bias must be factored in, which increases this

minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some

capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. 方程式 19 can

be used to calculate the RMS ripple current the output capacitor needs to support.

V_out´ V

- V_out

(

)

12 ´ V_inmax´L ´ ƒ_sw

inmax

I_corms

(19)

8.2.2.3 Input Capacitor Selection

The TPS65261, TPS65261-1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at

least 10 µF of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk

capacitance can also be required for the PVIN input. The effective capacitance includes any DC bias effects.

The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must

English Data Sheet: SLVSCD3

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also have a ripple current rating greater than the maximum input current ripple of The TPS65261, TPS65261-1.

The input ripple current can be calculated using 方程式20.

(

- V_out

)

V_out

inmin

= I_out

inrms

inmin

(20)

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple

voltage of the regulator. The input voltage ripple can be calculated using 方程式21.

_outmax´ 0.25

C_in´ ƒ_sw

(21)

8.2.2.4 Loop Compensation

The TPS65261, TPS65261-1 incorporates a peak current mode control scheme. The error amplifier is a trans-

conductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase

margin between 60° and 90°. C_badds a high frequency pole to attenuate high frequency noise when needed. To

calculate the external compensation components, follow these steps.

1. Select switching frequency f_swthat is appropriate for application depending on L and C sizes, output ripple,

and EMI. Switching frequency between 500kHz to 1MHz gives best trade-off between performance and cost.

To optimize efficiency, lower switching frequency is desired.

2. Set up cross over frequency, ƒc, which is typically between 1/5 and 1/20 of f_sw.

3. R_Ccan be determined by

2p´ ƒc ´ Vo´Co

R_C

G_m__EA´ Vref ´G_m_

(22)

Where G_{m_EA}is the error amplifier gain (300µS), G_{m_PS}is the power stage voltage to current conversion

gain (7.4A/V).

ƒp =

C_o´R_L´ 2p

4. Calculate C_Cby placing a compensation zero at or before the dominant pole

R_L´ Co

C_C

R_C

(23)

(24)

5. Optional C_bcan be used to cancel the zero from the ESR associated with C_O.

_ESR´ Co

C_b=

R_C

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VOUT

i^L

R^ESR

R^L

Current Sense

I/V Converter

G^m_PS= 7.4 A / V

C^o

C¹

R¹

Vfb

–

COMP

V^ref= 0.6 V

R²

G^m_EA= 300 uS

R^c

C^c

C^b

图8-2. DC/DC Loop Compensation

English Data Sheet: SLVSCD3

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8.2.3 Application Curves

图8-3. BUCK1, Soft-Start with No Load

图8-4. BUCK1, Soft-Start with Full Load

图8-6. BUCK2, Soft-Start with Full Load

图8-8. BUCK3, Soft-Start with Full Load

图8-5. BUCK2, Soft-Start with No Load

图8-7. BUCK3, Soft-Start with No Load

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图8-9. BUCK1, PSM Mode, Steady State Operation

at Light Load

图8-10. BUCK1, Steady State Operation with Full

Load

图8-12. BUCK2, Steady State Operation with Full

图8-11. BUCK2, PSM Mode, Steady State

Load

Operation at Light Load

图8-13. BUCK3, PSM Mode, Steady State

图8-14. BUCK3, Steady State Operation with Full

Operation with Light Load

Load

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图8-15. BUCK1, Load Transient, 0.75 A to 1.5 A SR 图8-16. BUCK1, Load Transient, 1.5 A to 2.25 A SR

= 0.25 A/µs = 0.25 A/µs

图8-17. BUCK2, Load Transient, 0.5 A to 1.0 A SR 图8-18. BUCK2, Load Transient, 1.0 A to 1.5 A SR

= 0.25 A/µs

图8-20. BUCK3, Load Transient, 1.0 A to 1.5 A SR

图8-19. BUCK3, Load Transient, 0.5 A to 1.0 A SR

= 0.25 A/µs

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图8-21. BUCK1, Overcurrent Protection

图8-22. BUCK1, Hiccup and Recovery

图8-24. BUCK2, Hiccup and Recovery

图8-23. BUCK2, Overcurrent Protection

图8-25. BUCK3, Overcurrent Protection

图8-26. BUCK3, Hiccup and Recovery

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图8-28. Automatic Power Sequencing,

图8-27. Automatic Power Sequencing,

MODE=EN1=EN2=HIGH

图8-30. Automatic Power Sequencing,

图8-29. Automatic Power Sequencing,

MODE=EN1=HIGH, EN2=LOW

MODE=EN1= HIGH, EN2=LOW

图8-31. Automatic Power Sequencing,

MODE=EN2=HIGH, EN1=LOW

图8-32. Automatic Power Sequencing,

MODE=EN2=HIGH, EN1=LOW

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图8-33. Trigger Voltage 1.23V, Reset vs VDIV

图8-34. Deglitch Time, Reset vs VDIV

V_IN= 12 V

V_OUT1= 1.2 V/1.5 A V_OUT2= 3.3 V/1 A

V_OUT3= 1.8 V/1 A

V_IN= 12 V V_OUT1= 1.2 V/3 A V_OUT2= 3.3 V/2 A

V_OUT3= 1.8 V/2 A

EVM Condition 4 Layers, 64 mm × 69 mm, T_A= 27.2°C

图8-35. Thermal Signature of TPS65261EVM

图8-36. Thermal Signature of TPS65261EVM

8.3 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 4.5 V and 18 V. This input

power supply must be well regulated. If the input supply is located more than a few inches from the TPS65261 or

TPS65261-1 converter additional bulk capacitance can be required in addition to the ceramic bypass capacitors.

An electrolytic capacitor with a value of 47 μF is a typical choice.

8.4 Layout

8.4.1 Layout Guidelines

The TPS65261, TPS65261-1 can be laid out on 2-layer PCB, illustrated in 图8-37.

Layout is a critical portion of good power supply design. See 图8-37 for a PCB layout example. The top contains

the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining pins of

the TPS65261, TPS65261-1 and a large top side area filled with ground. The top layer ground area must be

connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and

directly under the TPS65261, TPS65261-1 device to provide a thermal path from the exposed thermal pad land

to ground. The bottom layer acts as ground plane connecting analog ground and power ground.

For operation at full rated load, the top side ground area together with the bottom side ground plane must

provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or

voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power

English Data Sheet: SLVSCD3

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supplies performance. To help eliminate these problems, the PVIN pin must be bypassed to ground with a low

ESR ceramic bypass capacitor with X5R or X7R dielectric. Care must be taken to minimize the loop area formed

by the bypass capacitor connections, the PVIN pins and the ground connections. The VIN pin must also be

bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric.

Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor

ground must use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this

conductor length while maintaining adequate width. The small signal components must be grounded to the

analog ground path.

The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as

possible to the IC and routed with minimal lengths of trace. The additional external components can be placed

approximately as shown.

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8.4.2 Layout Example

VOUT1

VOUT3

BST1

LX1

BST3

LX3

PGND1

PVIN1

VIN

PGND3

PVIN3

PVIN2

PGND2

LX2

PVIN

VIN

VDIV

EN1

EN2

BST2

VOUT2

TOPSIDE

GROUND

AREA

0.010 in. Diameter

Thermal VIA to Ground Plane

VIA to Ground Plane

图8-37. PCB Layout

English Data Sheet: SLVSCD3

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Parts

PART NUMBER

DESCRIPTION

COMMENTS

TPS65262

4.5 V to 18 V, triple buck with dual adjustable Triple buck 3-A/1-A/1-A output current, dual LDOs 100-mA/200-mA

LDOs

output current, automatic power sequencing

TPS65263

4.5 V to 18 V, triple buck with I2C interface

Triple buck 3-A/2-A/2-A output current, I2C controlled dynamic voltage

scaling (DVS)

TPS65651-1/2/3

TPS65287

4.5 V to 18 V, triple buck with different

PGOOD deglitch time

Triple buck 3-A/2-A/2-A output current, support 1s, 32-ms, 256-ms

PGOOD deglitch time, adjustable current limit setting by external resistor

4.5 V to 18 V, triple buck with power switch

and push button control

Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB power with

overcurrent setting by external resistor, push button control for intelligent

system power-on/power-off operation

TPS65288

4.5 V to 18 V, triple buck with dual power

switches

Triple buck 3-A/2-A/2-A output current, 2 USB power switches current

limiting at typical 1.2 A (0.8/1.0/1.4/1.6/1.8/2.0/2.2A available with

manufacture trim options)

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS65261-1RHBR

TPS65261-1RHBT

TPS65261RHBR

TPS65261RHBT

ACTIVE

VQFN

RHB

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

TPS

65261-1

Samples

ACTIVE

RHB

NIPDAU

TPS

65261-1

RHB

TPS

65261

RHB

TPS

65261

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Apr-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65261-1RHBR

TPS65261-1RHBT

TPS65261RHBR

TPS65261RHBT

VQFN

RHB

3000

250

330.0

180.0

330.0

180.0

12.4

12.5

12.4

12.5

12.4

5.3

5.25

5.3

5.25

5.3

1.1

8.0

12.0

250

5.25

5.3

5.25

5.3

3000

250

5.25

5.3

5.25

5.3

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65261-1RHBR

TPS65261-1RHBT

TPS65261RHBR

TPS65261RHBT

VQFN

RHB

3000

250

346.0

338.0

210.0

205.0

338.0

346.0

338.0

210.0

346.0

355.0

185.0

200.0

355.0

346.0

355.0

185.0

33.0

50.0

35.0

33.0

50.0

33.0

50.0

35.0

250

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

EXPOSED

THERMAL PAD

28X 0.5

SEE SIDE WALL

DETAIL

SYMM

3.5

0.3

0.2

32X

0.1

C A B

0.05

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32X (0.6)

32X (0.25)

(1.475)

28X (0.5)

SYMM

(4.8)

(

0.2) TYP

VIA

(R0.05)

TYP

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32X (0.6)

32X (0.25)

28X (0.5)

(0.845)

SYMM

(4.8)

METAL

TYP

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS65261-1RHBR [TI]

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