TPS65262-1RHBR_技术文档

TPS65262-1

ZHCSCZ1B –JUNE 2014 –REVISED MAY 2023

TPS65262-1 具有双路可调350mA/150mA 低压降稳压器(LDO) 的4.5V 至18V 输

入电压，3A/1A/1A 输出电流三路同步降压转换器

1 特性

3 说明

• 工作输入电压范围：4.5V 至18V

• 反馈基准电压：0.6V ±1%

• 最大连续输出电流：3A/1A/1A

• 600kHz 固定开关频率

TPS65262-1 是一款具有 3A/1A/1A 输出电流的单片三

路同步步降（降压）转换器。4.5V 至 18V 的宽输入电

源电压范围包括大多数运行自 5V、9V、12V 或 15V

电源总线的中间总线电压。该转换器具有恒定频率峰值

电流模式，专用于简化应用，同时方便设计人员根据目

标应用来优化系统。此器件运行在 600kHz 的固定开关

频率上。为了减少外部组件数量，已经集成针对 buck2

和 buck3 的环路补偿。buck1 和 buck 2，buck3 之间

的 180° 异相运行（buck2 和 buck3 同相运行）可最大

限度降低对输入滤波器的要求。轻载条件下，该器件自

动在脉冲跳跃模式 (PSM) 下运行，从而通过减少开关

损耗来提供高效率。

• 集成双路LDO：

– 输入电压范围：1.3V 至5.5V

– 持续输出电流：350mA/150mA

• 针对Buck1 的可编程软启动时间

• 针对Buck2 和Buck3 的固定软启动时间1ms

• 针对Buck2 和Buck3 的内部环路补偿

• 针对每个降压转换器的专用使能引脚

• 自动加电和断电序列

• 轻负载条件下的脉冲跳跃模式(PSM)

• 输出电压电源正常状态指示器

• 热过载保护

TPS65262-1 内置两个低压降线性稳压器 (LDO)，它们

的输入电压范围为 1.3V 至 5.5V，持续输出电流为

350/150mA，具有独立使能和可调输出电压特性。

2 应用

TPS65262-1 特有自动电源序列，可将 MODE 引脚驱

动为高电平，并配置EN1、EN2 和EN3 引脚。

• 数字电视(DTV)

• 机顶盒

• 家庭网关和接入点网络

• 无线路由器

• 安全监控

该器件具有过压保护、过流保护、短路保护和过热保护

功能。电源正常引脚在任何降压输出电压降至稳压范围

之外时被置为有效。

封装信息⁽¹⁾

• POS 机

封装尺寸（标称值）

器件型号

TPS65262-1

封装

RHB（VQFN，32） 5.00mm × 5.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

Vout1

100%

90%

80%

70%

60%

50%

40%

30%

20%

Vin

VINx

LX1

PGOOD

MODE

ENx

FB1

LX2

Vout2

Vout3

SS1

TPS65262-1

LVIN1

LOUT1

LFB1

LDO1

LDO2

FB2

LX3

LEN1

GND

LVIN2

LOUT2

LFB2

VIN = 12 V

VOUT = 3.3 V

LEN2

10%

0%

FB3

AGND PGND

0.01

0.10

1.00

Output Load (A)

C001

典型应用

效率与输出负载之间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSCN5

TPS65262-1

ZHCSCZ1B –JUNE 2014 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................23

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 25

9.3 Power Supply Recommendations.............................35

9.4 Layout....................................................................... 35

10 Device and Documentation Support..........................37

10.1 接收文档更新通知................................................... 37

10.2 支持资源..................................................................37

10.3 Trademarks.............................................................37

10.4 静电放电警告.......................................................... 37

10.5 术语表..................................................................... 37

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................8

7.6 Typical Characteristics.............................................. 11

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................16

Information.................................................................... 37

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (October 2014) to Revision B (May 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 通篇去除了图像的颜色........................................................................................................................................1

• Changed the description of V7V pin in the Pin Functions table..........................................................................4

• Moved the storage temperature row in the ESD Ratings table to the Absolute Maximum Ratings table...........6

• Renamed the ESD Ratings table........................................................................................................................6

• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator

and Bootstrap .................................................................................................................................................. 20

• Changed the recommended value of C8 in the Typical Application Schematic................................................25

Changes from Revision * (June 2014) to Revision A (October 2014)

Page

• 将器件状态更改为量产数据................................................................................................................................ 1

English Data Sheet: SLVSCN5

2

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5 Device Comparison Table

PART

DESCRIPTION

NUMBER

COMMENTS

4.5 to 18 V, triple buck with

TPS65261/-1 input voltage power failure

indicator

Triple buck 3-A/2-A/2-A output current, features an open-drain RESET signal to monitor

input power failure, automatic power sequencing

4.5 to 18 V, triple buck with

TPS65262

Triple buck 3-A/1-A/1-A output current, automatic power sequencing. Dual LDOs 200

mA/100 mA

dual adjustable LDOs

4.5 to 18 V, triple buck with I²C

TPS65263

interface

Triple buck 3-A/2-A/2-A output current, I²C controlled dynamic voltage scaling (DVS)

4.5 to 18 V, triple buck with

Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB power with overcurrent setting by

TPS65287

TPS65288

power switch and push button external resistor, push-button control for intelligent system power-on and power-off

control

operation

4.5 to 18 V, triple buck with

dual power switches

Triple buck 3-A/2-A/2-A output current, two USB power switches current limiting at typical

1.2 A (0.8, 1.0, 1.4, 1.6, 1.8, 2.0, and 2.2 A available with manufacture trim options)

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English Data Sheet: SLVSCN5

TPS65262-1

ZHCSCZ1B –JUNE 2014 –REVISED MAY 2023

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6 Pin Configuration and Functions

24

23

22

21

20

19

18

17

16

15

BST3

LX3

25

BST1

LX1 26

PGND3

VIN3

14

13

12

PGND1

27

VIN1

28

29

Thermal Pad

VIN2

LEN1

PGND2

LX2

11

10

9

LFB1

LOUT1

LVIN1

30

31

32

BST2

1

2

3

4

5

6

7

8

(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal

performance.)

图6-1. RHB Package 32 Pins (Top View)

表6-1. Pin Functions

DESCRIPTION

NAME

NO.

Input power supply for LDO2. Connect LVIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor

(suggest 1 µF).

LVIN2

1

LDO2 output. Connect LOUT2 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest

1 µF).

LOUT2

2

LFB2

LEN2

3

4

Feedback Kelvin sensing pin for LDO2 output voltage. Connect this pin to LDO2 resistor divider.

Enable for LDO2. Float to enable.

An open-drain output, asserts low if the output voltage of any buck is beyond regulation range due to thermal shutdown,

overcurrent, undervoltage, or ENx shut down.

PGOOD

5

When high, an automatic power-up or power-down sequence is provided according to the states of EN1, EN2, and EN3

pins.

MODE

FB2

6

7

8

Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.

Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor

divider.

EN2

Boot-strapped supply to the high-side floating gate driver in buck2. Connect a capacitor (recommend 47 nF) from BST2

pin to LX2 pin.

BST2

LX2

9

Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a

diode voltage below the ground up to VIN2 voltage.

10

English Data Sheet: SLVSCN5

4

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表6-1. Pin Functions (continued)

DESCRIPTION

NAME

NO.

Power ground connection of buck2. Connect PGND2 pin as close as possible to the (–) terminal of VIN2 input ceramic

capacitor.

PGND2

11

12

13

14

15

16

Input power supply for buck2. Connect VIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor

(suggest 10 µF).

VIN2

VIN3

PGND3

LX3

Input power supply for buck3. Connect VIN3 pin as close as possible to the (+) terminal of an input ceramic capacitor

(suggest 10 µF).

Power ground connection of buck3. Connect PGND3 pin as close as possible to the (–) terminal of VIN3 input ceramic

capacitor.

Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a

diode voltage below the ground up to VIN3 voltage.

Boot-strapped supply to the high-side floating gate driver in buck3. Connect a capacitor (recommend 47 nF) from BST3

pin to LX3 pin.

BST3

Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck3 with a resistor

divider.

EN3

17

18

19

20

21

FB3

Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.

Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current

power grounds to the (–) terminal of the bypass capacitor of input voltage VIN.

AGND

V7V

Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground.

Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the

control loop of buck1 with peak current PWM mode.

COMP1

Soft-start and tracking input for buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time

can be programmed by connecting a capacitor between this pin and ground.

SS1

FB1

EN1

22

23

24

Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.

Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck1 with a resistor

divider.

Boot-strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1

pin to LX1 pin.

BST1

LX1

25

26

27

28

Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a

diode voltage below the ground up to VIN1 voltage.

Power ground connection of Buck1. Connect PGND1 pin as close as possible to the (–) terminal of VIN1 input ceramic

capacitor.

PGND1

VIN1

Input power supply for buck1. Connect VIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor

(suggest 10 µF).

LEN1

LFB1

29

30

Enable for LDO1. Float to enable.

Feedback Kelvin sensing pin for LDO1 output voltage. Connect this pin to LDO1 resistor divider.

LDO1 output. Connect LOUT1 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest

1 µF).

LOUT1

LVIN1

PAD

31

32

—

Input power supply for LDO1. Connect LVIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor

(suggest 1 µF).

There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for

optimal thermal performance.

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English Data Sheet: SLVSCN5

TPS65262-1

ZHCSCZ1B –JUNE 2014 –REVISED MAY 2023

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

MIN

–0.3

–1

MAX

20

7

UNIT

VIN1, VIN2, VIN3

LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

–0.3

–40

-55

Voltage

MODE, LEN1, LEN2, EN1, EN2, EN3, PGOOD, V7V

LOUT1, LOUT2, LVIN1, LVIN2

7

V

7

FB1, FB2, FB3, LFB1, LFB2, COMP1 , SS1

AGND, PGND1, PGND2, PGND3

Operating junction temperature

3.6

0.3

125

150

T_J

°C

T_stg

Storage temperature range

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

MIN

MAX

2000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

–2000

V _(ESD)Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101, all pins⁽²⁾

500

–500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

VIN1, VIN2, VIN3

4.5

18

LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

MODE, LEN1, LEN2, EN1, EN2, EN3, PGOOD, V7V

FB1, FB2, FB3, LFB1, LFB2, COMP1 , SS1

LOUT1, LOUT2, LVIN1, LVIN2

–0.8

–0.1

–40

6.8

V

6.3

Voltage

3

5.5

T_A

T_J

Operating ambient temperature

85

°C

Operating junction temperature

125

English Data Sheet: SLVSCN5

6

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7.4 Thermal Information

TPS65262-1

UNIT

RHB (32 PINS)

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

32.0

24.2

6.4

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JT

6.4

1.3

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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English Data Sheet: SLVSCN5

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MAX UNIT

7.5 Electrical Characteristics

T_A= 25°C, V_IN= 12 V, F_SW= 600 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

INPUT SUPPLY VOLTAGE

VIN

Input voltage range

4.5

4

18

4.5

4

V

VIN rising

VIN falling

Hysteresis

4.25

3.75

500

12

UVLO

VIN undervoltage lockout

Shutdown supply current

3.5

V

mV

µA

IDD_SDN

EN1 = EN2 = EN3 = MODE = LEN1 = LEN2 = 0 V

EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V, LEN1 =

LEN2 = 0

IDD_{Q_NSW}

790

µA

Input quiescent current without buck1,

buck2, buck3 switching

IDD_{Q_NSW1}

IDD_{Q_NSW2}

IDD_{Q_NSW3}

IDD_{Q_LDO1}

IDD_{Q_LDO2}

V_7V

EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V, LEN1 = LEN2 = 0

EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8 V, LEN1 = LEN2 = 0

EN3 = 5V, EN1 = EN2 = 0 V, FB3 = 0.8 V, LEN1 = LEN2 = 0

EN1 = EN2 = EN3 = LEN2 = 0 V, LFB1 = 0.8 V, LEN1 = 5 V

EN1 = EN2 = EN3 = LEN1 = 0 V, LFB2 = 0.8 V, LEN2 = 5 V

V_7Vload current = 0 A

340

370

190

6.3

µA

V

LDO input quiescent current

V7V LDO output voltage

V7V LDO current limit

6

6.6

I_{OCP_V7V}

175

mA

FEEDBACK VOLTAGE REFERENCE

V_COMP= 1.2 V, T_J= 25°C

0.595

0.594

0.6 0.605

0.6 0.606

V

V_FB

Feedback voltage

V

V_COMP= 1.2 V, T_J= –40°C to 125°C

I_OUT1= 1.5 A, I_OUT2= 1 A, I_OUT3= 1 A, 5 V < VINx < 18 V

VIN = 12 V, I_OUTx= (10–100%) × I_{OUTx_max}

V_{LINEREG_BUCK}

Line regulation-DC⁽¹⁾

0.002

%/V

%/A

V_{LOADREG_BUCK}Load regulation-DC⁽¹⁾

0.02

BUCK1, BUCK2, BUCK3

EN1, EN2, EN3 high-level input

voltage

V_ENXH

V_ENXL

1.2

1.26

V

EN1, EN2, EN3 low-level input voltage

1.1

4.3

1.15

3.6

6.6

3

ENx = 1 V

I_ENX

EN1, EN2, EN3 pullup current

µA

ENx = 1.5 V

I_ENhys

Hysteresis current

µA

ms

ns

I_SS1

Buck1 soft-start charging current

Buck2, buck3 soft-start time

Minimum on time

5

6

T_SS2/3

1

T_{ON_MIN}

G_{m_EA1/2/3}

80

300

100

Error amplifier trans-conductance

µs

–2 µA < ICOMPX < 2 µA

COMP voltage to inductor current G_m

G_{m_PS1/2/3}

ILX = 0.5 A

7.4

A/V

(1)

I_LIMIT1

Buck1 peak inductor current limit

Buck1 low-side source current limit

Buck1 low-side sink current limit

4.4

1.8

5.1

4.4

1.3

6.06

3

A

I_LIMITSOURCE1

I_LIMITS1

Buck2, buck3 peak inductor current

limit

I_LIMIT2/3

2.4

1.75

1

A

Buck2, buck3 low-side source current

limit

I_{LIMITSOURCE2/3}

I_LIMITS2/3

Buck2, buck3 low-side sink current

limit

T_{Hiccup_wait}

T_{Hiccup_re}

OC wait time⁽¹⁾

0.5

14

ms

Hiccup time before restart⁽¹⁾

Buck1 high-side switch resistance

Buck1 low-side switch resistance

Buck2 high-side switch resistance

Buck2 low-side switch resistance

Buck3 high-side switch resistance

Rdson_HS1

Rdson_LS1

Rdson_HS2

Rdson_LS2

Rdson_HS3

VIN1 = 12 V

100

65

mΩ

195

145

195

English Data Sheet: SLVSCN5

8

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7.5 Electrical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, F_SW= 600 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Rdson_LS3

Buck3 low-side switch resistance

VIN1 = 12 V

145

mΩ

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English Data Sheet: SLVSCN5

TPS65262-1

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7.5 Electrical Characteristics (continued)

T_A= 25°C, V_IN= 12 V, F_SW= 600 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER GOOD, MODE, POWER SEQUENCE

FBx undervoltage falling

FBx undervoltage rising

FBx overvoltage rising

FBx overvoltage falling

92.5

95

V_{th_PG}

Feedback voltage threshold

%V_REF

107.5

105

0.19

1

T_{DEGLITCH(PG)_F}PGOOD falling edge deglitch time

T_{RDEGLITCH(PG)_R}PGOOD rising edge deglitch time

ms

I_PG

PGOOD pin leakage

0.05

0.4

µA

V

V_{LOW_PG}

V_MODEH

V_MODEL

PGOOD pin low voltage

MODE high-level input voltage

MODE low-level input voltage

I_SINK= 1 mA

1.2

1.15

3.6

1.26

V

1.1

V

MODE = 1 V

I_MODE

MODE pullup current

µA

ms

MODE = 1.5 V

6.6

Delay time between bucks at

Tpsdelay

MODE = 1.5 V

1.7

automatic power sequencing mode⁽¹⁾

LDO1 AND LDO2

V_LENXH

LEN1, LEN2 high-level input voltage

LEN1, LEN2 low-level input voltage

1.2

1.15

3.6

1.26

5.5

V

V_LENXL

1.1

LENx = 1 V

I_LENX

LEN1, LEN2 pullup current

µA

LENx = 1.5 V

6.6

VIN_LDO1

VOUT_LDO1

V_LDOFB1

LDO input voltage range

LDO output voltage range

LDO voltage reference

LDO current limit

1.3

1

V

Load current = 350 mA

Load current = 10 mA

0.594

350

0.6 0.606

V

455

12

540

mA

mV

Imax_LDO1

I_OUT= 20 mA

I_OUT= 350 mA

V_dropout1

LDO dropout voltage

400

V_OUT= 1.8 V, I_OUT= 10 mA,

LVIN1 changes from 2 to 5.5 V

V_{LINEREG_LDO1}

LDO line regulation-DC⁽¹⁾

0.002

%/V

V_{LOADREG_LDO1}LDO load regulation-DC⁽¹⁾

I_OUT= 1 to 350 mA, LVIN1 = 5 V

0.2

56

%/A

dB

V

PSRR_LDO1

VIN_LDO2

Ripple rejection⁽¹⁾

LVIN1 = 5 V, Vout = 1.8 V, I_OUT= 10 mA, ƒ= 10 kHz

LDO input voltage range

LDO output voltage range

LDO voltage reference

LDO current limit

1.3

1

5.5

VOUT_LDO2

V_LDOFB2

Load current = 150 mA

Load current = 10 mA

V

0.594

170

0.6 0.606

V

I_{max_LDO2}

220

12

290

mA

I_OUT= 10 mA

I_OUT= 150 mA

V_dropout2

LDO dropout voltage⁽¹⁾

mV

250

V_OUT= 1.8 V, I_OUT= 10 mA,

LVIN2 changes from 2 to 5.5 V

V_{LINEREG_LDO2}

LDO line regulation-DC⁽¹⁾

0.002

%/V

V_{LOADREG_LDO2}LDO load regulation-DC⁽¹⁾

I_OUT= 1 to 150 mA, LVIN2 = 5 V

0.2

56

%/A

dB

PSRR_LDO2

OSCILLATOR

F_SW

Ripple rejection⁽¹⁾

LVIN2 = 5 V, Vout = 1.8 V, I_OUT= 10 mA, ƒ= 10 kHz

Switching frequency

570

600

630

kHz

THERMAL PROTECTION

T_{TRIP_OTP}

Temperature rising

Hysteresis

160

20

°C

Thermal protection trip point⁽¹⁾

T_{HYST_OTP}

(1) Lab validation result

English Data Sheet: SLVSCN5

10

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7.6 Typical Characteristics

T_A= 25°C, VIN = 12 V, V_OUT1= 1.2 V, V_OUT2= 1.8 V, V_OUT3= 3.3 V F_SW= 600 kHz (unless otherwise noted)

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

VOUT 1.2 V

VOUT 3.3 V

VOUT 5 V

VOUT 1.8 V

VOUT 3.3 V

VOUT 5 V

0.01

0.10

1.00

0.01

0.10

1.00

Output Load (A)

C002

图7-1. BUCK1 Efficiency

图7-2. BUCK2 Efficiency

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

VIN 5 V

VIN 12 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.2

0.4

0.6

0.8

1.0

Output Load (A)

C004

图7-3. BUCK1, Load Regulation

图7-4. BUCK2, Load Regulation

3.33

3.32

3.31

3.30

3.29

3.28

3.27

1.208

1.206

1.204

1.202

1.200

1.198

1.196

1.194

1.192

IOUT 0.1 A

VIN 5 V

VIN 12 V

1.0

IOUT 1.5 A

IOUT 3 A

0.0

0.2

0.4

0.6

0.8

4

6

8

10

12

14

16

18

Output Load (A)

Input Voltage (V)

C004

图7-5. BUCK3, Load Regulation

图7-6. BUCK1, Line Regulation

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7.6 Typical Characteristics (continued)

T_A= 25°C, VIN = 12 V, V_OUT1= 1.2 V, V_OUT2= 1.8 V, V_OUT3= 3.3 V F_SW= 600 kHz (unless otherwise noted)

1.808

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

3.320

3.315

3.310

3.305

3.300

3.295

3.290

3.285

3.280

IOUT 0.1 A

IOUT 0.5 A

IOUT 1 A

IOUT 0.1 A

IOUT 0.5 A

IOUT 1 A

4

6

8

10

12

14

16

18

4

6

8

10

12

14

16

18

Input Voltage (V)

C004

图7-7. BUCK2, Line Regulation

图7-8. BUCK3, Line Regulation

1.82

1.81

1.80

1.79

1.78

1.82

1.81

1.80

1.79

1.78

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.00

0.03

0.06

0.09

0.12

0.15

Output Load (A)

C010

图7-9. LDO1, Load Regulation

图7-10. LDO2, Load Regulation

1.82

1.81

1.80

1.79

1.78

1.81

1.80

1.79

1.78

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

C010

图7-11. LDO1, Line Regulation

图7-12. LDO2, Line Regulation

English Data Sheet: SLVSCN5

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7.6 Typical Characteristics (continued)

T_A= 25°C, VIN = 12 V, V_OUT1= 1.2 V, V_OUT2= 1.8 V, V_OUT3= 3.3 V F_SW= 600 kHz (unless otherwise noted)

0.606

0.604

0.602

0.600

0.598

0.596

0.594

640

620

600

580

560

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-13. Voltage Reference vs Temperature

图7-14. Oscillator Frequency vs Temperature

18

16

14

12

10

8

4.8

4.2

3.6

3.0

2.4

6

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-15. Shutdown Quiescent Current vs Temperature

图7-16. EN Pin Pullup Current vs Temperature, EN = 1 V

7.8

1.28

7.2

6.6

6.0

5.4

1.24

1.20

1.16

1.12

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-17. EN Pin Pullup Current vs Temperature, EN = 1.5 V

图7-18. EN Pin Threshold Rising vs Temperature

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7.6 Typical Characteristics (continued)

T_A= 25°C, VIN = 12 V, V_OUT1= 1.2 V, V_OUT2= 1.8 V, V_OUT3= 3.3 V F_SW= 600 kHz (unless otherwise noted)

1.23

1.19

1.15

1.11

1.07

5.8

5.4

5.0

4.6

4.2

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-19. EN Pin Threshold Falling vs Temperature

图7-20. SS Pin Charge Current vs Temperature

5.5

2.8

5.3

5.1

4.9

4.7

2.6

2.4

2.2

buck2

buck3

2.0

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-21. Buck1 High-Side Current Limit vs Temperature

图7-22. Buck2, 3 High-Side Current Limit vs Temperature

530

260

490

450

410

370

240

220

200

180

10

30

50

70

90

110 130

10

30

50

70

90

110 130

œ50 œ30 œ10

Junction Temperature (°C)

C014

图7-23. LDO Current Limit vs Temperature

图7-24. LDO2 Current Limit vs Temperature

English Data Sheet: SLVSCN5

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8 Detailed Description

8.1 Overview

The TPS65262-1 is a monolithic, triple-synchronous step-down (buck) converter with 3-A/1-A/1-A output

currents. A wide 4.5- to 18-V input supply voltage range encompasses most intermediate bus voltages operating

off 5-V, 9-V, 12-V, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is

independent with dedicated enable, soft-start, and loop compensation.

The TPS65262-1 implements a constant frequency, peak current mode control that simplifies external loop

compensation. The switching frequency is fixed 600 kHz. The switching clock of buck1 is 180° out-of-phase

operation from the clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size, and

power-supply-induced noise.

The TPS65262-1 is designed for safe monotonic startup into prebiased loads. The default start up is when VIN is

typically 4.25 V. The ENx pin can also be used to adjust the input voltage undervoltage lockout (UVLO) with an

external resistor divider. In addition, the ENx pin has an internal 3.6-µA current source, so the EN pin can be

floating for automatically powering up the converters.

The TPS65262-1 reduces the external component count by integrating the bootstrap circuit. The bias voltage for

the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit

monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the

threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65262-1 can operate at 100% duty

cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold, which is typically

2.1 V.

The TPS65262-1 features a PGOOD pin to supervise each output voltage of buck converters. The TPS65262-1

has power good comparators with hysteresis, which monitor the output voltages through feedback voltages.

When all bucks are in regulation range and power sequence is done, PGOOD is asserted to high.

The SS (soft-start/tracking) pin is used to minimize inrush currents during power-up. A small-value capacitor or

resistor divider is coupled to the pin for soft-start or voltage tracking.

At light loading, TPS65262-1 automatically operates in PSM to save power.

The TPS65262-1 integrates low dropout voltage linear regulators (LDO) with input voltage from 1.3 to 5.5 V,

independent enable, and adjustable outputs, up to 350 mA for LDO1 and 150 mA for LDO2 continuous output

current.

The TPS65262-1 is protected from overload and overtemperature fault conditions. The converter minimizes

excessive output overvoltage transients by taking advantage of the power good comparator. When the output is

more than 107.5% of the 0.6-V reference voltage, the high-side MOSFET is turned off until the internal feedback

voltage is lower than 105% of the 0.6-V reference voltage. The TPS65262-1 implements both high-side

MOSFET overload protection and bidirectional low-side MOSFET overload protections to avoid inductor current

runaway. If the overcurrent condition lasts for more than the OC wait time (0.5 ms), the converter shuts down

and restarts after the hiccup time (14 ms). The TPS65262-1 shuts down if the junction temperature is higher than

thermal shutdown trip point 160°C. When the junction temperature drops 20°C (typical) below the thermal

shutdown trip point, the TPS65262-1 is restarted under control of the soft-start circuit automatically.

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8.2 Functional Block Diagram

CLK2

CLK3

OSC-600-kHz

Phase Shift

V7V

VIN

CLK1

clk2

VIN2

VIN

V7V

V3V

V7V LDO

Bias

en_buck2

enable

BST2

LX2

BST

LX

BUCK2

MODE

PGND2

clk

1

PGND

vfb

V7V

FB2

VIN

VIN1

VIN

enable

en_buck1

BST1

LX1

BST

BUCK1

V7V

VIN

MODE

clk3

LX

VIN3

VIN

PGND1

PGND

Comp

vfb

en_buck3

MODE

enable

BST3

LX3

5 µA

SS1

BST

LX

BUCK3

SS

FB1

PGND3

PGND

vfb

COMP1

FB3

PGOOD

FB1

FB2

FB3

Power

Good

LVIN1

LVIN

LOUT

FB

VIN

3.6 µA

3 µA

LOUT1

en_ldo1

enable

LDO1

MODE

LFB1

2 kꢀ

6.3 V

1.2 V

3.6 µA

3 µA

en_buck1

en_buck2

en_buck3

en_ldo1

EN1(EN2, EN3)

State

Machine

2 kꢀ

6.3 V

1.2 V

VIN

LVIN2

LVIN

LOUT

FB

3.6 µA

3 µA

LOUT2

en_ldo2

enable

LDO2

LEN1(LEN2)

en_ldo2

2 kꢀ

6.3 V

LFB2

1.2 V

OT

Over

Temp

AGND

8.3 Feature Description

8.3.1 Adjusting the Output Voltage

The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI

recommends to use 1% tolerance, or better, divider resistors.

Vout

R1

FB

COMP

R2

0.6 V

图8-1. Voltage Divider Circuit

English Data Sheet: SLVSCN5

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0.6

R₂= R₁´

V_out- 0.6

(1)

To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator

is more sensitive to noise. 表8-1 shows the recommended resistor values.

表8-1. Output Resistor Divider Selection

R1

(kΩ)

R2

(kΩ)

Output Voltage

(V)

1

10

15

10

1.2

1.5

1.8

2.5

3.3

5

15

10

20

10

31.6

45.3

22.6

73.2

36.5

10

4.99

10

5

4.99

8.3.2 Enable and Adjusting UVLO

The EN1, EN2, and EN3 pins provide electrical on and off control of the device. When the EN1, EN2, and EN3

pins' voltage exceeds the threshold voltage, the device starts operation. If each ENx pin voltage is pulled below

the threshold voltage, the regulator stops switching and enters low I_qstate.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If

an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the

pin.

The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage

falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500 mV. If an

application requires a higher UVLO threshold on the VIN pin, then the ENx pin can be configured as shown in 图

8-2. When using the external UVLO function, TI recommends to set the hysteresis to be greater than 500 mV.

The EN pin has a small pullup current, I_p, which sets the default state of the pin to enable when no external

components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO

function because it increases by I_hafter the EN pin crosses the enable threshold. The UVLO thresholds can be

calculated using 方程式2 and 方程式3.

æ

ö

÷

ø

V_ENFALLING

V

- V

STOP

_STARTç

V_ENRISING

è

R₁

=

æ

ö

V_ENFALLING

I

1-

+ I

÷

h

_Pç

V_ENRISING

è

ø

(2)

(3)

R₁´ V_ENFALLING

V_STOP- V_ENFALLING+ R I + I

R₂

=

₁(_h)

p

where

• I_h= 3 µA

• I_p= 3.6 µA

• V_ENRISING= 1.2 V

• V_ENFALLING= 1.15 V

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VIN

i

h

R1

p

i

EN

R2

图8-2. Adjustable VIN UVLO

8.3.3 Soft-Start Time

The voltage on the SS1 pin controls the start-up of buck1 output. When the voltage on the SS1 pin is less than

the internal 0.6-V reference, The TPS65262-1 regulates the internal feedback voltage to the voltage on the SS1

pin instead of 0.6 V, allowing VOUT to rise smoothly from 0 V to its regulated voltage without inrush current. The

device has an internal pullup current source of 5 µA (typical) that charges an external soft-start capacitor to

provide a linear ramping voltage at SS1 pin.

Buck1’s soft-start time can be calculated approximately by 方程式4.

Buck2 and Buck3 have fixed 1-ms soft-start time.

Css(nF)´ Vref(V)

Tss(ms) =

Iss(mA)

(4)

8.3.4 Power-Up Sequencing

TPS65262-1 features a comprehensive sequencing circuit for the three bucks. If the MODE pin is driving to high

at the same time EN1 or EN2 pin (or both), the automatic power-up and power-down sequence function is

active. If MODE pin ties low to ground, three buck on or off is separately controlled by three enable pins.

8.3.4.1 External Power Sequencing

The TPS65262-1 has a dedicated enable pin for each converter. The converter enable pins are biased by a

current source that allows for easy sequencing with the addition of an external capacitor. Disabling the converter

with an active pulldown transistor on the ENx pin allows for a predictable power-down timing operation. 图 8-3

shows the timing diagram of a typical buck power-up sequence with a capacitor connected at ENx pin.

A typical 1.4-µA current charges the ENx pin from the input supply when the ENx pin voltage is lower than

typical 0.4 V. The internal V7V LDO turns on when the ENx pin voltage rises to typical 0.4 V and a 3.6-µA pullup

current sources ENx. After the ENx pin voltage reaches 1.2 V typical, 3-µA hysteresis current sources to the pin

to improve noise sensitivity. If all output voltages are in regulation, PGOOD is asserted after PGOOD deglitch

time.

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VIN

V7V

EN Threshold

ENx Rise Time

Dictated by C_EN

Charge C_EN

with 6.6 µA

ENx

Soft Start Rise Time

Dictated by C_SS

Pre-Bias Startup

PGOOD Deglitch Time

VOUTx

T = C_SS× 0.6 V /5 µA

T = C_EN× (1.2 œ 0.4) V / 3.6 µA

T = C_EN× 0.4 V / 1.4 µA

PGOOD

图8-3. Startup Power Sequence

8.3.4.2 Automatic Power Sequencing

The TPS65262-1 starts with a predefined power-up and power-down sequence when the MODE pin is driven to

high. As shown in 表 8-2, the sequence is dictated by different combinations of the EN1 and EN2 status. EN3 is

used to start or stop the converters. Buck2 and buck3 are identical converters and can be swapped in the

system operation to allow for additional sequencing stages. 图 8-4 shows the power sequencing when EN1 and

EN2 are pulled up high.

表8-2. Power Sequencing

MODE

High

EN1

High

Low

High

Low

EN2

High

Low

EN3

Start Sequencing

Buck1→buck2→buck3

Buck2→buck1→buck3

Buck2→buck3→buck1

Reserved

Shutdown Sequencing

Buck3→buck2→buck1

Buck3→buck1→buck2

Buck1→buck3→buck2

Reserved

Used to start or stop

bucks in sequence

Automatic power

sequencing

Reserved

Externally

controlled

sequencing

Used to start or

stop buck1

Used to start or Used to start or stop

stop buck2 buck3

Low

x

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VIN

V7V

MODE

EN1

EN2

EN3

Buck1

Buck2

Buck3

PGOOD

t1

t2

t3

t4

T_psdelay= t1 = t2 = t3 = t4 = 1.7 ms

图8-4. Automatic Power Sequencing

8.3.5 V7V Low Dropout Regulator and Bootstrap

Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V

pin. The internal built-in low dropout linear regulator (LDO) supplies 6.3 V (typical) from VIN to V7V. A 10-µF

ceramic capacitor must be connected from V7V pin to power ground.

If the input voltage, VIN decreases to UVLO threshold voltage, the UVLO comparator detects V7V pin voltage

and forces the converter off.

Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in 图 8-5, which is

normally recharged during each cycle through an internal low-side MOSFET or the body diode of low-side

MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less

than VIN and the BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47

nF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or

higher because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is

powered from V7V pin directly.

To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage

is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX

drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is

turned on allowing the boot capacitor to be recharged.

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VIN

LDO

(VBSTx –VLXx)

2.1 V

+

nBootUV

–

PVINx

V7V

BSTx

C^BIAS

10 µF

High-side

MOSFET

nBootUV

PWM

UVLO Bias Buck

Controller

Gate

Driver

C^B

LXx

Low-side

MOSFET

nBootUV

PWM

Gate

Driver

BootUV

Protection

CLK

图8-5. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram

8.3.6 Out-of-Phase Operation

To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.

This enables the system having less input current ripple to reduce input capacitors’size, cost, and EMI.

8.3.7 Output Overvoltage Protection (OVP)

The device incorporates an output OVP circuit to minimize output voltage overshoot. When the output is

overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin

voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier

demands maximum output current. After the condition is removed, the regulator output rises and the error

amplifier output transitions to the steady-state voltage. In some applications with small output capacitance, the

load can respond faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck

compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the

high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot.

When the FB voltage drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock

cycle.

8.3.8 PSM

The TPS65262-1 can enter high-efficiency PSM operation at light load current.

When the controller is enabled for PSM operation, the peak inductor current is sensed and compared with 230-

mA current typically. Because the integrated current comparator catches the peak inductor current only, the

average load current entering PSM varies with the applications and external output filters. In PSM, the sensed

peak inductor current is clamped at 230 mA.

When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current

comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and

going negative.

Due to the delay in the circuit and current comparator tdly (typical 50 ns at Vin = 12 V), the real peak inductor

current threshold to turn off high-side power MOSFET can shift higher depending on inductor inductance and

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input or output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET

with 方程式5.

vin - vout

IL_PEAK=230mA +

´ tdly

L

(5)

After the charge accumulated on the Vout capacitor is more than loading needs, the COMP pin voltage drops to

low voltage driven by error amplifier. There is an internal comparator at the COMP pin. If the comp voltage is

lower than 0.35 V, the power stage stops switching to save power.

230 mA

Turn off

High-Side Power MOSFET

Inductor

Current Peak

Current

Current Comparator

Delay: tdly

Sensing

x1

IL_Peak

Inductor Peak Current

图8-6. PSM Current Comparator

8.3.9 Slope Compensation

To prevent subharmonic oscillations when the device operates at duty cycles greater than 50%, the device adds

built-in slope compensation, which is a compensating ramp to the switch current signal.

8.3.10 Overcurrent Protection (OCP)

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side

MOSFET and low-side MOSFET.

8.3.10.1 High-Side MOSFET OCP

The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-

side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current

and the current reference generated by the COMP pin voltage are compared. When the peak switch current

intersects the current reference, the high-side switch is turned off.

8.3.10.2 Low-Side MOSFET OCP

While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During

normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-

side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side

sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the

next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing

current limit at the start of a cycle.

The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) lasts for more than the

hiccup wait time (which is programmed for 0.5 ms, shown in 图 8-7) the device shuts down itself and restarts

after the hiccup time, 14 ms. The hiccup mode helps to reduce the device power dissipation under severe

overcurrent condition.

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OCP peak inductor current

threshold

Soft Start Time

buck1: T = Css × 0.6

V / 5 µA

Hiccup

Time

14 ms

OC limiting (waiting) time

Output over

loading

0.5 ms

buck2/3: 1 ms

iL

Inductor

Current

Soft-start is reset after OC waiting time

About 2.1 V

0.6V

OC fault removed, soft-start & output recovery

SS

SS Pin

Voltage

Output hard short circuit

Vout

Output

Voltage

图8-7. OCP

8.3.11 Power Good

The PGOOD pin is an open-drain output. When feedback voltage of each buck is between 95% (rising) and

105% (falling) of the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI

recommends to use a pullup resistor between the values of 10 to 100 kΩ to a voltage source that is 6.3 V or

less. The PGOOD is in a defined state when the VIN input voltage is greater than 1 V but with reduced current

sinking capability. The PGOOD achieves full current sinking capability when the VIN input voltage is above

UVLO threshold, which is 4.25 V typically.

The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling) or greater than

107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low, if the input voltage is

undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start

period.

8.3.12 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C

typically.

8.4 Device Functional Modes

8.4.1 Operation With V_IN< 4.5 V (Minimum V_IN)

The device operates with input voltages above 4.5 V. The maximum UVLO voltage is 4.5 V and operates at input

voltages above 4.5 V. The typical UVLO voltage is 4.25 V, and the device can operate at input voltages above

that point. The device also can operate at lower input voltages; the minimum UVLO voltage is 4 V (rising) and

3.5 V (falling). At input voltages below the UVLO minimum voltage, the device does not operate.

8.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.2 V typical and 1.26 V maximum. With EN held below that voltage,

the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When the

input voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the

device becomes active. Switching is enabled, and the soft-start sequence is initiated. The device starts at the

soft-start time determined by the external soft start capacitor as shown in 图9-2 to 图9-7.

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8.4.3 Operation at Light Loads

The device is designed to operate in high-efficiency PSM under light load conditions. Pulse skipping is initiated

when the switch current falls to 0.23 A. During pulse skipping, the low-side FET is turned off. The switching node

(LX) waveform takes on the characteristics of DCM operation and the apparent switching frequency decreases

as shown in 图9-8, 图9-10, and 图9-12.

English Data Sheet: SLVSCN5

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The device is triple-synchronous, step-down DC/DC converter with dual LDOs. The device is typically used to

convert a higher DC voltage to lower DC voltages with continuous available output current of 3 A/1 A/1 A. The

following design procedure can be used to select component values for the TPS65262-1. This section presents

a simplified discussion of the design process.

9.2 Typical Application

9.2.1 Design Requirements

This example details the design of a triple-synchronous step-down converter. A few parameters must be known

to start the design process. These parameters are typically determined at the system level. For this example,

start with the following known parameters shown in 表9-1.

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表9-1. Design Parameters

PARAMETER

VALUE

Vout1

1.2 V

Iout1

3 A

Vout2

1.8 V

Iout2

Vout3

1 A

3.3 V

Iout3

1 A

Buck1 transient response 1-A load step

Buck2, buck3 transient response 0.5-A load step

Input voltage

±5%

12 V normal, 4.5 to 18 V

±1%

Output voltage ripple

Switching frequency

600 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use 方程式 6. LIR is a coefficient that represents the amount of

inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In

general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for

the majority of applications.

V

- V_out

V_out

V_inmax´ ƒ_sw

inmax

L =

´

I_o´LIR

(6)

For the output filter inductor, it is important not to exceed the RMS current and saturation current ratings. The

RMS and peak inductor current can be found from 方程式8 and 方程式9.

V

- V_out

´

V_out

V_inmax´ ƒ_sw

inmax

I_ripple

=

L

(7)

æ

ö²

V_out´ V

- V_out

(

)

inmax

ç

÷

V_inmax´L ´ ƒ_sw

è

ø

I_Lrms

=

I_O²+

12

(8)

(9)

I_ripple

I_Lpeak=I_out

+

2

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,

faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit

of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current

rating equal to or greater than the switch current limit rather than the peak inductor current.

9.2.2.2 Output Capacitor Selection

The designer needs to account for three primary considerations when selecting the value of the output capacitor.

The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds

to a large change in load current. The output capacitance must be selected based on the most stringent of these

three criteria.

English Data Sheet: SLVSCN5

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The first criterion is the desired response to a large change in the load current. The output capacitor needs to

supply the load with current when the regulator cannot. This situation can occur if there are desired hold-up

times for the regulator where the output capacitor must hold the output voltage above a certain level for a

specified amount of time after the input power is removed. The regulator is also temporarily not able to supply

sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from

no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change

in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be

sized to supply the extra current to the load until the control loop responds to the load change. The output

capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a

tolerable amount of droop in the output voltage. 方程式 10 shows the minimum output capacitance necessary to

accomplish this.

2´ DI_out

C_o=

ƒ_sw´ DV_out

(10)

where

• ΔI_outis the change in output current.

• ƒ_swis the regulator's switching frequency.

• ΔV_outis the allowable change in the output voltage.

方程式11 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

1

C_o>

´

V_oripple

8´ ƒ_sw

I_oripple

(11)

where

• ƒ_swis the switching frequency.

• V_orippleis the maximum allowable output voltage ripple.

• I_orippleis the inductor ripple current.

方程式 12 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification.

V_oripple

R_esr

<

I_oripple

(12)

Additional capacitance deratings for aging, temperature, and DC bias must be factored in, which increase this

minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some

capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. 方程式 13 can

be used to calculate the RMS ripple current the output capacitor needs to support.

V_out´ V

- V_out

(

)

12 ´ V_inmax´L ´ ƒ_sw

inmax

I_corms

=

(13)

9.2.2.3 Input Capacitor Selection

The TPS65262-1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF

of effective capacitance on the VIN input voltage pins. In some applications, additional bulk capacitance can also

be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the

input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current

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rating greater than the maximum input current ripple of the TPS65262-1. Calculate the input ripple current using

方程式14.

V

(

- V_out

)

V_out

inmin

I

=I_out

´

inrms

V

inmin

(14)

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple

voltage of the regulator. Calculate the input voltage ripple using 方程式15.

I

_outmax´ 0.25

DV

=

in

C_in´ ƒ_sw

(15)

9.2.2.4 Loop Compensation

The TPS65262-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance

amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin

between 60° and 90°. C_badds a high frequency pole to attenuate high-frequency noise when needed. To

calculate the external compensation components, follow these steps.

1. Switching frequency, ƒ_sw, 600 kHz is appropriate for application depending on L and C sizes, output ripple,

EMI, and so forth. It also gives the best trade-off between performance and cost.

2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒ_sw.

3. R_Ccan be determined by 方程式16.

2p´ fc ´ Vo´ Co

R_C

=

G_m-EA´ Vref ´ G_m-PS

(16)

where

• G_{m_EA}is the error amplifier gain (300 µS)

• G_{m_PS}is the power stage voltage to current conversion gain (7.4 A/V)

æ

1

ö

.

ç^{ƒp =}

÷

C_o´ R_L

è

^{´ 2p}ø

4. Calculate C_Cby placing a compensation zero at or before the dominant pole

R_L´ Co

C_C

=

R_C

(17)

(18)

5. Optional C_bcan be used to cancel the zero from the ESR associated with C_O.

R

_ESR´ Co

C_b=

R_C

English Data Sheet: SLVSCN5

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LX

VOUT

i_L

R_ESR

Current

Sense I/V

Converter

G_{m_PS}= 7.4 A / V

R_L

C_o

C₁

R₁

Vfb

EA

FB

COMP

V_ref= 0.6 V

G_{m_EA}= 300

R_c

s

C_b

C_c

GND

图9-1. DC/DC Loop Compensation

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9.2.3 Application Curves

图9-2. BUCK1, Soft-Start With No Load

图9-4. BUCK2, Soft-Start With No Load

图9-6. BUCK3, Soft-Start With No Load

图9-3. BUCK1, Soft-Start With Full Load

图9-5. BUCK2, Soft-Start With Full Load

图9-7. BUCK3, Soft-Start With Full Load

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图9-8. Buck1, Steady State Operation at Light

Load

图9-9. Buck1, Steady State Operation at Full Load

图9-10. Buck2, Steady State Operation at Light 图9-11. Buck2, Steady State Operation at Full Load

Load

图9-12. Buck3, Steady State Operation at Light 图9-13. Buck3, Steady State Operation at Full Load

Load

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图9-14. Buck1, Load Transient, 0.75 to 1.5 A SR = 图9-15. Buck1, Load Transient, 1.5 to 2.25 A SR =

0.25 A/µs 0.25 A/µs

图9-16. Buck2, Load Transient, 0.25 to 0.5 A SR = 图9-17. Buck2, Load Transient, 0.5 to 0.75 A SR =

0.25 A/µs 0.25 A/µs

图9-18. Buck3, Load Transient, 0.25 to 0.5 A SR = 图9-19. Buck3, Load Transient, 0.5 to 0.75 A SR =

0.25 A/µs

English Data Sheet: SLVSCN5

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图9-20. Buck1, OCP

图9-22. Buck2, OCP

图9-24. Buck3, OCP

图9-21. Buck1, Hiccup and Recovery

图9-23. Buck2, Hiccup and Recovery

图9-25. Buck3, Hiccup and Recovery

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图9-26. Automatic Power Sequencing, MODE =

图9-27. Automatic Power Sequencing, MODE =

EN1 = EN2 = HIGH

图9-28. Automatic Power Sequencing, MODE =

图9-29. Automatic Power Sequencing, MODE =

EN1 = HIGH, EN2 = LOW

图9-30. Automatic Power Sequencing, MODE =

图9-31. Automatic Power Sequencing, MODE =

EN2 = HIGH, EN1 = LOW

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Operating at VIN = 12 V, VOUT1 = 1.2 V / 1.5 A, VOUT2 = 1.8

Operating at VIN = 12 V, VOUT1 = 1.2 V / 3 A, VOUT2 = 1.8

V / 1 A, VOUT3 = 3.3 V / 1 A,

V / 0.5 A, VOUT3 = 3.3 V / 0.5 A,

EVM Condition 4 Layers, 64 mm × 69 mm T_A= 30.5°C

图9-32. Thermal Signature of TPS65262-1EVM

图9-33. Thermal Signature of TPS65262-1EVM

9.3 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 4.5 to 18 V. This input power

supply must be well regulated. If the input supply is located more than a few inches from the TPS65262-1

converter, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 47 μF is a typical choice.

9.4 Layout

9.4.1 Layout Guidelines

The TPS65262-1 supports a 2-layer PCB layout, shown in 图9-34.

Layout is a critical portion of good power supply design. See 图9-34 for a PCB layout example. The top contains

the main power traces for VIN, VOUT, and LX. The top layer also has connections for the remaining pins of the

TPS65262-1 and a large top-side area filled with ground. The top-layer ground area must be connected to the

bottom-layer ground using vias at the input bypass capacitor, the output filter capacitor, and directly under the

TPS65262-1 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer

acts as a ground plane connecting analog ground and power ground.

For operation at full-rated load, the top-side ground area and bottom-side ground plane must provide adequate

heat dissipating area. Several signals paths conduct fast changing currents or voltages that can interact with

stray inductance or parasitic capacitance to generate noise or degrade the power supply's performance. To help

eliminate these problems, the VIN pin must be bypassed to ground with a low-ESR ceramic bypass capacitor

with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections,

VIN pins, and ground connections. The VIN pin must also be bypassed to ground using a low-ESR ceramic

capacitor with X5R or X7R dielectric.

Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor

ground must use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor

length while maintaining adequate width. The small signal components must be grounded to the analog ground

path.

The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as

possible to the IC and routed with minimal lengths of trace. The additional external components can be placed

approximately as shown in 图9-34.

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9.4.2 Layout Example

VOUT1

VOUT3

BST1

LX1

BST3

LX3

PGND1

VIN1

PGND3

VIN3

VIN

LEN1

LFB1

LOUT1

LVIN1

VIN2

PGND2

LX2

BST2

VOUT2

TOPSIDE

GROUND

AREA

0.010-inch diameter

Thermal VIA to Ground Plane

VIA to Ground Plane

图9-34. PCB Layout

English Data Sheet: SLVSCN5

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10 Device and Documentation Support

10.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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English Data Sheet: SLVSCN5

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

SEE SIDE WALL

DETAIL

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS65262-1RHBR
厂家：	TEXAS INSTRUMENTS
描述：	具有 350mA/150mA 双 LDO 的 4.5V 至 18V 输入、3A/1A/1A 三路同步降压转换器 \| RHB \| 32 \| -40 to 85 开关转换器
文件：	总46页 (文件大小：2954K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65262-1RHBR [TI]

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