TPS65262-2RHBT [TI]
具有 350mA/150mA 双 LDO 的 4.5V 至 18V 输入电压、3A/1A/1A 三路同步降压转换器 | RHB | 32 | -40 to 85;
| 型号： | TPS65262-2RHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 350mA/150mA 双 LDO 的 4.5V 至 18V 输入电压、3A/1A/1A 三路同步降压转换器 | RHB | 32 | -40 to 85 开关 输出元件 转换器 |
| 文件： | 总44页 (文件大小：4015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65262-2
ZHCSEM0C –DECEMBER 2015 –REVISED MAY 2023
TPS65262-2 具有双路可调350mA/150mA LDO 的4.5V 至18V 输入电压、
3A/1A/1A 输出电流三路同步降压转换器
1 特性
3 说明
• 工作输入电压范围：4.5V 至18V
• 反馈基准电压：0.6V ±1%
• 最大连续输出电流：3A/1A/1A
• 600kHz 固定开关频率
• 集成双路LDO 的输入电压范围：1.3V 至18V，且
持续输出电流：350mA/150mA
• 针对Buck1 的可编程软启动时间
• 针对Buck2 和Buck3 的固定软启动时间1ms
• 针对Buck2 和Buck3 的内部环路补偿
• 针对每次降压的专用使能引脚
• 支持脉冲跳跃模式(PSM) 和强制连续电流模式
(FCCM)
• 输出电压电源正常状态指示器
• 热过载保护
• 32 引脚VQFN (RHB) 5mm × 5mm 封装
• 具有过压保护、过流和短路保护以及过热保护功能
TPS65262-2 是一款具有 3A/1A/1A 输出电流的单片三
路同步降压转换器。4.5V 至 18V 的宽输入电源电压范
围包括大多数由 5V、9V、12V 或 15V 电源总线提供
的中间总线电压。该转换器具有恒定频率峰值电流模
式，旨在简化应用，同时方便设计人员根据目标应用来
优化系统。此器件在 600kHz 的固定开关频率下运行。
为了减少外部元件数量，集成了针对 buck2 和 buck3
的环路补偿。buck1 和 buck 2，3 之间的 180°异相运
行（buck2 和 buck3 同相运行）最大限度地减少了对
输入滤波器的要求。
TPS65262-2 可通过将 MODE 引脚连接至 GND 进入
脉冲跳跃模式 (PSM)，通过将 MODE 引脚驱动为高电
平或保持悬空进入强制持续电流模式 (FCC)。PSM 模
式通过减少轻负载时的开关损耗来提供高效率，而
FCC 模式可降低噪声灵敏度和射频(RF) 干扰。
此外，TPS65262-2 还内置两个低压降线性稳压器
(LDO)，它们的输入电压范围为 1.3V 至 18V，持续输
出电流为 350mA/150mA，具有独立使能和可调输出电
压。
2 应用
• 数字电视(DTV)
• 机顶盒
• 家庭网关和接入点网络
• 无线路由器
• 安全监控
电源正常引脚在任何输出电压超出稳压范围时变为有
效。
封装信息(1)
• POS 机
封装尺寸（标称值）
器件型号
TPS65262-2
封装
RHB（VQFN，32）
5.00mm × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100%
Vout1
Vin
VINx
LX1
80%
60%
40%
20%
PGOOD
MODE
ENx
FB1
LX2
Vout2
Vout3
SS1
TPS65262-2
LVIN1
LOUT1
LFB1
LDO1
LDO2
FB2
LX3
LEN1
GND
GND
LVIN2
LOUT2
LFB2
PSM Mode
V IN = 5 V; V OUT = 1.2 V
PWM Mode
LEN2
0
10m
FB3
100m
Output Load (A)
1
AGND PGND
D001
效率与输出负载之间的关系
应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD87
TPS65262-2
ZHCSEM0C –DECEMBER 2015 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
8.3 Power Supply Recommendations.............................32
8.4 Layout....................................................................... 32
9 Device and Documentation Support............................35
9.1 接收文档更新通知..................................................... 35
9.2 支持资源....................................................................35
9.3 Trademarks...............................................................35
9.4 静电放电警告............................................................ 35
9.5 术语表....................................................................... 35
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................7
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................14
Information.................................................................... 35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2019) to Revision C (May 2023)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 通篇去除了图像的颜色........................................................................................................................................1
• Changed the description of V7V pin in the 表5-1 ..............................................................................................3
• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator
and Bootstrap .................................................................................................................................................. 17
• Changed the recommended value of C6 in 图8-1 .......................................................................................... 22
Changes from Revision A (December 2015) to Revision B (July 2019)
Page
• Added TJ = 25°C temperature condition for LDO1 current limit in the Electrical Characteristics .......................7
• Added TJ = 25°C temperature condition for LDO2 current limit in the Electrical Characteristics .......................7
Changes from Revision * (December 2015) to Revision A (December 2015)
Page
• 已将器件状态更新为量产数据.............................................................................................................................1
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English Data Sheet: SLVSD87
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5 Pin Configuration and Functions
24 23 22 21 20 19 18 17
16
15
14
13
12
BST3
LX3
25
26
27
28
BST1
LX1
PGND3
VIN3
PGND1
VIN1
Thermal Pad
VIN2
LEN1 29
LFB1 30
11 PGND2
LX2
10
9
LOUT1
31
LVIN1 32
BST2
2
3
4
5
6
7
8
1
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal
performance.)
图5-1. 32-Pin Plastic VQFN RHB Package Top View
表5-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
Input power supply for LDO2. Connect LVIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 1 µF).
LVIN2
1
LOUT2
LFB2
2
3
4
LDO2 output. Connect LOUT2 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
Feedback Kelvin sensing pin for LDO2 output voltage. Connect this pin to LDO2 resistor divider.
Enable for LDO2. Float to enable.
LEN2
An open-drain output, asserts low if output voltage of any buck is beyond regulation range due to thermal shutdown,
overcurrent, undervoltage, or ENx shut down.
PGOOD
5
MODE
FB2
6
7
Switch FCC mode and PSM mode. Pull high or leave floating, FCC mode. Pull low, PSM mode.
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor
divider.
EN2
8
Boot strapped supply to the high side floating gate driver in Buck2. Connect a capacitor (recommend 47 nF) from BST2
pin to LX2 pin.
BST2
LX2
9
Switching node connection to the inductor and bootstrap capacitor for Buck2. The voltage swing at this pin is from a
diode voltage below the ground up to VIN2 voltage.
10
11
12
13
14
15
Power ground connection of Buck2. Connect PGND2 pin as close as possible to the (–) terminal of VIN2 input ceramic
capacitor.
PGND2
VIN2
VIN3
PGND3
LX3
Input power supply for Buck2. Connect VIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
Input power supply for Buck3. Connect VIN3 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
Power ground connection of Buck3. Connect PGND3 pin as close as possible to the (–) terminal of VIN3 input ceramic
capacitor.
Switching node connection to the inductor and bootstrap capacitor for Buck3. The voltage swing at this pin is from a
diode voltage below the ground up to VIN3 voltage.
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表5-1. Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
Boot strapped supply to the high side floating gate driver in Buck3. Connect a capacitor (recommend 47 nF) from BST3
pin to LX3 pin.
BST3
16
Enable for Buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of Buck3 with a resistor
divider.
EN3
FB3
17
18 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to Buck3 resistor divider.
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current
power grounds to the (-) terminal of bypass capacitor of input voltage VIN.
AGND
V7V
19
20 Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground.
Error amplifier output and loop compensation pin for Buck1. Connect a series resistor and capacitor to compensate the
control loop of buck1 with peak current PWM mode.
COMP1
21
Soft-start and tracking input for Buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time
can be programmed by connecting a capacitor between this pin and ground.
SS1
FB1
EN1
22
23 Feedback Kelvin sensing pin for Buck1 output voltage. Connect this pin to Buck1 resistor divider.
Enable for Buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of Buck1 with a resistor
divider.
24
Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1
pin to LX1 pin.
BST1
LX1
25
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a
diode voltage below the ground up to VIN1 voltage.
26
Power ground connection of buck1. Connect PGND1 pin as close as possible to the (–) terminal of VIN1 input ceramic
capacitor.
PGND1
VIN1
27
Input power supply for buck1. Connect VIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
28
LEN1
LFB1
29 Enable for LDO1. Float to enable.
30 Feedback Kelvin sensing pin for LDO1 output voltage. Connect this pin to LDO1 resistor divider.
31 LDO1 output. Connect LOUT1 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
LOUT1
Input power supply for LDO1. Connect LVIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 1 µF).
LVIN1
PAD
32
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (operating in a typical application circuit)(1)
MIN
MAX
20
20
7
UNIT
VIN1, VIN2, VIN3, LVIN1, LVIN2
–0.3
–1.0
–0.3
–0.3
–0.3
–0.3
–0.3
–40
LX1, LX2, LX3 (Maximum withstand voltage transient <20 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
MODE, LEN1, LEN2, EN1, EN2, EN3, PGOOD, V7V
LOUT1, LOUT2
Voltage
7
V
7
FB1, FB2, FB3, LFB1, LFB2, COMP1 , SS1
AGND, PGND1, PGND2, PGND3
3.6
0.3
125
150
TJ
Operating junction temperature
°C
°C
Tstg
Storage temperature
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1 kV
can actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250
V can actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX UNIT
VIN1, VIN2, VIN3, LVIN1, LVIN2
18
18
LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
MODE, LEN1, LEN2, EN1, EN2, EN3, PGOOD, V7V
FB1, FB2, FB3, LFB1, LFB2, COMP1 , SS1
LOUT1, LOUT2
–0.8
–0.1
–0.1
–0.1
–0.1
–40
6.8
V
6.3
Voltage
3
5.5
TJ
Operating junction temperature
125
°C
6.4 Thermal Information
TPS65262-2
THERMAL METRIC(1)
RHB (VQFN)
UNIT
32 PINS
32
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
24.2
6.4
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
6.4
ψJB
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TPS65262-2
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TPS65262-2
RHB (VQFN)
32 PINS
THERMAL METRIC(1)
UNIT
RθJc(bot)
Junction-to-case (bottom) thermal resistance
1.3
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input voltage range
4.5
4
18
4.5
4
V
V
VIN rising
VIN falling
Hysteresis
4.25
3.75
500
12
UVLO
VIN undervoltage lockout
Shutdown supply current
3.5
mV
µA
IDDSDN
EN1 = EN2 = EN3 = MODE = LEN1 = LEN2 = 0 V
EN1 = EN2 = EN3 = 5V, FB1 = FB2 = FB3 = 0.8 V,
LEN1 = LEN2 = 0 V
IDDQ_NSW
790
340
370
370
190
190
µA
µA
µA
µA
µA
µA
EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V,
LEN1 = LEN2 = 0 V
IDDQ_NSW1
IDDQ_NSW2
IDDQ_NSW3
IDDQ_LDO1
IDDQ_LDO2
Input quiescent current without
buck1/2/3 switching
EN2 = 5 V, EN1 = EN3 = 0V, FB2 = 0.8 V,
LEN1 = LEN2 = 0 V
EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V,
LEN1 = LEN2 = 0 V
EN1 = EN2 = EN3 = LEN2 = 0 V, LFB1 = 0.8 V, LEN1 =
5 V
LDO input quiescent current
EN1 = EN2 = EN3 = LEN1 = 0 V, LFB2 = 0.8 V, LEN2 =
5 V
V7V
V7V LDO output voltage
V7V LDO current limit
VIN1 = 12 V; V7V load current = 0 A
6.0
6.3
6.6
V
IOCP_V7V
175
mA
FEEDBACK VOLTAGE REFERENCE
VCOMP = 1.2 V, TJ = 25°C
0.595
0.594
0.6
0.6
0.605
0.606
V
V
VFB
Feedback voltage
VCOMP = 1.2 V, TJ = –40°C to 125°C
IOUT1 = 1.5 A, IOUT2 = 1 A,
IOUT3 = 1 A, 5 V < VINx < 18 V
VLINEREG_Buck
VLOADREG_Buck
Line regulation-DC(1)
Load regulation-DC(1)
0.002
0.02
%/V
%/A
VIN = 12 V, IOUTx = (10-100%) × IOUTx_max
BUCK1, BUCK2, BUCK3
VENXH
VENXL
IENX
EN1/2/3 high level input voltage
1.2
1.15
3.6
6.6
3
1.27
V
EN1/2/3 low level input voltage
EN1/2/3 pullup current
1.0
4.3
V
ENx = 1 V
µA
µA
µA
µA
ms
ns
µS
IENX
EN1/2/3 pullup current
ENx = 1.5 V
IENhys
ISS1
Hysteresis current
Buck1 soft start charging current
Buck2/3 soft start time
5
6.1
TSS2/3
TON_MIN
Gm_EA1/2/3
1
Minimum on time
80
100
Error amplifier trans-conductance
300
–2 µA < ICOMPX < 2 µA
COMP voltage to inductor current Gm
Gm_PS1/2/3
ILX = 0.5 A
7.4
A/V
(1)
ILIMIT1
Buck1 peak inductor current limit
Buck1 low-side source current limit
Buck1 low-side sink current limit
Buck2/3 peak inductor current limit
Buck2/3 low-side source current limit
Buck2/3 low-side sink current limit
OC wait time(1)
4.2
1.8
5.1
4.4
1.3
2.4
1.75
1
6
3
A
A
ILIMITSOURCE1
ILIMITS1
A
ILIMIT2/3
A
ILIMITSOURCE2/3
ILIMITS2/3
tHiccup_wait
tHiccup_re
A
A
0.5
14
ms
ms
mΩ
mΩ
mΩ
mΩ
Hiccup time before restart(1)
Rdson_HS1
Rdson_LS1
Rdson_HS2
Rdson_LS2
Buck1 High-side switch resistance
Buck1 low-side switch resistance
Buck2 High-side switch resistance
Buck2 low-side switch resistance
VIN1 = 12 V
VIN1 = 12 V
VIN1 = 12 V
VIN1 = 12 V
100
65
195
145
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
195
145
MAX
UNIT
mΩ
Rdson_HS3
Rdson_LS3
Buck3 High-side switch resistance
Buck3 low-side switch resistance
VIN1 = 12 V
VIN1 = 12 V
mΩ
POWER GOOD, MODE, POWER SEQUENCE
FBx undervoltage falling
FBx undervoltage rising
FBx overvoltage rising
FBx overvoltage falling
92.5%
95%
Vth_PG
Feedback voltage threshold
VREF
107.5%
105%
0.19
tDEGLITCH(PG)_F
tRDEGLITCH(PG)_R
IPG
PGOOD falling edge deglitch time
PGOOD rising edge deglitch time
PGOOD pin leakage
ms
ms
µA
V
1
0.05
0.4
VLOW_PG
VMODEH
PGOOD pin low voltage
ISINK = 1 mA
MODE high level input voltage
MODE low level input voltage
MODE pullup current
1.2
1.15
3.6
1.27
V
VMODEL
1.0
1.0
V
IMODE
MODE = 1 V
µA
µA
IMODE
MODE pullup current
MODE = 1.5 V
6.6
LDO1 AND LDO2
VLENXH
LEN1, LEN2 high-level input voltage
LEN1, LEN2 low-level input voltage
1.2
1.15
3.6
1.27
V
V
VLENXL
LENx = 1 V
ILENX
LEN1, LEN2 pullup current
µA
LENx = 1.5 V
6.6
VINLDO1
LDO input voltage range
LDO output voltage range
LDO voltage reference
LDO current limit
1.3
1
18
5.5
V
V
VOUTLDO1
VLDOFB1
load current = 350 mA, VIN = 12 V
load current = 10 mA, VIN = 12 V
TJ = 25°C
0.593
350
0.6
440
12
0.607
559
V
Imax_LDO1
mA
mV
mV
IOUT = 20 mA
Vdropout1
LDO dropout voltage
IOUT = 200 mA
120
VOUT = 1.8 V, IOUT = 10 mA, LVIN1 changes from 2 to 18
V
VLINEREG_LDO1
VLOADREG_LDO1
PSRRLDO1
LDO line regulation-DC(1)
LDO load regulation-DC(1)
Ripple rejection(1)
0.002
0.2
%/V
%/A
dB
IOUT = 1 mA to 350 mA
Vin_LDO1 = 12 V, VOUT = 1.8 V, IOUT = 10 mA,
ƒ= 10 kHz
56
VINLDO2
LDO input voltage range
LDO output voltage range
LDO voltage reference
LDO current limit
1.3
1
18
5.5
V
V
VOUTLDO2
VLDOFB2
Load current = 150 mA, VIN = 12 V
Load current = 10 mA, VIN = 12 V
TJ = 25°C
0.593
160
0.6
230
12
0.607
295
V
Imax_LDO2
mA
mV
mV
IOUT = 10 mA
Vdropout2
LDO drop out voltage
IOUT = 100 mA
120
VOUT = 1.8 V, IOUT = 10 mA, LVIN1 changes from 2 to 18
V
VLINEREG_LDO2
VLOADREG_LDO2
PSRRLDO2
LDO line regulation-DC(1)
LDO load regulation-DC(1)
Ripple rejection(1)
0.002
0.2
%/V
%/A
dB
IOUT = 1 to 150 mA, VIN = 12 V
Vin_LDO2 = 12 V, VOUT = 1.8 V, IOUT = 10 mA,
ƒ= 10 kHz
56
OSCILLATOR
Switching frequency
540
600
670
kHz
ƒSW
THERMAL PROTECTION
TTRIP_OTP
Temperature rising
Hysteresis
160
20
°C
°C
Thermal protection trip point(1)
THYST_OTP
(1) Lab validation result.
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6.6 Typical Characteristics
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V, ƒSW = 600 kHz (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
PSM Mode VOUT 1.8 V
PSM Mode VOUT 3.3 V
PSM Mode VOUT 5 V
PSM Mode VOUT 1.2 V
PSM Mode VOUT 3.3 V
PSM Mode VOUT 5 V
0.01
0.10
1.00
0.01
0.10
1.00
Output Load t A
Output Load t A
C002
C002
图6-1. Buck1 Efficiency
图6-2. Buck2 Efficiency
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
VIN 5 V
VIN 5 V
VIN 12 V
VIN 12 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
0.6
0.8
1.0
Output Load t A
Output Load t A
C004
C004
图6-3. Buck1, PSM Mode Load Regulation
图6-4. Buck2, PSM Mode Load Regulation
3.33
3.32
3.31
3.30
3.29
3.28
3.27
1.208
1.206
1.204
1.202
1.200
1.198
1.196
1.194
1.192
IOUT 0.1 A
VIN 5 V
VIN 12 V
IOUT 1.5 A
IOUT 3 A
0.0
0.2
0.4
0.6
0.8
1.0
4
6
8
10
12
14
16
18
Output Load t A
Input Voltage t V
C004
C007
图6-5. Buck3, PSM Mode Load Regulation
图6-6. Buck1, PSM Mode Line Regulation
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6.6 Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V, ƒSW = 600 kHz (unless otherwise noted)
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
3.320
3.315
3.310
3.305
3.300
3.295
3.290
3.285
3.280
IOUT 0.1 A
IOUT 0.5 A
IOUT 1 A
IOUT 0.1 A
IOUT 0.5 A
IOUT 1 A
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
Input Voltage t V
Input Voltage t V
C007
C007
图6-7. Buck2, PSM Mode Line Regulation
图6-8. Buck3, PSM Mode Line Regulation
1.82
1.81
1.8
1.82
1.81
1.8
1.79
1.79
1.78
0
1.78
0
0.05
0.1
0.15 0.2
Output Load - A
0.25
0.3
0.35
0.03
0.06 0.09
Output Load - A
0.12
0.15
D001
D001
图6-9. LDO1, Load Regulation, VIN = 3.3 V
图6-10. LDO2, Load Regulation, VIN = 3.3 V
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
IOUT 0.02 A
IOUT 0.1 A
IOUT 0.2 A
IOUT 0.01 A
IOUT 0.05 A
IOUT 0.1 A
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
Input Voltage t V
Input Voltage t V
C007
C007
图6-11. LDO1, Line Regulation
图6-12. LDO2, Line Regulation
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6.6 Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V, ƒSW = 600 kHz (unless otherwise noted)
0.606
0.604
0.602
0.600
0.598
0.596
0.594
640
620
600
580
560
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C014
C014
图6-13. Voltage Reference vs Temperature
图6-14. Oscillator Frequency vs Temperature
18
16
14
12
10
8
4.8
4.2
3.6
3.0
2.4
6
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C014
C014
图6-15. Shutdown Quiescent Current vs Temperature
图6-16. EN Pin Pullup Current vs Temperature, EN = 1 V
7.8
1.28
7.2
6.6
6.0
5.4
1.24
1.20
1.16
1.12
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C014
C014
图6-17. EN Pin Pullup Current vs Temperature, EN = 1.5 V
图6-18. EN Pin Threshold Rising vs Temperature
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6.6 Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V, ƒSW = 600 kHz (unless otherwise noted)
1.23
1.19
1.15
1.11
1.07
5.8
5.4
5.0
4.6
4.2
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C014
C014
图6-19. EN Pin Threshold Falling vs Temperature
图6-20. SS Pin Charge Current vs Temperature
5.5
2.8
5.3
5.1
4.9
4.7
2.6
2.4
2.2
buck2
buck3
2.0
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C014
C014
图6-21. Buck1 High-Side Current Limit vs Temperature
图6-22. Buck2, 3 High-Side Current Limit vs Temperature
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7 Detailed Description
7.1 Overview
The TPS65262-2 is a monolithic, triple, synchronous step-down (buck) converter with 3-A/1-A/1-A output
currents. A wide 4.5- to 18-V input supply voltage range encompasses most intermediate bus voltages operating
off 5-V, 9-V, 12-V, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is
independent with dedicated enable, soft-start and loop compensation.
The TPS65262-2 implements a constant frequency, peak current mode control that simplifies external loop
compensation. The switching frequency is fixed 600 kHz. The switching clock of buck1 is 180° out-of-phase
operation from the clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size and
power supply induced noise.
The TPS65262-2 has been designed for safe monotonic startup into pre-biased loads. The default start-up is
when VIN is typically 4.5 V. The ENx pin also can be used to adjust the input voltage undervoltage lockout
(UVLO) with an external resistor divider. In addition, the ENx pin has an internal 3.6-µA current source, so the
EN pin can be floating for automatically powering up the converters.
The TPS65262-2 reduces the external component count by integrating the bootstrap circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit
monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the
threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65262-2 can operate at 100% duty
cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is typically
2.1 V.
The TPS65262-2 features a PGOOD pin to supervise each output voltage of buck converters. The TPS65262-2
has power good comparators with hysteresis, which monitor the output voltages through feedback voltages.
When all bucks are in regulation range and power sequence is done, PGOOD is asserted to high.
The SS (soft start, tracking) pin is used to minimize inrush currents during power up. A small value capacitor or
resistor divider is coupled to the pin for soft start or voltage tracking.
The TPS65262-2 operates in pulse skipping mode (PSM) with connecting MODE pin to GND and operates in
forced continuous current (FCC) mode with driving MODE pin to high or leaving float.
The TPS65262-2 integrates low drop-out voltage linear regulators (LDO) with input voltage from 1.3 to 18 V,
independent enable and adjustable outputs, up to 350 mA for LDO1 and 150 mA for LDO2 continuous output
current.
The TPS65262-2 is protected from overload and over temperature fault conditions. The converter minimizes
excessive output overvoltage transients by taking advantage of the power good comparator. When the output is
over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6-V
reference voltage. The TPS65262-2 implements both high-side MOSFET overload protection and bidirectional
low-side MOSFET overload protections to avoid inductor current runaway. If the over current condition has
lasted for more than the OC wait time (0.5 ms), the converter shuts down and restart after the hiccup time (14
ms). The TPS65262-2 shuts down if the junction temperature is higher than thermal shutdown trip point 160°C.
When the junction temperature drops 20°C (typical) below the thermal shutdown trip point, the TPS65262-2 is
restarted under control of the soft-start circuit automatically.
The TPS65262-2 is available in a 32-lead thermally-enhanced VQFN (RHB) package.
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7.2 Functional Block Diagram
CLK2
CLK3
OSC-600kHz
Phase Shift
V7V
VIN
CLK1
clk2
VIN2
VIN
V7V
V3V
V7V LDO
Bias
en_buck2
enable
BST2
LX2
BST
LX
BUCK2
MODE
PGND2
PGND
vfb
clk1
V7V
VIN
FB2
VIN
VIN1
BST1
enable
en_buck1
BST
LX
BUCK1
V7V
VIN
LX1
clk3
MODE
VIN3
VIN
PGND1
PGND
Comp
vfb
en_buck3
MODE
enable
BST3
LX3
5uA
BST
LX
BUCK3
SS1
SS
FB1
PGND3
PGND
vfb
COMP1
FB3
PGOOD
FB1
FB2
FB3
Power
Good
LVIN1
LVIN
VIN
3.6uA
3uA
3uA
3uA
LOUT1
en_ldo1
enable
LOUT
LDO1
MODE
LFB1
2K
FB
6.3V
1.2V
3.6uA
en_buck1
en_buck2
en_buck3
en_ldo1
EN1(EN2, EN3)
State
Machine
2K
6.3V
1.2V
LVIN2
LVIN
LOUT
FB
VIN
3.6uA
LOUT2
en_ldo2
enable
LDO2
LEN1(LEN2)
AGND
en_ldo2
2K
6.3V
LFB2
1.2V
OT
Over
Temp
7.3 Feature Description
7.3.1 Adjusting the Output Voltage
The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI
recommends to use 1% tolerance or better divider resistors.
Vout
R1
FB
COMP
–
+
R2
0.6 V
图7-1. Voltage Divider Circuit
0.6
R2 = R1 ´
Vout - 0.6
(1)
To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. The recommended resistor values are shown in 表7-1.
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表7-1. Output Resistor Divider Selection
R1
(kΩ)
R2
(kΩ)
OUTPUT VOLTAGE
(V)
1
10
10
15
10
1.2
1.5
1.8
2.5
3.3
3.3
5
15
10
20
10
31.6
45.3
22.6
73.2
36.5
10
10
4.99
10
5
4.99
7.3.2 Enable and Adjusting Undervoltage Lockout
The EN1/2/3 pin provides electrical on/off control of the device. After the EN1/2/3 pin voltage exceeds the
threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low Iq state.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500mV. If an
application requires a higher UVLO threshold on the VIN pin, then the ENx pin can be configured as shown in 图
7-2. When using the external UVLO function TI recommends to set the hysteresis to be greater than 500mV.
The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using 方程式2 and 方程式3.
æ
ö
÷
ø
VENFALLING
V
- V
STOP
START ç
VENRISING
è
R1
=
æ
ö
VENFALLING
I
1-
+ I
÷
h
P ç
VENRISING
è
ø
(2)
(3)
spacer
R1 ´ VENFALLING
VSTOP - VENFALLING + R I + I
R2
=
1 (h )
p
where
• Ih= 3 µA
• Ip= 3.6 µA
• VENRISING= 1.2 V
• VENFALLING= 1.15 V
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VIN
EN
i
h
R1
R2
i
p
图7-2. Adjustable VIN Undervoltage Lockout
7.3.3 Soft-Start Time
The voltage on the SS1 pin controls the start-up of buck1 output. When the voltage on the SS1 pin is less than
the internal 0.6-V reference, The TPS65262-2 regulates the internal feedback voltage to the voltage on the SS1
pin instead of 0.6 V, allowing VOUT to rise smoothly from 0 V to its regulated voltage without inrush current. The
device has an internal pullup current source of 5 µA (typical) that charges an external soft-start capacitor to
provide a linear ramping voltage at SS1 pin.
Buck1 soft-start time can be calculated approximately by 方程式4.
Buck2 and Buck3 have fixed 1-ms soft start time.
æ
ç
è
ö
÷
ø
0.6V
Tss(ms) =Css(nF)´
5mA
(4)
7.3.4 Power-Up Sequencing
The TPS65262-2 has dedicated enable pin for each converter. The converter enable pins are biased by a
current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter
with an active pull-down transistor on the ENx pin allows for a predictable power-down timing operation. 图 7-3
shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.
A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the
internal V7V LDO turns on. A 3.6-µA pullup current is sourcing ENx. After ENx pin voltage reaches to 1.2 V
typical, 3-µA hysteresis current sources to the pin to improve noise sensitivity. If all output voltages are in the
regulation, PGOOD is asserted after PGOOD deglitch time.
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VIN
V7 V
EN Threshold
Enx Rise Time
Dectated by CEN
EN Threshold
Charge CEN
with 6.6 uA
ENx
Soft Start Rise Time
Dictated by CSS
Pre-Bias Startup
PGOOD Deglitch Time
VOUTx
T = CSS × 0.6V / 5 uA
T = CEN × (1.2 - 0.4) V / 3.6 uA
T = CEN × 0.4 V / 1.4 uA
PGOOD
图7-3. Startup Power Sequence
7.3.5 V7V Low Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low dropout linear regulator (LDO) supplies 6.3 V (typical) from VIN to V7V. A 10-µF
ceramic capacitor must be connected from V7V pin to power ground.
If the input voltage, VIN decreases to UVLO threshold voltage, the UVLO comparator detects V7V pin voltage
and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in 图 7-4, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF. TI
recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher
because of the stable characteristics overtemperature and voltage. Each low-side MOSFET driver is powered
from V7V pin directly.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
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VIN
LDO
(VBSTx –VLXx)
+
nBootUV
–
2.1 V
PVINx
V7V
BSTx
CBIAS
10 µF
High-side
MOSFET
nBootUV
PWM
UVLO Bias Buck
Controller
Gate
Driver
CB
LXx
Low-side
MOSFET
nBootUV
PWM
Gate
Driver
BootUV
Protection
CLK
图7-4. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
7.3.6 Out-of-Phase Operation
To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.
This enables the system having less input current ripple to reduce input capacitor size, cost, and EMI.
7.3.7 Output Overvoltage Protection (OVP)
The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded,
the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is
lower than the internal reference voltage for a considerable time, the output of the error amplifier demands
maximum output current. After the condition is removed, the regulator output rises and the error amplifier output
transitions to the steady state voltage. In some applications with small output capacitance, the load can respond
faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB
pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET
is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage
drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.
7.3.8 PSM
If the MODE pin is connected to GND, the TPS65262-2 can enter high-efficiency PSM operation at light load
current.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 230-mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak
inductor current is clamped at 230 mA.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing
and going negative.
Due to the delay in the circuit and current comparator tdly (typical 50 ns at Vin = 12 V), the real peak inductor
current threshold to turn off high-side power MOSFET can shift higher depending on inductor inductance and
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input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be
calculated by 方程式5.
vin - vout
ILPEAK =230mA +
´ tdly
L
(5)
After the charge accumulated on Vout capacitor is more than loading need, COMP pin voltage drops to low
voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is lower than 0.35
V, power stage stops switching to save power.
230mA
Turn off
high-side Power MOSFET
Inductor
Current Peak
Current
Current Comparator
Delay: tdly
Sensing
x1
IL_Peak
Inductor Peak Current
图7-5. PSM Current Comparator
7.3.9 Slope Compensation
To prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the device
adds built-in slope compensation, which is a compensating ramp to the switch current signal.
7.3.10 Overcurrent Protection
The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
7.3.10.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared. When the peak switch current
intersects the current reference, the high-side switch is turned off.
7.3.10.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 0.5 ms shown in 图7-6, the device will shut down itself and restart
after the hiccup time 14ms. The hiccup mode helps to reduce the device power dissipation under severe
overcurrent condition.
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OCP peak inductor current
threshold
Soft Start Time
buck1: T = Css × 0.6
V / 5 µA
Hiccup
Time
14 ms
OC limiting (waiting) time
Output over
loading
0.5 ms
buck2/3: 1 ms
iL
Inductor
Current
Soft-start is reset after OC waiting time
~ 2.1 V
0.6 V
OC fault removed, soft-start & output recovery
SS
SS Pin
Voltage
Output hard short circuit
Vout
Output
Voltage
图7-6. Overcurrent Protection
7.3.11 Power Good
The PGOOD pin is an open drain output. After feedback voltage of each buck is between 95% (rising) and 105%
(falling) of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. TI
recommends to use a pullup resistor between the values of 10 and 100 kΩ to a voltage source that is 5.5 V or
less. The PGOOD is in a defined state after the VIN input voltage is greater than 1 V, but with reduced current
sinking capability. The PGOOD achieves full current sinking capability after the VIN input voltage is above UVLO
threshold, which is 4.25 V.
The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling) or greater than
107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low, if the input voltage is
under-voltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start
period.
7.3.12 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 140°C
typically.
表7-2. Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
4.5- to 18-V, triple buck with input
voltage power failure indicator
Triple buck 3-A/2-A/2-A output current, features an open drain RESET signal
to monitor power down, automatic power sequencing
TPS65261
4.5- to 18-V, triple buck with I2C
interface
Triple buck 3-A/2-A/2-A output current, I2C controlled dynamic voltage
scaling (DVS)
TPS65263
TPS65287
Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB power with over
current setting by external resistor, push button control for intelligent system
power-on/power-off operation
4.5- to 18-V, triple buck with power
switch and push button control
Triple buck 3-A/2-A/2-A output current, 2 USB power switches current limiting
at typical 1.2 A (0.8/1.0/1.4/1.6/1.8/2.0/2.2 A available with manufacture trim
options)
4.5- to 18-V, triple buck with dual power
switches
TPS65288
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7.4 Device Functional Modes
7.4.1 Operation With VIN < 4.5 V (Minimum VIN)
The device operates with input voltages above 4.5 V. The maximum UVLO voltage is 4.5 V and operates at input
voltages above 4.5 V. The typical UVLO voltage is 4.25 V, and the device can operate at input voltages above
that point. The device also can operate at lower input voltages; the minimum UVLO voltage is 4 V (rising) and
3.5 V (falling). At input voltages below the UVLO minimum voltage, the device does not operate.
7.4.2 Operation with EN Control
The enable rising edge threshold voltage is 1.2-V typical and 1.26-V maximum. With EN held below that voltage,
the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When the
input voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the
device becomes active. Switching is enabled, and the soft-start sequence is initiated. The device starts at the
soft-start time determined by the external soft start capacitor as shown in 图8-3 to 图8-8.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The device is triple-synchronous, step-down DC/DC converter with dual LDOs. The device is typically used to
convert a higher DC voltage to lower DC voltages with continuous available output current of 3 A/1 A/1 A. The
following design procedure can be used to select component values for the TPS65262-2. This section presents
a simplified discussion of the design process.
8.2 Typical Application
C4
3.3nF
R12
20K
R32
10K
C182pF
C322pF
C5
22pF
R1
20K
R11 20K
R31 45.3K
C7
10nF
C6
10uF
R5
0
R4
0
16
15
Vout1
+1.2V
Max. 3A
Vout3
+3.3V
Max. 1A
25
BST3
LX3
BST1
L3
C8
C9
L1
47nF
47nF
26
27
LX1
4.7uH
4.7uH
C12
22uF
C10
22uF
C11
22uF
14
13
PGND1
VIN1
PGND3
VIN3
C13
10uF
C14
10uF
Vin
Vin
Vin
28
29
30
TPS65262-2
12
11
LEN1
LFB1
LOUT1
LVIN1
VIN2
C15
10uF
R42
10K
PGND2
LX2
LDO1
L2 C18
22uF
R40
31.6K
2.5V
C16
1uF
10
9
200mA
31
32
C17
47nF
4.7uH
Vout2
+1.8V
Max. 1A
R6
0
Vin_LDO1
BST2
C19
4.7uF
Vin_LDO2
LDO2
5.0V
C20
4.7uF
R21
C2
R51
73.2K
20K
R8
100mA
100K
R22
10K
C21
1uF
R52
10K
82pF
图8-1. Typical Application Schematic
8.2.1 Design Requirements
This example details the design of a triple-synchronous step-down converter. A few parameters must be known
to start the design process. These parameters are typically determined at the system level. For this example,
start with the following known parameters shown in 表8-1.
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表8-1. Design Parameters
PARAMETER
VALUE
Vout1
1.2 V
Iout1
3 A
Vout2
1.8 V
Iout2
Vout3
1 A
3.3 V
Iout3
1 A
Buck1 transient response 1-A load step
Buck2, buck3 transient response 0.5-A load step
Input voltage
±5%
±5%
12 V normal, 4.5 to 18 V
±1%
Output voltage ripple
Switching frequency
600 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use 方程式 6. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications.
V
- Vout
Vout
Vinmax ´ ƒsw
inmax
L =
´
Io ´LIR
(6)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from 方程式8 and 方程式9.
V
- Vout
´
Vout
Vinmax ´ ƒsw
inmax
Iripple
=
L
(7)
spacer
æ
ö2
Vout ´ V
- Vout
(
)
inmax
ç
ç
÷
÷
Vinmax ´L ´ ƒsw
è
ø
ILrms
=
IO2 +
12
(8)
(9)
spacer
ILpeak =Iout
Iripple
+
2
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
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8.2.2.2 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation can occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. 方程式 10 shows the minimum output capacitance necessary to
accomplish this.
2´ DIout
Co =
ƒsw ´ DVout
(10)
where
• ΔIout is the change in output current.
• ƒsw is the regulator's switching frequency.
• ΔVout is the allowable change in the output voltage.
方程式11 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
1
1
Co >
´
Voripple
8´ ƒsw
Ioripple
(11)
where
• ƒsw is the switching frequency
• Voripple is the maximum allowable output voltage ripple
• Ioripple is the inductor ripple current
方程式 12 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
Resr
<
Ioripple
(12)
Additional capacitance de-ratings for aging, temperature and DC bias must be factored in which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. 方程式 13 can
be used to calculate the RMS ripple current the output capacitor needs to support.
Vout ´ V
- Vout
(
)
12 ´ Vinmax ´L ´ ƒsw
inmax
Icorms
=
(13)
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8.2.2.3 Input Capacitor Selection
The TPS65262-2 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF
of effective capacitance on the VIN input voltage pins. In some applications additional bulk capacitance can also
be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the
input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current
rating greater than the maximum input current ripple of The TPS65262-2. The input ripple current can be
calculated using 方程式14.
V
(
- Vout
)
Vout
inmin
I
=Iout
´
´
inrms
V
V
inmin
inmin
(14)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using 方程式15.
I
outmax ´ 0.25
DV
=
in
Cin ´ ƒsw
(15)
8.2.2.4 Loop Compensation
The TPS65262-2 incorporates a peak current mode control scheme. The error amplifier is a transconductance
amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin
between 60° to 90°. Cb adds a high-frequency pole to attenuate high frequency noise when needed. To calculate
the external compensation components, follow the following steps.
1. Switching frequency ƒsw 600 kHz is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth, also gives best trade-off between performance and cost.
2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw.
3. RC can be determined by
2p´ fc ´ Vo´ Co
RC
=
Gm-EA ´ Vref ´ Gm-PS
(16)
Where Gm_EA is the error amplifier gain (300 µS), Gm_PS is the power stage voltage to current conversion
gain (7.4 A/V).
æ
ç
è
ö
÷
ø
1
ƒp =
.
Co ´RL ´ 2p
4. Calculate CC by placing a compensation zero at or before the dominant pole
RL ´ Co
CC
=
RC
(17)
(18)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
R
ESR ´ Co
Cb =
RC
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C1 is calculated from 方程式19.
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1
C 1 =
2 p ì R1 ì ƒ
c
(19)
LX
VOUT
iL
RESR
Current
Sense I/V
Converter
Gm_PS = 7.4 A / V
RL
Co
C1
R1
Vfb
EA
FB
COMP
Vref = 0.6 V
Gm_EA = 300
Rc
s
Cb
Cc
GND
图8-2. DC/DC Loop Compensation
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8.2.3 Application Curves
TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V, ƒSW = 600 kHz, PSM mode (unless otherwise noted)
图8-3. PSM Mode Buck1, Soft-Start with No Load 图8-4. PSM Mode Buck1, Soft-Start With Full Load
图8-5. PSM Mode Buck2, Soft-Start with No Load 图8-6. PSM Mode Buck2, Soft-Start with Full Load
图8-7. PSM Mode Buck3, Soft-Start With No Load 图8-8. PSM Mode Buck3, Soft-Start with Full Load
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图8-9. PSM Mode Buck1, Steady State Operation
图8-10. Buck1, Steady State Operation with Full
with Light Load
Load
图8-11. PSM Mode Buck2, Steady State Operation 图8-12. Buck2, Steady State Operation with Full
With Light Load
Load
图8-13. PSM Mode Buck3, Steady State Operation 图8-14. Buck3, Steady State Operation with Full
with Light Load
Load
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图8-15. Buck1, Load Transient, 0.75 to 1.5 A SR = 图8-16. Buck1, Load Transient, 1.5 to 2.25 A SR =
0.25 A/µs
0.25 A/µs
图8-17. Buck2, Load Transient, 0.25 to 0.5 A SR =
图8-18. Buck2, Load Transient, 0.5 to 0.75 A SR =
0.25 A/µs
0.25A/µs
图8-19. Buck3, Load Transient, 0.25 to 0.5 A SR = 图8-20. Buck3, Load Transient, 0.5 to 0.75 A SR =
0.25 A/µs
0.25A/µs
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图8-22. Buck1, Hiccup and Recovery
图8-21. Buck1, Overcurrent Protection
图8-23. Buck2, Overcurrent Protection
图8-25. Buck3, Overcurrent Protection
图8-24. Buck2, Hiccup and Recovery
图8-26. Buck3, Hiccup and Recovery
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图8-27. PWM Mode, Buck1, Soft-Start with No
图8-28. PWM Mode, Buck1, Soft-Start with Full
Load
Load
图8-29. PWM Mode, Buck2, Soft-Start with No
图8-30. PWM Mode, Buck2, Soft-Start with Full
Load
Load
图8-31. PWM Mode, Buck3, Soft-Start with No
图8-32. PWM Mode, Buck3, Soft-Start with Full
Load
Load
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图8-33. PWM Mode, Buck1, Steady State Operation 图8-34. PWM Mode, Buck2, Steady State Operation
with No Load with No Load
Operating at VIN = 12 V
VOUT3 = 3.3 V/0.5 A
VOUT1 = 1.2 V/1.5 A
VOUT2 = 1.8 V/0.5 A
Operating at VIN = 12 V
VOUT3 = 3.3 V/1 A
VOUT1 = 1.2 V/3 A
VOUT2 = 1.8 V/1 A
图8-35. Thermal Signature of TPS65262-2EVM
EVM Condition 4 Layers, 64 mm × 69 mm, TA =
30.5°C
图8-36. Thermal Signature of TPS65262-2EVM
EVM Condition 4 Layers, 64 mm × 69 mm, TA =
30.5°C
8.3 Power Supply Recommendations
A wide 4.5- to 18-V input supply voltage range encompasses the most intermediate bus voltage operating off 5-,
9-, 12-, or 15-V power bus. The converter, with constant frequency peak current mode, is designed to simplify its
application while giving designers options to optimize the system according to targeted applications.
8.4 Layout
8.4.1 Layout Guidelines
The TPS65262-2 supports a 2-layer PCB layout, shown in 图8-37.
Layout is a critical portion of good power supply design. See 图8-37 for a PCB layout example. The top contains
the main power traces for VIN, VOUT, and LX. Also on the top layer are connections for the remaining pins of the
TPS65262-2 and a large top side area filled with ground. The top layer ground area must be connected to the
bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and directly under the
TPS65262-2 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer
acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top side ground area together with the bottom side ground plane must
provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or
voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supplies performance. To help eliminate these problems, the VIN pin must be bypassed to ground with a low
ESR ceramic bypass capacitor with X5R or X7R dielectric. Care must be taken to minimize the loop area formed
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by the bypass capacitor connections, the VIN pins, and the ground connections. The VIN pin must also be
bypassed to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground must use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor
length while maintaining adequate width. The small signal components must be grounded to the analog ground
path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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8.4.2 Layout Example
VOUT1
VOUT3
BST1
LX1
BST3
LX3
PGND1
VIN1
PGND3
VIN3
VIN
VIN
LEN1
LFB1
LOUT1
LVIN1
VIN2
PGND2
LX2
BST2
VOUT2
TOPSIDE
GROUND
AREA
0.010-inch Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
图8-37. PCB Layout
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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35
Product Folder Links: TPS65262-2
English Data Sheet: SLVSD87
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65262-2RHBR
TPS65262-2RHBT
ACTIVE
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TPS
65262-2
Samples
Samples
ACTIVE
RHB
NIPDAU
TPS
65262-2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65262-2RHBR
TPS65262-2RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65262-2RHBR
TPS65262-2RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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