TPS65265RHBR_技术文档

TPS65265

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

TPS65265 4.5V 至17V 输入电压、5A/3A/2A 输出电流三路同步降压转换器

1 特性

3 说明

• 工作输入电压范围：4.5V 至17V

• 反馈基准电压为0.6V ±1.33%

• 持续输出电流：5A/3A/2A

• 可调节时钟频率范围为250kHz 至

2.3MHz

• 外部同步振荡器

• Buck1、Buck2 和Buck3 之间具有120° 相位差

• 针对每个降压转换器的专用使能引脚

• 针对每个降压转换器的固定软启动(SS) 时间

(2.4ms)

TPS65265 整合了三路同步降压转换器，支持 4.5V 至

17V 宽范围输入电压，该电压范围包括大部分中间总

线关闭电压为 5、9、12 或 15V 的电源总线或电池。

这款转换器具有恒定频率峰值电流模式，专用于简化应

用，同时方便设计人员根据目标应用来优化系统。可通

过外部电阻或外部时钟在 250kHz 至2.3MHz 范围内调

节转换器的开关频率。Buck1、Buck2 和 Buck3 之间

的 120° 异相运行可最大限度降低对输入滤波器的要

求。

TPS65265 可通过将 MODE 引脚驱动为高电平或保持

悬空进入脉冲跳跃模式 (PSM)，通过将 MODE 引脚连

接至 GND 进入强制持续电流模式 (FCC)。PSM 模式

通过减少轻负载时的开关损耗来提供高效率，而 FCC

模式可降低噪声灵敏度和射频(RF) 干扰。

• 自动加电/断电序列以及各降压转换器间可调节的间

隔时间（6 种组合）

• 支持脉冲跳跃模式(PSM) 和强制持续电流模式

(FCCM)

• 输出电压电源正常状态指示器和可调节延迟时间

• 热过载保护

• 32 引脚QFN (RHB) 5mm × 5mm 封装

TPS65265 采用 32 引脚 5mm × 5mm 耐热增强型

QFN (RHB) 薄型封装。

2 应用

封装信息⁽¹⁾

封装尺寸（标称值）

器件型号

TPS65265

封装

• 数字电视(DTV)

• 机顶盒/OTT

RHB（VQFN，32） 5.00mm × 5.00mm

• 家庭网关和接入点网络

• 监控

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

Vout1

100%

90%

80%

70%

60%

50%

40%

30%

20%

Vin

PVINx

LX1

FB1

LX2

MODE

PSM

Vout2

Vout3

PG_DLY

TPS65265

SEQ_DLY

ENx

FB2

LX3

PGOOD

ROSC

PSM Mode, V_OUT= 1.2 V

10%

PWM Mode, V_OUT= 1.2 V

AGND

FB3

PGND

0

0.01

0.1

Output Current (A)

1

5

D100

简化版应用电路

效率与输出负载之间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

Table of Contents

8.3 Feature Description...................................................14

8.4 Device Functional Modes..........................................25

9 Application and Implementation..................................27

9.1 Application Information............................................. 27

9.2 Typical Application.................................................... 27

9.3 Power Supply Recommendations.............................38

9.4 Layout....................................................................... 38

10 Device and Documentation Support..........................40

10.1 接收文档更新通知................................................... 40

10.2 支持资源..................................................................40

10.3 Trademarks.............................................................40

10.4 静电放电警告.......................................................... 40

10.5 术语表..................................................................... 40

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................5

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics................................................9

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

Information.................................................................... 40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (December 2015) to Revision B (May 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 通篇去除了图像的颜色........................................................................................................................................1

• Renamed section 5 to Device Comparison Table ..............................................................................................3

• Change the description of V7V pin in 表6-1 ......................................................................................................3

• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator

and Bootstrap .................................................................................................................................................. 21

• Changed the recommended value of C5 in 图9-1........................................................................................... 27

Changes from Revision * (December 2015) to Revision A (December 2015)

Page

• 将器件状态更改为量产数据并发布了完整数据表................................................................................................1

English Data Sheet: SLVSD86

2

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

5 Device Comparison Table

PART

DESCRIPTION

NUMBER

COMMENTS

TPS65261,

4.5 V to 18 V, triple bucks with input Triple bucks 3-A/2-A/2-A output current, features an open drain RESET signal to

monitor input power failure, automatic power sequencing

TPS65261-1 voltage power failure indicator

TPS65262, 4.5 V to 18 V, triple bucks with dual Triple bucks 3-A/1-A/1-A output current, automatic power sequencing, dual LDOs

TPS65262-1 adjustable LDOs

100 mA/200 mA for TPS65262, 350 mA/150 mA for TPS65262-1

4.5 V to 18 V, triple bucks with I²C

interface

Triple bucks 3-A/2-A/2-A output current, I²C controlled dynamic voltage scaling

(DVS)

TPS65263

TPS65266

2.7 V to 6.5 V, triple bucks

Triple bucks 3 A/2 A/2 A

6 Pin Configuration and Functions

24

23

22

21

20

19

18

17

16

15

BST3

PGND3

LX3

BST1

PGND1

LX1

25

26

27

14

13

12

PVIN3

PVIN2

LX2

28

29

Thermal Pad

LX1

PVIN1

11

10

9

30

31

32

PVIN1

PSM

PGND2

BST2

1

2

3

4

5

6

7

8

There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal

performance.

图6-1. RHB Package 32-Lead Plastic QFN Top View

表6-1. Pin Functions

DESCRIPTION

NO.

NAME

1

2

V7V

Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground

An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal

shutdown, over-current, under-voltage or ENx shut down.

PGOOD

EN1

Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck1

with a resistor divider.

3

4

5

6

EN2

EN3

FB2

Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.

Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider.

Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.

Submit Document Feedback

3

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

表6-1. Pin Functions (continued)

DESCRIPTION

NO.

NAME

COMP2

Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to

compensate the control loop of buck2 with peak current PWM mode.

7

8

9

When floating, Buck1/2/3 are controlled separate by EN1/2/3. When tied to HIGH or tied to GND, an automatic

power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.

MODE

BST2

Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF)

from BST2 pin to LX2 pin.

Power ground connection of buck2. Connect PGND2 pin as close as practical to the (-) terminal of PVIN2 input

ceramic capacitor.

10

11

12

13

14

15

16

17

18

PGND2

LX2

Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is

from a diode voltage below the ground up to PVIN2 voltage.

Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 10 µF).

PVIN2

PVIN3

LX3

Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 10 µF).

Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is

from a diode voltage below the ground up to PVIN3 voltage.

Power ground connection of buck3. Connect PGND3 pin as close as practical to the (-) terminal of PVIN3 input

ceramic capacitor.

PGND3

BST3

Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF)

from BST3 pin to LX3 pin.

Delay time programmable between bucks at automatic power sequencing mode. Connect an external capacitor

to set the interval delay time.

SEQ_DLY

COMP3

Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to

compensate the control loop of buck3 with peak current PWM mode.

19

20

21

22

FB3

Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.

Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.

Analog ground common to buck controllers and other analog circuits.

ROSC

AGND

FB1

Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.

Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to

compensate the control loop of buck1 with peak current PWM mode.

23

24

25

COMP1

PG_DLY

BST1

PGOOD delay programmable pin. Connect an external capacitor to set the delay time.

Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF)

from BST1 pin to LX1 pin.

Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (-) terminal of PVIN1 input

ceramic capacitor.

26, 27 PGND1

28, 29 LX1

Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is

from a diode voltage below the ground up to PVIN1 voltage.

Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic

capacitor (suggest 22 µF).

30, 31 PVIN1

32

PSM

Ties to HIGH or leaves floating, PSM mode; Ties to GND, FCCM mode.

There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to

PCB for optimal thermal performance.

PAD

English Data Sheet: SLVSD86

4

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1.0

–0.3

–40

–55

MAX

20

UNIT

V

PVIN1, PVIN2, PVIN3, PGOOD

LX1, LX2, LX3

19

V

LX1, LX2, LX3 (maximum withstand voltage transient <10 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins, respectively

EN1, EN2, EN3, V7V, MODE, PSM

21

V

7

V

7

V

FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY

AGND, PGND1, PGND2, PGND3

3.6

0.3

150

V

Operating junction temperature, T_J

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

PVIN1, PVIN2, PVIN3

17

19

V

LX1, LX2, LX3 (Maximum withstand voltage transient <10 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

EN1, EN2, EN3, V7V, MODE, PSM

–0.8

–0.1

–40

6.8

6.3

3.3

125

V

FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY

Operating junction temperature, T_J

V

°C

7.4 Thermal Information

TPS65265

RHB (QFN)

32 PINS

32

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

24.2

6.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.2

6.4

ψ_JB

Submit Document Feedback

5

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

TPS65265

RHB (QFN)

32 PINS

1.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

English Data Sheet: SLVSD86

6

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.5 Electrical Characteristics

T_J= –40°C to 125°C, typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY VOLTAGE

V_IN

Input voltage range

4.5

3.6

3.0

17

4

V

VIN rising

3.8

3.2

UVLO

VIN undervoltage lockout

VIN falling

Hysteresis

3.4

V

600

mV

PVIN = 12 V, EN1 = EN2 =

EN3 = MODE = 0 V

IDD_SDN

Shutdown supply current

9

550

280

11.5

680

350

14

800

425

µA

EN1 = EN2 = EN3 = 5 V, FB1

= FB2 = FB3 = 0.8 V

IDD_{Q_NSW}

IDD_{Q_NSW1}

IDD_{Q_NSW2}

IDD_{Q_NSW3}

EN1 = 5 V, EN2 = EN3 = 0 V,

FB1 = 0.8 V

Input quiescent current without buck1/2/3

switching

EN2 = 5 V, EN1 = EN3 = 0 V,

FB2 = 0.8 V

EN3 = 5 V, EN1 = EN2 = 0 V,

FB3 = 0.8 V

PVIN1 = 12 V, V_7Vload

current = 0 A

V_7V

V7V LDO output voltage

V7V LDO current limit

5.9

6.1

6.3

V

I_{OCP_V7V}

110

177

235

mA

FEEDBACK VOLTAGE REFERENCE

V_FBFeedback voltage

Buck1, Buck2, Buck3

V_COMP= 1.2 V

0.592

0.6

0.608

V

V_ENXH

V_ENXL

I_ENX1

EN1/2/3 high-level input voltage

1.08

1.06

2.3

1.15

1.12

2.9

6

1.22

1.17

3.4

V

EN1/2/3 low-level input voltage

EN1/2/3 pullup current

V

ENx = 1 V

µA

ns

µS

I_ENX2

EN1/2/3 pullup current

ENx = 1.5 V

5.1

6.8

I_ENhys

t_{ON_MIN}

G_{m_EA}

hysteresis current

3.1

75

Minimum on time

I_load= 100 mA

120

530

Error amplifier transconductance

COMP1/2/3 voltage to inductor current

174

350

–2 µA < I_COMPX< 2 µA

G_{m_PS1/2/3}

I_LX= 0.5 A

12

A/V

(1)

G_m

I_LIMIT1

buck1 peak inductor current limit

buck1 low-side source current limit

buck1 low-side sink current limit

buck2 peak inductor current limit

buck2 low-side source current limit

buck2 low-side sink current limit

buck3 peak inductor current limit

buck3 low-side source current limit

buck3 low-side sink current limit

Overcurrent wait time⁽¹⁾

6.0

5.3

8.0

7.7

1.4

5.2

4.8

1.2

3.6

3.7

1.2

256

8192

39

9.6

10

A

I_LIMITSOURCE1

I_LIMITSINK1

I_LIMIT2

A

3.85

3

6.65

5.5

A

I_LIMITSOURCE2

I_LIMITSINK2

I_LIMIT3

A

2.6

4.45

4.6

A

I_LIMITSOURCE3

I_LIMITSINK3

t_{Hiccup_wait}

t_{Hiccup_re}

A

cycles

mΩ

Hiccup time before restart⁽¹⁾

R_{dson_HS1}

R_{dson_LS1}

R_{dson_HS2}

R_{dson_LS2}

buck1 high-side switch resistance

buck1 low-side switch resistance

buck2 high-side switch resistance

buck2 low-side switch resistance

PVIN = 12 V

25

52

43

Submit Document Feedback

7

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.5 Electrical Characteristics (continued)

T_J= –40°C to 125°C, typical values are at T_J= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

70

MAX

UNIT

mΩ

R_{dson_HS3}

R_{dson_LS3}

buck3 high-side switch resistance

buck3 low-side switch resistance

PVIN = 12 V

65

mΩ

PGOOD, MODE, PSM, SEQ_DLY, PG_DLY

FBx undervoltage falling

FBx undervoltage rising

FBx overvoltage rising

FBx overvoltage falling

92.5

95

%VREF

V_{th_PG}

Feedback voltage threshold

107.5

105

%VREF

t_{DEGLITCH(PG)_F}

t_{DEGLITCH(PG)_R}

I_PG

PGOOD falling edge deglitch time

PGOOD rising edge deglitch time

PGOOD pin leakage

256

cycles

256

cycles

µA

V

0.08

0.25

2.8

V_{LOW_PG}

V_{MODE_H}

V_{MODE_L}

V_{PG_DLYTH}

I_{PG_DLY}

PGOOD pin low voltage

MODE high level input voltage

MODE low level input voltage

PG_DLY threshold

PVIN1 = 12 V, I_SINK= 1 mA

2.4

0.11

1.4

2.0

0.7

1.4

2

2.6

0.16

1.5

3.0

0.75

1.5

3

V

0.23

1.6

V

PG_DLY pullup current

PG_DLY = 0.5 V

SEQ_DLY = 0.5 V

4.1

µA

V

V_{SEQ_DLYTH1}

V_{SEQ_DLYTH2}

I_{SEQ_DLY}

SEQ_DLY threshold

0.8

SEQ_DLY threshold

1.58

4.1

V

SEQ_DLY pullup current

PSM pin high level input voltage

PSM pin low level input voltage

µA

V

V_PSMH

1.3

1

1.4

1.1

1.55

1.2

V_PSML

V

OSCILLATOR

F_SW

Switching frequency

580

250

80

610

640

kHz

ns

R_OSC= 82.5 kΩ

F_{SW_range}

t_{SYNC_w}

F_{SYNC_HI}

V_{SYNC_LO}

Switching frequency

2300

Clock sync minimum pulse width

Clock sync high threshold

Clock sync low threshold

2

V

0.4

V

THERMAL PROTECTION

T_{TRIP_OTP}

Thermal protection trip point⁽¹⁾

T_{HYST_OTP}

Temperature rising

Hysteresis

160

20

°C

(1) Lab validation result

English Data Sheet: SLVSD86

8

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.6 Typical Characteristics

0.606

650

630

610

590

570

0.604

0.602

0.6

0.598

0.596

0.594

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D001

Temperature (èC)

D002

图7-1. Voltage Reference vs Temperature

图7-2. Oscillator Frequency vs Temperature

18

16

14

12

10

8

4

3.9

3.8

3.7

3.6

3.5

3.4

6

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D004

D003

图7-4. Vin UVLO Raising vs Temperature

图7-3. Shutdown Quiescent vs Temperature

3.4

3.3

3.2

3.1

3

3.5

3.3

3.1

2.9

2.7

2.5

2.3

2.9

2.8

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D005

D006

图7-5. Vin UVLO Falling vs Temperature

图7-6. EN Pin Pullup Current vs Temperature, EN = 1.0 V

Submit Document Feedback

9

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.6 Typical Characteristics (continued)

6.6

1.19

1.18

1.17

1.16

1.15

1.14

1.13

1.12

1.11

6.4

6.2

6

5.8

5.6

5.4

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D008

D007

图7-8. EN Pin Threshold Raising vs Temperature

图7-7. EN Pin Pullup Current vs Temperature, EN = 1.5 V

3.4

1.16

3.3

3.2

3.1

3

1.15

1.14

1.13

1.12

1.11

1.1

2.9

2.8

2.7

2.6

1.09

1.08

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D009

D010

图7-9. EN Pin Threshold Falling vs Temperature

图7-10. PG_DLY Pin Pullup Current vs Temperature, PG_DLY =

0.5 V

3.4

3.6

3.3

3

3.3

3.2

3.1

3

2.7

2.4

2.1

1.8

1.5

1.2

2.9

2.8

2.7

2.6

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D011

D012

图7-11. SEQ_DLY Pin Pullup Current vs Temperature, PG_DLY

图7-12. Soft-Start Time vs Temperature

= 0.5 V

English Data Sheet: SLVSD86

10

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.6 Typical Characteristics (continued)

9

8.75

8.5

8.25

8

6.2

6

5.8

5.6

5.4

5.2

5

7.75

7.5

7.25

7

4.8

4.6

4.4

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D013

D014

图7-13. Buck1 High-Side Current Limit vs Temperature

图7-14. Buck2 High-Side Current Limit vs Temperature

4.4

4.2

4

140

IOUT = 10 mA

IOUT = 100 mA

120

100

80

60

40

20

3.8

3.6

3.4

3.2

3

2.8

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D016

D015

图7-16. Minimum On Time vs Temperature

图7-15. Buck3 High-Side Current Limit vs Temperature

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

30%

PSM Mode, V_OUT= 1.2 V

PSM Mode, V_OUT= 1.8 V

PWM Mode, V_OUT= 1.2 V

PWM Mode, V_OUT= 1.8 V

PSM Mode, V_OUT= 1.5 V

PSM Mode, V_OUT= 3.3 V

PWM Mode, V_OUT= 1.5 V

PWM Mode, V_OUT= 3.3 V

20%

10%

0

0.01

0.1

Output Current (A)

1

5

0.01

0.1

Output Current (A)

1

3

D017

D018

图7-17. Buck1 Efficiency, V_IN= 12 V, F_sw= 610 kHz

图7-18. Buck2 Efficiency, V_IN= 12 V, F_sw= 610 kHz

Submit Document Feedback

11

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

7.6 Typical Characteristics (continued)

100%

90%

80%

70%

60%

50%

40%

30%

1.22

1.21

1.2

PSM Mode, V_IN= 12 V

PWM Mode, V_IN= 12 V

1.19

1.18

PSM Mode, V_OUT= 1.8 V

20%

10%

0

PSM Mode, V_OUT= 3.3 V

PWM Mode, V_OUT= 1.8 V

PWM Mode, V_OUT= 3.3 V

0.01

0.1

Output Current (A)

1

2

0

1

2 3

Output Current (A)

4

5

D019

D020

图7-19. Buck3 Efficiency, V_IN= 12 V, F_sw= 610 kHz

图7-20. Buck1, Load Regulation

1.52

1.82

1.81

1.8

PSM Mode, V_IN= 12 V

PWM Mode, V_IN= 12 V

PSM Mode, V_IN= 12 V

PWM Mode, V_IN= 12 V

1.51

1.5

1.79

1.78

1.49

1.48

0

0.2 0.4 0.6 0.8

1

Output Current (A)

1.2 1.4 1.6 1.8

2

0

0.5

1

1.5

Output Current (A)

2

2.5

3

D022

D021

图7-22. Buck3, Load Regulation

图7-21. Buck2, Load Regulation

English Data Sheet: SLVSD86

12

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

8 Detailed Description

8.1 Overview

The TPS65265 is a monolithic triple synchronous step-down (buck) converter with 5-A/3-A/2-A output currents. A

wide 4.5-V to 17-V input supply voltage range encompasses most intermediate bus voltages operating off 5-V, 9-

V, 12-V, or 15-V power bus. The feedback voltage reference for each buck is 0.6 V. Each buck is independent

with dedicated enable, soft-start and loop compensation pins.

The TPS65265 implements a constant frequency, peak current mode control that simplifies external loop

compensation. The wide switching frequency of 250 kHz to 2.3 MHz allows optimizing system efficiency, filtering

size and bandwidth. The switching frequency can be adjusted with an external resistor connecting between

ROSC pin and ground. The switching clock is 120° out-of-phase operation from the clocks of buck1, buck2, and

buck3 channels to reduce input current ripple, input capacitor size and power supply induced noise.

The TPS65265 has been designed for safe monotonic startup into pre-biased loads. The default start up is when

VIN is typically 3.8 V. The ENx pin also can be used to adjust the input voltage undervoltage lockout (UVLO) with

an external resistor divider. In addition, the ENx pin has an internal 2.9µA current source, so the EN pin can be

floating for automatically powering up the converters.

The TPS65265 reduces the external component count by integrating the bootstrap circuit. The bias voltage for

the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit

monitors the bootstrap capacitor voltage VBST-VLX in each buck. When V_BST-V_LXvoltage drops to the

threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65265 can operate at 100% duty

cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is typically

2.2 V.

The TPS65265 features PGOOD pin to supervise each output voltage of buck converters. The TPS65265 has

power good comparators with hysteresis, which monitor the output voltages through feedback voltages. When all

bucks are in regulation range and power sequence is done, PGOOD is asserted to high after the adjustable

delay time.

The TPS65265 operates in PSM with connecting PSM pin to high or leaving float and operates in force

continuous current mode (FCC) with driving PSM pin to GND.

The TPS65265 is protected from overload and over temperature fault conditions. The converter minimizes

excessive output overvoltage transients by taking advantage of the power good comparator. When the output is

over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6V

reference voltage. The TPS65265 implements both high-side MOSFET overload protection and bidirectional low-

side MOSFET overload protections to avoid inductor current runaway. If the overcurrent condition has lasted for

more than the OC wait time (256 clock cycle), the converter will shut down and restart after the hiccup time

(8192 clock cycles). The TPS65265 shuts down if the junction temperature is higher than thermal shutdown trip

point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the TPS65265

will be restarted under control of the soft start circuit automatically.

Submit Document Feedback

13

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

8.2 Functional Block Diagram

ROSC

V7V

V3V

OSC/Phase Shift

V7V LDO

Bias

V7V

VIN

clk

PVIN2

BST2

LX2

V7V

VIN

clk

VIN

en_buck2

enable

PVIN1

BST1

VIN

enable

en_buck1

BST

LX

psm

mode

BUCK2

BST

LX

psm

BUCK1

seq_dly

LX1

mode

PGND2

PGND

Comp

vfb

seq_dly

PGND1

PGND

Comp

vfb

FB2

FB1

COMP1

-

1.5 V

COMP2

3 µA

1 µA

PG_DLY

PGOOD

+

Power

Good

1.4 V

clk

V7V

VIN

PSM

FB1

FB2

FB3

PVIN3

BST3

LX3

en_buck3

enable

VIN

-

0.75 V

BST

LX

psm

mode

BUCK3

+

3 µA

mode

psm

seq_dly

SEQ_DLY

PGND3

PGND

Comp

vfb

seq_dly

-

1.5 V

2.6 V

-

State

Machine

FB3

en_buck1

en_buck2

en_buck3

+

MODE

-

COMP3

AGND

+

0.16 V

OT

Over

Temp

2.9 µA

3.1 µA

EN1(EN2, EN3)

6.3 V

1.15 V

2 kꢀ

8.3 Feature Description

8.3.1 Adjusting the Output Voltage

The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI

recommends to use 1% tolerance or better resistors.

V_OUT

R1

FB

COMP

0.6V

R2

图8-1. Voltage Divider Circuit

English Data Sheet: SLVSD86

14

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

0 .6

œ 0 .6

R ₂= R ₁

ì

V

o u t

(1)

To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator

is more sensitive to noise. The recommended resistor values are shown in 表8-1.

表8-1. Output Resistor Divider Selection

OUTPUT VOLTAGE

(V)

R1

(kΩ)

R2

(kΩ)

1

10

15

10

1.2

1.5

1.8

2.5

3.3

5

15

10

20

10

31.6

45.3

22.6

73.2

36.5

10

4.99

10

5

4.99

8.3.2 Mix PGOOD, PG_DLY Functions

The PGOOD pin is an open drain output and withstands voltage higher to 17 V. After feedback voltage of each

buck is between 95% (rising) and 105% (falling) of the internal voltage reference and PG_DLY pin voltage overs

1.5 V, the PGOOD pin pull-down is deasserted and the pin floats. TI recommends to use a pullup resistor

between the values of 10 kΩ and 100 kΩ to a voltage source that is below 17 V.

The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling), greater than

107.5% (rising) of the nominal internal reference voltage, or PG_DLY pin voltage is below 1.5V (typical). Also,

the PGOOD is pulled low, if the input voltage is under-voltage locked up, thermal shutdown is asserted, the EN

pin is pulled low or the converter is in soft-start period.

Different combinations of PGOOD, PG_DLY can implement different functions.

8.3.2.1 Programmable PGOOD DELAY

An internal 3-µA pullup current source is connected to PG_DLY pin. The PGOOD delay time can be

programmed by connecting a capacitor between PG_DLY pin and ground. The delay time can be calculated as

方程式2.

V_{P G _ D L Y}ì C ₁

t_{p g o o d _ d e la y}

=

I_p

(2)

where

• V_{PG_DLY}= 1.5 V

• I_p= 3 µA

Submit Document Feedback

15

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

VDD_1.8V

3 µA

PGOOD

PG_DLY

Power

Good

Logic

C1

1.5 V

State Machine

BUCK1,2,3

PG_DLY

PGOOD deglitch time 256 cycles

1.5 V

t_{pgood_delay}= 1.5 V × C₁/ 3 µA

PGOOD

图8-2. Power Good Delay Timing Diagram

8.3.2.2 Relay Control

PGOOD pin can implement one buck output’s relay control through an N-MOSFET, circuit as in 图8-3.

16

Submit Document Feedback

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

BUCKx

PVIN_12V

Q1

3 µA

R1

C2

PGOOD

PG_DLY

C1

Power

Good

Logic

1.5 V

Relay_BUCKx

State Machine

BUCK1,2,3

PG_DLY

PGOOD deglitch time 256 cycles

1.5 V

t_{pgood_delay}= 1.5 V × C₁/ 3 µA

Q1 gate threshold

PGOOD

Determined by R1 and C2

Relay_BUCKx

图8-3. Relay Control Circuit

8.3.3 Enable and Adjusting UVLO

The EN1/2/3 pin provides electrical on/off control of the device. After the EN1/2/3 pin voltage exceeds the

threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the

regulator stops switching and enters low I_qstate.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If

an application requires controlling the EN pin, use open drain or open collector output logic to interface with the

pin.

The device implements internal UVLO circuitry on the PVIN1 pin. The device is disabled when the PVIN1 pin

voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 600

mV. If an application requires a higher UVLO threshold on the PVIN1, in split-rail applications, then the ENx pin

can be configured as shown in 图 8-4. When using the external UVLO function TI recommends to set the

hysteresis to be greater than 500 mV.

The EN pin has a small pullup current I_pwhich sets the default state of the pin to enable when no external

components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO

function because it increases by I_hafter the EN pin crosses the enable threshold. The UVLO thresholds can be

calculated using 方程式3 and 方程式4.

Submit Document Feedback

17

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

≈

∆

«

’

÷

◊

V_{E N F A L L IN G}

V_{E N R IS IN G}

V

œ V

S T O P

S T A R T

R ₁

=

≈

∆

’

÷

V_{E N F A L L IN G}

I

1 œ

+ I

h

P

V_{E N R IS IN G}

«

◊

(3)

(4)

R ₁ì V_{E N F A L L IN G}

+ R

R ₂

=

V

œ

V

I

+ I

h P

(

)

S T O P

E N F A L L IN G

1

where

• I_h= 3.1µA

• I_p= 2.9 µA

• V_ENRISING= 1.15 V

• V_ENFALLING= 1.12 V

PVIN

i_h

R1

R2

i_p

EN

图8-4. Adjustable PVIN UVLO, PVIN > 4.5 V

8.3.4 Soft-Start Time

TPS65265 has fixed 2.4-ms (typical) soft-start time.

8.3.5 Power-Up Sequencing

TPS65265 features a comprehensive sequencing circuit for the three bucks. If MODE pin was tied to HIGH or

tied to GND and at the same time EN1 or EN2 (or both) was (were) pulled high, the automatic power-up and

power-down sequence function is active. If MODE pin was left floating, three Buck on/off were separately

controlled by three enable pin.

8.3.5.1 External Power Sequencing

The TPS65265 has dedicated enable pin and soft-start pin for each converter. The converter enable pins are

biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the

converter with an active pulldown transistor on the ENx pin allows for a predictable powerdown timing operation.

The 图 8-5 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx

pin.

A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the

internal V7V LDO turns on. A 2.9-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx

enabling threshold, 3.1-µA hysteresis current sources to the pin to improve noise sensitivity. After soft start time

of 2.4 ms (typical), PGOOD monitor is enabled. If all output voltages are in the regulation and after PGOOD

delay time, PGOOD is asserted.

English Data Sheet: SLVSD86

18

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

VIN

V7V

EN Threshold

ENx Rise Time

Dictated by C_EN

Charge C_EN

with 6 µA

ENx

Pre-Bias Startup

PGOOD Delay Time

VOUTx

2.4 ms

t = C_ENx× (1.2 œ 0.4) V / 2.9 µA

t = C_ENx× 0.4 V / 1.4 µA

PGOOD

图8-5. Startup Power Sequence

8.3.5.2 Automatic Power Sequencing

The TPS65265 starts with a predefined power-up and power-down sequence when MODE pin ties HIGH or ties

to GND. As shown in 表 8-2, the sequence is determined by the different combinations of EN1 and EN2 status.

EN3 is used to start and stop the converters. 图 8-6 shows the power sequencing when MODE ties to GND,

EN1, and EN2 are tied to HIGH.

An internal 3-µA pullup current source is connected to SEQ_DLY pin. The interval time between bucks can be

programmed by connecting a capacitor between SEQ_DLY pin and ground. The interval time can be calculated

with 方程式5.

V₁ì C ₁

t₁

=

i_p

(5)

(6)

V

œ

V₁ì C

(

)

2

1

t₂

=

i_p

where

• V₁= 0.75 V

• V₂= 1.5 V

• I_p= 3 µA

Submit Document Feedback

19

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

表8-2. Power Sequencing

START

SEQUENCING

SHUTDOWN

SEQUENCING

MODE

Connect to GND

EN1

EN2

EN3

buck1 →buck2 →

buck3 →buck2 →

High

Low

High

Low

High

Low

High

buck3

buck1

buck2 →buck1 →

buck3 →buck1 →

Connect to GND

buck3

buck2

buck2 →buck3 →

buck1 →buck3 →

Used to start and

stop bucks in

sequence

buck1

buck2

Connect to high or

float

buck1 →buck3 →

buck2 →buck3 →

Automatic

Power

Sequencing

buck2

buck1

Connect to high or

float

buck3 →buck1 →

buck2 →buck1 →

buck2

buck3

Connect to high or

float

buck3 →buck2 →

buck1 →buck2 →

High

Low

buck1

buck3

Connect to GND

Reserved

Connect to high or

float

Externally

Controlled

Sequencing

Used to start Used to start

Used to start and

stop buck3

Floating

and stop

buck1

and stop

buck2

x

English Data Sheet: SLVSD86

20

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

High or Low

MODE

High or Low

EN1

EN2

1.5 V

EN3

State Machine

3uA

SEQ_DLY

C1

0.75 V

Example

MODE(Low)

EN1(High)

EN2(High)

EN3

V₂= 1.5 V

V₁= 0.75 V

SEQ_DLY

t₁= 0.75 V × C₁/ 3 µA

Buck1

Buck2

Buck3

t₂= (1.5 V œ 0.75 V) × C₁/ 3 µA

t₁

t₂

t₃

t₄

t₁= t₂= t₃= t₄

图8-6. Automatic Power Sequencing

8.3.6 V7V Low Dropout Regulator and Bootstrap

Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V

pin. The internal built-in low dropout linear regulator (LDO) supplies 6.1 V (typical) from PVIN1 to V7V. A 10-µF

ceramic capacitor must be connected from V7V pin to power ground.

If the input voltage, PVIN1, decreases to UVLO threshold voltage, the UVLO comparator detects V7V pin voltage

and forces the converter off.

Each high-side MOSFET driver is biased from the floating bootstrap capacitor CB, shown in 图 8-7, which is

normally recharged during each cycle through an internal low-side MOSFET or the body diode of low-side

MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less

than PVIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF.

A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended

because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered

from V7V pin directly.

Submit Document Feedback

21

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage

is greater than the BST-LX UVLO threshold, which is typically 2.2 V. When the voltage between BST and LX

drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is

turned on allowing the boot capacitor to be recharged.

PVIN1

PVINx

LDO

+

–

(VBSTx-VLXx)

+2.2 V

nBootUV

V7V

BSTx

High-side

MOSFET

Vbias

10 µF

CB

UVLO

Bias

Buck Controller

nBootUV

Gate Driver

PWM

LXx

Low-side MOSFET

nBootUV

PWM

BootUV

Protection

Gate Driver

Clk

图8-7. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram

8.3.7 Out of Phase Operation

To reduce input ripple current, three switching clocks are 120° out-of-phase. This enables the system having less

input current ripple to reduce input capacitors’size, cost, and EMI.

8.3.8 Output Overvoltage Protection (OVP)

The device incorporates an output OVP circuit to minimize output voltage overshoot. When the output is

overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin

voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier

demands maximum output current. After the condition is removed, the regulator output rises and the error

amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the

load can respond faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck

compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the

high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot.

When the FB voltage drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock

cycle.

English Data Sheet: SLVSD86

22

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

8.3.9 PSM

The TPS65265 can enter high-efficiency PSM operation at light load current when PSM pin connects to high or

leave floating.

When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 180 mA

current typically. Because the integrated current comparator catches the peak inductor current only, the average

load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak

inductor current is clamped at 180 mA.

When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current

comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing

and going negative.

Due to the delay in the circuit and current comparator t_dly(typical 50 ns at PVIN = 12 V), the real peak inductor

current threshold to turn off high-side power MOSFET must shift higher depending on inductor inductance and

input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be

calculated by 方程式7.

V_in

œ V_{o u t}

IL _{P E A K}= 1 8 0 m A

+

ì td ly

L

(7)

After the charge accumulated on Vout capacitor is more than loading need, COMP pin voltage drops to low

voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is lower than 0.35

V, power stage stops switching to save power.

180 mA

Turn off

high-side Power MOSFET

+

œ

Inductor Current

Peak Current

Sensing

Current Comparator

Delay: tdly

x1

IL_Peak

Inductor Peak Current

图8-8. PSM Current Comparator

8.3.10 Slope Compensation

To prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the device

adds built-in slope compensation, which is a compensating ramp to the switch current signal.

8.3.11 Overcurrent Protection

The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side

MOSFET and the low-side MOSFET.

8.3.11.1 High-Side MOSFET Overcurrent Protection

The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-

side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current

and the current reference generated by the COMP pin voltage are compared, when the peak switch current

intersects the current reference, the high-side switch is turned off.

Submit Document Feedback

23

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

8.3.11.2 Low-Side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During

normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side

MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side

sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the

next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing

current limit at the start of a cycle.

The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than

the hiccup wait time which is programmed for 256 switching cycles shown in 图 8-9, the device will shut down

itself and restart after the hiccup time of 8192 cycles. The hiccup mode helps to reduce the device power

dissipation under severe overcurrent condition.

OCP peak inductor current threshold

OC limiting (waiting) time

256 cycles

Hiccup time

8192 cycles

Soft-start time

2.4-ms typical

Output overloading

iL

Inductor Current

Output hard short circuit

OC fault removed, soft-start, and output recovery

Vout

Output Voltage

图8-9. Overcurrent Protection

8.3.12 Adjustable Switching Frequency

The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching

frequency of the device is adjustable from 250 kHz to 2.3 MHz.

To determine the switching frequency for a given ROSC resistance, use 方程式 8 or the curve in 图 8-10. To

reduce the solution size one must set the switching frequency as high as possible, but tradeoffs of the supply

efficiency and minimum controllable on time must be considered.

ƒ_osc(kHz) = 30975 × R_osc(kΩ)^–0.889

(8)

English Data Sheet: SLVSD86

24

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

2400

2200

2000

1800

1600

1400

1200

1000

800

600

400

200

0

20

40

60

80

100

120

140

160

180

200

Oscillator Resistance (kW)

D023

图8-10. Switching Frequency versus ROSC

When an external clock applies to ROSC pin, the internal phase locked loop (PLL) has been implemented to

allow internal clock synchronizing to an external clock between 250 kHz and 2.3 MHz. To implement the clock

synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to

80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the

switching cycle is synchronized to the falling edge of ROSC pin.

In applications where both resistor mode and synchronization mode are needed, the device can be configured

as shown in 图 8-11. Before an external clock is present, the device works in resistor mode and ROSC resistor

sets the switching frequency. When an external clock is present, the synchronization mode overrides the resistor

mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches from

the resistor mode to the Synchronization mode and the ROSC pin becomes high impedance as the PLL starts to

lock onto the frequency of the external clock. TI does not recommend to switch from the synchronization mode

back to the resistor mode because the internal switching frequency drops to 100 kHz first before returning to the

switching frequency set by ROSC resistor.

Mode

Selection

IC

ROSC

图8-11. Works With Resistor Mode and Synchronization Mode

8.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C

typically.

8.4 Device Functional Modes

8.4.1 Operation With VIN < 4 V (Minimum VIN)

The device operates with input voltages above 4 V. The maximum UVLO voltage is 4 V and will operate at input

voltages above 4 V. The typical UVLO voltage is 3.8 V and the device can operate at input voltages above that

point. The device also can operate at lower input voltages, the minimum UVLO voltage is 3.6V (rising) and 3V

(falling). At input voltages below the UVLO minimum voltage, the devices will not operate.

Submit Document Feedback

25

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

8.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.08 V minimum and 1.22 V maximum. With EN held below that

voltage the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When

input voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the

device becomes active. Switching is enabled, and the internal soft-start sequence is initiated as shown in 图 8-7

to 图9-5.

English Data Sheet: SLVSD86

26

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The device is triple synchronous step down dc/dc converter. It is typically used to convert a higher dc voltage to

lower dc voltages with continuous available output current of 5 A/3 A/2 A. .

9.2 Typical Application

The following design procedure can be used to select component values for the TPS65265. This section

presents a simplified discussion of the design process

C15

22pF

C26

82pF

R153

10k

R263

10k

R262

10k

R152 20k

C231

C181

2.7nF

R20

82.5k

C232

22pF

R23

10k

R18

6.8k

C182

22pF

C24

10nF

C17

10nF

R16

0

R25

0

16

25

BST3

BST1

C25

47nF

C16

47nF

V_OUT3

1.8V

15

26

27

28

PGND1

LX1

PGND3

LX3

L3

4.7µH

Max. 2A

V_OUT1

14

13

1.2V

Max. 5A

L1

C152

22µF

C151

22µF

Vin

C12

PVIN3

PVIN2

LX2

2.2uH

C13

10µF

TPS65265

10µF

C261 C262

22µF 22µF

C263

22µF

29

30

12

11

LX1

L2

4.7µH

C101

22µF

C102

22µF

Vin

PVIN1

PSM

C29

22µF

V_OUT2

1.5V

Max. 3A

10

9

31

32

PGND2

BST2

C9

47nF

R9

0

DNI

R29

R7

6.8k

0

C72

22pF

DNI

C5

R2

10µF

C71

2.7nF

100K

R102 15k

R103

10k

C10

22pF

图9-1. Typical Application Circuit

Submit Document Feedback

27

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9.2.1 Design Requirements

This example details the design of triple synchronous step-down converter. A few parameters must be known to

start the design process. These parameters are typically determined at the system level. For this example, start

with the following known parameters shown in 表9-1.

表9-1. Design Parameters

PARAMETER

VALUE

Vout1

Iout1

Vout2

Iout2

Vout3

Iout3

1.2 V

5 A

1.5 V

3 A

1.8 V

2 A

Transient response 1-A load step

Input voltage

±5%

12-V normal, 4.5 V to 17 V

±1%

Output voltage ripple

Switching frequency

610 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use 方程式 9. LIR is a coefficient that represents the amount of

inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In

general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for

the majority of applications.

V

- V_OUT

V_OUT

V_{IN max}´ ƒ_SW

IN max

L =

´

I_O´LIR

(9)

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.

The RMS and peak inductor current can be found from 方程式11 and 方程式12.

V

- V_OUT

´

V_OUT

V_{IN max}´ ƒ_SW

IN max

I_ripple

=

L

(10)

æ

ö²

V_OUT´ V

- V_OUT

(

)

IN max

ç

÷

V_{IN max}´L ´ ƒ_SW

2

è

ø

I_Lrms

= I_O+

12

(11)

(12)

I_ripple

I

_Lpeak= I_OUT

+

2

The current flowing through the inductor is the inductor ripple current plus the output current. During power up,

faults or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of

the device. For this reason, the most conservative approach is to specify an inductor with a saturation current

rating equal to or greater than the switch current limit rather than the peak inductor current.

English Data Sheet: SLVSD86

28

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9.2.2.2 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor

determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in

load current. The output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to

supply the load with current when the regulator cannot. This situation must occur if there are desired hold-up

times for the regulator where the output capacitor must hold the output voltage above a certain level for a

specified amount of time after the input power is removed. The regulator is also temporarily not able to supply

sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from

no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change

in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be

sized to supply the extra current to the load until the control loop responds to the load change. The output

capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a

tolerable amount of droop in the output voltage. 方程式 13 shows the minimum output capacitance necessary to

accomplish this.

2´ DI_OUT

C_O

=

ƒ_SW´ DV_OUT

(13)

where

• ΔI_outis the change in output current

• ƒ_swis the regulators switching frequency

• ΔV_outis the allowable change in the output voltage.

方程式14 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

1

C_O

>

´

V_Oripple

8 ´ ƒ_SW

I_Oripple

(14)

where

• ƒ_swis the switching frequency.

• V_rippleis the maximum allowable output voltage ripple.

• I_rippleis the inductor ripple current.

方程式 15 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification.

V_Oripple

<

R_esr

I_Oripple

(15)

Additional capacitance de-ratings for aging, temperature and DC bias must be factored in which increases this

minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some

capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. 方程式 16 can

be used to calculate the RMS ripple current the output capacitor needs to support.

V_OUT´ V

- V_OUT

(

12 ´ V_{IN max}´L ´ ƒ_SW

)

IN max

I_Lrms

=

(16)

Submit Document Feedback

29

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9.2.2.3 Input Capacitor Selection

The TPS65265 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF of

effective capacitance on the PVIN input voltage pins. In some applications additional bulk capacitance can also

be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the

input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current

rating greater than the maximum input current ripple of The TPS65265. The input ripple current can be

calculated using 方程式17.

V

_{IN min}´ V_OUT

V_OUT

(

)

I

= I_OUT

´

INrms

V

IN min

(17)

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple

voltage of the regulator. The input voltage ripple can be calculated using 方程式18.

I_OUTmax´0.25

DV

=

IN

C_IN´ ƒ_SW

(18)

9.2.2.4 Loop Compensation

The TPS65265 incorporates a peak current mode control scheme. The error amplifier is a trans-conductance

amplifier with a gain of 350 µS. A typical type II compensation circuit adequately delivers a phase margin

between 30 and 90 degrees. Cb adds a high frequency pole to attenuate high frequency noise when needed. To

calculate the external compensation components, follow the following steps.

1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple,

EMI, and so forth. Switching frequency between 600 kHz to 1 MHz gives best trade-off between

performance and cost. To optimize efficiency, lower switching frequency is desired.

2. Set up crossover frequency, ƒ_c, which is typically between 1/5 and 1/20 of ƒ_sw.

3. R_Ccan be determined by

2 p ì ƒ _cì V_oì C _o

R _C

=

G _m

ì V_{re f}ì G _{m _ P S}

_ E A

(19)

where

• G_{m_EA}is the error amplifier gain (350 µS).

• G_{m_PS}is the power stage voltage to current conversion gain (12 A/V).

1

ƒ _p

=

C _oì R _Lì 2 p

4. Calculate C_Cby placing a compensation zero at or before the dominant pole (

).

R _Lì C _o

C _c

=

R _C

(20)

(21)

5. Optional C_bcan be used to cancel the zero from the ESR associated with C_O.

R _{E S R}ì C _o

C _b

=

R _C

6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly

higher loop bandwidths and higher phase margins. If used, C1 is calculated from 方程式22.

English Data Sheet: SLVSD86

30

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

1

C ₁

=

2 p ì R ì ƒ

1

c

(22)

LX

VOUT

i_L

R_ESR

Current

Sense I/V

Converter

G_{m_PS}= 12 A / V

R_L

C_o

C₁

R₁

Vfb

EA

FB

COMP

V_ref= 0.6 V

G_{m_EA}= 350

R_c

s

C_b

C_c

GND

图9-2. DC-DC Loop Compensation

Submit Document Feedback

31

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9.2.3 Application Curves

T_A= 25°C, V_IN= 12 V, V_OUT1= 1.2 V, V_OUT2= 1.5 V, V_OUT3= 1.8 V F_SW= 610 kHz (unless otherwise noted)

图9-3. Buck1, PSM Mode, Soft-Start, Iout = 0 A

图9-4. Buck1, FCC Mode, Soft-Start, Iout = 0 A

图9-5. Buck1, PSM Mode, Soft-Start, Iout = 5 A

图9-6. Buck1, FCC Mode, Soft-Start, Iout = 5 A

图9-7. Buck2, PSM Mode, Soft-Start, Iout = 0 A

图9-8. Buck2, FCC Mode, Soft-Start, Iout = 0 A

32

Submit Document Feedback

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-9. Buck2, PSM Mode, Soft-Start, Iout = 3 A

图9-10. Buck2, FCC Mode, Soft-Start, Iout = 3 A

图9-12. Buck3, FCC Mode, Soft-Start, Iout = 0 A

图9-14. Buck3, FCC Mode, Soft-Start, Iout = 2 A

图9-11. Buck3, PSM Mode, Soft-Start, Iout = 0 A

图9-13. Buck3, PSM Mode, Soft-Start, Iout = 2 A

Submit Document Feedback

33

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-15. Buck1, PSM Mode, Output Ripple, Light

图9-16. Buck1, FCC Mode, Iout = 0 A

Load

图9-17. Buck1, Output Ripple, Iout = 5 A

图9-18. Buck2, PSM Mode, Output Ripple, Light

Load

图9-19. Buck2, FCC Mode, Iout = 0 A

图9-20. Buck2, Output Ripple, Iout = 3 A

34

Submit Document Feedback

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-21. Buck3, PSM Mode, Output Ripple, Light

图9-22. Buck3, FCC Mode, Iout = 0 A

Load

图9-23. Buck3, Output Ripple, Iout = 2 A

图9-24. Buck1, Load Transient, 1.25 A to 2.5 A, SR

0.25 A/µs

图9-25. Buck1, Load Transient, 2.5 A to 3.75 A, SR 图9-26. Buck2, Load Transient, 0.75 A to 1.5 A, SR

0.25 A/µs

Submit Document Feedback

35

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-27. Buck2, Load Transient, 1.5 A to 2.25 A, SR

图9-28. Buck3, Load Transient, 0.5 A to 1 A, SR

0.25 A/µs

图9-29. Buck3, Load Transient, 1 A to 1.5 A, SR

图9-30. Buck1, Hiccup and Recovery

0.25 A/µs

图9-31. Buck2, Hiccup and Recovery

图9-32. Buck3, Hiccup and Recovery

36

Submit Document Feedback

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-33. Automatic Power Sequencing, MODE =

图9-34. Automatic Power Sequencing, MODE =

LOW, EN1 = HIGH, EN2 = HIGH

LOW, EN1 = LOW, EN2 = HIGH

图9-35. Automatic Power Sequencing, MODE =

图9-36. Automatic Power Sequencing, MODE =

LOW, EN1 = HIGH, EN2 = LOW

HIGH, EN1 = HIGH, EN2 = HIGH

图9-37. Automatic Power Sequencing, MODE =

图9-38. Automatic Power Sequencing, MODE =

HIGH, EN1 = LOW, EN2 = HIGH

HIGH, EN1 = HIGH, EN2 = LOW

Submit Document Feedback

37

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

图9-39. 120° Out of Phase for Buck1, Buck2,

图9-40. PGOOD Delay, C_{PG_DLY}= 10 nF

Buck3

9.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4.5 V and 17 V. This input power

supply must be well regulated. If the input supply is located more than a few inches from the TPS65265

converter additional bulk capacitance can be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 47 μF is a typical choice.

9.4 Layout

9.4.1 Layout Guidelines

The TPS65265 can be layout on 2-layer PCB, illustrated 图9-41.

Layout is a critical portion of good power supply design. See 图9-41 for a PCB layout example. The top contains

the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining pins of

the TPS65265 and a large top side area filled with ground. The top layer ground area must be connected to the

bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and directly under the

TPS65265 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts

as ground plane connecting analog ground and power ground.

For operation at full rated load, the top-side ground area together with the bottom side ground plane must

provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or

voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power

supplies performance. To help eliminate these problems, the PVIN pin must be bypassed to ground with a low-

ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the

bypass capacitor connections, the PVIN pins, and the ground connections. The PVIN pin must also be bypassed

to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.

Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor

ground must use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this

conductor length while maintaining adequate width. The small signal components must be grounded to the

analog ground path.

The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as

possible to the IC and routed with minimal lengths of trace. The additional external components can be placed

approximately as shown.

English Data Sheet: SLVSD86

38

Submit Document Feedback

Product Folder Links: TPS65265

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

9.4.2 Layout Example

VOUT1

VOUT3

BST1

PGND1

LX1

BST3

PGND3

LX3

PVIN3

PVIN2

LX2

VIN

LX1

PVIN1

PSM

VIN

PGND2

BST2

VOUT2

TOPSIDE

GROUND

AREA

0.010 in. Diameter

Thermal VIA to Ground Plane

VIA to Ground Plane

图9-41. PCB Layout

Submit Document Feedback

39

Product Folder Links: TPS65265

English Data Sheet: SLVSD86

TPS65265

www.ti.com.cn

ZHCSEL9B –DECEMBER 2015 –REVISED MAY 2023

10 Device and Documentation Support

10.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLVSD86

40

Submit Document Feedback

Product Folder Links: TPS65265

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

SEE SIDE WALL

DETAIL

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65265RHBR
厂家：	TEXAS INSTRUMENTS
描述：	4.5V 至 17V 输入电压、5A/3A/2A 输出电流、三路降压转换器 \| RHB \| 32 \| -40 to 85 开关输出元件转换器
文件：	总49页 (文件大小：3374K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65265RHBR [TI]

相关型号：

TPS65265RHBT

TPS65266

TPS65266-1

TPS65266-1RHBR

TPS65266-1RHBT

TPS65266RHBR

TPS65266RHBT

TPS65268-Q1

TPS65268QRHBRQ1

TPS65268QRHBTQ1

TPS65270

TPS65270PWPR