TPS65295 [TI]

4.5V 至 18V 输入电压完整 DDR4 存储器电源解决方案;


型号：	TPS65295
厂家：	TEXAS INSTRUMENTS
描述：	4.5V 至 18V 输入电压完整 DDR4 存储器电源解决方案双倍数据速率存储
文件：	总39页 (文件大小：1908K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS65295

ZHCSJF4 –FEBRUARY 2019

TPS65295 完整 DDR4 存储器电源解决方案

1 特性

3 说明

•

同步降压转换器 (VDDQ)

TPS65295 器件能够以最低的总成本和最小的空间为

DDR4 存储器系统提供完整的电源解决方案。它符合

JEDEC 标准中的 DDR4 加电和断电顺序要求。

TPS65295 将两个同步降压转换器（VPP 和 VDDQ）

与 1A 灌电流和拉电流跟踪 LDO (VTT) 以及缓冲低噪

声基准 (VTTREF) 集成在一起。TPS65295 采用耦合

了 600kHz 开关频率的 D-CAP3™模式，此模式可在无

需外部补偿电路的情况下实现易于使用的快速瞬变并支

持陶瓷输出电容器。

–

输入电压范围：4.5V 至 18V

输出电压固定为 1.2V

D-CAP3™模式控制，用于快速瞬态响应

持续输出电流：8A

高级 Eco-mode™脉冲跳跃

集成 22mΩ 和 8.6mΩ R_DS(on)内部电源开关

600kHz 开关频率

内部软启动：1.6ms

逐周期过流保护

VTTREF 跟踪 ½ VDDQ 的精度优于 0.8%。VTT 可同

时提供 1A 持续灌电流和拉电流功能，而仅需 10μF 的

陶瓷输出电容。

锁存输出 OV 和 UV 保护

•

同步降压转换器 (VPP)

–

输入电压范围：3V 至 5.5V

输出电压固定为 2.5V

TPS65295 可提供丰富的功能和卓越的电源性能。它

支持灵活功耗状态控制，将 VTT 置于高阻抗状态（处

于 S3）并在 S4/S5 状态下对 VDDQ、VTT 和

VTTREF 进行放电。另外还提供 OVP、UVP、OCP、

UVLO 和热关断保护。此器件采用热增强型 18 引脚

HotRod™VQFN 封装，额定结温范围为 –40°C 至

125°C。

D-CAP3™模式控制，用于快速瞬态响应

持续输出电流：1A

高级 Eco-mode™脉冲跳跃

集成 150mΩ 和 120mΩ R_DS(on)内部电源开关

580kHz 开关频率

内部软启动：1ms

器件信息⁽¹⁾

逐周期过流保护

器件型号

TPS65295

封装

VQFN (18)

封装尺寸（标称值）

锁存输出 OV 和 UV 保护

3.00mm × 3.00mm

•

1A LDO (VTT)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

1A 持续灌电流和拉电流

仅需 10μF 的陶瓷输出电容

在 S3 状态下支持高阻态输出

±30mV VTT 输出精度（直流 + 交流）

典型应用

L_VPP

VPP

SW_VPP

PVIN

Cout_VPP

VPPSNS

缓冲基准 (VTTREF)

PVIN_VPP

C-bst

L_VDDQ

BST

–

经缓冲的低噪声 ±10mA 功能

0.8% 输出精度

VCC_5V

VLDOIN

VDDQ

Cout_VDDQ

TPS65295

VDDQSNS

VDDQ

•

低静态电流：150µA

VTT

Cout_VTT

VTT

PGOOD

SLP_S4

电源正常指示器

VTTSNS

VTT_REF

Cout_VTTREF

输出放电功能

VTTREF

VTT_CNTL

AGND

加电和断电排序控制

PGND_VPP

PGND

非锁存 OT 和 UVLO 保护

18 引脚 3.0mm × 3.0mm HotRod™VQFN 封装

2 应用

•

DDR4 存储器电源

笔记本电脑、台式机和服务器

超极本、平板电脑

单板计算机、模块化计算机

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDK5

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

特性.......................................................................... 1

Application and Implementation ........................ 18

8.1 Application Information............................................ 18

8.2 Typical Application ................................................. 18

Power Supply Recommendations...................... 25

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 17

10 Layout................................................................... 26

10.1 Layout Guidelines ................................................. 26

10.2 Layout Example .................................................... 26

11 器件和文档支持 ..................................................... 27

11.1 器件支持 ............................................................... 27

11.2 接收文档更新通知 ................................................. 27

11.3 社区资源................................................................ 27

11.4 商标....................................................................... 27

11.5 静电放电警告......................................................... 27

11.6 术语表 ................................................................... 27

12 机械、封装和可订购信息....................................... 27

12.1 Package Option Addendum .................................. 28

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 2 月

初始发行版。

TPS65295

www.ti.com.cn

ZHCSJF4 –FEBRUARY 2019

5 Pin Configuration and Functions

RJE Package

18-Pin VQFN

Top View

SW PGND_VPP

BST

SW_VPP

VLDOIN

VTT

PVIN_VPP

VCC_5V

AGND

VTTSNS

VPPSNS

SLP_S4

VDDQSNS

VTTREF

VTT_CNTL

PVIN PGOOD PGND

Pin Functions

I/O

DESCRIPTION

NAME

VLDOIN

VTT

NO.

Power supply input for VTT LDO. Connect VDDQ in typical application.

VTT 1-A LDO output. Recommend to connect to 10-μF or larger capacitance for stability.

Signal ground.

AGND

VTTSNS

VTT output voltage feedback.

VDDQSNS

VTTREF

PVIN

VDDQ output voltage feedback.

Buffered VTT reference output. Recommend to connect to 0.22-μF or larger capacitance for stability.

Input power supply for VDDQ buck.

Power good signal open-drain output. PGOOD goes high when VPP and VDDQ output voltage are within

the target range.

PGOOD

PGND

Power ground for VDDQ buck.

VTT_CNTL

VTT_CNTL signal input for VTT LDO enable control. For detail control setup, please refer to表 1.

SLP_S4 signal input for VDDQ buck and VPP buck enable control. For detail control setup, please refer to

表 1.

SLP_S4

VPPSNS

VCC_5V

PVIN_VPP

SW_VPP

PGND_VPP

VPP output voltage feedback.

Power supply for VPP and VDDQ buck converter control logic circuit.

Input power supply for VPP buck.

VPP switching node connection to the inductor and bootstrap capacitor.

Power ground for VPP buck.

VDDQ switching node connection to the inductor and bootstrap capacitor.

High-side MOSFET gate driver bootstrap voltage input for VDDQ buck. Connect a capacitor between the

BST pin and the SW pin.

BST

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

UNIT

PVIN

VBST

VBST-SW

Input voltage

VTT_CNTL, SLP_S4, VCC_5V, PVIN_VPP,

VLDOIN, VDDQSNS, VTTSNS, VPPSNS

–0.3

PGND, AGND,PGND_VPP

SW DC

–0.3

–3

0.3

SW (20-ns transient)

SW_VPP DC

Output voltage

–0.3

–3

SW_VPP (20-ns transient)

PGOOD, VTT,VTTREF

–0.3

–40

–55

T_J

Operating junction temperature

Storage temperature

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22- V C101⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

PVIN

VBST

–0.3

VBST-SW

5.5

Input voltage

VTT_CNTL, SLP_S4, VCC_5V, PVIN_VPP,

VLDOIN, VDDQSNS, VTTSNS, VPPSNS

–0.3

5.5

PGND, AGND,PGND_VPP

SW DC

–0.3

–3

0.3

SW (20-ns transient)

SW_VPP DC

Output voltage

–0.3

–3

5.5

6.5

5.5

SW_VPP (20-ns transient)

PGOOD, VTT,VTTREF

–0.3

I_VDDQOUT

T_J

VDDQ Output current

Operating junction temperature

–40

125

°C

TPS65295

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ZHCSJF4 –FEBRUARY 2019

6.4 Thermal Information

TPS65295

THERMAL METRIC⁽¹⁾

RJE (VQFN)

18 PINS

58.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.1

17.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

17.7

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

T_J=-40^oC to 125^oC, V_PVIN=12V, V_{PVIN_VPP}=5V (unless otherwise noted)

PARAMETER

INPUT SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{SLP_S4}= V_{VTT_CNTL}= 0 V

µA

V_{SLP_S4}= 5 V, V_{VTT_CNTL}= 0 V, no

load

I_{VCC_5V}

VCC_5V supply current

PVIN input voltage range

110

150

V_{SLP_S4}= V_{VTT_CNTL}= 5 V, no load

µA

VIN

4.5

3.3

UVLO

Wake up VCC_5V voltage

Shut down VCC_5V voltage

Hysteresis VCC_5V voltage

4.1

3.6

500

4.5

UVLO

VCC_5V under-voltage lockout

VDDQ

V_VDDQSNS

I_VDDQSNS

VDDQ sense voltage

1.188

1.2

1.212

2.65

VDDQSNS input current

V_VDDQSNS=1.2 V

µA

V_{SLP_S4}= V_{VTT_CNTL}= 0 V,

V_VDDQSNS= 0.5 V

I_VDDQDIS

VDDQ discharge current

t_VDDQSS

VDDQ soft-start time

1.6

t_VDDQDLY

VDDQ ramp up delay time

T_J= 25°C, V_PVIN= 19V, V_{VCC_5V}

R_DSONH

R_DSONL

High-side switch resistance

Low-side switch resistance

mΩ

T_J= 25°C, V_PVIN= 19V, V_{VCC_5V}

8.6

I_VDDQOCL

f_sw

Low-side valley current limited

VDDQ switching freqency

Minimum off time

V_OUT= 1.2 V, L = 0.68 µH

8.2

9.8

600

198

11.5

kHz

t_OFF(MIN)

PGOOD (VDDQ, VPP)

VDDQSNS / VPPSNS falling (Fault)

VDDQSNS / VPPSNS rising (Good)

VDDQSNS / VPPSNS rising (Fault)

VDDQSNS / VPPSNS falling (Good)

V_THPG

PGOOD threshold

115

110

V_PGOOD=0.5V, V_{SLP_S4}=V_{VTT_CNTL}

= 5 V, no load

I_PGMAX

PG sink current

t_PGDLY

VPP

PG start-up delay

PG from low to high

V_VPPSNS=2.5 V

V_VPPSNS

I_VPPSNS

VPP sense voltage

2.45

2.5

2.55

VPPSNS input current

µA

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

Electrical Characteristics (continued)

T_J=-40^oC to 125^oC, V_PVIN=12V, V_{PVIN_VPP}=5V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{SLP_S4}= V_{VTT_CNTL}= 0 V, V_VPPSNS

= 0.5 V

I_VPPDIS

t_VPPSS

VPP discharge current

VPP soft-start time

1 .0

150

T_J= 25°C, V_{PVIN_VPP}= 5V, V_{VCC_5V}

= 5V

R_DSONH

High-side switch resistance

mΩ

T_J= 25°C, V_{PVIN_VPP}=5V, V_{VCC_5V}

R_DSONL

Low-side switch resistance

120

mΩ

I_VPPOCL

f_sw

t_OFF(MIN)

t_OOA

Low-side valley current limited

VPP switching frequency

Minimum off time

V_OUT= 2.5 V, L = 4.7 µH

1.05

1.6

580

195

2.1

kHz

OOA mode operation period

V_VPPSNS=2.5 V

µs

OVP AND UVP (VDDQ, VPP)

V_OVP

OVP threshold voltage

OVP detect voltage

UVP detect voltage

120

125

130

V_UVP1

t_OVPDLY

t_UVPDLY

UVP threshold voltage

OVP delay

µs

UVP delay

250

VTTREF OUTPUT

1/2*

V_VDDQSNS

V_VTTREFOutput voltage

T_J= 25°C, |I_VTTREF| ≤100 µA,

V_VDDQSNS= 1.2 V

49.2

50.8

V_VTTREF

Output voltage tolerance to VDDQ

T_J= 25°C, |I_VTTREF| ≤10mA,

V_VDDQSNS= 1.2 V

I_VTTREFOCLSRCSource current limit

V_VDDQSNS= 1.2 V, V_VTTREF= 0 V

V_VDDQSNS= 1.2 V, V_VTTREF= 1.2 V

I_VTTREFOCLSnk

Sink current limit

T_J= 25°C, V_{SLP_S4}= V_{VTT_CNTL}= 0

V, V_VTTREF= 0.5 V

I_VTTREFDIS

VTTREF discharge current

0.8

1.3

VTT OUTPUT

V_VTT

Output voltage

V_VTTREF

|I_VTT| ≤10 mA, V_VDDQSNS= 1.2 V,

I_VTTREF= 0 A

–20

–30

V_VTTTOL

Output voltage tolerance

T_J= 25°C,|I_VTT| ≤1A, V_VDDQSNS

1.2 V, I_VTTREF= 0 A

V_VDDQSNS= 1.2 V, V_VTT= V_VTTSNS

0.5 V, I_VTTREF=0 A

I_VTTOCLSRC

I_VTTOCLSnk

I_VTTLK

Source current limit

Sink current limit

1.7

V_VDDQSNS= 1.2 V, V_VTT= V_VTTSNS

0.7 V, I_VTTREF=0 A

T_J= 25°C, V_{SLP_S4}= 5 V, V_{VTT_CNTL}

= 5 V, V_VTT=V_VTTREF

Leakage current

0.5

V_{SLP_S4}= 5 V, V_{VTT_CNTL}= 5 V,

V_VTT=V_VTTREF

I_VTTSNSBIAS

I_VTTSNSLK

I_VTTDLY

VTTSNS input bias current

VTTSNS leakage current

–0.5

–1

µA

V_{SLP_S4}= 5 V, V_{VTT_CNTL}= 0 V,

V_VTT=V_VTTREF

VTT output delay relative to

VTT_CNTL

T_J= 25°C, V_{SLP_S4}= V_{VTT_CNTL}= 0

V, V_VDDQSNS= 1.2 V, V_VTT=0.5V,

I_VTTREF=0 A

I_VTTDIS

VTT discharge current

5.7

SLP_S4, VTT_CNTL LOGIC THRESHOLD

SLP_S4/VTT_CNTL high-level

voltage

V_IH

1.6

TPS65295

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ZHCSJF4 –FEBRUARY 2019

Electrical Characteristics (continued)

T_J=-40^oC to 125^oC, V_PVIN=12V, V_{PVIN_VPP}=5V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SLP_S4/VTT_CNTL low-level

voltage

V_IL

0.5

SLP_S4/VTT_CNTL resistance to

GND

R_TOGND

500

kΩ

THERMAL PROTECTION

T_OTP

OTP trip threshold

OTP hysteresis

150

°C

T_OTPHSY

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

6.6 Typical Characteristics

190

180

170

160

150

140

130

120

5.6

5.4

5.2

4.8

4.6

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D001

D002

V_{SLP_S4}= 5 V

V_{VTT_CNTL}= 5 V

V_{SLP_S4}= 0 V

V_{VTT_CNTL}= 0 V

图 1. VCC_5V Supply Current vs Junction Temperature

1.21

图 2. VCC_5V Shutdown Current vs Temperature

2.55

2.53

2.51

2.49

2.47

2.45

1.206

1.202

1.198

1.194

1.19

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D003

D004

图 3. VDDQ Output Voltage vs Junction Temperature

图 4. VPP Output Voltage vs Junction Temperature

1.14

1.12

1.1

1.05

0.95

0.9

1.08

1.06

1.04

1.02

0.85

0.8

0.75

0.7

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D005

D007

图 5. Enable On Voltage (SLP_S4) vs Junction Temperature

图 6. Enable Off Voltage (SLP_S4) vs Junction Temperature

TPS65295

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ZHCSJF4 –FEBRUARY 2019

Typical Characteristics (接下页)

1.12

0.95

0.9

1.1

1.08

1.06

1.04

1.02

0.85

0.8

0.75

0.7

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D006

D008

图 7. Enable On Voltage (VTT_CNTL) vs Junction

图 8. Enable Off Voltage (VTT_CNTL) vs Junction

Temperature

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D009

D010

图 9. VDDQ High-Side R_DS(on)vs Junction Temperature

200

图 10. VDDQ Low-Side R_DS(on)vs Junction Temperature

150

140

130

120

110

100

180

160

140

120

100

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D011

D012

图 11. VPP High-Side R_DS(on)vs Junction Temperature

图 12. VPP Low-Side R_DS(on)vs Junction Temperature

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Typical Characteristics (接下页)

130

128

126

124

122

120

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D013

D014

图 13. VDDQ OVP Threshold vs Junction Temperature

129

图 14. VDDQ UVP Threshold vs Junction Temperature

128

127

126

125

124

123

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D015

D016

图 15. VPP OVP Threshold vs Junction Temperature

图 16. VPP UVP Threshold vs Junction Temperature

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D017

D018

图 17. VDDQSNS Discharge Current vs Junction

图 18. VPPSNS Discharge Current vs Junction Temperature

Temperature

TPS65295

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ZHCSJF4 –FEBRUARY 2019

Typical Characteristics (接下页)

6.5

1.35

1.3

5.5

1.25

1.2

4.5

1.15

1.1

-50

-20

100

130

-50

-20

100

130

Junction Temperature (^oC)

D019

D036

图 19. VTTSNS Discharge Current vs Junction Temperature

图 20. VTTREF Discharge Current vs Junction Temperature

1.65

10.6

10.2

9.8

9.4

1.6

1.55

1.5

1.45

1.4

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D020

D021

图 21. VDDQ Valley Current Limit vs Junction Temperature

图 22. VPP Valley Current Limit vs Junction Temperature

1.8

1.2

1.75

1.7

1.16

1.12

1.08

1.04

1.65

1.6

1.55

1.5

-50

-20

100

130

-50

-20

100

130

Junction Temperature (èC)

D022

D023

图 23. VDDQ Soft-Start Time vs Junction Temperature

图 24. VPP Soft-Start Time vs Junction Temperature

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www.ti.com.cn

Typical Characteristics (接下页)

800

700

600

500

400

300

200

800

700

600

500

400

300

200

3.25 3.5 3.75

4.25 4.5 4.75

5.25 5.5

PVIN (V)

PVIN_VPP(V)

D025

D024

I_OUT= 1 A

I_OUT= 8 A

图 26. VPP Switching Frequency vs Input Voltage

图 25. VDDQ Switching Frequency vs Input Voltage

800

700

600

500

400

300

200

100

800

700

600

500

400

300

200

100

V_PVIN=7.4V

V_PVIN=12V

V_PVIN=19V

V_{PVIN_VPP}=3.3V

V_{PVIN_VPP}=5V

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I-Load (A)

D026

D027

图 27. VDDQ Switching Frequency vs Load Current

图 28. VPP Switching Frequency vs Load Current

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7 Detailed Description

7.1 Overview

The TPS65295 integrates two synchronous step-down buck converters and two LDOs to support complete DDR4

power solution. The VDDQ buck converter has the fixed 1.2-V output and supports continuous 8-A output

current, and it can operate from 4.5-V to 18-V PVIN input voltage. The VPP buck converter has the fixed 2.5-V

output and supports continuous 1-A output current, and can operate from 3-V to 5.5-V PVIN_VPP input voltage.

The VTTREF LDO tracks the ½ VDDQ output and has about 10-mA both sink and source current capability. The

VTT LDO tracks the VTTREF output and has continuous 1-A both sink and source current capability.

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7.2 Functional Block Diagram

PG high threshold

VPP

VPPSNS

PG low threshold

VPP

PGOOD

Logic

PG high threshold

VDDQ

PGOOD

UV threshold

VDDQ

PG low threshold

VDDQ

OV threshold

VDDQ

VCC_5V

0.8 V

VCC_5V OK

Control Logic

4.1 V /

3.6 V

Error

Amp

PWM

VDDQSNS

BST

Discharge

control

PVIN

On/Off time

Minimum On/Off

Light load PSM

OVP/UVP/OCP

TSD

Soft-Start

Discharge

PGOOD

Disable/Enable

Sequence Control

VDDQ

Internal Ramp

VDDQ

Ripple injection

VDDQ

Softstart

XCON

PGND

VDDQ One Shot

OCL

SLP_S4 Threshold

SLP_S4

NOCL

THOK

150°C /20°C

VCC_5V

PVIN_VPP

UV threshold

VPP

AGND

OV threshold

VPP

SW_VPP

XCON

0.8 V

PGND_VPP

Error Amp

PWM

VPPSNS

OCL

Discharge

control

VPP

Internal Ramp

VPP

Ripple injection

VPP

Softstart

NOCL

SW_VPP

VTT_CNTL

VPP One Shot

VTT_CNTL

threshold

VTTREF

VDDQSNS

VLDOIN

Discharge

control

VTT

Discharge

control

VTTSNS

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7.3 Feature Description

7.3.1 PWM Operation and D-CAP3™ Control

The main control loop of the two bucks is adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time control

with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration

with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The

TPS65295 also includes an error amplifier that makes the output voltage very accurate.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal

one-shot timer expires. This one-shot duration is set proportional to the converter input voltage, VIN, and is

inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage

range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is

turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit

is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output

capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation

is required for DCAP3™ control topology.

Both VDDQ buck and VPP buck include an error amplifier that makes the output voltage very accurate. For any

control topology that is compensated internally, there is a range of the output filter it can support. The output filter

used with the TPS65295 is a low-pass L-C circuit. This L-C filter has a double-pole frequency described in 公式

2´ p´ L_OUT´ C_OUT

(1)

At low frequencies, the overall loop gain is set by the internal output set-point resistor divider network and the

internal gain of the TPS65295. The low-frequency L-C double pole has a 180 degree in phase. At the output filter

frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple

generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per

decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection

high-frequency zero is related to the switching frequency. The inductor and capacitor selected for the output filter

must be such that the double pole is placed close enough to the high-frequency zero, so that the phase boost

provided by this high-frequency zero provides adequate phase margin for the stability requirement. The

crossover frequency of the overall system should usually be targeted to be less than one-fifth of the switching

frequency (F_SW).

7.3.2 Advanced Eco-mode™ Control

The VDDQ buck and VPP buck are designed with advanced Eco-mode™ control schemes to maintain high light

load efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced

and eventually comes to a point where the rippled valley touches zero level, which is the boundary between

continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero

inductor current is detected. As the load current further decreases, the converter runs into discontinuous

conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode, so that it

takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage.

This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency

high. The light load current where the transition to Eco-mode™ operation happens ( I_OUT(LL)) can be calculated

from 公式 2.

(V -V_OUT) × V_OUT

I_OUT(LL)

2 × L_OUT× F_SW

(2)

After identifying the application requirements, design the output inductance (L_OUT) so that the inductor peak-to-

peak ripple current is approximately between 20% and 30% of the I_OUT(max)(peak current in the application). It is

also important to size the inductor properly so that the valley current does not hit the negative low-side current

limit.

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Feature Description (接下页)

7.3.3 Soft Start and Prebiased Soft Start

The VDDQ buck has an internal 1.6-ms soft start and VPP buck has an internal 1-ms soft start. Provide the

voltage supply to PVIN, PVIN_VPP and VCC_5V before asserting SLP_S4 to be high, when the SLP_S4 pin

becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the

internal reference voltage becomes greater than the feedback voltage. This scheme ensures that the converters

ramp up smoothly into regulation point.

7.3.4 Power Good

The Power Good (PGOOD) pin is an open-drain output. Once the VDDQSNS and VPPSNS pins voltage are

between 90% and 110% of the target output voltage, the PGOOD is deasserted and floats after a 1-ms de-glitch

time. A pullup resistor of 100 kΩ is recommended to pull the voltage up to VCC_5V. The PGOOD pin is pulled

low when:

•

the VDDQSNS pin voltage or VPPSNS pin voltage is lower than 85% or greater than 115% of the target

output voltage

•

in an OVP, UVP, or thermal shutdown event

during the soft-start period.

7.3.5 Overcurrent Protection and Undervoltage Protection

Both VDDQ and VPP bucks have the overcurrent protection and undervoltage protection, and the implementation

is same. The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit.

The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage.

This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,

Vout, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current

decreases linearly. The average value of the switch current is the load current I_OUT. If the monitored current is

above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even

the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent

switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of overcurrent protection. When the load current is higher

than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and

the current is being limited, the output voltage tends to drop because the load demand is higher than what the

converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator

detects it, the output will be discharged and latched after a wait time of 256 µs. When the overcurrent condition is

removed, the output voltage is latched till the SLP_S4 is toggled or repower the VCC_5V power input.

7.3.6 Overvoltage Protection

Both VDDQ and VPP bucks have the overvoltage protection feature and have the same implementation. When

the output voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, and

then the output will be discharged and latched after a wait time of 20 µs. When the over current condition is

removed, the output voltage is latched till the SLP_S4 is toggled or repower the VCC_5V power input.

7.3.7 UVLO Protection

Undervoltage Lockout protection (UVLO) monitors the VCC_5V power input. When the voltage is lower than

UVLO threshold voltage, the device is shut off and outputs are discharged. This is a non-latch protection.

7.3.8 Output Voltage Discharge

The VPP buck, VDDQ buck, VTT LDO, and VTTREF LDO block all have the discharge function by using internal

MOSFETs, which are connected to the corresponding output terminals VPPSNS, VDDQSNS, VTT, and

VTTREF. The discharge is slow due to the lower current capability of these MOSFETs.

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Feature Description (接下页)

7.3.9 Thermal Shutdown

The TPS65295 monitors the internal die temperature. If the temperature exceeds the threshold value (typically

150°C), the device is shut off and the output will be discharged. This is a non-latch protection. The device

restarts switching when the temperature goes below the thermal shutdown recover threshold.

7.4 Device Functional Modes

7.4.1 Light Load Operation for VDDQ Buck and VPP Buck

When the load is light on the VDDQ or VPP output, the buck enters pulse skip mode after the inductor current

crosses zero. This is the Eco-mode™ which improves the efficiency at light load with a lower switching

frequency. Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when

the VDDQSNS or VPPSNS voltage falls below the Eco-mode™ threshold voltage. As the output current

decreases, the period time between switching pulses increases.

7.4.2 Output State Control

The TPS65295 has two enable input pins, SLP_S4 and VTT_CNTL, to provide simple control scheme of output

state. All of VPP, VDDQ, VTTREF and VTT are turned on at S0 state (SLP_S4=VTT_CNTL=high). In S3 state

(VTT_CNTL=low, SLP_S4=high), VPP, VDDQ, and VTTREF voltages are kept on while VTT is turned off and left

at high impedance state (high-Z). The VTT output floats and does not sink or source current in this state. In

S4/S5 states (SLP_S4=VTT_CNTL =low), all of the three outputs are turned off and discharged to GND. Each

state code represents as follow: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 =

soft OFF (see 表 1).

表 1. VTT_CNTL and SLP_S4 Control for Output State

STATE

VTT_CNTL

SLP_S4

VPP

VDDQ

VTTREF

VTT

OFF (High-Z)

OFF (discharge)

S5/S4

OFF (discharge)

7.4.3 Output Sequence Control

There are specific sequencing requirements for the DDR4 VDDQ and VPP rails. The TPS65295 follows the

DDR4 power rail sequence requirements as shown in 图 29 and 图 30. VPP is greater than VDDQ at all times

during ramp up, operating, and ramp down. The VTT output ramp and stable within 35 µs after VTT_CNTL

asserted.

SLP_S4

VTT_CNTL

VPP

VTT

VDDQ

High-Z

T1: 1 ms

T2: 2.0 ms

T3: 1.6 ms

T4: 30 ms to 60 ms

T<35 us

图 29. Power Sequence, VPP and VDDQ vs SLP_S4

图 30. Power Sequence, VTT vs VTT_CNTL

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The schematic of 图 31 shows a typical application for TPS65295. For VDDQ buck, the PVIN supports 4.5-V to

18-V input range with 1.2-V VDDQ output, the continuous current capability is 8 A. Usually the PVIN_VPP and

VCC_5V can share one 5-V power input and supports 2.5-V VPP output with 1-A continuous current capability,

of course the PVIN_VPP can be lowered down to a 3.3-V power supply. The VLDOIN power input usually is

connected to VDDQ output, while also it can be connected to external 1.2-V power supply input. The VTTREF

output voltage will follow the ½ VDDQSNS voltage, and VTT output voltage will follow the VTTREF output

voltage, this is required by DDR4 power supply standard.

8.2 Typical Application

图 31. Application Schematic

8.2.1 Design Requirements

表 2 lists the design parameters for this example.

表 2. Design Parameters

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

VDDQ OUTPUT

V_OUT

Output voltage

1.2

I_OUT

Output current

ΔV_OUT

V_IN

Transient response

Input voltage

8-A load step

±60

4.5

V_OUT(ripple)

F_SW

Output voltage ripple

Switching frequency

mV_(P-P)

kHz

600

VPP OUTPUT

V_OUT

Output voltage

Output current

Transient response

Input voltage

2.5

I_OUT

ΔV_OUT

V_IN

1-A load step

±125

5.5

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Typical Application (接下页)

表 2. Design Parameters (接下页)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

mV_(P-P)

kHz

V_OUT(ripple)

F_SW

Output voltage ripple

Switching frequency

580

OTHERS

Internal

UVLO

Start VCC_5V input voltage

Stop VCC_5V input voltage

VCC_5V Input voltage rising

VCC_5V Input voltage falling

V_{VCC_5V}

Internal

UVLO

Light load operating mode

Ambient temperature

ECO

T_A

°C

8.2.2 Detailed Design Procedure

8.2.2.1 External Component Selection

8.2.2.1.1 Inductor Selection

The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output

capacitor should have a ripple current rating higher than the inductor ripple current. See 表 3 for recommended

inductor values.

The RMS and peak currents through the inductor can be calculated using 公式 3 and 公式 4. It is important that

the inductor is rated to handle these currents.

²ö

V_OUT× V

- V_OUT

(

× L_OUT× F_SW

IN(max)

)

IN(max)

ç ²

IL(rms)=

OUT

(3)

(4)

I_OUT(ripple)

= I_OUT

L(peak)

During transient and short-circuit conditions, the inductor current can increase up to the current limit of the device

so it is safe to choose an inductor with a saturation current higher than the peak current under current limit

condition.

8.2.2.1.2 Output Capacitor Selection

After selecting the inductor the output capacitor needs to be optimized. In DCAP3, the regulator reacts within one

cycle to the change in the duty cycle so the good transient performance can be achieved without needing large

amounts of output capacitance. The recommended output capacitance range is given in 表 3.

Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than

V_OUT(ripple)/I_OUT(ripple)

表 3. Recommended Component Values

V_OUT(V)

F_sw(kHz)

600

L_OUT(µH)

0.68

0.56

0.47

6.8

C_OUT(min)(µF)

C_OUT(max)(µF)

132

1.2

600

580

2.5

580

4.7

580

3.3

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For VTT output, high quality X5R or X7R 10-µF capacitor is recommended and a 0.47 µF is recommended for

VTTREF output.

8.2.2.1.3 Input Capacitor Selection

The TPS65295 requires input decoupling capacitors on both power supply input PVIN and PVIN_VPP, and the

bulk capacitors are needed depending on the application. The minimum input capacitance required is given in 公

式 5.

I_OUT×V_OUT

C_IN(min)

_INripple×V ×F_SW

(5)

TI recommends using a high-quality X5R or X7R input decoupling capacitors of 30 µF on the VDDQ buck input

voltage pin PVIN, and 10 µF on the VPP buck input voltage pin PVIN_VPP. The voltage rating on the input

capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating

greater than the maximum input current ripple of the application. The input ripple current is calculated by 公式 6:

VIN(min)-VOUT

(

)

VOUT

I_CIN(rms)= IOUT ×

VIN(min)

(6)

An additional 0.1-µF capacitor from PVIN to ground and from PVIN_VPP to ground is optional to provide

additional high frequency filtering. One ceramic capacitor of 10 µF is recommended for the decoupling capacitor

on VLDOIN pin for providing stable power on VTT LDO block. A 1-µF ceramic capacitor is needed for the

decoupling capacitor on VCC_5V input.

8.2.2.1.4 Bootstrap Capacitor and Resistor Selection

A 0.1-µF ceramic capacitor serialized with a 5.1-Ω resistor is recommended between the BST and SW pin for

proper operation. TI recommends using a ceramic capacitor.

8.2.3 Application Curves

图 32 through 图 60 apply to the circuit of 图 31. V_IN= 12 V. T_A= 25°C unless otherwise specified.

100

V_PVIN=7.4V,V_OUT=1.2V

V_PVIN=12V, V_OUT=1.2V

V_PVIN=19V, V_OUT=1.2V

V_{PVIN_VPP}=3.3V,V_OUT=2.5V

V_{PVIN_VPP}=5V , V_OUT=2.5V

0.001

0.01

0.1

0.001

0.01

0.1

I-Load (A)

D029

D028

图 32. VDDQ Efficiency Curve, V_OUT= 1.2 V

图 33. VPP Efficiency Curve, V_OUT= 2.5 V

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1.25

1.24

1.23

1.22

1.21

1.2

2.55

2.54

2.53

2.52

2.51

2.5

1.19

1.18

1.17

1.16

2.49

2.48

2.47

2.46

2.45

V_PVIN=7.4V

V_PVIN=12V

V_PVIN=19V

V_{PVIN_VPP}=3.3V

V_{PVIN_VPP}=5V

1.15

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I-Load (A)

D030

D031

图 34. VDDQ Load Regulation, V_OUT= 1.2 V

图 35. VPP Load Regulation, V_OUT= 2.5 V

0.65

0.64

0.63

0.62

0.61

0.6

0.65

0.64

0.63

0.62

0.61

0.6

0.59

0.58

0.57

0.56

0.55

0.59

0.58

0.57

0.56

0.55

-1 -0.8 -0.6 -0.4 -0.2

0.2 0.4 0.6 0.8

-10

-8

-6

-4

-2

I-Load (A)

I-Load (mA)

D034

D035

图 36. VTT Load Regulation, V_OUT= 0.6 V

图 37. VTTREF Load Regulation, V_OUT= 0.6 V

2.55

1.3

1.28

1.26

1.24

1.22

1.2

2.54

2.53

2.52

2.51

2.5

2.49

2.48

2.47

2.46

2.45

1.18

1.16

1.14

1.12

I_OUT=0A

I_OUT=1A

I_OUT=0A

I_OUT=8A

1.1

3.25 3.5 3.75

4.25 4.5 4.75

PVIN_VPP (V)

5.25 5.5

PVIN (V)

D033

D032

图 39. VPP Line Regulation, V_OUT= 2.5 V

图 38. VDDQ Line Regulation,V_OUT= 1.2 V

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VDDQ=50mV/div

Io=500mA/div

VPP=50mV/div

Io=500mA/div

40ms/div

10ms/div

图 40. VDDQ Output Voltage Ripple, I_OUT= 0 A

图 41. VPP Output Voltage Ripple, I_OUT= 0 A

VDDQ=10mV/div

VPP=10mV/div

Io=500mA/div

Io=5A/div

1us/div

图 42. VDDQ Output Voltage Ripple, I_OUT= 8 A

图 43. VPP Output Voltage Ripple, I_OUT= 1 A

SLP_S4=2V/div

VPP=2V/div

SLP_S4=2V/div

VPP=2V/div

VDDQ=1V/div

PGOOD=5V/div

VDDQ=1V/div

PGOOD=5V/div

2ms/div

图 44. Start-Up Through SLP_S4, I_VPPOUT= 0 A, I_VDDQOUT

图 45. Start-Up Through SLP_S4, I_VPPOUT= 1 A, I_VDDQOUT=

0 A

8 A

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SLP_S4=2V/div

VPP=2V/div

SLP_S4=2V/div

VPP=2V/div

VDDQ=1V/div

PGOOD=5V/div

VDDQ=1V/div

PGOOD=5V/div

20ms/div

图 46. Shutdown Through SLP_S4, I_VPPOUT= 0 A, I_VDDQOUT

图 47. Shutdown Through SLP_S4, I_VPPOUT= 1 A, I_VDDQOUT

= 0 A

= 8 A

SLP_S4=2V/div

VTT_CTRL=2V/div

VDDQ=1V/div

VTT=500mV/div

2ms/div

I_VDDQOUT= 0 A

I_VTT= 0 A

I_VTTREF= 0 A

I_VDDQOUT= 8 A

图 49. VTT Start-Up Through VTT_CNTL

SLP_S4=2V/div

I_VTT= 1 A

I_VTTREF= 10m A

图 48. VTT Start-Up Through VTT_CNTL

SLP_S4=2V/div

VTT_CTRL=2V/div

VDDQ=1V/div

VTT=500mV/div

4ms/div

I_VTT= 1 A

10ms/div

I_VTT= 0 A

I_VDDQOUT= 8 A

I_VTTREF= 10 mA

I_VDDQOUT= 0 A

I_VTTREF= 0 A

图 51. VTT Shutdown Through VTT_CNTL

图 50. VTT Shutdown Through VTT_CNTL

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SLP_S4=2V/div

VDDQ=1V/div

VTT=500mV/div

VTT_REF=500mV/div

4ms/div

I_VTT= 0 A

4ms/div

I_VTT= 1 A

I_VDDQOUT= 0 A

I_VTTREF= 0 A

I_VDDQOUT= 8 A

I_VTTREF= 10 mA

图 52. VTT Start-Up Through SLP_S4

图 53. VTT Start-Up Through SLP_S4

SLP_S4=2V/div

VDDQ=1V/div

SLP_S4=2V/div

VDDQ=1V/div

VTT=500mV/div

VTT_REF=500mV/div

10ms/div

I_VTT= 0 A

4ms/div

I_VTT= 1 A

I_VDDQOUT= 0 A

I_VTTREF= 0 A

I_VDDQOUT= 8 A

I_VTTREF= 10 mA

图 54. VTT Shutdown Through SLP_S4

图 55. VTT Shutdown Through SLP_S4

VPP=100mV/div

VDDQ=50mV/div

Io=5A/div

Io=1A/div

400us/div

Slew Rate=2.5A/us

图 56. VPP Transient Response, 0 A to 1 A

图 57. VDDQ Transient Response, 1.6 A to 8 A

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VDDQ=50mV/div

SW=5V/div

VPP=2V/div

Io=5A/div

IL=1A/div

400us/div

100us/div

Slew Rate=2.5A/us

图 58. VDDQ Transient Response, 0.1 A to 6.4 A

图 59. VPP Normal Operation to Output Hard Short

SW=5V/div

IL=5A/div

VDDQ=500mV/div

100us/div

图 60. VDDQ Normal Operation to Output Hard Short

9 Power Supply Recommendations

TPS65295 is designed for DDR4 complete power solution. PVIN is the power input for VDDQ buck, PVIN_VPP is

the power input for VPP buck, VLDOIN input is for VTT LDO power supply, VCC_5V is power supply for internal

control logic. Below lists the power on sequence scenarios.

•

SLP_S4 is high before PVIN or PVIN_VPP has the power input, VCC_5V power supply must be provided

after or same time with PVIN or PVIN_VPP, otherwise the output will be latched, this latch can be recovered

by toggling the SLP_S4 pin or re-power the VCC_5V

•

SLP_S4 is low before PVIN and PVIN_VPP has the power input, then there is no power supply input

sequence requirement for VCC_5V, PVIN and PVIN_VPP.

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

•

Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-

inch, four-layer PCB with 2-oz. copper used as example.

•

Place the decoupling capacitors right across PVIN, PVIN_VPP, and VLDOIN as close as possible.

Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to

minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND

connection of output capacitor and also as close to the output pin as possible. Reserve some space between

VDDQ choke and VPP choke, just minimize radiation crosstalk.

•

Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace

is recommended to reduce line parasitic inductance.

VPPSNS/VDDQSNS/VTTSNS could be 10 mil and must be routed away from the switching node, BST node

or other high efficiency signal.

PVIN and PVIN_VPP trace must be wide to reduce the trace impedance and provide enough current

capability.

Output capacitors for VTT and VTTREF should be put as close as output pin.

10.2 Layout Example

图 61 shows the recommended top-side layout. Component reference designators are the same as the circuit

shown in 图 31.

PVIN

VDDQ

PGND_VPP

PGND

VPP

图 61. Top-Side Layout

TPS65295

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ZHCSJF4 –FEBRUARY 2019

11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

D-CAP3, Eco-mode, HotRod, DCAP3, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

12.1 Package Option Addendum

12.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

Lead/Ball

Finish⁽³⁾

(1)

(2)

(4)

Orderable Device

TPS65295RJER

TPS65295RJET

Status

Pins

Eco Plan

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking⁽⁵⁾⁽⁶⁾

PRE_PRO

Green (RoHS

& no Sb/Br)

Level-2-260C-1

YEAR

VQFN-HR

RJE

3000

250

CU NIPDAU

65295

PRE_PRO

Green (RoHS

& no Sb/Br)

Level-2-260C-1

YEAR

VQFN-HR

-40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the

finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TPS65295

www.ti.com.cn

ZHCSJF4 –FEBRUARY 2019

12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS65295RJER

TPS65295RJET

VQFN-HR

RJE

3000

250

330

180

12.4

3.3

1.1

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

TPS65295RJER

TPS65295RJET

VQFN-HR

RJE

367

210

367

185

TPS65295

www.ti.com.cn

ZHCSJF4 –FEBRUARY 2019

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

RJE0018B

PLASTIC QUAD FLATPACK- NO LEAD

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

1 MAX

SEATING PLANE

0.08

0.05

0.00

2X 0.45

0.25

0.15

0.5

0.3

0.6

0.4

(0.1) TYP

0.48

0.28

6X 0.5

2.09

1.99

PKG

1.5

2.5

0.3

0.2

0.1

C A B

0.3

0.2

0.5

0.3

0.05

10X

0.25

0.15

2X 0.65

0.33

0.23

PKG

0.1

C A B

2X 2.48

0.05

4223865 / B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

TPS65295

ZHCSJF4 –FEBRUARY 2019

www.ti.com.cn

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

RJE0018B

PLASTIC QUAD FLATPACK- NO LEAD

4X (1.24)

2X (0.65)

6X (0.2)

8X (0.6)

4X (0.58)

8X (0.25)

(1.25)

(2.243)

6X (0.5)

PKG

(2.83)

(0.58)

(R0.05) TYP

4X (0.25)

(2.238)

(0.7)

4X (0.6)

PKG

(2.8)

4X (0.28)

2X (0.45)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

SOLDER MASK

OPENING

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223865 / B 02/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

TPS65295

www.ti.com.cn

ZHCSJF4 –FEBRUARY 2019

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

RJE0018B

PLASTIC QUAD FLATPACK- NO LEAD

4X (1.23)

2X (0.65)

9X (0.2)

8X (0.6)

4X (0.58)

4X (0.225)

8X (0.25)

(1.24)

3X (1.19)

6X (0.5)

PKG

(1.022)

(2.83)

2X (0.028)

(0.034)

(R0.05) TYP

(1.35)

EXPOSED METAL

(1.019)

(0.7)

PKG

(2.8)

4X (0.25)

4X (0.6)

2X (0.45)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 6, 10 &15: 93% & PADS 7-9,17:89%

SCALE: 20X

4223865 / B 02/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS65295RJER

TPS65295RJET

ACTIVE

VQFN-HR

RJE

3000 RoHS & Green

250 RoHS & Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 125

65295

Samples

NIPDAU | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2022

Addendum-Page 2

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RJE0018B

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 0.45

0.25

0.5

0.3

0.6

0.4

(0.1) TYP

0.48

0.28

0.15

6X 0.5

2.14

1.94

PKG

1.5

2.5

0.3

0.2

0.1

C A B

0.3

0.2

0.5

0.3

0.05

10X

0.25

0.15

2X 0.65

0.33

0.23

PKG

0.1

C A B

2X 2.48

0.05

4223865 / C 03/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RJE0018B

4X (1.24)

2X (0.65)

6X (0.2)

8X (0.6)

4X (0.58)

8X (0.25)

(1.25)

(2.243)

6X (0.5)

PKG

(2.83)

(0.58)

(R0.05) TYP

4X (0.25)

(2.238)

(0.7)

PKG

(2.8)

4X (0.28)

4X (0.6)

2X (0.45)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

SOLDER MASK

OPENING

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223865 / C 03/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RJE0018B

4X (1.23)

2X (0.65)

9X (0.2)

8X (0.6)

4X (0.58)

4X (0.225)

8X (0.25)

(1.24)

3X (1.19)

6X (0.5)

PKG

(1.022)

(2.83)

2X (0.028)

(0.034)

(R0.05) TYP

(1.35)

EXPOSED METAL

(1.019)

(0.7)

PKG

(2.8)

4X (0.25)

4X (0.6)

2X (0.45)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 6, 10 &15: 93% & PADS 7-9,17:89%

SCALE: 20X

4223865 / C 03/2020

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS65295 [TI]

相关型号：

TPS65295RJER

TPS65295RJET

TPS65296

TPS65296RJER

TPS65300-Q1

TPS65300QPWPRQ1

TPS65300QRHFRQ1

TPS65301-Q1

TPS65301QPWPRQ1

TPS65310A-Q1

TPS65310AQRVJQ1

TPS65310AQRVJRQ1