TPS65290_14 [TI]
LOW QUIESCENT CURRENT, MULTI-MODE PMIC FOR BATTERY POWERED, ENERGY HARVESTING APPLICATIONS;
| 型号： | TPS65290_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW QUIESCENT CURRENT, MULTI-MODE PMIC FOR BATTERY POWERED, ENERGY HARVESTING APPLICATIONS 集成电源管理电路 |
| 文件： | 总59页 (文件大小：4536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65290
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
LOW QUIESCENT CURRENT, MULTI-MODE PMIC FOR BATTERY POWERED, ENERGY
HARVESTING APPLICATIONS
1
FEATURES
•
Operating Input Voltage Range: 2.2 V to 5 V
•
Input Voltage Recovery Comparator With
Selectable Threshold
•
500-mA Buck-Boost Converter, Stand-Alone
Operation or Serial Bus Controlled
•
•
•
Factory Selectable SPI/I2C Interface
-40°C to 85°C Ambient Temperature Range
24-Pin RHF (QFN) Package
•
•
•
PFM/PWM Operation With Forced PWM Option
150 mA LDO
Stand-Alone or Serial Bus (SPI or I2C)
Controlled
APPLICATIONS
•
•
Low Power, Energy Harvesting Systems
Battery Powered Applications
•
•
•
Two Power Distribution Switches Powered
from Buck-Boost Output
One Power Distribution Switch Powered from
the Maximum of Buck Boost or Battery Input
VIN
BB_OUT
I2C/SPI
Buck boost
EN BB
PWR_BB1
I2C/SPI
GPIO3
Two Power Distribution Switches Powered
from LDO Output
VMAX
PWR_VMAX
PWR_BB2
I2C/SPI
GPIO3
MAX
I2C/SPI
GPIO4
•
•
One Power Switch Powered from Battery Input
One Power Switch to Connect BB Output to
LDO Output and Improve System Efficiency
VMAX
I2C/SPI
LDO_IN
LDO_OUT
LDO
PWR_LDO1
I2C/SPI
•
Automatic Power Max Function Between
Battery Supply and Buck-Boost With Smart
Capabilities to Maximize System Energy
Management
I2C/SPI
GPIO2
CE
PWR_LDO2
VMICRO
I2C/SPI
GPIO2
I2C/SPI
GPIO1
Zero Leak Adjustable Bias
TPS65290ZB
I2C/SPI
Low IQQ ldo
TPS65290LM
I2C/SPI
I2C/SPI
Buck Mini
TPS65290BM
•
Low Power Always-On Bias Supply for
Microcontroller Sleep Mode With Three
Factory Selectable Options:
Vin
PWR_VIN
I2C/SPI
CHIP_EN*
2.5-3.6
INT management
INT
–
10-mA, 100-nA IDDQ Deep Sleep Zero
Leakage Current Bias Controller With Pre-
Set Voltage
Control options
I2C
SPI
Serial Interface
GPIO control
GPIO1,2,3,4
Always on
–
–
10-mA, 400-nA IDDQ LDOMINI
30-mA, 300-nA IDQQ BuckMINI
DESCRIPTION
TPS65290 is a PMIC designed to operate in applications dependent on efficient power management over a wide
range of system load conditions ranging from fractions of a microamp to a few hundred miliamps. The device
operates over a wide 2.2-V to 5-V input-voltage range and incorporates a very low quiescent current always-on
power supply, a 500-mA buck/boost converter, a 150-mA low dropout regulator and 8 power distribution
switches. The always-on supply features three different factory selectable options: 30mA buck converter with
300-nA quiescent current. 10-mA LDO with 400-nA quiescent current and 10-mA Zero IDDQ drop with 100-nA
quiescent current. The buck-boost converter employs PFM/PWM operation with forced PWM option, for
maximum overall efficiency. The switches can be used to support different configurations for the various loads
supported by the TPS65290. For energy harvesting applications, a programmable input voltage monitor is
integrated to allow for connection and disconnection of the different power blocks and switches without the
intervention of the master processor.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65290
SLVSBY5B –APRIL 2013–REVISED JUNE 2013
www.ti.com
DESCRIPTION (CONTINUED)
To maximize control flexibility, the TPS65290 includes a factory-selectable choice between SPI and I2C
interfaces. To minimize PC board footprint and reduce bill of materials (BOM) components and cost, the PMIC
internally includes resistive dividers (boost/buck, LDO, VIN monitor); I2C pull-up resistors; SPI pull-down resistors;
boost/buck compensation; and interrupt pull-up resistor. Only low-cost ceramic capacitors and power inductors
are needed to complete a comprehensive multi-rail solution for efficient flow meter, handheld industrial, fitness
and other long-term data-acquisition systems.
ORDERING INFORMATION
DEVICE
FEATURES
MARKING
PART NUMBER
ZERO
LEAK
TPS65290
LDOMINI
BUCKMINI
SPI
I2C
GPIO
TPS65290ZBRHFR
reel of 3000
reel of 250
reel of 3000
reel of 250
reel of 3000
reel of 250
with zero bias
IDQQ
TPS65290ZB
TPS65290LM
TPS65290BM
√
√
TPS65290ZBRHFT
TPS65290LMRHFR
TPS65290LMRHFT
TPS65290BMRHFR
TPS65290BMRHFT
with LDOMINI
with buckMINI
√
√
√
√
2
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
OUT
Host
INT
PWR_BB2
CE
Host
Host
MISO
CS
VMICRO
AGND
OUT
OUT
Host
Host
Host
TPS65290
SCL/SCK
MOSI/SDA
PWR_LDO2
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
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TYPICAL FLOW METER APPLICATION
PA
DRV8833
Stepper
controller
Host
INT
PWR_BB2
LDO_EN
VMICRO
Host
MISO
CS
Host
MSP430
TPS65290
SCL/SCK
Host
AGND
MOSI/SDA
Host
PWR_LDO2
CC1120
TLV 2404
Ultrasound
Ultrasound
Temp Pressure
Analog
front-end
circuitry
LCD
4
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
FUNCTION BLOCK DIAGRAM
10µF
BB_VIN
VIN
BB_OUT
100nF
BB_LX1
BB_LX2
3.3µH
GPIO
10,000uF
DSC
VMICRO
0.1µF
PWR_BB1
0.1Ω BB=4.5V
PWR_BB1
BB_EN
10MΩ
BUCK BOOST (BB)
PWR_AUX1_BB
0.6Ω BB=4.5V
PWR_VMAX
VMAX
X
Y
VMAX
MAX
0.1µF
PWR_BB2
0.6Ω
0.1µF
PWR_BB2
PWR_BB_LDO
1Ω
DSC
LDO
2.2µF
1µF
LDO_OUT
LDO_IN
Buck mini
1µF
PWR_LDO1
0.3Ω VLDO=2.8V
VMICRO
PWR_LDO1
CE
GPIO
PMIC ENABLE
10MΩ
CHIP_EN*
PWR_LDO2
0.6Ω VLDO=2.8V
0.1µF
VIN
VIN
Deep sleep control
(DSC)
PWR_LDO2
VMICRO
VIN
If buck mini is enabled
Do not fit cap
Fit inductor
10kΩ
10kΩ
PWR_MICRO_LDO
0.6Ω VLDO=2.8V
2.5-3.6
CHIP_EN
*I2C MODE
3.3µH
Recovery
comparator
CS
1µF
100kΩ
VMICRO
DSC
Zero Bias
VIN
SCL/SCK
State Machine
100kΩ
Serial
Interface
SPI/I2C
Low Iqq LDO
LDO_IN
VIN
MOSI/SDA
HOST
100kΩ
PWR_VIN
MISO
INT
DSC
PWR_Vin
1Ω VIN=3.6V
100kΩ
1µF
INT MANAGEMENT
PGND
AGND
*I2C MODE = Factory configured
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
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FUNCTIONALITY
POWER SAVING OPTIONS
BLOCK
Reg
[0]
Bit
[0]
Reg
Bit
Enable
Set voltage
PFM/PWM mode
[3]
[6]
Buck boost
[3]
[0,5]
[5]
UVLO disable
Enable
[3]
[0]
[1]
LDO
Set voltage
[4]
[0,4]
Zero drop, LDOMINI
BUCKMINI
,
Set voltage
[2]
[2]
[0,3]
[5,4]
BUCKMINI low and high
current mode
Operation Mode
Low current mode (for standby operation)
See VMAX options section
[2]
[8]
[5,4]
[0]
Latch on turn-off
Turn-on options
Set falling voltage
Set rising voltage
[3]
[6]
[6]
[6]
[0]
[7]
[7]
[7]
[6,7]
[5,3]
[0,2]
[2,7]
[1]
MAX
Recovery comparator
Enable/Disable
Enable/disable pull-down
Fast/slow turn-on
[5]
[5]
[1,7]
[0]
Enable (BB, LDO, BAT, VMAX
)
Power switches
Enable (PWR_BB_LDO)
INT status and masking
[0]
Interruption
management (INT)
Power switches automatic disable when INT
asserted
[7]
[2,7]
[8]
[4]
[1,7]
[5]
Bandgap
Enable/disable
6
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
PIN OUT
RGE PACKAGE
(TOP VIEW)
19
18
17
16
15
14
13
INT
MISO
20
21
22
23
24
12
11
10
9
PWR_BB2
CE
CS
VMICRO
AGND
RHF 24 PIN
SCL/SCK
MOSI/SDA
8
PWR_LDO2
1
2
3
4
5
6
7
TERMINAL FUNCTIONS
NAME
PWR_VIN
VIN
NO.
1
I/O
O
I
DESCRIPTION
Power for system output from Vin
Battery supply
2
PWR_VMAX
VMAX
3
O
O
I
Switch Controlled supply connected to VMAX. Decouple with a ceramic capacitor
This pin shows the maximum of VBAT or VBB. Decouple with a 1µF ceramic capacitor
LDO input. Decouple this pin with a 2.2µF ceramic capacitor
4
LDO_IN
LDO_OUT
PWR_LDO1
PWR_LDO2
AGND
5
6
O
O
O
LDO output. Decouple this pin with a 2µF ceramic capacitor
7
Switch Controlled supply connected to LDO output. Decouple with a ceramic capacitor.
Switch Controlled supply connected to LDO output. Decouple with a ceramic capacitor.
Analog ground connection. Connect to PGND and power Pad.
Microcontroller supply
8
9
VMICRO
CE
10
11
O
I
When low the PMIC is in deep sleep and BIAS supply to the micro is enabled. The Interrupt output is
disabled with a pull down termination. When high, the I2C/SPI is active; the internal switches can be
operated, along with the interrupt logic, and Boost/Buck.
PWR_BB2
BB_EN
PWR_BB1
BB_OUT
BB_LX2
PGND
12
13
14
15
16
17
18
19
20
21
22
23
24
O
I
Switch Controlled supply connected to BB output. Decouple with a 1µF ceramic capacitor.
Buck-Boost converter enable pin
O
O
O
Switch Controlled supply connected to BB output. Decouple with a 1µF ceramic capacitor.
Buck-Boost converter output
Buck-boost Boost converter switching node
Power ground connection. Connect to AGND and power pad.
Buck-boost Boost converter switching node
BB_LX1
BB_VIN
INT
O
I
Input pin to Buck-Boost converter
O
O
I
Push-pull output, asserted when low
MISO
Serial Data Transmit interface (Master Input Slave Output)
SPI bus Chip Select (active high) when SPI enabled
Serial Data Clock (SPI and I2C)
CS
SCL/ SCK
MOSI/SDA
I
I
Serial Data Receive interface (Master Output Slave Input) for SPI and I2C
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TERMINAL FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
POWER PAD
Connect the pad to AGND, PGND and PCB GND. Thermal pad does not have electrical connections to
IC.
OUTPUTS AND OPERATIONAL RANGE
TYPE
VOUT (V)
DEFAULT
IO MAX
(mA)
SET ACCURACY
FEATURES
Buck Boost
1.0-5V, ~200mV steps
4.06V
2.8V
500
150
3%
4%
0.8V for external divider 1.0-4.0V,~
100mV steps
LDO
0.6-2.0V Selective drop from battery
voltage, 8 steps adjustment
Vin-1.4
10
10% at 25°C
No IDQQ
Low bias supply
1.8-3.3 V 200mV steps
1.8-3.3V 200mV steps
PWR_BB1
2.2V
2.2V
10
30
5%
Low Iqq LDO
Low Iqq Buck
5%
800
350
100 mΩ switch
600 mΩ switch,
Power switches powered
from BB output
1kΩ pull-down Single P
mosfet
Disabled
Disabled
Disabled
PWR_BB2
Power switches powered
from VMAX
1kΩ pull-down Single P
mosfet
PWR_VMAX
250
600 mΩ switch,
600 mΩ switch,
PWR_LDO2
250
NA
1kΩ pull-down Single P
mosfet
Power switches powered
from LDO output
PWR_MICRO_LDO
1kΩ pull-down Single P
mosfet
PWR_LDO1
PWR_BB_LDO
PWR_Vin
Disabled
Disabled
Disabled
250
250
100
300 mΩ
1.0 Ω
Power switch connecting
output of BB to LDO
1kΩ pull-down Back to back
P mosfets
Power switch powered
from battery
1kΩ pull-down Single P
mosfet
1.0 Ω
1.7-2.4V 100mV steps falling edge
2.4-3.1V 100mV steps rising edge
2.0V
2.4V
Recovery comparator
NA
3%
NA
Configurable for turn-on and
turn-off operation
MAX (Analog multiplexer) Highest of BB and LDO
INT (maskable)
NA
150
All switches disabled
by interruption
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
BB_VIN, BB_OUT, BB_FB, LDO_IN, PWR_BB2. PWR_VMAX
–0.3 to 7
–1 to 7
V
V
BB_LX1, BB_LX2
Any other pin
–0.3 to 5.5
–0.3 to 0.3
–40 to 125
–55 to 150
V
AGND, PGND
V
TJ
Operating junction temperature range
Storage temperature range
°C
°C
TSTG
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
BB_VIN,
VBAT
Input operating voltage BOOST CONVERTER
1.8
3.6
5
V
LDO_VIN
TA
Input operating voltage LDO (VOUT = 2.8V)
Ambient temperature
3
5
V
–40
125
°C
8
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
ELECTROSTATIC DISCHARGE (ESD) PROTECTION(1)
MIN
2000
500
MAX
UNIT
V
Human body model (HBM)
Charge device model (CDM)
V
(1) SW_OUT1/2 pins’ human body model (HBM) ESD protection rating 4 kV, and machine model (MM) rating 200V.
DISSIPATION RATINGS
TA = 25°C
Power Rating (W)
TA = 85°C
Power Rating (W)
PACKAGE
θJC (°C/W)
θJA (°C/W)
RHF
29
30.6
3.26
1.30
ELECTRICAL CHARACTERISTICS
TJ = -40°C to 125°C, VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY
Input voltage range for all blocks to be
operational
VBAT
2.2
5
V
Zero bias mode
100
400
300
5
LDOMINI mode
Quiescent current always on blocks
Factory configured
BUCKMINI mode
IDDQ
nA
CHIP_EN=0
VIN = 3.6V LDO enabled
VIN = 3.6V, BB enabled VBB_OUT = 4.5V
PFM mode
40
RECOVERY VOLTAGE COMPARATOR
Rising VIN 8 steps 0.1V threshold
Falling VIN 8 steps 0.1V threshold
2.4
1.7
3.1
2.4
Threshold voltage serial interface
selectable
COMPRVLEVEL
COMPRVACCURACY
IQQCOMPRV
V
%
Comparator accuracy
3
10
10
Buck boost enabled
Buck boost disabled
µA
ENABLE PINS (CE, BB_EN)
VH
Enable high
VMICRO = 2.2 TO 2.8V
VMICRO = 2.2 TO 2.8V
1.2
1.8
V
V
VL
Enable Low
0.4
5
BUCK-BOOST (BB)
VIN
Input voltage range
V
V
Start-up voltage, no load VBB<4.5
Start-up voltage, no load VBB>4.5
-40°C ≤ TA ≤ 85°C
-40°C ≤ TA ≤ 85°C
1.8
2.5
VINSTART_UP
The minimum input voltage in which the
buck-boost converter sustains it’s
operation after starting up
(1)
VINSUSTAIN
-40°C ≤ TA ≤ 85°C
1.8
V
DC output accuracy (PWM mode)
Maximum line regulation
TJ = 25°C
-3
1
3
VBB
VIN = 3 to 3.6V IOUT = 300mA
IO = 100 to 500mA
0.5
0.5
%
Maximum load regulation
VBBOUTRANGE
29 steps 0.1V from 1 to 5V
5
V
f
Oscillator frequency
1600
25
kHz
%
DUTYBUCK_MIN
Minimum duty cycle in buck mode
Average high side switch current limit
High side switch on resistance
Low side switch on resistance
Startup time
30
VIN = 3.6 V, TA = 25°C
2400
120
120
500
mA
mΩ
mΩ
µs
ISW
VIN = 3.6 V, TA = 25°C
VIN = 3.6 V, TA = 25°C
tSTR_BB
IOUT = 150mA, COUT = 2X 4.7µF, VOUT = 4.0V
LDO
VLDO_IN
Input voltage range
Full load operation
2.2
1
5
4
V
V
VLDO_OUT_RANGE
32 steps 0.1V from 1 to 4V
(1) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = -40°C to 125°C, VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 3.6V, VOUT = 2.8V, TJ = -40°C to 125°C
ILoad = 5mA
VLDO_OUT_ACCURACY
DC output accuracy
-4
4
%
LDOLINE_REG
LDOLOAD_REG
Line regulation
Load regulation
3.3V ≤ VIN ≤ 6V, VOUT = 2.8V, IOUT = 5mA
VIN = 2.2~5V, 0 ≤ IOUT ≤ 110mA
-1
-2
1
2
%
%
Dropout voltage- allow for 5% output
voltage droop
VDROOP
VIN = 3.6~6V, 0 ≤ IOUT ≤ 150mA
300
mV
ICL
Output current limit
VLDO_OUT = 2.8V, output voltage shorted
VLDO_OUT = 2.8V, VIN = 3.1V, 150mA loading
COUT = 2.2µF, VOUT = 2.8V, no load
300
28
mA
dB
µS
PSRR
tSTRLDO
Power-supply rejection ratio 10 kHz
Startup time, bandgap already enabled
200
MICRO BIAS CIRCUIT (Different options)
Zero Leak Adjustable Bias (TPS65290ZB)
VIN
Input voltage range
2.2
5
V
V
VMICRO_MIN
Minimum output voltage
1.3
Voltage difference between VBAT (pin#4)
and Vmicro
VBIAS_DROP
VOUT
9 200mV drop steps from 0.6 to 2V
TJ = +25°C, IOUT = 1µA, BAT=3.6V
0.6
-10
2.0
10
15
V
%
%
DC output accuracy measured by
VBIAS_DROP
.
IOUT = 100nA-10mA , TJ = +25°C, BAT = 3.6V,
VMICRO[3:0] = 0000
ZEROLOAD_REG
Load regulation
Low IDDQ LDO, aka LDOMINI (TPS65290LM)
VIN
Input voltage range
2.2
1.8
-5
5
3.3
5
V
V
VLDO_RANGE
VOUT
16 steps 0.2V from 1.8 to 3.3V
TJ = +25°C, VIN = 3.6V, IOUT = 1µA
1µA ≤ IOUT ≤ 10mA
DC output accuracy
%
%
LDOLOAD_REG
Load regulation
-5
5
Dropout voltage– allow for 5% output
VDROOP
ICL
VOUT = 2.2V, IOUT = 10mA
VLDO_OUT = 2.8V
300
50
mV
mA
voltage drop at VDROOP
.
Output current limit
20
BUCKMINI Internal Converter Hysteretic (TPS65290BM)
VIN_BM
Input voltage range
Output load range
2.2
0
5
V
ILoad_BM
30
mA
LBM = 33µH, CBM = 1µF, ESR_CBM = 1Ω,
No load
(2)
FSW_BM
BuckMINI switching frequency
Peak inductor current
5
Hz
TJ = +25°C , LBM = 33µH, CBM = 1µF,
ESR_CBM = 1Ω, VIN = 3.6V, VOUT = 2.5V,
IOUT = 30mA with high-power mode
(2)
IPK_IND
80
mA
TJ = +25°C , LBM = 33µH, CBM = 1µF,
ESR_CBM = 1Ω, VIN = 3.6V, VOUT = 2.5V,
IOUT = 30mA with high-power mode
(2)
IPK_IND_STARTUP
Peak inductor current during start up
Ripple voltage
140
5
mA
%
TJ = +25°C , VIN = 3.6V, VOUT = 2.5V),
LBM = 33µH, CBM = 1µF, ESR_CBM = 1Ω,
(2)
VBM_RIPPLE
POWER SWITCHES
Distribution switch on resistance from
BB_OUT to pin PWR_BB1 (Single P
Mosfet)
PWR_BB1
VIN = 3.6 V, VBB = 4.5 V, TA = 25°C
VIN = 3.6 V, VBB = 4.5 V, TA = 25°C
VIN = 3.6 V, VBB = 4.5 V, TA = 25°C
VIN = 3.6 V, VLDO = 2.8 V, TA = 25°C
VIN = 3.6 V, VLDO = 2.8 V, TA = 25°C
100
600
600
300
600
mΩ
mΩ
mΩ
mΩ
mΩ
Distribution switch on resistance from
VMAX to pin PWR_VMAX (Single P
Mosfet)
PWR_VMAX_
VMAX
Distribution switch on resistance from
BB_OUT to pin PWR_BB2 (Single P
Mosfet)
PWR_BB2
Distribution switch on resistance from
LDO_OUT to pin PWR_LDO1 (Single P
Mosfet)
PWR_LDO1
PWR_LDO2
Distribution switch on resistance from
LDO_OUT to pin PWR_LDO2 (Single P
Mosfet)
(2) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = -40°C to 125°C, VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Distribution switch on resistance from
PWR_MICRO_
LDO
LDO_OUT to pin VMICRO (Single P
Mosfet)
VIN = 3.6 V, VLDO = 2.8 V, TA = 25°C
VIN = 3.6 V, TA = 25°C
600
mΩ
Distribution switch on resistance from VIN
to pin PWR_VIN (Single P Mosfet)
PWR_VIN
1000
1000
1.2
mΩ
mΩ
kΩ
Distribution switch on resistance (internal
use only) from BB_OUT to LDO_OUT pin
(Back to back P Mosfet)
PWR_BB_LDO
RPULLDOWN
VIN = 3.6 V, VBB = 4.5 V, TA = 25°C
Pull-down resistance (Connection
selectable by EEPROM bit)
LOGIC LEVEL OUTPUTS (INT, MISO)
VOL
VOH
Output level low
Output level high
VMICRO = 2.2 to 2.8V , Iload = 1mA
VMICRO =2.2 to 2.8V , Iload = 1mA
0.4
V
V
VMICRO
-
0.4
LOGIC LEVEL INPUT (CS, MOSI, CLK, SDA SCK )
0.67 *
VMICRO
VH
Input high level
VMICRO = 2.2 to 2.8V
VMICRO = 2.2 to 2.8V
V
0.33 *
VMICRO
VL
Input low level
V
VHYS
RPULLUP
Input hysteresis
10
mV
kΩ
Pull-up resistor to VMICRO
When I2C mode enabled
10
Pull-down resistor to GND
When SPI mode enabled
RPULLDOWN
100
kΩ
THERMAL SHUT-DOWN FOR BUCK BOOST CIRCUIT
TTRIP_BB
141
12
°C
°C
THYST_BB
CENTRAL THERMAL SHUTDOWN
TTRIP_IC
THYST_IC
Thermal protection trip point
Thermal protection hysteresis
Rising temperature
160
20
°C
°C
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TYPICAL CHARACTERISTICS (BUCK BOOST)
TJ = 25°C (unless otherwise noted)
Figure 1. Buck Boost Startup Waveform with I2C Command
Ch1: BB output. Ch2: I2C SCLK turns on buck-boost, Ch3:
VMICRO. Startup time is 330µs. Buck Boost L and C are per
application circuit.
Figure 2. Buck Boost Startup Waveform with BB_EN Pin
Command
Ch2: BB output. Ch1: BB_EN signal. Ch3: VMICRO. Startup
time is 330µs. Buck Boost L and C are per application
circuit.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0
50
100 150 200 250 300 350 400 450 500
Io (mA)
Figure 3. Buck Boost Line Regulation, Boost Mode
Figure 4. Buck Boost Efficiency VIN = 3.6V, VO = 4.5V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0
50
100 150 200 250 300 350 400 450 500
0
50
100
150
200
250
300
350
400
450
Io(mA)
Io(mA)
Figure 5. Buck Boost Efficiency VIN = 2.5V, VO = 4.5V
Figure 6. Buck Boost Efficiency VIN = 3.6V, VO = 2.8V
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TYPICAL CHARACTERISTICS (BUCK BOOST) (continued)
TJ = 25°C (unless otherwise noted)
LoadRegulationVin=3.6V, Vo=4.5V PFM mode
LoadRegulationVin=3.6V, Vo=2.8V PFM mode
4.50
4.48
4.46
4.44
4.42
4.40
4.38
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
0
50
100 150 200 250 300 350 400 450 500
0
50
100 150 200 250 300 350 400 450 500
Io (mA)
Io (mA)
Figure 7. Buck Boost Load Regulation
Figure 8. Buck Boost Load Regulation
Buck Boost Loading 85°C Ambient VBB < 4.5V
Figure 9. Buck Boost Loading
25°C Ambient VBB < 4.5V
Figure 10. Buck Boost Loading
-40°C Ambient VBB < 4.5V
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TYPICAL CHARACTERISTICS (BUCK BOOST) (continued)
TJ = 25°C (unless otherwise noted)
600
500
400
300
200
100
0
2.2 2.5 3.0 3.6 4.0 4.5 5.0
Vin(V)
Figure 11. Buck Boost Loading
-10°C Ambient VBB < 4.5V
Figure 12. Buck Boost Loading
25°C Ambient VBB > 4.5V
600
500
400
300
200
100
0
600
400
200
0
2.2 2.5 3.0 3.6 4.0 4.5 5.0
200 200 300 400 400 200 500
Vin(V)
loading
2.2
2.5
3.0
3.6
4.0
4.5
5.0
Vin(V)
Figure 13. Buck Boost Loading
85°C Ambient VBB > 4.5V
Figure 14. Buck Boost Loading
-10°C Ambient VBB > 4.5V
600
500
400
300
200
100
0
2.2
2.5
3.0
3.6
Vin(V)
4.0
4.5
5.0
Figure 15. Buck Boost Loading
-40°C Ambient VBB > 4.5V
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
TYPICAL CHARACTERISTICS (LDO)
TJ = 25°C (unless otherwise noted)
Figure 16.
Figure 17.
Line Regulation Vo=2.8V, Io=5mA
2.85
2.84
2.83
2.82
2.81
2.8
2.79
2.78
2.77
2.76
2.75
3
3.5
4
4.5
5
5.5
6
6.5
Vin(V)
Figure 18.
Figure 19.
Figure 20. LDO Startup Waveform with I2C Command
Ch1: LDO output. Ch 2: I2C SCLK, Ch3: VMICRO, Ch4: VIN
current. Startup time is about 200µs.
Figure 21. LDO Load Transient Response (0 to 150mA)
Ch1: LDO output (10mV/div). Ch4 Load current (20mA/div).
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TYPICAL CHARACTERISTICS (LDO) (continued)
TJ = 25°C (unless otherwise noted)
Figure 22. LDO Input to Output Voltage
Ch1: LDO output. Ch 2: LDO input, Ch3: Ch4: LDO current
Figure 23. LDO PSRR(dB), 10 to 100kHz LDO output = 2.8V,
LDO input = 3.1V, 150mA loading.
Figure 24.
TYPICAL CHARACTERISTICS (LDOMINI
)
TJ = 25°C (unless otherwise noted)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (LDOMINI) (continued)
TJ = 25°C (unless otherwise noted)
Figure 27.
Figure 28. LDOMINI Load Transient Response (0 to 10mA)
Ch1: VBAT, Ch3: VMICRO (LDOMINI output) (100mV/div).
Ch4 Load current (10mA/div).
Line RegulationVo=2.2V, no load
2.255
2.250
2.245
2.240
2.235
2.230
2.225
2.220
3
3.5
4
4.5
5
5.5
6
6.5
Vin(V)
Figure 29. LDOMINI Startup Waveform with VIN Rising
Input battery connected to 27Ω resistor and 1000µF
capacitor Ch1: VBAT rising. Ch 3: VMICRO (LDOMINI output)
Figure 30.
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TYPICAL CHARACTERISTICS (ZERO IDQQ)
TJ = 25°C (unless otherwise noted)
Figure 31.
Figure 32. ZEROiddq Load Transient Response (0 to 10mA)
Code 4, 1.4V drop. Ch1: VBAT, Ch3: VMICRO (LDOMINI
output) (100mV/div). Ch4 Load current (10mA/div).
Figure 33. ZEROiddq Startup Waveform with VIN Rising
Code 4, 1.4V drop Ch2: VBAT rising. Ch 3: VMICRO
(ZEROIDDQ output)
Figure 34.
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
TYPICAL CHARACTERISTICS (BUCKMINI
)
TJ = 25°C (unless otherwise noted)
Figure 35. BUCKMINI Efficiency
CO = 1µF, ESR = 1Ω, L = 33µF Automatic Mode
Figure 36. BUCKMINI Efficiency
CO = 100µF, L = 33µF Automatic Mode
Figure 37. BUCKMINI Transient Response
VIN = 3.6V, VO = 2.5V 0-50mA Step
Figure 38. BUCKMINI Output Ripple
VIN = 3.6V, VO = 2.5V, IO = 50mA
Load Regulation BuckMini Vin=3.6V
2.34
2.32
2.30
2.28
2.26
2.24
2.22
2.20
2.18
2.16
0
10
20
30
40
50
60
Io(mA)
Figure 39. BUCKMINI Output Ripple
VIN = 3.6V, VO = 2.5V, IO = 50mA
Figure 40. BUCKMINI Output Ripple
VIN = 3.6V, VO = 2.5V, IO = 50mA
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TYPICAL CHARACTERISTICS (BUCKMINI) (continued)
TJ = 25°C (unless otherwise noted)
BUCKmini Output Ripple when Vout=2.5V, Vin=3.6V for
Low- and High-Power Mode
BUCKmini Efficiency
when Vout=2.5V,
Vin=3.6V for
800
700
600
500
400
300
200
100
0
100.00%
50.00%
0.00%
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02 1.00E-01
Load Current (A)
Low-Power ModeVpk-pk
High-Power ModeVpk-pk
Load Current (A)
Figure 41.
Figure 42.
BUCKmini Switching
Frequency when
Buck Mini IDDQ -
40°C
Vout=2.5V, Vin=3.6V for
Low - and High - Power
1000000
0.5
0.45
0.4
0.35
0.3
10000
0.25
0.2
0.15
0.1
100
2
3
4
5
Vin
2.2
1
1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02 1.00E-01
1.8
3.3
Load Current (A)
Figure 43.
Figure 44.
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
TYPICAL CHARACTERISTICS (BUCKMINI) (continued)
TJ = 25°C (unless otherwise noted)
Buck Mini IDDQ 85°C
Buck Mini IDDQ 25°C
0.5
0.5
0.45
0.4
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
2
3
4
5
2
3
4
5
Vin
2.2
Vin
2.2
1.8
3.3
1.8
3.3
Figure 45.
Figure 46.
TYPICAL CHARACTERISTICS (VMAX)
TJ = 25°C (unless otherwise noted)
Figure 47. Typical VMAX Waveforms. Rising BB output.
Figure 48. VMAX waveform. Falling BB output. Switch
configured for VMAX = MAX(VBAT,VBBout) when BB output
is disabled.
Figure 49. VMAX waveform. Falling BB output. Switch
configured for VMAX = VBAT when BB output is disabled.
Figure 50. VMAX waveform. Falling BB output. Switch
configured for VMAX = MAX(VBAT,VBBout)-diode when BB
output is disabled. Note: VMAX is not loaded.
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TYPICAL CHARACTERISTICS (VMAX) (continued)
TJ = 25°C (unless otherwise noted)
Figure 51. VMAX waveform. Falling BB output. Switch is configured for VMAX = MAX(VBAT,BBout). The VMAX comparator
turns off automatically when BBout falls below VBAT at BB turn off.
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
CHOICE OF TPS65290 VERSION AND SERIAL INTERFACE
Once a voltage higher than 2.2V is applied to the VIN the always on supply will start as per the factory default
setting. This will be the only block available within the device and will always stay on as long as the input supply
does not drop beyond 2.2V.
There are 3 possible choices of always on supply. The main parameter for choice is the “efficiency” of the supply
during sleep mode, mostly processor current.
VIN
BB_OUT
I2C/SPI
Buck boost
EN BB
PWR_BB1
I2C/SPI
GPIO3
VMAX
PWR_VMAX
I2C/SPI
GPIO3
MAX
PWR_BB2
I2C/SPI
GPIO4
VMAX
I2C/SPI
LDO_IN
LDO_OUT
LDO
PWR_LDO1
I2C/SPI
I2C/SPI
GPIO2
CE
PWR_LDO2
VMICRO
I2C/SPI
GPIO2
I2C/SPI
GPIO1
Zero Leak Adjustable Bias
TPS65290ZB
I2C/SPI
Low IQQ ldo
TPS65290LM
I2C/SPI
I2C/SPI
Buck Mini
TPS65290BM
Vin
PWR_VIN
I2C/SPI
CHIP_EN*
2.5-3.6
INT management
INT
Control options
I2C
SPI
Serial Interface
GPIO control
GPIO1,2,3,4
Always on
Figure 52.
Zero Bias set to VIN-1.4
•
•
•
•
•
Takes the least amount of quiescent current
Provides voltage drops from 0.6 to 2V in 200mV steps
Is not a regulated output
Can be programmed to zero drop or to open circuit
10mA max
LDOMINI set to 2.2V
•
•
•
Provides a regulated output
Can be programmed from 1.8 to 3.3V in 100mV steps
10mA max
BUCKMINI set to 2.2V
•
•
•
•
•
Provides a regulated output
Can be programmed from 1.8 to 3.3V in 100mV steps
30mA max
Output has a ripple content
Requires additional inductor (0603) and resistor (0402) PWR_AUX2 switch is disabled (pin becomes
switching node)
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The chosen serial interface for the part is SPI as I2C lines are open drain lines with internal 20kΩ pull-up
resistors that guarantees 400kHz operation, but also create power losses when any of the bus lines are low. It is
expected that operation with SPI will produce less average current consumption when compared to I2C. For
I2C/GPIO operation please check with the factory.
FACTORY PROGRAMMED SETTINGS
The following blocks are programmed in the factory.
Buck boost
•
•
•
•
•
•
•
Can be enabled or disabled when IC is enabled (can also be enabled with pin 15 high)
Voltage can be set to
1.0 to 3.4V, 200mV steps
3.5 to 4.7V, 100mVsteps
4.9V, 5.0V
Forced PWM or PFM (low power mode)
Input UVLO comparator enabled/disabled. If disabled BB will try to operate with any input voltage higher than
1.8V LDO
•
•
Can be disabled or enabled when IC is enabled
Output voltage can be set to 1 to 4.0V, 100mV steps
Recovery comparator
•
•
•
Can be enabled or disabled when IC is enabled
Falling edge can be set to 1.7 to 2.4V, 100mV. An interruption is generated.
Rising edge can be set to 2.4 to 3.1V, 100mV. The interruption is released.
Power switches
•
•
•
•
Can be enabled or disabled when IC is enabled
Pull-down resistance can be connected or disconnected when IC is enabled
Power switches can be disabled when an Interruption is generated
Switches can be turned on at slow or fast speed
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
USING THE TPS65290
Power UP and Enabling the IC
There are two ways of enabling the PMIC by setting the CE or BB_EN pins. If CE IS disabled only the always on
blocks (as per default) and pull-down resistors are enabled by default.
VMICRO
BB_EN
GPIO
BUCK-BOOST
10MΩ
VMICRO
CE
GPIO
PMIC ENABLE
10MΩ
Figure 53. Power UP and Enabling the IC
When CE and BB_EN are low the PMIC is in deep sleep and bias supply to the micro is enabled. When high, the
I2C/SPI is active; the internal switches can be operated, along with the interrupt logic, and Boost/Buck. The Buck
boost is enabled either by BB_EN (high) or EN_BB bit (1). BB_EN can be used to enable the buck boost
converter without need of the serial interface.
With the serial interface ACTIVE it is possible to enable, disable AND change settings for the power blocks. All
changes on registers will be kept as long as the input supply is higher than 1.8V. If power is recycled the
registers will be re-loaded with the programmed factory defaults.
Band-Gap Enable (Non EEPROM Setting)
The LDO bandgap is normally disabled to reduce consumption and it is enabled when either of the of LDO,
LDOMINI or BUCKMINI blocks are enabled. However, to speed up the power-up timing of the LDO it can be
enabled in advance (register 4, bit 5)
BUCKMINI operation (Non EEPROM setting)
LDO_VOUT
SWITCH_AUX2
LDO_VIN
AUX2
LDO_VIN
VMICRO
Figure 54.
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BUCKMINI is a hysteretic buck converter that can deliver up to 30mA and therefore can be used beyond the sleep
mode operation of the micro. When using this block is important to keep the following in mind:
•
•
AUX2 output is not available as this pin is used to connect the external inductor required by the converter.
If VMICRO has a ceramic capacitor, it is recommend to add a small resistor (0.5 to 1Ω) to guarantee a fixed
ripple value at the output.
•
•
BUCKMINI does not feature a current limit circuit. Overcurrent protection (if needed) needs to be provided
externally.
When used to support loads between 100µA to 1mA there is trade-off between input quiescent current and
output ripple. It is suggested to use the settings for low and high power mode (Register 2, Bits [5,4]) to
determine which power mode is most suitable for the application. Plots on the characteristics section show
the typical trade-off between efficiency and ripple.
•
•
BUCKMINI starts at automatic power selection mode. If loading higher than 100µA-1mA is required, set the
BUCKMINI setting to (Register 2, Bits [5,4]) [11] to reduce ripple.
Once the loading is removed, set (Register 2, Bits [5,4]) [10] to reduce power consumption
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BUCK-BOOST OPERATION
Inductor Selection
To estimate the inductance of the buck-boost converter the following equations can be used:
L1 = (VIN_MAX - VOUT) x 0.5 x (µs/A)
L2 = VOUT x 0.5 x (µs/A)
(1)
(2)
L1 is used for step down mode operation . VIN is the maximum input voltage. L2 is used for boost mode
operation is calculated. The recommended minimum inductor value is either L1 or L2 whichever is higher. As an
example, a suitable inductor for generating 3.3V from a Li-ion battery with a battery voltage range from 2.5V up
to 4.2V is 2.2µH. The recommended inductor range is between 1.5µH and 4.7µH. In general, this means that at
high voltage conversion rates, higher inductor values offer better performance.
The table below shows the recommended inductance for input and output voltage combinations. The highest
inductance among the region of interest is recommended.
Figure 55. Recommended Inductance for Input and Output Voltage Combination (µH)
With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated.
Equation 3 shows how to calculate the peak current I1 in step down mode operation and Equation 4 show how to
calculate the peak current I2 in boost mode operation.
VOUT (VIN_MAX - VOUT
2 · VOUT · f · L
)
IOUT
0.8
I1 =
+
(3)
V
IN_MIN (VOUT - VIN_MIN
2 · VOUT · f · L
)
VOUT · IOUT
0.8 · VIN_MIN
I2 =
+
(4)
In both equations f is the switching frequency. The critical current value for selecting the right inductor is the
higher value of I1 and I2. It also needs to be taken into account that load transient and error conditions may
cause higher inductor currents. This also needs to be taken into account when selecting an appropriate inductor.
The table below shows the recommended inductor current rating for input and output voltage combinations with
assumption of 1.6MHz switching frequency, 500mA loading, 3.3µH inductance. The highest current rating among
the region of interest is recommended.
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Figure 56. Recommended Inductor Current Rating for Input and Output Voltage Combination with 3.3µH
Inductor, 1.6MHz Switching Frequency and 500mA load (A)
Buck-Boost Input Capacitor Selection
A 10µF ceramic capacitor is recommended to improve transient behavior of the regulator and EMI behavior of
the total power supply circuit. A ceramic capacitor placed as close as possible to the buck-boost input pin and
power ground of the IC is recommended.
Battery Input Pin Capacitor Selection
To make sure that the internal control circuits are supplied with a stable low noise supply voltage, a capacitor can
be connected between VIN and AGND. Using a ceramic capacitor with a value of 0.1µF is recommended. The
value of this capacitor should not be higher than 0. 22µF
Buck-Boost Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
BB_OUT and PGND. If, for any reason, the application requires the use of large capacitors which can not be
placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended. This small
capacitor should be placed as close as possible to the BB_OUT and PGND pins of the IC.
To get an estimate of the recommended minimum output capacitance, the following equation can be used.
(5)
A capacitor with a value in the range of the calculated minimum should be used. There are no additional
requirements regarding minimum ESR. There is also no upper limit for the output capacitor value. Larger
capacitors will cause lower output voltage ripple as well as lower output voltage drop during load transients.
Setting VMAX (Non EEPROM Setting)
The operation of VMAX is not set on EEPROM and the switches inside the block can be programmed for specific
conditions such as diode drops, To connect to VBAT, To follow the maximum voltage with its logic enabled or to
follow the maximum voltage and to connect to VBAT when VBB is lower than VBAT and to disconnect the VMAX
logic. The following table shows the options available.
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Table 1. Setting VMAX (Non EEPROM Setting)
REG6_BIT6
VMAXx_DIS
REG6_BIT7
VMAXx_EN
REG3_BIT7
OPERATION
VMAX_LATCH
Enabled when BB
enabled
VBAT
BB_OUT
BB_OUT
VBAT
VMAX switch comparator is enabled when BB is
enabled. When BB is disabled, the switch that
connects VMAX to VBAT is turned on.
0
0
0
Y
X
VMAX
Enabled when BB
enabled
VBAT
BB_OUT
BB_OUT
VBAT
VMAX switch comparator is enabled when BB is
enabled. When BB is disabled, the VMAX
switches are BOTH turned off.
1
0
0
Y
X
VMAX
OFF when BB
disabled
OFF when BB
disabled
Enabled when BB enabled
Disabled when BB_OUT <VMAX
VBAT
BB_OUT
VMAX switch comparator is enabled when BB is
enabled. When BB is disabled, the comparator
BB_OUT
VBAT
remains on until BB_OUT goes below VMAX
.
0
0
1
VMAX follows BB output until BB output voltage
goes below VBAT voltage. At that point, VMAX
switch comparator is disabled, and VMAX is
connected to VBAT with 0 Iddq static logic.
Y
X
VMAX
ON when
BB_OUT <VMAX
ON when
BB_OUT >VMAX
Enabled when BB enabled
Disabled when BB_OUT <VBAT
VBAT
BB_OUT
BB_OUT
VBAT
VMAX switch comparator is enabled when BB is
enabled. When BB is disabled and BB_OUT
drops below VBAT, both switches in VMAX block
are disabled and VMAX will be a diode below
VBAT when BB is turned off.
1
0
1
Y
X
VMAX
ON when
BB_OUT >VBAT
OFF
Always on
VBAT
BB_OUT
When VMAX_EN=1 regardless of other bits
status, VMAX logic is always ON and monitors
VBAT vs. BB_OUT voltage and connect to the
maximum voltage. The comparator consumes
about 25µA. VMAX_EN can be set to 1 before
transmission phase and then set to zero at the
end of transmission phase when chip goes to
sleep mode.
BB_OUT
VBAT
X
1
X
Y
X
VMAX
ON when
BB_OUT >VBAT
ON when
BB_OUT <VBAT
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LDO Output Capacitor
A 2.2µH capacitor is recommended to be placed as close as possible to the LDO output pin and AGND . In
particular, a good ground plane for the TPS65290 and the LDO output capacitor is highly recommended to
prevent LDO overshoot during the buck-boost converter operation.
Recovery Comparator (EEPROM Setting)
The recovery comparator is designed to track the operation of a high output impedance battery. When a load is
applied the battery voltage collapses and the input voltage monitor detects the falling edge and issues and
interruption when the programmable falling edge threshold an interruption is generated and the PMIC switches
are automatically disabled as per the choice set in register 8. Once the switches are disabled the loading on the
battery will collapse and its voltage will rise. The recovery comparator will monitor this rising edge (as per the
programmed setting) and will automatically re-start the switches disabled when the battery voltage collapsed.
Input recovery
comparator
monitors this edge
When the rising edge
threshold is detected the
Interruption is cleared
Input recovery
comparator
monitors this edge
When the falling edge
threshold is detected an
Interruption is generated
Power switches can be
programmed to
disable/enable with INT
assertion
Figure 57. Recovery Comparator (EEPROM Setting)
Thermal Shut Down
TPS65290 has two over temperature sensors. The buck boost temperature sensor is close to the buck boost
power FETs and monitors the power and heat going into the buck-boost block. The central temperature sensor is
monitoring the rest of the chip and its temperature is set at a higher temperature. At the digital core level, outputs
of both temperature sensors are ORed together. The following diagrams show the logic for buck-boost enable
(BB_EN) and power switches. In the example below, the diagram for BB_PWR_PA switch is shown. The same
diagram applies to 1Wire, SEI, AUX1, AUX2, RF, and LDOBB switches.
OTS_BB
OTS
OTS_central
EN_BB
Reg00[0]
OTS
COMPout
BB_EN
EN_PWR_PA
UVLOdisable
Reg03[5]
EN_PWR_PA_reg
Reg00[2]
COMPRVout
EN_BBpin
OTS_BB
EN_PA_SHUTDN
Reg08[2]
COMPRVout: output of recovery
comparator
Figure 58. Thermal Shut Down
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Operation of the IC During RF Transmission at Full Power
For high power output transmission, BB output voltage will power up the power amplifier with a voltage set to 3V
to 5V at buck boost output. Pulse currents of tens to hundreds of mA are common in wireless sensor systems
during transmit and receive modes. These high current pulses place special demands on batteries. Repeated
delivery of pulse currents exceeding the recommended load current of a given chemistry diminishes the useful
life of the cell. The effects can be severe, depending on the amplitude of the current and the particular cell
chemistry and construction. Also the internal impedance of the cell often results in an internal voltage drop that
precludes the cell from delivering the pulse current at the voltage necessary to operate the external circuit.
One method of mitigating these effects is to place a low equivalent series resistance (ESR) capacitor across the
battery. The battery charges the capacitor between discharge pulses, and the capacitor delivers the pulse current
to the load. To determine the required capacitance the following parameters are required:
•
•
•
•
•
•
Battery impedance (at temperature and state-of-charge)
Battery voltage (as a function of state-of-charge)
Operating temperatures
Pulse current amplitude
Pulse current duration
Allowable voltage drop during pulse discharge
The following equations are used to calculate the output capacitance needed to deliver the specified pulse
current of a known duration and the latency time that must be imposed between pulses to allow the capacitor to
be recharged by the battery. Both formulas assume that the capacitor ESR is sufficiently low to result in
negligible internal voltage drop while delivering the specified pulse current; consequently, only the battery
resistance is considered in the formula used to compute capacitor charging time, and only the load resistance is
considered when computing the capacitance needed to deliver the discharge current.
The first step in creating a battery-capacitor couple for pulse-current applications is to size the capacitance using
the following discharge formula:
C = t / R × [–ln (VMIN / VMAX)]
(6)
Where:
C = output capacitance in parallel with battery
t = pulse duration
R = load resistance = VOUT(average) / Ipulse
VMIN and VMAX are determined by the combination of the battery voltage at a given state-of-charge and the
operating voltage requirement of the external circuit. Once the capacitance has been determined, the capacitor
charging time can be calculated using the following charge formula:
t = R × C × [–ln (1 – VMIN / VMAX)]
(7)
Where:
t = capacitor charging time from VMIN to VMAX
R = battery resistance
C = output capacitance in parallel with battery
Again, VMIN and VMAX are functions of the battery voltage and the circuit operating specifications. Battery
resistance varies according to temperature and state-of-charge as described above. Worst-case conditions are
often applied to the calculations to ensure proper system operation over temperature extremes, battery condition,
capacitance tolerance, etc.
Due to high input impedance of the battery used, a high input capacitor in order of thousands of µF is therefore
placed at battery input to store charge. During the RF transmission phase that takes in order of 5-10msec, the
storage capacitor provides power for transition. The input voltage VBAT is dropping from 3.6V at beginning of
operation to about 2V at the receive time. Main LDO is powered by VMAX, which would be at buck boost output
during this transition. The blocks that would see low voltage operation of VBAT are buck-boost and digital logic.
Buck boost is designed to work down to 1.8V of typical falling input voltage (note: this is for when buck boost was
enabled at higher input voltage, started up successfully and then its input voltage is falling. If buck boost starts
from a disable mode, rising VIN voltage is higher).
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Digital reset (nPUC) is designed for rising VBAT voltage of 1.76V and falling voltage of 1.25V. To prevent digital
logic from reset, the recovery voltage comparator levels should be set higher than falling voltage (i.e., 1.9V).
If recovery voltage is lower, or the feature is disabled, PMIC can be reset. When reset happens, PMIC disables
both main LDO, BB block (if BB_EN=0), and all switches. However, VMICRO function will be still provided. After
digital reset and when all blocks are disabled, the input voltage will rise again, and PMIC starts again with default
register values.
RF transmission voltage at 4.5V
VBAT (3.6V)
COMPRV level
BB_OUT
Figure 59. Operation of the IC During RF Transmission at Full Power
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APPLICATION INORMATION
State Machine
Power ON Reset
Typical rising threshold is
1.8V @ 25°C
Digital Core is operational
Load Pulse
Enable Clock, Load EEPROM
Reset=0
UV detect
EN_BB
EN_LDO
...
Disable Clock
Enable Zero Iddq Bias/LDOMINI/
BUCKMINI
EEPROM
Register File
Trim and
adjustment
CHIP_EN=0
Wait Mode: PMIC is in deep sleep,
Zero Iddq State
ASYNC state
Disable VMAX control. VMAX=VBAT
the outputs are all off, with
terminating resistors enabled . The
Interrupt output is disabled. All
functions including the voltage
comparator are off.
EN_BB=0
EN_BB=1
CHIP_EN=1
Reverse Recovery Comp Logic
Control
Enable VMAX control
CHIP_EN=1
INT flag
I2C/SPI logic, they are ASYNC
designs running by their own
clocks.
Internal switches can be
operated, interrupt logic, and
BB.
Serial Interface
The following pins are allocated to the serial interface:
Table 2. Serial Interface
NO.
PIN
SPI INTERFACE
I2C INTERFACE
COMMENT
Can be pulled down to ground with 100kΩ
Setting Bit 1, Register 5
1
SCL/SCK
Clock
Clock
Can be pulled down to ground with 100kΩ
Setting Bit 1, Register 5
2
MOSI/SDA
INT
Master to slave data
Interruption pin
Data
Push-pull interruption output, powered from
VMICRO
22
Interruption pin
1 mA output drive. Can be pulled down to ground
with 100kΩ
Setting Bit 1, Register 5
Not used. Connect to
ground
23
24
MISO
CS
Slave to master data
Slave select (active
high)
Not used. Connect to Can be pulled down to ground with 100kΩ
ground
Setting Bit 1, Register 5
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VIN
VMICRO
10kΩ
10kΩ
CHIP_EN
*I2C MODE
CS
100kΩ
SCL/SCK
100kΩ
MOSI/SDA
State Machine
Serial
Interface
SPI/I2C
100kΩ
MISO
INT
100kΩ
INT MANAGEMENT
Bit 1, Register 5
*I2C MODE = Factory configured
Figure 60. State Machine Serial Interface
NOTE
CS level must be low when the device is powered-up . Using SPI the interface should be
powered with VMICRO to avoid level shifting issues.
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SPI Interface Timing Diagram
The SPI frequency range is from 32kHz to 10MHz with a minimum voltage of 2.2V. Operation at 1.8V requires a
maximum clock frequency of 5MHz.
The following figures show SPI write and read transaction timing diagram. It assumes SPI master drives CS and
MOSI at falling edge of SCK clock and SPI slave drives MOSI at falling edge of SCK. It requires enough CS idle
time of at least four SPI clock cycles between transactions. CS idle time means the time CS is low. CS is chip
select and it is active high. SPI master drives CS and MISO at falling edge of SCK and SPI slave samples MISO
data at rising edge of SCK during address phase and data phase of write transaction. SPI host samples MOSI
data at rising edge of SCK. Frame error is used to indicate frame error from the previous transaction. If Frmerr
(frame error) is 1, it indicates the previous transaction does not contain exact 24 clock cycles. The write data will
be ignored if frame error occur.
CS
1
2
3
5
8
10 11
13
16 17
20 21 22 23 24
4
6
7
9
12
14 15
18 19
SCLK
MOSI
MISO
a7 a6
a3 a2
a0
a5 a4
a1
r/wz
0
Frmerr
d2
d0
d7
d3
d1
d5
d6
d4
0
0
0
Frame error
SPI read transaction timing diagram
r/wz= 1 to read data
MOSI when reading 0x02 register
0000 // 0010 // 1 000 // 0000 // 0000 // 0000
Figure 61. SPI Read Transaction
CS
SCLK
MOSI
MISO
1
2
3
5
8
10 11
13
16 17
20 21 22 23 24
4
6
7
9
12
14 15
18 19
d7
0
0
0
0
d6
d5 d4
d3
d2
a7 a6
a3 a2
a0
0
a5 a4
a1
r/wz
0
0
d1 d0
0
Frmerr
0
0
Frame error
SPI write transaction timing diagram
r/wz=0 to write data
MOSI when writing 0xA5 date to 0x02 register to iridium
0000 // 0010 // 0 000 // 0000 // 1010 // 0101
Figure 62. SPI Write Transaction
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Table 3. SPI Interface Timing (Minimum Supply Voltage is 2.2V)
SYMBOL
tc(CLK)
tw(CLKH)
tw(CLKL)
PARAMETER
Cycle time CLK
CONDITIONS
1 (see timing diagram)
2 (see timing diagram)
3 (see timing diagram)
MIN
100
TYP
MAX
UNIT
ns
Pulse duration, CLK high
Pulse duration, CLK low
40
40
ns
ns
Delay time, MISO valid before CLK
high, CLOAD= 20 pF
tsu(MISO-CLKH)
tsu(MOSI - CLKH)
Th(CLKH - MOSI)
4 (see timing diagram)
5 (see timing diagram)
20
ns
ns
ns
Setup time, MOSI valid before CLK
high
25
25
Hold time, MOSI valid after CLK
high
6 (see timing diagram)
7 (see timing diagram)
tsu(CS - CLKH)
Th(CS - CLKH)
CS setup rising time to CLK high
50
50
ns
ns
CS Hold time falling after CLK high 7 (see timing diagram)
1
CLK
2
3
4
Data out
MISO
valid
5
6
Data in
MOSI
valid
8
7
CS
Figure 63. Timing Diagram
I2C Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400kHz. The device has a 7bit address: ‘01010110’. Attempting to read data from register addresses not listed in
this section will result in 00h being read out. For normal data transfer, SDA is allowed to change only when SCK
is low. Changes when SCK is high are reserved for indicating the start and stop conditions. During data transfer,
the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Eh data
transfer is initiated with a start condition and terminated with a stop condition. When addressed, the device
generates an knowledge bit after the reception of eh byte. The master device (microprocessor) must generate an
extra clock pulse that is associated with the knowledge bit. The device must pull down the SDA line during the
knowledge clock pulse so that the SDA line is a stable low during the high period of the knowledge clock pulse.
The SDA line is a stable low during the high period of the knowledge–related clock pulse. Setup and hold times
must be taken into count. During read operations, a master must signal the end of data to the slave by not
generating an knowledge bit on the last byte that was clocked out of the slave. In this case, the slave device
must leave the data line high to enable the master to generate the stop condition.
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SDA
SCK
Figure 64. Bit Transfer on the Serial Interface
SDA
SCK
Figure 65. START and STOP Conditions
SCK
SDA
Start
Figure 66. Serial i/f WRITE to Device
SCK
SDA
Start
Figure 67. Serial i/f READ Protocol A
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SCK
SDA
Start
Figure 68. Serial i/f READ Protocol B
SDA
SCK
Figure 69. Serial i/f Timing Diagram
MIN
MAX
400
UNIT
kHz
ns
fMAX
Clock frequency
twH(HIGH)
twL(LOW)
tR
Clock high time
600
Clock low time
1300
ns
SDA and CLK rise time
SDA and CLK fall time
300
300
ns
tF
ns
Hold time (repeated) START condition (after this period the first clock pulse is
generated)
th(STA)
600
ns
th(SDA)
th(SDA)
tsu(SDA)
tsu(STO)
t(BUF)
Setup time for repeated START condition
Data input hold time
600
0
ns
ns
ns
ns
ns
Data input setup time
100
600
1300
STOP condition setup time
Bus free time
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Register Tables
NOTE
To access registers: Write 1 to bit 7, register 1
To lock registers write 0 to bit 7, register 1
Register 0, Block Enable, Address 00H
This register enables the buck boost converter, the main LDO and most of the power switches. All options can be
pre-set with EEPROM bits. The enable logic for all switches and power blocks is:
0 Disabled
1 Enabled
Note that the buck boost block can be enabled either by a register OR the BB_EN pin (15) high.
NAME
BIT
7
CATEGORY
PWR_ON
PWR_ON
PWR_ON
PWR_ON
PWR_ON
R/W
R/W
R/W
R/W
R/W
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
EN_PWR_VIN_VIN
Y
Y
Y
Y
Y
0
0
0
0
0
Enables switch from VIN to 1WIRE power
Enables switch from LDO output to VMICRO
Enables switch from LDO to AUX2
EN_PWR_MICRO_LDO
EN_PWR_LDO2_LDO
EN_PWR_LDO1_LDO
EN_PWR_VMAX_VMAX
6
5
4
Enables switch from LDO output to RF
Enables switch from VMAX output to AUX1
3
Enables switch from BB output to Power
Amplifier
EN_PWR_BB2_BB
2
PWR_ON
R/W
Y
0
EN_LDO
EN_BB
1
0
PWR_ON
PWR_ON
R/W
R/W
Y
Y
0
0
Enables LDO
Enables Buck Boost
Register 1, Rev ID and write protect , Address 01H
Bit 7 must be set to 1 before any other register can be read o write. If set to 0 all registers are locked Bits 0 to 3
are for TI internal usage to track IC revisions.
NAME
BIT
7
CATEGORY
GLOBAL
GLOBAL
GLOBAL
GLOBAL
GLOBAL
R/W
R/W
R
EEPROM BIT
DEFAULT
DESCRIPTION
If 1, allows access to TI internal registers
Revision ID
WRITE_EN
Revision[3]
Revision[2]
Revision[1]
Revision[0]
N
N
N
N
N
N.A.
3
0
1
1
0
2
R
Revision ID
1
R
Revision ID
0
R
Revision ID
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Register 2, VMICRO_VOUT, Address 02H
Depending on the factory setting, this register sets the voltage drop from battery to VMICRO for the zero leak bias
or the VMICRO set voltage (LDOMINI, BUCKMINI options).
NAME
BIT
CATEGORY
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
BMINI[1]
BMINI[0]
BMINI[1]
BMINI[0]
7
BUCKMINI
R/W
N
0
Low power mode
High power mode
1
1
0
1
6
5
4
3
2
1
0
BUCKMINI
RESERVED
RESERVED
VMICRO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N
N
N
Y
Y
Y
Y
0
0
0
0
1
0
0
RESERVED
RESERVED
VMICRO_VOUT[3]
VMICRO_VOUT[2]
VMICRO_VOUT[1]
VMICRO_VOUT[0]
VMICRO
Zero Leak Bias, LDOMINI (only one is set to work as per factory
setting)
VMICRO
VMICRO
ZERO LEAK BIAS
SETTING
VMICRO[3]
VMICRO[2]
VMICRO[1]
VMICRO[0]
LDOMINI (V)
BUCKMINI (V)
(V)
VBAT-0.6
VBAT-0.8
VBAT-1
VBAT-1.2
VBAT-1.4
VBAT-1.6
VBAT-1.8
VBAT-2
VBAT
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.806
1.903
1.998
2.101
2.194
2.295
2.407
2.496
2.592
2.696
2.806
2.885
2.969
3.058
3.152
3.254
1.806
1.903
1.998
2.101
2.194
2.295
2.407
2.496
2.592
2.696
2.806
2.885
2.969
3.058
3.152
3.254
2
3
4
5
6
7
8
9
VBAT
10
11
12
13
14
15
VBAT
VBAT
VBAT
VBAT
N/A
Disconnect
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Register 3, BUCK-BOOST_VOUT, Address 03H
The buck boost voltage is set with this register (bits 0 to 4) which can be set by EEPROM.
UVLO operation on the buck boost can be enabled/disabled by setting bit 5.
Forced PWM operation can be set with bit 6.
NAME
BIT
CATEGORY
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
When 0 VMAX switches off instantaneously
when disabled.
When 1 VMAX Switches off when VBB goes
below VBAT
VMAX_LATCH
7
VMAX
R/W
Y
0
If 0, automatic PWM/PFM. If 1, is forced
PWM.
BB_FORCE_PWM
UVLO disable
6
5
BUCK_BOOST
BUCK_BOOST
R/W
R/W
Y
Y
0
1
If 1, UVLO comparator does NOT shut down
BB.
INT is still generated.
VBB_VOUT[4]
VBB_VOUT[3]
VBB_VOUT[2]
VBB_VOUT[1]
VBB_VOUT[0]
4
3
2
1
0
BUCK_BOOST
BUCK_BOOST
BUCK_BOOST
BUCK_BOOST
BUCK_BOOST
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
1
0
0
1
1
SETTING
0
VBUCK_BOOST[4]
VBUCK_BOOST[3]
VBUCK_BOOST[2]
VBUCK_BOOST[4]
VBUCK_BOOST[1]
VBB
0.995
1.194
1.394
1.594
1.784
1.985
2.189
2.381
2.587
2.779
2.972
3.161
3.374
3.452
3.576
3.664
3.756
3.853
3.954
4.062
4.176
4.235
4.359
4.424
4.559
4.779
4.857
4.938
5.022
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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Register 4, LDO_VOUT, BANDGAP Address 04H
The LDO voltage is set with this register (bits 0 to 4) which can be set by EEPROM.
To speed up system start-up the internal bandgap can be enabled before the LDO and switches are enabled.
NAME
BIT
7
CATEGORY
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
6
BGLP_EN
5
Bandgap
LDO
R/W
R/W
R/W
R/W
R/W
R/W
N
Y
Y
Y
Y
Y
When 1, Enables internal bandgap.
LDO_VOUT[4]
LDO_VOUT[3]
LDO_VOUT[2]
LDO_VOUT[1]
LDO_VOUT[0]
4
1
0
0
1
0
3
LDO
2
LDO
1
LDO
0
LDO
SETTING
0
VLDO[4]
VLDO[3]
VLDO[2]
VLDO[1]
VLDO[0]
VLDO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.001
1.103
1.202
1.303
1.399
1.506
1.606
1.712
1.81
1
2
3
4
5
6
7
8
9
1.921
2.019
2.127
2.23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.33
2.438
2.534
2.637
2.725
2.845
2.948
3.031
3.148
3.243
3.343
3.449
3.563
3.643
3.769
3.858
3.952
4.05
0.803
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
Register 5, Pull-down resistors, Address 05H
The power switches can be pulled-down when disabled using bits 1 to 7.
The enable logic for all pull-downs is:
0 Disable
1 Enable
Bit 0 is used to increase the turn-on speed of the switches.
NAME
BIT
CATEGORY
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
Enable pull-down resistor from VIN to
PWR_VIN
EN_PWR_VIN_VIN Pull-down
7
PWR_ON
R/W
Y
1
Enable pull-down resistor from Buck Boost
EN_PWR_BB1_BB Pull-down
6
PWR_ON
R/W
Y
1
(BB).
BB output to switch
EN_PWR_LDO2_LDO Pull-
down
5
4
3
2
PWR_ON
PWR_ON
PWR_ON
PWR_ON
R/W
R/W
R/W
R/W
Y
Y
Y
Y
0
0
0
0
Enable pull-down resistor from LDO to switch
EN_PWR_LDO1_LDO Pull-
down
Enable pull-down resistor from LDO output to
switch
EN_PWR_VMAX_VMAX Pull-
down
Enable pull-down resistor from BB output to
switch
Enable pull-down resistor from BB output to
switch
EN_PWR_BB2_BB Pull-down
Enable pull-down resistor for serial interface
pins
SPI pull-down resistor
FAST
1
0
PWR_ON
PWR_ON
R/W
R/W
Y
Y
1
0
If 1 makes switch turn on 10x faster.
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Register 6, VMAX control and Recovery comparator, Address 06H
Bits 5 to 3 are used to set the threshold for falling voltage on the recovery comparator.
Bits 2 to 0 are used to set the threshold for rising voltage on the recovery comparator.
Bits 7 and 6 are used to set the VMAX operation (see VMAX options section).
NAME
BIT
7
CATEGORY
VMAX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
See VMAX OPTIONS
VMAX_DIS
VMAX_EN
N
N
Y
Y
Y
Y
Y
Y
0
0
0
1
1
0
0
0
6
VMAX
VRECOVERY[2]_FALLING
VRECOVERY[1]_FALLIING
VRECOVERY[0]_FALLIING
VRECOVERY[2]_RISING
VRECOVERY[1]_RISING
VRECOVERY[0]_RISING
5
VINPUT
VINPUT
VINPUT
VINPUT
VINPUT
VINPUT
INT pin will be asserted when VIN reaches the
falling threshold voltage.
And will be cleared when VIN recovers to the
rising threshold voltage. See table below
4
3
2
1
See Table below
0
SETTING
VRECOVERY_FALLING[2]
VRECOVERY_FALLING[1]
VRECOVERY_FALLING[0]
VRECOVERY COMPARATOR
0
0
0
0
1.7
1
0
0
1
1.8
2
0
1
0
1.9
3
0
1
1
2
4
1
0
0
2.1
5
1
0
1
2.2
6
0
1
1
2.3
7
1
1
1
2.4
SETTING
VRECOVERY_FALLING[2]
VRECOVERY_FALLING[1]
VRECOVERY_FALLING[0]
VRECOVERY COMPARATOR
0
1
2
3
4
5
6
7
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
Register 7, PWR_BB_LDO switch control AND interruption management, Address 07H
The alarm status of the device can be verified with this register.
Bit 7 and 3 report on the UVLO comparator status. Bit 5 masks this alarm.
Bit 6 and 2 report on the over temperature status. Bit 4 masks this alarm.
Bits 1 and 0 are used to control the switches associated with the internal connection between the LDO and the
buck boost converter..
The enable logic for the switches is:
0 Disabled
1 Enabled
NAME
BIT
CATEGORY
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
Set to 1 when recovery comparator is
asserted (falling edge), cleared to 0 when
register is read by serial interface.
UVLO_INT
OTS_INT
7
INT
R
N
0
Set to 1 when over temperature is asserted,
cleared to 0 when register is read by serial
interface.
6
INT
R
N
0
Masks the recovery comparator assertion
(falling edge).
Reported to the INT PIN
UVLO_MASK
OTS_MASK
5
4
INT
INT
R/W
R/W
N
N
0
1
Masks the over temperature assertion.
Reported to the INT PIN
UVLO_STATUS
OTS_STATUS
3
2
INT
INT
RD only
RD only
N
N
0
0
Status report of recovery comparator fault
Status report of an overt temperature fault
Enable switch to SEL from Buck Boost (BB)
BB output OR LDO
EN_PWR_SEL_BB
EN_PWR_BB_LDO
1
0
PWR_ON
PWR_ON
R/W
R/W
Y
Y
0
0
Enables the back to back switch from Ldo
output to BB output
Register 8, interruption block disable, Address 08H
Bit 7 to 1 can be used to automatically disable the power switches when an interruption is asserted.
Bit 0 disables the recovery comparator to reduce power consumption.
NAME
EN_Vin_SHUTDN
BIT
7
CATEGORY
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EEPROM BIT
DEFAULT
DESCRIPTION
If 1, switch turns off at interruption.
If 1, switch turns off at interruption.
If 1, switch turns off at interruption.
If 1, switch turns off at interruption.
If 1, switch turns off at interruption.
If 1, switch turns off at interruption.
If 1, PWR_BB_LDO switch turns off at INT
If 1, COMPrv is disabled
Y
Y
Y
Y
Y
Y
Y
Y
1
0
1
1
1
0
1
1
EN_BB2_SHUTDN
EN_LDO2_SHUTDN
EN_LDO1_SHUTDN
EN_AUX1_SHUTDN
EN_BB1_SHUTDN
EN_LDOBBbb_SHUTDN
COMPrv_ENmask
6
5
4
3
2
1
0
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
www.ti.com
Recommended Board Layout
This section provides the recommendation of the TPS65290 board layout based on TI evaluation board. Close
placement to the chip and to the ground plane is required for power components including C21, C2, C6, C15,
C15a, L1, C10 and C4. The priority among the components is C21 → C2 → C8 → C6 → C15 → C15A → L1 →
C10 → C4. In particular, a good ground plane for the TPS65290 and the LDO output capacitor (C6) is highly
recommended to prevent LDO overshoot during the buck-boost converter operation. A good ground connection
for C21 and C2 is also required for the high performance of the buck-boost converter. The pin is regarded as a
noise generator because of the buck-boost converter switching operation. Therefore, do not tap the trace to pin2
from the trace from C21. Use star connection for two inputs of pin 19 and pin 4 from the power supply.
Figure 70. Schematic
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
Figure 71. Component Placement
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Figure 72. Top Layer
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
Figure 73. Second Layer (Full Copper Ground Plane)
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Figure 74. Third Layer
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SLVSBY5B –APRIL 2013–REVISED JUNE 2013
Figure 75. Bottom Layer
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2013
PACKAGING INFORMATION
Orderable Device
TPS65290BMRHFR
TPS65290BMRHFT
TPS65290LMRHFR
TPS65290LMRHFT
TPS65290ZBRHFR
TPS65290ZBRHFT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHF
24
24
24
24
24
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
TPS
65290BM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHF
RHF
RHF
RHF
RHF
250
3000
250
Green (RoHS
& no Sb/Br)
TPS
65290BM
Green (RoHS
& no Sb/Br)
TPS
65290LM
Green (RoHS
& no Sb/Br)
TPS
65290LM
3000
250
Green (RoHS
& no Sb/Br)
TPS
65290ZB
Green (RoHS
& no Sb/Br)
TPS
65290ZB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65290BMRHFR
TPS65290BMRHFT
TPS65290LMRHFR
TPS65290LMRHFT
TPS65290ZBRHFR
TPS65290ZBRHFT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
RHF
RHF
24
24
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
5.3
5.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65290BMRHFR
TPS65290BMRHFT
TPS65290LMRHFR
TPS65290LMRHFT
TPS65290ZBRHFR
TPS65290ZBRHFT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
RHF
RHF
24
24
24
24
24
24
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
Pack Materials-Page 2
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