TPS65642AYFFR [TI]
用于笔记本 PC、平板 PC 和监视器的具有集成伽马参考的 LCD 偏置 | YFF | 56 | -40 to 85;
| 型号： | TPS65642AYFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于笔记本 PC、平板 PC 和监视器的具有集成伽马参考的 LCD 偏置 | YFF | 56 | -40 to 85 PC CD 监视器 开关 |
| 文件： | 总79页 (文件大小：4044K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65642A
www.ti.com
SLVSC21 –OCTOBER 2013
LCD Bias With Integrated Gamma Reference for Notebook PCs, Tablet PCs and Monitors
Check for Samples: TPS65642A
1 Introduction
1.1 Features
123
• 2.6 V to 6 V Input Voltage Range
• Synchronous Boost Converter (AVDD
• Panel Discharge Signal (XAO)
• System Reset Signal (RST)
)
• Non-Synchronous Boost Converter With
Temperature Compensation (VGH
• Synchronous Buck Converter (VCORE
• Synchronous Buck Converter (VIO1
• Low Dropout Linear Regulator (VIO2
• 14-Channel, 10-Bit Programmable Gamma
Voltage Correction
• On-Chip EEPROM with Write Protect
• I2C™ Interface
)
)
)
)
• Thermal Shutdown
• Programmable VCOM Calibrator With Two
Integrated Buffer Amplifiers
• Gate Voltage Shaping
• Supports GIP and Non-GIP Displays
• 56-Ball, 3,16-mm × 3,45-mm 0,4-mm Pitch
DSBGA
1.2 Applications
•
•
•
Notebook PCs
Tablet PCs
Monitors
1.3 Description
The TPS65642A device is a compact LCD bias solution primarily intended for use in notebook and tablet
PCs. The device comprises two boost converters to supply the source driver and gate driver, or level
shifter, of the LCD panel; two buck converters and a low-dropout (LDO) linear regulator to supply the
system logic voltages; a programmable VCOM generator with two high-speed amplifiers; 14-channel
gamma-voltage correction; and a gate-voltage shaping function.
VIN
Boost Converter 1
Buck Converter 1
Buck Converter 2
LDO Regulator
AVDD
VCORE
VIO1
VIO1
VIO2
AVDD
VGH
Boost Converter 2
Reset Generator
RST
XAO
VGH
Gate Voltage Shaping
VGHM
VGAM
VCOM
Programmable
Gamma Voltages
14
2
Programmable
VCOM + Buffers
I2C
I2C Interface
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excel is a registered trademark of Microsoft Corporation.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS65642A
SLVSC21 –OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Electrical Specifications
2.1 ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN, SW2, VCORE, SW3, VIO1, VIO2 RSET, COMP, SCL, SDA,
EN, FLK, WP, TCOMP, XAO, RST
–0.3
7
V
AVDD, SW1, OUT1, OUT2, OUTA-OUTN
SW4
–0.3
–0.3
–0.3
12
36(2)
12(3)
2
40(5)
2000
200
700
85
V
V
Pin
voltage
POS1, NEG1, POS2, NEG2
|POS1-NEG1|(4), |POS2-NEG2|(4)
VGH, VGHM, RE
V
V
–0.3
V
Human Body Model
V
ESD
Rating
Machine Model
V
Charged Device Model
Ambient temperature
V
TA
–40
–40
–65
°C
°C
°C
°C
TJ
Junction temperature
150
150
300
TSTG
Storage temperature
Lead temperature (soldering, 10 seconds)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VGH supplies up to 40 V can be generated, but require an external cascode transistor or charge pump.
(3) For supply voltages less than 12 V, the absolute maximum input voltage is equal to the supply voltage.
(4) Differential input voltage.
(5) The combination of low temperatures and high VGH voltages can cause increased leakage current through the RE pin. In GIP
applications that do not use the gate-voltage shaping function it is recommended to leave the RE pin open to minimize this effect.
2.2 THERMAL INFORMATION(1)
TPS65642A
THERMAL METRIC
YFF
56 PINS
45
UNIT
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.2
6.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
6.1
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2.3 RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
2.6
6
V
BOOST CONVERTER 1
AVDD
Boost converter 1 output voltage range
7
10.1
V
IAVDD
Boost converter 1 output current when 6 V ≥ VIN ≥ 4 V
700(1)
400(1)
mA
mA
Boost converter 1 output current when 3.63 V ≥ VIN ≥ 2.64 V
(1) This figure includes the current that must be supplied to the input of boost converter 2.
Electrical Specifications
2
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SLVSC21 –OCTOBER 2013
RECOMMENDED OPERATING CONDITIONS (continued)
MIN
2.2
10
TYP
MAX
UNIT
µH
L
Boost converter 1 inductor range
4.7
10
COUT
Boost converter 1 output capacitance
µF
BOOST CONVERTER 2
AVDD
VGH
IGH
Input voltage range
7
8.4
24
15
15
4.7
10
10.1(2)
40(3)
40
V
V
Output voltage range
Output current
16
mA
µH
µF
kΩ
L
Inductor
10
1
COUT
RNTC
Output capacitance
Thermistor resistance at 25°C
BUCK CONVERTER 1 (VCORE
)
VCORE
ICORE
L
Output voltage
Output current
Inductor
1
1.1
1.3
600
4.7
22
V
mA
µH
µF
1
2.2
10
COUT
Output capacitance
4.7
BUCK CONVERTER 2 (VIO1
)
VIO1
IIO1
L
Output voltage
Output current
Inductor
1.7
2.5
200(4)
4.7
V
mA
µH
µF
1
2.2
10
COUT
Output capacitance
4.7
22
LDO Regulator (VIO2
)
VIO2
IIO
Output voltage
1.7
1.8
200
10
V
Output current
mA
µF
COUT
Output capacitance
4.7
50
PROGRAMMABLE VCOM
ISET Programmable VCOM set current
PROGRAMMABLE GAMMA CORRECTION
µA
IGAM
Output current per channel
Output capacitance
–100
100
50
µA
pF
CGAM
(2)
VGH− AVDD must be greater than 9 V.
(3) Output voltages greater than 36 V require an external cascode transistor.
(4) This figure includes the current supplied to the input of the linear regulator.
2.4 ELECTRICAL CHARACTERISTICS
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
POWER SUPPLY
Supply current into VIN pins
Supply current into AVDD pins
Supply current into VGH
Converters not switching
1.9
0.1
4.3
4.0
0.1
3
1
Pin G5.
IIN
Pin B7. No load on gamma reference outputs
Pin F4. No load on op-amp outputs
No load on VGHM
6
mA
7.5
1
mA
UNDERVOLTAGE LOCKOUT
Undervoltage lockout threshold
Hysteresis
VIN rising
VIN falling
2.3
2.1
2.42
2.19
0.23
2.5
2.4
VUVLO
V
(1) When VIO1 = 1.7 V or 1.8 V, the LDO regulator is disabled. When VIO1 = 2.5 V, the LDO regulator is enabled.
Electrical Specifications
Copyright © 2013, Texas Instruments Incorporated
3
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ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL PINS (EN, FLK, WP)
VIN = 2.64 V
1
1.8
1.8
1.8
VIH
EN high-level input voltage threshold EN rising
VIN = 3.3 V
VIN = 6 V
1.1
1.7
0.9
1
V
VIN = 2.64 V
VIN = 3.3 V
VIN = 6 V
0.7
0.7
VIL
EN low-level input voltage threshold
EN falling
V
0.7
1.6
IIH
IIL
EN high-level input current
EN low-level input current
EN = 2.5 V
EN = 0 V
–100
–100
100
100
1.8
1.8
1.8
nA
nA
VIN = 2.64 V
VIN = 3.3 V
VIN = 6 V
0.9
1
VIH
FLK high-level input voltage threshold FLK rising
FLK low-level input voltage threshold FLK falling
V
V
1.4
0.8
0.9
1.3
VIN = 2.6 V
VIN = 3.3 V
VIN = 6 V
0.6
0.6
VIL
0.6
IIH
IIL
FLK high-level input current
FLK-low-level input current
FLK = 2.5 V
FLK = 0 V
–100
–100
100
100
1.8
1.8
1.8
nA
nA
VIN = 2.64 V
VIN = 3.3 V
VIN = 6 V
1
VIH
WP high-level input voltage threshold WP rising
1.1
1.7
0.9
1
V
VIN = 2.64 V
VIN = 3.3 V
VIN = 6 V
0.7
0.7
0.7
30
VIL
WP low-level input voltage threshold
WP internal pullup resistance
WP falling
V
1.6
52
RPULL-UP
75
kΩ
BOOST CONVERTER 1 (AVDD
)
Output voltage range
Tolerance
7
10.1
1%
AVDD
V
–1%
% of
AVDD
VUVP
VSCP
Undervoltage protection threshold
Short-circuit threshold
AVDD falling
AVDD falling
65
25
70
30
75
35
% of
AVDD
ILK
Switch leakage current
Switch ON resistance
Switch current limit
VSW = VIN = 3.3 V, EN = 0 V, TJ = –40°C to 85°C
ISW = 1 A
10
µA
mΩ
A
rDS(ON)
ILIM
114
3
250
3.5
400
2.5
rDS(ON)
Rectifier ON resistance
ISW = 1 A
242
750
1200
76
mΩ
FREQ = 0
FREQ = 1
IAVDD = 10 mA
fSW
Switching frequency
kHz
rDS(ON)
Discharge ON resistance
100
Ω
BUCK CONVERTER 1 (VCORE
)
Output voltage
VCORE
1
1.1
1.3
3%
V
Tolerance
–3%
% of
VCORE
VUVP
Undervoltage protection threshold
VCORE falling
VCORE falling
65
70
30
75
35
% of
VCORE
VSCP
ILIMA
rDS(ON)
Short-circuit threshold
Switch current limit
25
ISW ramps from 0 A to 2 A
High-side, ISW = ILIM
Low-side, ISW = 1 A
VIN = 3.3 V
0.8
1
1.2
310
150
480
750
A
183
95
Switch ON resistance
Off time
mΩ
260
380
370
560
tOFF
ns
VIN = 5 V
4
Electrical Specifications
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Product Folder Links: TPS65642A
TPS65642A
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SLVSC21 –OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK CONVERTER 2 (VIO1
)
Output voltage
Tolerance
1.7
1.8
2.5
3%
VIO1
V
–3%
% of
VIO1
VUVP
Undervoltage protection threshold
Short-circuit threshold
VIO1 falling
VIO1 falling
65
70
30
75
35
% of
VIO1
VSCP
ILIM
25
High-side switch current limit
High-side switch ON resistance
Low-side switch ON resistance
High-side, ISW ramps from 0 A to 2 A
ISW = ILIM
0.8
1
1.2
350
400
330
500
50
A
183
255
250
370
15
rDS(ON)
mΩ
ISW = 1 A
VIN = 3.3 V
170
250
tOFF
Off time
ns
VIN = 5 V
rDS(ON)
Discharge ON resistance
Measured with 10 mA
Ω
(2)
LINEAR REGULATOR (VIO2
)
Output voltage
1.7
–3%
65
1.8
3%
75
VIO2
IIO2 = 1 mA
VIO2 falling
V
Tolerance
VUVP
VSCP
Undervoltage protection threshold
70
30
% of
VIO2
Short circuit threshold
VIO2 falling
25
35
% of
VIO2
BOOST CONVERTER 2 (VGH
)
Output voltage range
Tolerance
16
–3%
65
40(3)
3%
75
35
10
1
VGH
V
VUVP
VSCP
ILK
Undervoltage protection threshold
Short-circuit threshold
Switch leakage current
Switch ON resistance
Maximum tON time
tOFF time
VGH falling
70
30
% of VGH
VGH falling
25
% of VGH
VEN = 0 V; VSW4 = 36 V
ISW = 1 A
µA
Ω
rDS(ON)
tON(MAX)
tOFF
0.41
1.67
2.11
1
2.5
3
µs
µs
1.5
48
85°C
25°C
54
ITCOMP
Thermistor reference current
ISET = 50 μA, VTCOMP = 1 V
µA
50
RESET (RST)
Reset pulse duration range
2
16
30%
0.5
1
Measured from end of VCORE ramp to 50% of RST rising
edge with a 10k pullup resistor
tRESET
ms
Tolerance
–20%
VOL
IOH
Low output voltage
High output current
IRST = 1 mA (sinking)
VRST = 2.5 V
0.27
V
–1
µA
PROGRAMMABLE GAMMA CORRECTION
Code = 1023; load = 10 µA, sourcing
Code = 1023; load = 100 µA, sourcing
Code = 0; load = 10 µA, sinking
5.6
100
200
100
200
25
VDROPH
High-side output voltage drop
Low-side output voltage drop
mV
mV
44.2
49.1
65.5
VDROPL
Code = 0; load = 100 µA, sinking
Code = 512
Offset
–25
–3.6
–1
mV
LSB
LSB
INL
Integral nonlinearity
Differential nonlinearity
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V
5.9
1.5
DNL
PROGRAMMABLE VCOM CALIBRATOR
SETZSE
SETFSE
VRSET
DNL
Set zero-scale error
Set full-scale error
–1
–7
1
7
LSB
LSB
V
Voltage on RSET pin
Differential nonlinearity
IRSET = 50 µA
–2%
–1
1.25
2%
1.5
LSB
(2) LDO is enabled, when VIO1 = 2.5 V.
(3) Output voltages greater than 36 V require an external cascode transistor or charge pump circuit.
Copyright © 2013, Texas Instruments Incorporated
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Electrical Specifications
5
Product Folder Links: TPS65642A
TPS65642A
SLVSC21 –OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCM = AVDD / 2, VOUT1 = 2 V, VOUT2 = AVDD –2 V, RL = ∞
VCM = AVDD / 2, VOUT = AVDD / 2
MIN
70
TYP
MAX
UNIT
dB
AVOL
VIO
IB
Open loop gain
91
Input offset voltage
Input bias current
–15
–150
15
mV
nA
VCM = AVDD / 2, VOUT = AVDD / 2
150
VPOS = AVDD / 2, VNEG = AVDD / 2 – 1 V,
IOUT = 10 mA sourcing
VDROPH
VDROPL
High-side voltage drop
Low-side voltage drop
0.05
0.03
0.1
0.1
V
V
VPOS = AVDD / 2, VNEG = AVDD / 2 + 1 V,
IOUT = 10 mA sinking
High-side peak output current
Low-side peak output current
Common-mode rejection ratio
Power supply rejection ratio
200
294
–349
78
VCM = AVDD / 2, VSIGNAL = 2 VPP, open-loop,
RL = ∞, CL = 1 µF
IPK
mA
–200
CMRR
PSRR
VCM1 = 2 V, VCM2 = AVDD –2 V, VOUT = AVDD / 2
40
40
18
25
dB
dB
AVDD1 = 7 V, AVDD2 = 10.1 V, VCM = 3 V, VOUT = 3 V
110
30
TA = –40°C
Open-loop,
SR
Slew rate
V/μs
VPOS = AVDD / 2 ±1 V
TA = 25°C to 85°C
38
GATE VOLTAGE SHAPING
VGH to VGHM ON resistance
VGH = 24 V, IGHM = 10 mA, FLK = 2.5 V
VGHM = 24 V, IGHM = 10 mA, FLK = 0 V
VGHM = 6 V, IGHM = 10 mA, FLK = 0 V
12
12
12
25
25
25
rDS(ON)
Ω
VGHM to RE ON resistance
VGHM rising, 2.5 V, 50% thresholds, COUT = 150 pF, RE
0 Ω
=
tPLH
tPHL
PANEL RESET / LCD BIAS READY (XAO)
72
81
175
200
Propagation delay
ns
VGHM falling, 2.5 V, 50% thresholds, COUT = 150 pF, RE
0 Ω
=
VOL
IOH
Low output voltage
High output current
XAO threshold voltage
Tolerance
IXAO = 1 mA (sinking)
VXAO = 2.5 V
0.23
0.5
1
V
µA
2.2
–2.5%
3%
3.9
XAO falling
XAO rising
VDET
2.5%
11%
V
Hysteresis
6.3%
TIMING
Boost converter 1 delay range
Tolerance
0
70
tDLY1
ms
ms
ms
–20%
30%
Gate voltage shaping; LCD bias-
ready delay range
0
35
tDLY6
Tolerance
–20%
0.5
30%
4
Soft-start ramp time
Tolerance
tSS1
VCORE, VIO1, VIO2
–20%
4
30%
7.5
30%
65
Soft-start ramp time
Tolerance
tSS2
tUVP
AVDD, VGH
ms
ms
–20%
40
Undervoltage protection timeout
50
I2C INTERFACE
Configuration parameters slave
address
74h
4Fh
ADDR
Programmable VCOM slave address
Low level input voltage
High level input voltage
Hysteresis
VIL
Rising edge, standard and fast mode
Rising edge, standard and fast modes
Applicable to fast mode only
Sinking 3 mA
0.75
V
V
VIH
VHYS
VOL
CI
1.75
125
mV
mV
pF
Low level output voltage
Input capacitance
500
10
Standard mode
Fast mode
100
400
fSCL
Clock frequency
Clock low period
kHz
µs
Standard mode
Fast mode
4.7
1.3
tLOW
6
Electrical Specifications
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SLVSC21 –OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
VIN= 3.3 V, VCORE= 1.1 V, VIO1= 1.7 V, VIO2= 1.8 V(1), AVDD= 8.4 V, VGH= 24 V, TA= −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
4
TYP
MAX
UNIT
Standard mode
Fast mode
tHIGH
Clock high period
µs
0.6
4.7
1.3
4
Standard mode
Fast mode
Bus free time between a STOP and a
START condition
tBUF
µs
µs
µs
ns
µs
Standard mode
Fast mode
Hold time for a repeated START
condition
thd:STA
tsu:STA
tsu:DAT
thd:DAT
0.6
4
Standard mode
Fast mode
Set-up time for a repeated START
condition
0.6
250
100
0.05
0.05
Standard mode
Fast mode
Data set-up time
Data hold time
Standard mode
Fast mode
3.45
0.9
20 +
0.1CB
Standard mode
Fast mode
1000
1000
1000
300
Rise time of SCL after a repeated
START condition and after an ACK
bit
tRCL1
tRCL
tFCL
tRDA
tFDA
ns
ns
ns
ns
ns
20 +
0.1CB
20 +
0.1CB
Standard mode
Fast mode
Rise time of SCL
Fall time of SCL
Rise time of SDA
Fall time of SDA
20 +
0.1CB
20 +
0.1CB
Standard mode
Fast mode
300
20 +
0.1CB
300
20 +
0.1CB
Standard mode
Fast mode
1000
300
20 +
0.1CB
20 +
0.1CB
Standard mode
Fast mode
300
20 +
0.1CB
300
Standard mode
Fast mode
4
tsu:STO
Set-up time for STOP condition
Capacitive load on SDA and SCL
µs
pF
0.6
Standard mode
Fast mode
400
400
CB
EEPROM
NWRITE
tWRITE
Number of write cycles
Write time
1000
100
100
180
ms
Data retention
Storage temperature = 150°C
1000 hrs
THERMAL SHUTDOWN
(4)
TSD
Thermal shutdown threshold
120
150
°C
(4) Once triggered, thermal shutdown will remain in the shutdown state until the device is powered down.
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Terminal Description
7
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SLVSC21 –OCTOBER 2013
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3 Terminal Description
3.1 Pin Assignment
NEG2
OUT2
OUT1
OUTD
OUTC
OUTB
OUTA
VIO1
AVDD
AVDD
OUTH
OUTG
OUTF
OUTE
RST
SW1
GND
GND
WP
GND
SW4
GND
VGH
SW4
GND
VGH
VGHM
RE
GND
GND
GND
WP
SW1
AVDD
AVDD
OUTH
OUTG
OUTF
OUTE
OUT2
OUT1
OUTD
OUTC
OUTB
OUTA
NEG2
H3
G3
F3
E3
D3
C3
B3
A3
H5
G5
F5
E5
D5
C5
B5
A5
H6
H2
G2
F2
E2
D2
C2
B2
A2
H4
G4
F4
E4
D4
H7
G7
F7
E7
D7
C7
B7
A7
H1
G1
F1
E1
D1
C1
B1
A1
GND
SW1
EN
EN
SW1
GND
NEG1
POS2
POS1
RSET
G6
F6
E6
D6
C6
B6
A6
NEG1
AVDD
COMP
COMP
AVDD
OUTK
OUTJ
OUTI
POS2
OUTN
OUTM
OUTL
VIN
SCL
VGHM
SCL
OUTK
OUTJ
OUTI
OUTN
OUTM
OUTL
SDA
RE
SDA
POS1
RSET
AVDD
GND
FLK
GND
GND
TCOMP
SW2
FLK
C4
B4
A4
VCORE
VCORE
TCOMP
VIN
VIO1
AVDD
XAO
XAO
RST
SW3
VIO2
GND
SW3
GND
GND
SW2
VIN
GND
VIO2
GND
VIN
TOP VIEW
BOTTOM VIEW
3.2 Pin Assignment
Table 3-1. PIN DESCRIPTIONS
PIN
I/O
DESCRIPTION
NAME
GND
SW2
NO.
A1
A2
A3
A4
A5
A7
A6
B1
B2
B3
B4
B5
P
O
P
O
P
P
O
I
Ground
Buck converter 1 (VCORE) switch pin
Supply voltage
VIN
SW3
Buck converter 2 (VIO1) switch pin
Ground
GND
GND
VIO2
VCORE
TCOMP
VIN
Ground
Linear regulator (VIO2) output and output sense
Buck converter 1 (VCORE) output sense
Boost converter 2 (VGH) thermistor network connection
Supply voltage
I
P
O
O
XAO
Panel discharge
RST
System reset
Buck converter 2 (VIO1) output sense. (Internally connected as supply voltage for LDO
regulator.)
VIO1
B6
B7
I
I
Boost converter 1 (AVDD) output sense. (Internally connected as supply voltage for
programmable gamma correction.)
AVDD
FLK
GND
OUTL
C1
C2
C3
I
Gate voltage shaping flicker clock
Ground
P
O
Gamma correction
8
Terminal Description
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SLVSC21 –OCTOBER 2013
Table 3-1. PIN DESCRIPTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
OUTI
OUTE
OUTA
RSET
RE
NO.
C4
C5
C6
C7
D1
D2
D3
D4
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
O
O
O
O
O
I/O
O
O
O
O
I
Gamma correction
Gamma correction
Gamma correction
Reference current-setting resistor connection
Gate voltage shaping discharge resistor connection
I2C serial data
SDA
OUTM
OUTJ
OUTF
OUTB
POS1
VGHM
SCL
Gamma correction
Gamma correction
Gamma correction
Gamma correction
VCOM 1 non-inverting input
Gate voltage shaping output
I2C serial clock
O
I/O
O
O
O
O
I
OUTN
OUTK
OUTG
OUTC
POS2
Gamma correction
Gamma correction
Gamma correction
Gamma correction
VCOM2 non-inverting input.
Boost converter 2 (VGH) output sense. (Internally connected as supply voltage for the gate
voltage shaping.)
VGH
F1
I
COMP
WP
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
H1
H2
H3
H4
H5
H6
H7
O
I
Boost converter 1 (AVDD) compensation network connection
EEPROM write protect
VCOM1 and VCOM2 supply voltage
Gamma correction
AVDD
OUTH
OUTD
NEG1
GND
EN
I
O
O
I
Gamma correction
VCOM1 inverting input
P
I
Ground.
Boost converter 1 (AVDD) enable
Ground.
GND
SW1
P
O
O
O
P
O
P
P
O
O
O
I
Boost converter 1 (AVDD) switch pin
Boost converter 1 (AVDD) rectifier output
VCOM1 output
AVDD
OUT1
GND
SW4
Ground.
Boost converter 2 (VGH) switch pin
Ground
GND
GND
SW1
Ground
Boost converter 1 (AVDD) switch pin
Boost converter 1 (AVDD) rectifier output
VCOM2 output
AVDD
OUT2
NEG2
VCOM2 inverting input
Copyright © 2013, Texas Instruments Incorporated
Terminal Description
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4 Typical Characteristics
4.1 Table of Graphs
FUNCTIONAL BLOCK
PARAMETER
TEST CONDITIONS
FIGURE
Boost Converter 1 (AVDD
)
Efficiency
AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V, IAVDD = 1 mA to 500 mA
VIN = 3.3 V
VIN = 5 V
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 4-17
Figure 4-18
Figure 4-19
Figure 4-20
Figure 4-21
Figure 4-22
Figure 4-23
Figure 4-24
Figure 4-25
Figure 4-26
Figure 4-27
Figure 4-28
Figure 4-29
Figure 4-30
Figure 4-31
Figure 4-32
Figure 4-33
Figure 4-34
Figure 4-35
Figure 4-35
Figure 4-35
Figure 4-38
Figure 4-39
Figure 4-40
Figure 4-41
Line Regulation
VIN = 2.6 V to 6 V, AVDD = 8.4 V, IAVDD = 100 mA
VIN = 3.3 V, 5 V, AVDD = 8.4 V, IAVDD = 1 mA to 500 mA
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V
Load Regulation
Line Transient Response
RL = 82 Ω
RL = 33 Ω
VIN = 3.3 V
VIN = 5 V
Load Transient Response
Output Voltage Ripple
Switching Waveforms
AVDD = 8.4 V, IAVDD = 20 mA – 200 mA
AVDD = 8.4 V, RL = 82 Ω
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V, AVDD = 8.4 V
RL = 820 Ω
RL = 82 Ω
RL = 82 Ω
VIN = 3.4 V
VIN = 5 V
Switching Frequency
Efficiency
VIN = 2.6 V to 6 V, AVDD = 7 V, 8.4 V, 10.1 V
Buck Converter 1 (VCORE
)
VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500 mA
Line Regulation
VIN = 2.6 V to 6 V, VCORE = 1.1 V, ICORE = 300 mA
Load Regulation
VIN = 3.4 V, 5 V, VCORE= 1.1 V, ICORE = 1 mA to 500 mA
Line Transient Response
Load Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VCORE= 1.1 V, Load = 3.9 Ω
VCORE = 1.1 V, ICORE = 50 mA - 200 mA
VCORE = 1.1 V, RL = 3.9 Ω
VIN = 3.3 V
VIN = 5 V
Output Voltage Ripple
Switching Waveforms
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V, VCORE = 1.1 V
RL = 120 Ω
RL = 3.9 Ω
RL = 12 Ω
VIN = 3.3 V
VIN = 5 V
Switching Frequency
Efficiency
VIN = 2.6 V to 6 V, VCORE = 1.1 V
Buck Converter 2 (VIO1
)
VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
Line Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 500 mA
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 1.7 V, RL = 27 Ω
VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
Load Regulation
Line Transient Response
Load Transient Response
VIN = 3.3 V
VIN = 5 V
Output Voltage Ripple
Switching Waveforms
VIO1 = 1.7 V, RL = 27 Ω
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V, VIO1 = 1.7 V
RL = 270 Ω
RL = 27 Ω
RL = 27 Ω
Switching Frequency
Load Regulation
VIN = 2.6 V to 6 V, VIO1 = 1.7 V
LDO Regulator (VIO2
)
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
Line Transient Response
Load Transient Response
Output Voltage Ripple
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA - 100 mA
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
10
Typical Characteristics
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SLVSC21 –OCTOBER 2013
FUNCTIONAL BLOCK
PARAMETER
Efficiency
TEST CONDITIONS
VIN = 3.7 V, AVDD = 8.4 V, VGH = 16 V, 24 V, 31 V
FIGURE
Boost Converter 2 (VGH
)
Figure 4-42
Figure 4-43
Figure 4-44
Figure 4-45
Figure 4-46
Line Regulation
VIN = 3.7 V, AVDD = 7 V to 10.1 V, VGH = 24 V, IGH = 10 mA
VIN = 3.7 V, AVDD = 8.4 V, VGH = 24 V, IGH = 1 mA to 50 mA
Load Regulation
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V (RL = 82
Ω), VGH = 24 V
RL = 4.8 kΩ
RL = 1.2 kΩ
Load Transient Response
Output Voltage Ripple
Switching Waveforms
VIN = 3.3V V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V
VIN = 3.3 V, AVDD = 8.4 V(RL = 82 Ω), VGH = 24 V
VIN = 3.3 V, AVDD = 7 V, 8.4 V, 10.1 V, VGH = 16 V to 31 V
IGH = 5 mA - 10 mA
IGH = 10 mA - 30 mA
RL = 4.8 kΩ
Figure 4-47
Figure 4-48
Figure 4-49
Figure 4-50
Figure 4-51
Figure 4-52
Figure 4-53
Figure 4-54
RL = 1.2 kΩ
RL = 4.8 kΩ
RL = 1.2 kΩ
Switching Frequency
VIN, VIO1, VIO2, VCORE
Power-Up Behavior
VIN = 3.3 V, tSS1 = 0.5 ms, VIO1 = 2.5 V, VIO2 = 1.8 V, VCORE
1.1 V
=
RL = 3.9 Ω
EN, AVDD, VGH
VIN = 3.3 V, tSS2 = 4 ms, AVDD = 8.1 V (RL = 33 Ω), VGH = 24 tDLY1 = 0 ms
Figure 4-55
Figure 4-56
Figure 4-57
Figure 4-58
Figure 4-49
Figure 4-60
Figure 4-61
Figure 4-62
Figure 4-63
Figure 4-64
Figure 4-65
Figure 4-66
Figure 4-67
V (RL = 1.2 kΩ)
tDLY1 = 10 ms
XAO, AVDD, VGH, VGHM
XAO, AVDD, VGH, VGHM
VIN = 3.3 V, AVDD = 8.1 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ), GIP = 0
tDLY6 = 0 ms
tDLY6 = 10 ms
tDLY6 = 0 ms
tDLY6 = 10 ms
VIN = 3.3 V, AVDD = 8.1 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ), GIP = 1
AVDD, VGH, VCOM, VGAMA
RST, VIO1, VIO2, VCORE
VIN = 3.3 V, AVDD = 8.1 V, VGH = 24 V, VCOM = 4.05 V, VGAMA = 4.05 V
Power-Down Behavior
VDET = 2.5 V
RMODE = 0
RMODE = 1
VIN, XAO, AVDD, VGHM
GIP = 0
AVDD, VGH, VCOM, VGAMA
SMODE = 0
SMODE = 1
Gate Voltage Shaping
Op-Amp
FLK, VGHM
VIN = 3.3 V, RE = 1 kΩ, CL = 10 nF, AVDD = 8.4 V (RL = 33 Ω), VGH = 24 V (RL = 1.2
kΩ)
Large-Signal Response
Small-Signal Bandwidth
Gain Bandwidth
AVDD = 8.4 V, VPOS = 3.8 V ±0.5 V
Figure 4-68
Figure 4-69
Figure 4-70
Figure 4-71
Figure 4-72
Figure 4-73
AVDD = 8.4 V, VPOS = 4 V + 65 mVPP, AV = +1, RF = 0 Ω
AVDD = 8.4 V, VPOS = 4 V + 65 mVPP, AV = +1, RF = 0 Ω
VIN = 3.3 V, AVDD = 8.4 V, RL = 2 kΩ to AVDD / 2, CL = 1 μF
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V, VCOM = 4 V, RL = ∞
Peak Output Current
Line Transient Response
Output Voltage Ripple and VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VCOM = 4 V, RL = ∞
Noise
Programmable Gamma
Dynamic Response
AVDD = 8.4 V, RL = 909 k, CL = 55 pF
GAMA = 0x0ff to
0x2ff
Figure 4-74
Figure 4-75
GAMA = 0x2ff to
0x0ff
Line Transient Response
VIN = 3 V to 4.8 V (dV/dt = 7.5 V/ms), AVDD = 8.4 V (RL = 82
Ω)
GAMA = 0x0ff
GAMA = 0x1ff
GAMA = 0x2ff
GAMA = 0x1ff
Figure 4-76
Figure 4-77
Figure 4-78
Figure 4-79
Output Voltage Ripple and VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω)
Noise
Copyright © 2013, Texas Instruments Incorporated
Typical Characteristics
11
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Boost Converter 1 — Efficiency
Boost Converter 1 — Efficiency
VIN = 3.3 V, AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V
VIN = 5 V, AVDD = 7 V, 8.4 V, 9.4 V, 10.1 V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
AVDD = 7.0 V
AVDD = 7.0 V
AVDD = 8.4 V
AVDD = 9.4 V
AVDD = 8.4 V
AVDD = 9.4 V
AVDD = 10.1 V
L=Toko 1269AS-H-4R7M
L=Toko 1269AS-H-4R7M
AVDD = 10.1 V
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Iout - Output Current - mA
Iout - Output Current - mA
G401
G402
Figure 4-1.
spacer
Figure 4-2.
spacer
Boost Converter 1 — Line Regulation
Boost Converter 1 — Load Regulation
VIN = 2.6 V to 6 V, AVDD = 8.4 V, IAVDD = 100 mA
8.55
VIN = 3.3 V, 5 V, AVDD = 8.4 V, IAVDD = 1 mA to 500 mA
8.55
8.50
8.45
8.40
8.35
8.30
8.25
8.50
8.45
8.40
8.35
8.30
VIN = 3.3 V
L=Toko 1269AS-H-4R7M
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
8.25
2.6
3.1
3.6
4.1
4.6
5.1
5.6
0
50 100 150 200 250 300 350 400 450 500
VIN - Input Voltage - V
IAVDD - Output Current - mA
G403
G404
Figure 4-3.
spacer
Figure 4-4.
spacer
Boost Converter 1 — Line Transient Response
Boost Converter 1 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL = 82 Ω
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL= 33 Ω
Figure 4-5.
Figure 4-6.
12
Typical Characteristics
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Boost Converter 1 — Load Transient Response
Boost Converter 1 — Load Transient Response
VIN = 3.3 V, AVDD = 8.4 V, IAVDD = 20 mA - 200 mA
VIN = 5 V, AVDD = 8.4 V, IAVDD = 20 mA - 200 mA
Figure 4-7.
spacer
Figure 4-8.
spacer
Boost Converter 1 — Output Voltage Ripple
Boost Converter 1 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.4 V, RL = 82 Ω
VIN = 5 V, AVDD = 8.4 V, RL = 82 Ω
Figure 4-9.
spacer
Figure 4-10.
spacer
Boost Converter 1 — Switching Waveforms
Boost Converter 1 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V, RL = 820 Ω
VIN = 3.3 V, AVDD = 8.4 V, RL = 82 Ω
Figure 4-11.
spacer
Figure 4-12.
spacer
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Typical Characteristics
13
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Buck Converter 1 — Efficiency
Boost Converter 1 — Switching Frequency
VIN = 3.4 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500
VIN = 2.6 V to 6 V, AVDD = 7 V, 8.4 V, 10.1 V, RL = 82 Ω
mA
100
1,500
90
80
70
60
50
40
30
1,300
1,100
900
700
VCORE = 1.0 V
AVDD=7.0V
20
VCORE = 1.1 V
500
AVDD=8.4V
10
VCORE = 1.2 V
L=Toko 1269AS-H-4R7M
L=Toko 1269AS-H-2R2M
AVDD=10.1V
VCORE = 1.3 V
300
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
50 100 150 200 250 300 350 400 450 500
VIN - Input Voltage - V
ICORE - Output Current - mA
G413
G416
Figure 4-13.
spacer
Figure 4-14.
spacer
Buck Converter 1 — Efficiency
Buck Converter 1 — Line Regulation
VIN = 5 V, VCORE = 1 V, 1.1 V, 1.2 V, 1.3 V, ICORE = 1 mA to 500 mA
VIN = 2.6 V to 6 V, VCORE = 1.1 V, ICORE = 300 mA
1.15
100
90
80
70
60
50
40
30
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
1.05
VCORE = 1.0 V
20
VCORE = 1.1 V
10
VCORE = 1.2 V
L=Toko 1269AS-H-2R2M
L=Toko 1269AS-H-4R7M
VCORE = 1.3 V
0
0
50 100 150 200 250 300 350 400 450 500
2.6
3.1
3.6
4.1
4.6
5.1
5.6
ICORE - Output Current - mA
VIN - Input Voltage - V
G417
G416
Figure 4-15.
spacer
Figure 4-16.
spacer
Buck Converter 1 — Load Regulation
Buck Converter 1 — Line Transient Response
VIN = 3.4 V, 5 V, VCORE = 1.1 V, ICORE = 0 mA to 500 mA
VIN = 3 V to 4.8 V, VCORE = 1.1 V, RL = 3.9 Ω
1.15
1.14
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
1.05
VIN = 3.4 V
VIN = 5.0 V
L=Toko 1269AS-H-2R2M
0
50 100 150 200 250 300 350 400 450 500
ICORE - Output Current - mA
G419
Figure 4-17.
spacer
Figure 4-18.
14
Typical Characteristics
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Buck Converter 1 — Load Transient Response
Buck Converter 1 — Load Transient Response
VIN = 3.3 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
VIN = 5 V, VCORE = 1.1 V, ICORE = 50 mA - 200 mA
Figure 4-19.
Figure 4-20.
spacer
Buck Converter 1 — Output Voltage Ripple
Buck Converter 1 — Output Voltage Ripple
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
VIN = 5 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-21.
spacer
Figure 4-22.
spacer
Buck Converter 1 — Switching Waveforms
Buck Converter 1 — Switching Waveforms
VIN = 3.3 V, VCORE = 1.1 V, RL = 120 Ω
VIN = 3.3 V, VCORE = 1.1 V, RL = 3.9 Ω
Figure 4-23.
spacer
Figure 4-24.
Copyright © 2013, Texas Instruments Incorporated
Typical Characteristics
15
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Buck Converter 1 — Switching Frequency
VCORE = 1.1 V, RL = 12 Ω
Buck Converter 2 — Efficiency
VIN = 3.3 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
1,700
1,500
1,300
1,100
900
100
90
80
70
60
50
40
30
700
20
VIO1 = 1.7 V
500
10
0
VIO1 = 1.8 V
VIO1 = 2.5 V
L=Toko 1269AS-H-2R2M
L=Toko 1269AS-H-2R2M
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
50 100 150 200 250 300 350 400 450 500
VIN - Input Voltage - V
IIO1 - Output Current - mA
G425
G428
Figure 4-25.
Figure 4-26.
spacer
Buck Converter 2 — Efficiency
Buck Converter 2 — Line Regulation
VIN = 5 V, VIO1 = 1.7 V, 1.8 V, 2.5 V, IIO1 = 1 mA to 500 mA
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, IIO1 = 100 mA
1.80
100
90
80
70
60
50
40
30
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
20
VIO1 = 1.7 V
10
0
VIO1 = 1.8 V
VIO1 = 2.5 V
L=Toko 1269AS-H-2R2M
L=Toko 1269AS-H-2R2M
0
50 100 150 200 250 300 350 400 450 500
2.6
3.1
3.6
4.1
4.6
5.1
5.6
IIO1 - Output Current - mA
VIN - Input Voltage - V
G429
G428
Figure 4-27.
spacer
Figure 4-28.
spacer
Buck Converter 2 — Load Regulation
Buck Converter 2 — Line Transient Response
VIN = 3.4 V, 5 V, VIO1 = 1.7 V, IIO1 = 1 mA to 500 mA
1.80
VIN = 3 V to 4.8 V, VIO1 = 1.7 V, RL = 27 Ω
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
VIN = 3.4 V
1.62
L=Toko 1269AS-H-2R2M
VIN = 5.0 V
1.60
0
50 100 150 200 250 300 350 400 450 500
IIO1 - Output Current - mA
G431
Figure 4-29.
spacer
Figure 4-30.
16
Typical Characteristics
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Buck Converter 2 — Load Transient Response
Buck Converter 2 — Load Transient Response
VIN = 3.3 V, VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
VIN = 5 V, VIO1 = 1.7 V, IIO1 = 50 mA - 100 mA
Figure 4-31.
Figure 4-32.
spacer
Buck Converter 2 — Output Voltage Ripple
Buck Converter 2 — Output Voltage Ripple
VIN = 3.3 V, VIO1 = 1.7 V, RL = 27 Ω
VIN = 5 V, VIO1 = 1.7 V, RL = 27 Ω
Figure 4-33.
spacer
Figure 4-34.
spacer
Buck Converter 2 — Switching Waveforms
Buck Converter 2 — Switching Waveforms
VIN = 3.3 V, VIO1 = 1.7 V, RL = 270 Ω
VIN = 3.3 V, VIO1 = 1.7 V, RL = 27 Ω
Figure 4-35.
spacer
Figure 4-36.
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Buck Converter 2 — Switching Frequency
VIN = 2.6 V to 6 V, VIO1 = 1.7 V, RL = 27 Ω
LDO Regulator — Load Regulation
VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 1 mA to 100 mA
1.85
2,000
1,900
1,800
1,700
1,600
1,500
1,400
1,300
1,200
1,100
1,000
1.83
1.81
1.79
1.77
1.75
L=Toko 1269AS-H-2R2M
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
10
20
30
40
50
60
70
80
90 100
VIN - Input Voltage - V
IIO2 - Output Current - mA
G437
G438
Figure 4-37.
Figure 4-38.
spacer
LDO Regulator — Line Transient Response
LDO Regulator — Load Transient Response
VIN = 3 V to 4.8 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
VIN = 3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, IIO2 = 50 mA - 100 mA
Figure 4-39.
Figure 4-40.
Boost Converter 2 — Efficiency
(AVDD losses are excluded)
LDO Regulator — Output Voltage Ripple
VIN =3.3 V, VIO1 = 2.5 V, VIO2 = 1.8 V, RL = 27 Ω
VIN = 3.7 V, AVDD = 8.4 V, VGH = 16 V, 24 V, 31 V
100
90
80
70
60
50
40
30
20
VGH = 16 V
VGH = 24 V
10
L=Murata LQH3NPN150NG0
VGH = 31 V
0
0
10
20
30
40
50
IGH - Output Current - mA
G444
Figure 4-41.
Figure 4-42.
18
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Boost Converter 2 — Line Regulation
Boost Converter 2 — Load Regulation
VIN = 3.7 V, AVDD = 7 V to 10.1 V, VGH = 24 V, IGH = 10 mA
VIN = 3.7 V, AVDD = 8.4 V, VGH = 24 V, IGH = 1 mA to 50 mA
24.20
24.20
24.15
24.10
24.05
24.00
23.95
23.90
23.85
24.15
24.10
24.05
24.00
23.95
23.90
23.85
L=Murata LQH3NPN150NG0
L=Murata LQH3NPN150NG0
23.80
23.80
7
7.5
8
8.5
9
9.5
10
0
5
10
15
20
25
30
35
40
45
50
AVDD - Input Voltage - V
IGH - Output Current - mA
G443
G446
Figure 4-43.
spacer
Figure 4-44.
spacer
Boost Converter 2 — Line Transient Response
Boost Converter 2 — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-45.
spacer
Figure 4-46.
Boost Converter 2 — Load Transient Response
Boost Converter 2 — Load Transient Response
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, IGH = 5 mA - 10 VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, IGH = 10 mA - 30
mA
mA
Figure 4-47.
Figure 4-48.
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Boost Converter 2 — Output Voltage Ripple
Boost Converter 2 — Output Voltage Ripple
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-49.
Figure 4-50.
Boost Converter 2 — Switching Waveforms
Boost Converter 2 — Switching Waveforms
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 4.8k
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VGH = 24 V, RL = 1.2k
Figure 4-51.
Figure 4-52.
Boost Converter 2 — Switching Frequency
AVDD = 7 V, 8.4 V, 10.1 V, VGH = 16 V to 31 V, RL = 4.8 kΩ
Power-Up Sequencing
VIN, VIO1, VIO2, VCORE
550
500
450
400
350
AVDD=7.0V
300
AVDD=8.4V
L=Murata LQH3NPN150NG0
AVDD=10.1V
250
16
18
20
22
24
26
28
30
VGH - Output Voltage - V
G453
Figure 4-53.
Figure 4-54.
20
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Power-Up Sequencing
Power-Up Sequencing
EN, AVDD, VGH (tDLY1 = 0 ms)
EN, AVDD, VGH (tDLY1 = 10 ms)
Figure 4-55.
Figure 4-56.
Power-Up Sequencing — GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-Up Sequencing — GIP = 0
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-57.
Figure 4-58.
Power-Up Sequencing — GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 0 ms
Power-Up Sequencing — GIP = 1
XAO, AVDD, VGH, VGHM, tDLY6 = 10 ms
Figure 4-59.
Figure 4-60.
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Power-Up Sequencing
AVDD, VGH, VCOM, VGAMA
Power-Down Sequencing — RMODE = 0
VDET = 2.5 V, RST, VIO1, VIO2, VCORE
Figure 4-61.
Figure 4-62.
Power-Down Sequencing – RMODE = 1
VDET = 2.5 V, RST, VIO1, VIO2, VCORE
Power-Down Sequencing — GIP = 0
VIN, XAO, AVDD, VGHM
Figure 4-63.
Figure 4-64.
Power-Down Sequencing — SMODE = 0
AVDD, VGH, VCOM, VGAMA
Power-Down Sequencing — SMODE = 1
AVDD, VGH, VCOM, VGAMA
Figure 4-65.
Figure 4-66.
22
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Gate Voltage Shaping — FLK, VGHM
VIN = 3.3 V, AVDD = 8.4 V (RL = 33 Ω), VGH = 24 V (RL = 1.2 kΩ), RE
= 1 kΩ, CL = 10 nF
VCOM Buffer — Large Signal Response
AVDD = 8.4 V, RL = 82 Ω, VPOS = 3.8 V + 0.5 Vpp
Figure 4-67.
Figure 4-68.
VCOM Buffer — Small-Signal Bandwidth
AVDD = 8.4 V, VPOS = 4 V + 65 mVpp
VCOM Buffer — Gain-Bandwidth Product
AVDD = 8.4 V, VPOS = 4 V + 65 mVpp
Figure 4-69.
Figure 4-70.
VCOM Buffer — Peak Output Current
VCOM Buffer — Line Transient Response
VIN = 3.3 V, AVDD = 8.4 V, RL = 2k to AVDD / 2, CL = 1 μF
VIN = 3 V to 4.8 V, AVDD = 8.4 V, RL = 82 Ω, VCOM = 4 V, RL = ∞
Figure 4-71.
Figure 4-72.
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VCOM Buffer — Output Voltage Ripple and Noise
Programmable GAMMA — Dynamic Response
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), VCOM = 4 V, RL = ∞
GAMA = 0x0ff to 0x2ff, RL = 909 kΩ, CL = 55 pF
Figure 4-73.
Figure 4-74.
GAMMA Voltage — Dynamic Response
Programmable GAMMA — Line Transient Response
GAMA = 0x2ff to 0x0ff, RL= 909 kΩ, CL= 55 pF
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x0ff
Figure 4-75.
Figure 4-76.
Programmable GAMMA — Line Transient Response
Programmable GAMMA — Line Transient Response
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x1ff
VIN = 3 V to 4.8 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x2ff
Figure 4-77.
Figure 4-78.
24
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Programmable GAMMA — Output Voltage Ripple and Noise
VIN = 3.3 V, AVDD = 8.4 V (RL = 82 Ω), GAMA = 0x1ff
Figure 4-79.
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5 Detailed Description
Figure 5-1 shows an internal block diagram of the TPS65642A device.
EN
Internal
VUVLO
+
–
XAO
RST
Sequencing
VDET
+
–
SW2
VIN
Buck 1
Buck 2
VCORE
SW3
VIO1
LDO
VIO2
SW1
Boost 1
Boost 2
COMP
AVDD
SW4
VGH
Temperature
Compensation
TCOMP
VGHM
RE
Gate Voltage
Shaping
FLK
AVDD
RSET
OUTA
OUTN
Programmable
Gamma
Programmable
VCOM
AVDD
OUT1
POS1
NEG1
+
–
POS2
NEG2
+
–
OUT2
SCL
SDA
WP
I2C
Interface
Internal
Figure 5-1. Internal Block Diagram
26
Detailed Description
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5.1 BOOST CONVERTER 1 (AVDD)
Boost converter 1 is synchronous and uses a virtual current mode topology that:
•
•
Achieves high efficiencies
Allows the converter to work in continuous-conduction mode under all operating conditions, which
simplifies compensation
•
•
Provides a better drive signal for the negative charge pump connected to the switch node (because the
converter always runs in continuous-conduction mode, even at low output currents)
Provides true input-output isolation when the boost converter is disabled
VIN
AVDD
VIN
SW1
Q1B
AVDD
AVDD
FREQ
PWM
VREF
+
–
Control
AVDD
SMODE
UVLO
&
Q1A
Q2
GND
COMP
Figure 5-2. Boost Converter 1 Internal Block Diagram
5.1.1 Switching Frequency (Boost Converter 1)
The nominal switching frequency of boost converter 1 can be programmed to 750 kHz or 1200 kHz using
the FREQ bit in the MISC register. The factory default value is 1200 kHz.
5.1.2 Compensation (Boost Converter 1)
Boost converter 1 uses an external compensation network connected to the COMP pin to stabilize its
feedback loop. A simple series R-C network connected between the COMP pin and ground is sufficient to
achieve good performance, in effect, stable and with good transient response. Good starting values, which
will work for most applications, are 100 kΩ and 1 nF for 1200 MHz AVDD switching frequency and 56 kΩ
and 1.5 nF for 750 kHz AVDD switching frequency.
In some applications (for example, those using electrolytic output capacitors), it may be necessary to
include a second compensation capacitor between the COMP pin and ground. This has the effect of
adding an additional pole in the frequency response of the feedback loop, which cancels the zero
introduced by the ESR of the output capacitor.
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The COMP pin is directly connected to the input current comparator of the converter, which means that
any noise present on this pin can directly affect converter operation. In practical applications the most
likely source of noise is the switch pin on the converter, and for proper operation it is essential that the
stray capacitance between the SW1 and the COMP pins is minimized. This can be ensured using good
PCB layout practices, namely:
•
•
Locating the compensation components close to the COMP pin
Removing the GND plane from underneath the SW1 PCB tracks (to prevent this high dV/dt signal from
inducing currents locally in the GND plane)
•
Connecting the ground side of the compensation components to a noise-free GND location, in effect,
away from noisy power ground signals
NOTE
For the most robust operation TI recommends to ensure that the parasitic capacitance
between the SW1 and COMP is below 0.1 pF.
5.1.3 Power Up (Boost Converter 1)
Boost converter 1 starts tDLY1 milliseconds after EN or RST goes high, whichever occurs later. Delay time
tDLY1 can be programmed from 0 ms to 70 ms using the DLY1 register. Once asserted, the EN signal must
remain high to ensure normal device operation. Once disabled (EN = 0), boost converter 1 remains
disabled until the device is powered down (even if EN is re-asserted).
To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS2 milliseconds.
Start-up time tSS2 can be programmed from 4 ms to 7.5 ms using the SS2 register. Longer soft-start times
generate lower inrush currents.
The same ramp rate is also used for boost converter 2 – changing the SS2 register affects both boost
converters.
The soft-start function is not implemented if the output voltage of boost converter 1 is re-programmed
during operation. During normal operation (when AVDD remains constant) the non-implementation of soft-
start is not a problem, however, it may cause problems during production if AVDD is changed while the
converter is enabled. Problems can occur under such conditions because, without a soft-start, the
converter draws a high inrush current when the output voltage of the converter is changed. If the converter
is supplied from a high-impedance source, this inrush current can, under certain circumstances, pull VIN
below the UVLO threshold, disabling the IC and interrupting the writing of the configuration parameters.
Use one or more of the following recommendations to ensure trouble-free configuration during production:
•
•
Program the configuration parameters before the IC is soldered to the PCB
Supply the PCB with a voltage high enough to ensure that the voltage on the VIN pin remains above
the UVLO threshold when the value of AVDD is changed
•
•
Ensure that the supply impedance is low enough to ensure that the voltage on the VIN pin remains
above the UVLO threshold when the value of AVDD is changed
Disable boost converter 1 while the value of AVDD is changed
5.1.4 Power Down (Boost Converter 1)
Boost converter 1 is disabled when EN = 0 or VIN<VUVLO. When disabled, boost converter 1 actively
discharges AVDD by turning on Q2. The active discharge feature is disabled by setting SMODE = 1 in the
CONFIG register. Once disabled (EN = 0), boost converter 1 remains disabled until the device powers
down (even if EN is re-asserted).
5.1.5 Isolation (Boost Converter 1)
The synchronous topology of boost converter 1 ensures that AVDD is fully isolated from VIN when the
converter is disabled.
28
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5.1.6 Output Voltage (Boost Converter 1)
The output voltage of boost converter 1 can be programmed from 7 V to 10.1 V in 100 mV steps using the
AVDD register. The factory default setting is 8.4 V.
5.1.7 Input Supply Characteristics
Boost converter 1 exhibits a fast response with excellent line transient performance. Its fast reaction to
changes in input voltage means that excessive input impedance can cause the converter to become
unstable. This can happen, for example, if VIN is supplied via an excessively long cable, in which case the
parasitic inductance of the cable forms a resonant circuit with the input capacitance of the IC. The
following guidelines help avoid such problems and ensure proper operation:
•
•
•
•
Minimize supply cable inductance
Minimize supply cable resistance
Maximize input capacitance
Avoid using ceramic types for the bulk input capacitance
–
Capacitors with higher ESR help to damp any tendency to ring on the part of the input cable
5.2 BUCK CONVERTER 1 (VCORE
)
Buck converter 1 is synchronous and uses a constant off-time topology that offers high efficiency, fast
transient response, and constant ripple-current amplitude under all operating conditions. The output
voltage VCORE can be programmed by the user. The off-time of the converter is inversely proportional to
the output voltage, and therefore is constant when the converter is in regulation. Thus, for a given VIN, the
converter operates at a constant frequency that changes temporarily when the converter reacts to load
changes.
VIN
VCORE
VIN
Q1A
Q1B
GND
PWM
Control
SW2
VREF
VCORE
+
–
VCORE
Figure 5-3. Buck Converter 1 Block Diagram
5.2.1 Output Voltage (Buck Converter 1)
The output voltage of buck converter 1 can be programmed from 1 V to 1.3 V in 100 mV steps. The
factory default setting is 1.1 V.
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5.2.2 Power Up (Buck Converter 1)
Buck converter 1 starts as soon as VIN > VUVLO (the same time buck converter 2 and LDO regulator
starts).
To minimize inrush current during start-up, buck converter 1 ramps VCORE from zero to the final value in
tSS1 milliseconds. Soft-start time tSS1 can be programmed from 0.5 ms to 4 ms using the SS1 register.
The same ramp rate is used for buck converter 2 and the linear regulator. Changing SS1 affects all three
regulators.
5.2.3 Power Down (Buck Converter 1)
Buck converter 1 is disabled when VIN< VUVLO. The output of buck converter 1 is not actively discharged.
5.3 BUCK CONVERTER 2 (VIO1
)
Buck converter 2 is a low-power synchronous-buck converter that in typical applications generates the I/O
supply voltage for the timing controller and source drivers. Buck converter 2 is essentially the same as
buck converter 1: the output voltage VIO1 can be programmed by the user, but the output is actively
discharged during power-down.
VIN
VIO1
VIN
Q2
UVLO
Q1A
Q1B
GND
PWM
Control
SW3
VREF
VIO1
+
–
VIO1
Figure 5-4. Buck Converter 2 Internal Block Diagram
5.3.1 Output Voltage (Buck Converter 2)
The output voltage of buck converter 2 can be programmed to 1.7 V, 1.8 V, or 2.5 V using the VIO
register. The factory default setting is 1.7 V. When VIO1 = 1.7 V or 1.8 V, the LDO regulator is disabled.
5.3.2 Power-Up (Buck Converter 2)
Buck converter 2 starts as soon as VIN > VUVLO (the same time buck converter 1 and LDO regulator
starts), and implements the same voltage ramping as buck converter 1.
5.3.3 Power-Down (Buck Converter 2)
Buck converter 2 is disabled and actively discharges its output when VIN < VUVLO
.
30
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5.4 LDO REGULATOR (VIO2
)
In applications in which the timing controller and source drivers use different I/O voltages, the low-dropout
(LDO) regulator can be used to generate the lower I/O supply voltage VIO2. The LDO regulator is supplied
from the VIO1 pin, which is the output of buck converter 2.
VIO1
VIO2
+
–
DAC
VIO2
Figure 5-5. Linear Regulator Block Diagram
5.4.1 Output Voltage (LDO Regulator)
When VIO1 = 2.5 V, the output voltage of the LDO regulator can be programmed to 1.7 V or 1.8 V using
the VIO register. When VIO1= 1.7 V or 1.8 V, the LDO regulator is disabled (factory default setting). Once
the device is powered up, the EN signal must remain high, to ensure reliable LDO programming.
5.4.2 Power-Up (LDO Regulator)
At power up, the LDO regulator starts as soon as VIN > VUVLO (the same time buck converter 1 and buck
converter 2 starts). The LDO regulator ramps the output linearly from zero to VIO2 in tSS1 milliseconds.
Soft-start time tSS1 can be programmed from 0.5 ms to 4 ms using the SS1 register.
The same ramp rate is used for both buck converters and the LDO regulator. Changing the SS1 register
affects all three regulators.
When the LDO is turned on or turned off during normal device operation (that is: programming VIO1 from
1.7 V to 2.5 V or vice versa), the ramp or discharge characteristic is defined by the load connected to the
LDO.
5.4.3 Power-Down (LDO Regulator)
The LDO regulator is supplied from the VIO1 pin, which is actively discharged during power-down. The
output of the LDO regulator therefore discharges through the body diode of transistor Q1 as long as VIO2
is high enough to forward bias the body diode. Thereafter, VIO2 continues to discharge through the load
connected to it.
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5.5 BOOST CONVERTER 2 (VGH)
Boost converter 2 is non-synchronous, and uses a constant off-time topology. The switching frequency of
the converter is not constant, but automatically adjusts for best performance according to VIN and VGH
.
Boost converter 2 uses peak current control and is designed to operate permanently in discontinuous-
conduction mode (DCM), thereby allowing the internal compensation circuit to achieve stable operation
over a wide range of output voltages and currents, such as when temperature compensation is used.
Figure 5-6 shows a simplified block diagram of boost converter 2.
AVDD
VGH
VGH
AVDD
SW4
PWM
Control
Q1
–
+
27:1
Temperature
Compensation
VGHCOLD
VGHHOT
TCOMP
RT1
GND
RNTC
RT2
Figure 5-6. Boost Converter 2 Block Diagram
Boost converter 2 can be temperature compensated, allowing the output voltage to transition from a
higher voltage at low temperatures VGH(COLD) to a lower voltage at high temperatures VGH(HOT) (see
Figure 5-7 and Figure 5-8). The values of VGH(HOT) and VGH(COLD) are programmed using the VGHHOT and
VGHCOLD registers. The values of THOT and TCOLD are programmed by selecting the appropriate resistor
values for the thermistor network connected to the TCOMP pin.
VGH
VGH(COLD)
VGH(HOT)
TCOLD
THOT
Temperature
Figure 5-7. Boost Converter 2 Temperature Compensation Characteristic
32
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1.429V
DAC1
TCOMP
RT1
+
−
A1
Q1
ISET
0.893V
1.107V
DAC2
RNTC
RT2
R1
R2
+
−
A2
PWM
Controller
0.571V
VGH
R4
R3
R2= 2∙R1
R4= 27∙R3
Figure 5-8. Boost Converter 2 Temperature Compensation Block Diagram
With proper selection of the external components RT1, RT2 and RNTC, temperatures THOT and TCOLD can be
configured to suit the characteristics of each display. A Microsoft Excel® spreadsheet allowing easy
calculation of component values is available from Texas Instruments free of charge.
5.5.1 Power-Up (Boost Converter 2)
When AVDD is finished ramping up, boost converter 2 enables. To minimize inrush current during start-up,
boost converter 2 ramps VGH linearly to the programmed value in tSS2 seconds. Soft-start time tSS2 can be
programmed from 4 ms to 7.5 ms using the SS2 register. The same ramp rate is also used for boost
converter 1. Changing SS2 affects both boost converters.
5.5.2 Power-Down (Boost Converter 2)
Boost converter 2 is disabled when EN = 0 or VIN< VUVLO. The output of the converter is not actively
discharged when the converter is disabled. Once disabled (EN = 0), boost converter 2 remains disabled
until the device is powered down (even if EN is re-asserted).
5.5.3 Setting the Output Voltage (Boost Converter 2)
(1)
The output voltage of boost converter 2 at cold temperatures can be programmed from 25 V to 40 V
using the VGHCOLD register. The output voltage of boost converter 2 at hot temperatures can be
programmed from 16 V to 31 V using the VGHHOT register.
In applications that do not require temperature compensation, the TCOMP pin must be tied to ground and
the VGHHOT register must set the voltage of VGH
.
See Figure 5-8 and note that between VGHHOT and VGHCOLD, the output voltage of boost converter 2 is
given by Equation 1.
V
= 28 ´ V
(
+ 3 ´ V
(
- V
)
)
GH
DAC2
TCOMP DAC2
(1)
Equation 1 calculates the voltage required on the TCOMP pin at temperatures THOT and TCOLD
.
V
GHHOT
V
=
TCOMPHOT
28
(2)
(3)
2 ´ V
+ V
GHCOLD
GHHOT
V
=
TCOMPCOLD
84
(1) Output voltages greater than 36 V require an external cascode transistor.
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Equation 4 calculates the appropriate value for RT2
-b ± b2 - 4ac
RT2
=
2a
where
•
V
- V
TCOMPCOLD
TCOMPHOT
a = R
- R
-
NTCCOLD
NTCHOT
I
SET
æ V
ç
- V
ö
÷
ø
TCOMPCOLD
TCOMPHOT
b = R
(
+ R
´
)
NTCCOLD
NTCHOT
I
è
SET
•
æ V
ç
- V
ö
TCOMPCOLD
TCOMPHOT
c = R
(
´ R
´
)
÷
NTCCOLD
NTCHOT
I
è
SET
ø
•
•
•
RNTCCOLD is the resistance of the thermistor at temperature TCOLD
RNTCHOT is the resistance of the thermistor at temperature THOT
(4)
Once the value of RT2 has been calculated, use Equation 5 to calculate the appropriate value of RT1.
æ V
ç
ö
÷
ø
æ R
ç
´ R
ö
TCOMPCOLD
NTCCOLD
T2
R
= ´
-
÷
RT1
I
R
+ R
è
SET
è
NTCCOLD
T2 ø
(5)
5.5.4 Protection (AVDD, VCORE, VIO1, VIO2, VGH)
Each voltage regulator is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if a regulator output falls below 70% of the programmed voltage for longer than 50
ms, in which case the IC is disabled. To recover normal operation following an undervoltage condition, the
cause of the error condition must be removed and the supply voltage, VIN, must be cycled. A short-circuit
condition is detected if a regulator output falls below 30% of its programmed voltage, in which case the IC
is disabled immediately. To recover normal operation following a short-circuit condition, the cause of the
error must be removed and the supply voltage,VIN, must be cycled.
5.6 RESET GENERATOR
The RST pin generates an active-low reset signal for the timing controller. During power up, the reset
timer starts when VCORE has finished ramping. The reset pulse duration tRESET can be programmed from 2
ms to 16 ms using the RESET register. The RST signal is latched when it goes high and is not taken low
again until the device is powered down (even if VCORE temporarily falls out of regulation). The active
power-down threshold (VUVLO or VDET) can be selected using the RMODE bit in the CONFIG register.
The RST output is an open-drain type that requires an external pullup resistor. Pullup-resistor values in
the range 10 kΩ to 100 kΩ are recommended for most applications.
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5.7 GATE VOLTAGE SHAPING
The gate-voltage shaping function reduces image sticking in LCD panels by modulating the gate ON
voltage (VGH) of the LCD panel. Figure 5-9 shows a block diagram of the gate voltage shaping function
and Figure 5-10 shows the typical waveforms during operation.
VGH
VGH
Q1
FLK
VGHM
Control
Logic
VGHM
FLK
Q2
RE
RE
Figure 5-9. Gate-Voltage Shaping Block Diagram
VPG4
VIO2
FLK
Don’t Care
VGH
tDLY6
VGHM
Figure 5-10. Gate-Voltage Shaping Waveforms
Gate-voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2 is off, and VGHM is
equal to VGH. When FLK is low, Q1 is turned off, Q2 is turned on, and the LCD-panel load connected to
the VGHM pin discharges through the external resistor connected to the RE pin. This resistor is typically
connected to GND or AVDD
.
During power-up Q2 is held permanently on and Q1 permanently off, regardless of the state of the FLK
signal, until tDLY6 milliseconds after boost converter 2 (VGH) has finished ramping. The value of tDLY6 can
be programmed from 0 ms to 35 ms using the DLY6 register.
During power-down Q1 is held permanently on and Q2 permanently off, regardless of the state of the FLK
signal.
Non-GIP or Non-ASG panels that do not use the gate-voltage shaping function must leave the RE pin
floating and connect the FLK pin to GND.
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5.8 PANEL RESET / LCD BIAS READY (XAO)
The TPS65642A device provides an output signal through the XAO pin that is used to reset a level-shifter
or gate-driver IC during power up and power down. The GIP bit in the CONFIG register defines whether
the XAO pin works in GIP mode or non-GIP mode.
The primary purpose of the XAO signal in non-GIP applications is to drive the outputs of the display-panel
gate-driver IC high during power down by generating an active-low signal. When the GIP = 0, the XAO pin
is pulled low whenever VIN < VDET. The VDET threshold voltage can be configured using the VDET register.
When the GIP = 1, the XAO output is used to delay the start of level-shifter activity during power up. The
delay time tDLY6 starts when VGH is done ramping up, and can be configured using the DLY6 register.
The XAO output is an open-drain type and requires an external pull up, typically in the range 10 kΩ to 100
kΩ.
5.9 PROGRAMMABLE VCOM CALIBRATOR
The programmable VCOM calibrator uses a digital-to-analog converter (DAC) to generate an offset current
IDAC for an external resistor divider connected to AVDD (see Figure 5-11 and Figure 5-12). Higher values of
the 7-bit digital word N written to the DAC generate higher IDAC sink currents, and therefore lower VCOM
voltages.
Figure 5-11 shows the recommended circuit for the most commonly used application, when the LCD panel
requires only one VCOM supply voltage. The second op-amp is shown wired as a unity-gain buffer with an
input tied to GND (the recommended configuration if a second op-amp is not used), however, using a
second op-amp for other purposes, such as generating a half-AVDD supply rail, is acceptable.
AVDD
R3
IDAC
POS1
POS1
NEG1
VCOM
DAC
+
–
OUT1
VCOM1
R5
ISET
SMODE
&
VIN < VUVLO
VFB1
VREF
+
POS2
NEG2
–
+
–
OUT2
VCOM2
RSET
RSET
Figure 5-11. Single-Programmable VCOM Supply
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The external resistor RSET generates a reference current ISET for the DAC. Since this reference current is
also used by the temperature compensation function of boost converter 2, care must be taken to ensure
that a suitable value is chosen. For most applications, a value of 24.9 kΩ is recommended, which
generates a reference current given by Equation 6.
V
REF
I
=
SET
R
SET
1.25 V
I
=
= 50.2mA
SET
24.9 W
(6)
(7)
The output current IDAC sunk by the DAC is given by Equation 7.
N + 1 ´I
(
)
SET
I
=
DAC
128
where
•
N is the 7-bit word written to the DAC, and ranges from 0 to 127
Equation 8 and Equation 9 can calculate appropriate values for R3 and R5.
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ V
+ DVCOM
)
(
COM(MAX)
(8)
(9)
128 ´ DV
´ R3
COM
R5 =
127 ´ I
(
´R3 - 128 ´ DV
) (
COM
)
SET
Figure 5-12 shows the recommended connection for the case when two VCOM supplies VCOM1 and VCOM2
are to be generated.
AVDD
R3
IDAC
POS1
POS1
NEG1
VCOM
DAC
+
–
OUT1
VCOM1
ISET
SMODE
&
VIN < VUVLO
R4
VFB1
VREF
+
POS2
NEG2
–
+
–
OUT2
VCOM2
R5
RSET
RSET
VFB2
Figure 5-12. Dual-Programmable VCOM Supplies
In Figure 5-12, the voltage VCOM2 generated by the second op-amp is slightly lower than VCOM1. If two
identical VCOM supplies are required, these can be generated by setting R4 = 0.
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Equation 10 through Equation 12 calculate the correct values for R3 through R5 for the case when two
(slightly different) VCOM voltages are required.
128 ´ DVCOM ´ AVDD
R3 =
ISET ´ 127 ´ VCOM1(MAX) + DVCOM
(
)
(10)
(11)
(12)
æ
ö
æ
÷´
ç
V
ö
128 ´ DV
´ R3
COM2(MAX)
COM
R4 = ç
÷
÷
ø
ç
è
÷ ç
V
127 ´ I ´ R3 - 128 ´ DV
) (
SET COM
(
)
COM1(MAX)
è
ø
æ
ö
V
- V
æ
ö
128 ´ DV
´R3
COM1(MAX)
COM2(MAX)
COM
R5 = ç
÷ ´
÷
ø
ç
ç
è
÷
÷
ø
ç
è
V
127 ´ I ´ R3 - 128 ´ DV
( ) (
SET COM
)
COM1(MAX)
A Microsoft Excel spreadsheet is available free of charge that calculates the values of R3, R4 and R5 —
contact a local TI sales representative for a copy.
5.9.1 Operational Amplifier Performance
Like most operation amplifiers (op amps), the VCOM op amps are not designed to drive purely capacitive
loads, so TI does not recommend to connect a capacitor directly to the outputs of the op amps in an
attempt to increase performance; however, the amplifiers are capable of delivering high peak currents that
make such capacitors unnecessary.
High-speed op amps such as those in the TPS65642A device require care when using them. The most
common problem is when parasitic capacitance at the inverting input creates a pole with the feedback
resistor, reducing amplifier stability. Two things can minimize the likelihood of this happening which work
by shifting the pole (which can never be completely eliminated) to a frequency outside the bandwidth of
the op amp, where it has no effect.
1. Reduce the value of the feedback resistor. In applications where no feedback from the panel is used,
the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be
used, a small capacitor (10 pF – 100 pF) across the feedback resistor will minimize ringing.
2. Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB
traces between the feedback resistor and the inverting input, and by removing ground planes and other
copper areas above and below this PCB trace.
5.9.2 Power Up (Programmable VCOM)
The programmable VCOM is enabled when AVDD > ≈ 3 V.
5.9.3 Power Down (Programmable VCOM)
The programmable VCOM supports two kinds of power-down behavior, and the SMODE bit in the CONFIG
register determines which behavior is active (see Figure 5-41 and Figure 5-42).
If SMODE = 0, the active discharge transistor Q1 is permanently disabled; during power-down, VCOM
tracks AVDD until VCOM is too low to support operation. If SMODE = 1, Q1 turns on when VIN < VUVLO
,
actively pulling VCOM low.
5.10 PROGRAMMABLE GAMMA-VOLTAGE GENERATOR
The gamma-voltage correction supplies 14 reference voltages that can be used by the system source
driver IC to match the LCD-panel luminance characteristics more closely to the response of the human
eye.
The gamma-correction voltages can be programmed individually using the I2C interface. During power up,
the default gamma voltage for each channel is loaded from EEPROM into the corresponding DAC.
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During operation, the output voltages of the DAC can be changed by programming new values via the I2C
interface. Values programmed to the DACs but not transferred to EEPROM are lost when power is
removed from the device. The next time the device is powered up, the DACs are programmed with
whatever values are stored in the EEPROM. The current DAC settings can be transferred to EEPROM
(thereby becoming the new default values used during power-up) at any time by sending the appropriate
command to the Control Register through the I2C interface.
AVDD
AVDD
OUTA
GAMA
DAC
OUTN
GAMN
DAC
Figure 5-13. Gamma Correction Block Diagram
The output stages of the gamma correction block are capable of extending close to the supply rails (AVDD
and ground); however, they can only achieve this rail-to-rail performance with the specified accuracy if the
outputs are lightly loaded. The gamma reference outputs are only intended to drive high impedance loads
such as those presented by a gamma buffer or a high impedance source driver input.
The output voltage VGAM of each channel is given by:
N
VGAM
=
×AVDD
1024
where
•
N is the 10-bit digital word programmed to the gamma register and ranges from 0 to 1023
(13)
Any non-used output can be left open and, to save power, must be programmed to the maximum voltage
(approximately 180-µA saving per output).
5.11 CONFIGURATION
The TPS65642A device divides the configuration parameters into two categories:
1. VCOM
2. all other configuration parameters
In typical applications, all configuration parameters except VCOM are programmed by the subcontractor
during PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.
5.11.1 RAM, EEPROM, and Write Protect
Configuration parameters are changed by writing the desired values to the appropriate RAM register(s).
The RAM registers are volatile and their contents are lost when power is removed from the device. By
writing to the Control Register, storing the active configuration in non-volatile EEPROM is possible; during
power up, the contents of the EEPROM are copied into the RAM registers and used to configure the
device.
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An active-high Write Protect (WP) pin prevents the configuration parameters from being changed by
accident. This pin is internally pulled high and must be actively pulled low to access to the EEPROM or
RAM registers. Note that the WP pin disables all I2C traffic to and from the TPS65642A device, and must
also be pulled low during read operations. This is to ensure that noise present on the I2C lines does not
erroneously overwrite the active configuration stored in RAM (which would not be protected by a simple
EEPROM write-protect scheme).
5.11.2 Configuration Parameters (Excluding VCOM)
Table 5-1 shows the memory map of the configuration parameters.
Table 5-1. Configuration Memory Map
REGISTER
ADDRESS
FACTORY
DEFAULT
REGISTER NAME
DESCRIPTION
00h
01h
02h
03h
04h
05h
CONFIG
AVDD
00h
0Eh
00h
00h
00h
05h
Sets miscellaneous configuration bits
Sets the output voltage of boost converter 1
VGHHOT
VGHCOLD
VIO
Sets the output voltage of boost converter 2 at high temperatures
Sets the output voltage of boost converter 2 at low temperatures
Sets the output voltage of buck converter 2 and the LDO regulator
Sets the output voltage of buck converter 1 (VCORE) and the switching
MISC
frequency of boost converter 1 (AVDD
)
06h
SS1
03h
Sets the soft-start time for buck converters 1 and 2 and the linear
regulator
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
SS2
RESET
DLY1
DLY6
VDET
00h
01h
02h
04h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
02h
00h
Sets the soft-start time for boost converters 1 and 2
Sets the reset pulse duration
Sets the boost converter 1 start-up delay
Sets the gate voltage shaping and LCD ready start-up delay
Sets the threshold of the /RST and /XAO signals
Contains the 2 MSBs of the 10-bit gamma voltage A
Contains the 8 LSBs of the 10-bit gamma voltage A
Contains the 2 MSBs of the 10-bit gamma voltage B
Contains the 8 LSBs of the 10-bit gamma voltage B
Contains the 2 MSBs of the 10-bit gamma voltage C
Contains the 8 LSBs of the 10-bit gamma voltage C
Contains the 2 MSBs of the 10-bit gamma voltage D
Contains the 8 LSBs of the 10-bit gamma voltage D
Contains the 2 MSBs of the 10-bit gamma voltage E
Contains the 8 LSBs of the 10-bit gamma voltage E
Contains the 2 MSBs of the 10-bit gamma voltage F
Contains the 8 LSBs of the 10-bit gamma voltage F
Contains the 2 MSBs of the 10-bit gamma voltage G
Contains the 8 LSBs of the 10-bit gamma voltage G
Contains the 2 MSBs of the 10-bit gamma voltage H
Contains the 8 LSBs of the 10-bit gamma voltage H
Contains the 2 MSBs of the 10-bit gamma voltage I
Contains the 8 LSBs of the 10-bit gamma voltage I
Contains the 2 MSBs of the 10-bit gamma voltage J
Contains the 8 LSBs of the 10-bit gamma voltage J
Contains the 2 MSBs of the 10-bit gamma voltage K
Contains the 8 LSBs of the 10-bit gamma voltage K
Contains the 2 MSBs of the 10-bit gamma voltage L
Contains the 8 LSBs of the 10-bit gamma voltage L
GAMMA-A
GAMMA-B
GAMMA-C
GAMMA-D
GAMMA-E
GAMMA-F
GAMMA-G
GAMMA-H
GAMMA-I
GAMMA-J
GAMMA-K
GAMMA-L
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Table 5-1. Configuration Memory Map (continued)
REGISTER
ADDRESS
FACTORY
DEFAULT
REGISTER NAME
DESCRIPTION
24h
02h
Contains the 2 MSBs of the 10-bit gamma voltage M
Contains the 8 LSBs of the 10-bit gamma voltage M
Contains the 2 MSBs of the 10-bit gamma voltage N
Contains the 8 LSBs of the 10-bit gamma voltage N
GAMMA-M
25h
00h
26h
02h
GAMMA-N
Control
27h
00h
FFh
00h
Controls whether read and write operations access RAM or EEPROM
registers
5.11.3 CONFIG (00h)
Figure 5-14. CONFIG Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
RMODE
R/W-0
SMODE
R/W-0
GIP
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-2. CONFIG Register Field Descriptions
Bit
Field
Value
Description
7–3
Not implemented.
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2
1
0
RMODE
SMODE
GIP
Configures the RST power-down threshold voltage.
VUVLO threshold used.
0
1
VDET Threshold used.
Configures the power-down behavior of AVDD and VCOM
AVDD is actively discharged (but not VCOM).
VCOM is actively discharged (but not AVDD).
.
0
1
This bit configures the device for use with either GIP or non-GIP LCD panels.
0
The device operates in non-GIP mode, and XAO functions as a panel reset during power-
down.
1
The device operates in GIP mode, and the XAO functions as an enable for the panel level shifter
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5.11.4 AVDD (01h)
Figure 5-15. AVDD Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
AVDD
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-3. AVDD Register Field Descriptions
Bit
Field
Value
Description
7–4
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
4–0
AVDD
These bits configure boost converter 1's output voltage (AVDD).
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
7.0 V
7.1 V
7.2 V
7.3 V
7.4 V
7.5 V
7.6 V
7.7 V
7.8 V
7.9 V
8.0 V
8.1 V
8.2 V
8.3 V
8.4 V
8.5 V
8.6 V
8.7 V
8.8 V
8.9 V
9.0 V
9.1 V
9.2 V
9.3 V
9.4 V
9.5 V
9.6 V
9.7 V
9.8 V
9.9 V
10.0 V
10.1 V
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5.11.5 VGHHOT (02h)
Figure 5-16. VGHHOT Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VGHHOT
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-4. VGHHOT Register Field Descriptions
Bit
Field
Value Description
7–4
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
3–0
VGHHOT
These bits configure boost converter 2's output voltage (VGH) of at high temperatures.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
16 V
17 V
18 V
19 V
20 V
21 V
22 V
23 V
24 V
25 V
26 V
27 V
28 V
29 V
30 V
31 V
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5.11.6 VGHCOLD (03h)
Figure 5-17. VGHCOLD Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VGHCOLD
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-5. VGHCOLD Register Field Descriptions
Bit
Field
Value
Description
7–4
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
3–0
VGHCOLD
These bits configure boost converter 2's output voltage (VGH) at low temperatures.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
25 V
26 V
27 V
28 V
29 V
30 V
31 V
32 V
33 V
34 V
35 V
36 V
37 V
38 V
39 V
40 V
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5.11.7 VIO (04h)
Figure 5-18. VIO Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VIO
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-6. VIO Register Field Descriptions
Bit
Field
Value
Description
7–2
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
1–0
VIO
These bits configure the output voltage of buck converter 2 (VIO1) and the LDO regulator (VIO2).
Once the device is powered up, the EN signal must remain high, to ensure reliable LDO
programming.
0h
1h
2h
3h
VIO1 = 1.7 V, LDO regulator disabled.
VIO1 = 1.8 V, LDO regulator disabled.
VIO1 = 2.5 V, VIO2 = 1.7 V.
VIO1 = 2.5 V, VIO2 = 1.8 V.
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5.11.8 MISC (05h)
Figure 5-19. MISC Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
FREQ
R/W-1
VCORE
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-7. MISC Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2
FREQ
This bit configures boost converter 1's (AVDD) switching frequency.
0h
750 kHz
1h
1200 kHz
1–0
VCORE
These bits configure buck converter 1's (VCORE) output voltage.
0h
1h
2h
3h
1 V
1.1 V
1.2 V
1.3 V
46
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5.11.9 SS1 (06h)
Figure 5-20. SS1 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
SS1
R/W-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-8. SS1 Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2–0
SS1
These bits configure the soft-start time for buck converter 1 (VCORE), buck converter 2 (VIO1) and
the LDO linear regulator (VIO2).
0h
1h
2h
3h
4h
5h
6h
7h
0.5 ms
1 ms
1.5 ms
2 ms
2.5 ms
3 ms
3.5 ms
4 ms
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5.11.10 SS2 (07h)
Figure 5-21. SS2 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
SS2
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-9. SS2 Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented N/A 0 1 These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2–0
SS2
These bits configure the soft-start time for boost converter 1 (AVDD) and boost converter 2 (VGH).
0h
1h
2h
3h
4h
5h
6h
7h
4 ms
4.5 ms
5 ms
5.5 ms
6 ms
6.5 ms
7 ms
7.5 ms
48
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5.11.11 RESET (08h)
Figure 5-22. RESET Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
RESET
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-10. RESET Register Field Descriptions
Bit
Field
Value
Description
7–2
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
1–0
RESET
These bits configure the duration of the reset pulse during start-up.
0h
1h
2h
3h
2 ms
4 ms
8 ms
16 ms
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5.11.12 DLY1 (09h)
Figure 5-23. DLY1 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY1
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-11. DLY1 Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2–0
DLY1
These bits configure the start-up delay for boost converter 1 (AVDD).
0h
1h
2h
3h
4h
5h
6h
7h
0 ms
10 ms
20 ms
30 ms
40 ms
50 ms
60 ms
70 ms
50
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5.11.13 DLY6 (0Ah)
Figure 5-24. DLY6 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY6
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-12. DLY6 Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2–0
DLY6
These bits configure the delay between VGH reaching its final value and gate voltage shaping or
XAO being enabled.
0h
1h
2h
3h
4h
5h
6h
7h
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
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5.11.14 VDET (0Bh)
Figure 5-25. VDET Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VDET
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-13. VDET Register Field Descriptions
Bit
Field
Value
Description
7–3
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
2–0
VDET
These bits configure the threshold for XAO and RST (if RMODE is "1" in the CONFIG register).
0h
1h
2h
3h
4h
5h
6h
7h
2.2 V
2.3 V
2.4 V
2.5 V
3.6 V
3.7 V
3.8 V
3.9 V
52
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5.11.15 GAMxHI (0Ch, 0Eh…26h)
Figure 5-26. GAMxHI Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
GAMxHI
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-14. GAMxHI Register Field Descriptions
Bit
Field
Value
Description
7–2
Not Implemented
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
1–0
GAMxHI
0h–3h These bits form the two most significant bits of the 10-bit GAMx value used to program the gamma
correction voltage for channel x.
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5.11.16 GAMxLO (0Dh, 0Fh…27h)
Figure 5-27. GAMxLO Register Bit Allocation
7
6
5
4
3
2
1
0
GAMxLO
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-15. GAMxLO Register Field Descriptions
Bit
Field
Value
Description
7–0
GAMxLO
00h–FF These bits form the least significant eight bits of the 10-bit value used to program the gamma
correction voltage for channel x.
h
54
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5.11.17 Control (FFh)
Figure 5-28. CONTROL Register Bit Allocation
7
6
5
4
3
2
1
0
WED
R/W-0
Not Implemented
RED
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-16. CONTROL Register Field Descriptions
Bit
Field
Value
Description
7
WED
Setting this bit forces the contents of all DAC registers to be copied to the EEPROM, thereby
making them the default values during power-up.
0
1
Not used. This bit is automatically reset to 0 when the contents of the DAC registers have
been copied to EEPROM.
The contents of all DAC registers are copied to the EEPROM, making them the new default values
following power-up.
6–1
0
Not Implemented
RED
N/A
These bits are not implemented in hardware. During write operations data for these bits is ignored,
and during read operations 0 is returned.
This bit configures the data returned by read operations.
Read operations return the contents of the DAC registers.
Read operations return the content of the EEPROM registers.
0
1
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5.11.18 Example – Writing to a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of RAM register (00h)
5. TPS65642A acknowledges
6. Bus master sends data to be written
7. TPS65642A acknowledges
8. Bus master sends STOP condition
74h
00h
DATA
RAM Register Address
RAM Register Data
7-Bit Slave Address
P
S
0
A
A
A
Figure 5-29. Writing to a Single RAM Register
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5.11.19 Example – Writing to Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65642A acknowledges
4. Bus master sends address of first RAM register to be written to (00h)
5. TPS65642A acknowledges
6. Bus master sends data to be written to first RAM register
7. TPS65642A acknowledges
8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
9. TPS65642A acknowledges
10. Steps (8) and (9) repeated until data for final RAM register has been sent
11. TPS65642A acknowledges
12. Bus master sends STOP condition
74h
00h
DATA
DATA
RAM Register Address (n)
RAM Register Data (n)
RAM Register Data (n+1)
7-Bit Slave Address
S
0
A
A
A
A
DATA
RAM Register Data (Last)
P
A
Figure 5-30. Writing to Multiple RAM Registers
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5.11.20 Example – Saving Contents of all RAM Registers to EEPROM
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data to be written to the Control Register (80h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
74h
FFh
80h
Control Register Address
Control Register Data
7-Bit Slave Address
P
S
0
A
A
A
Figure 5-31. Saving Contents of all RAM Registers to E2PROM
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5.11.21 Example – Reading from a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of RAM register (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends RAM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
74h
FFh
00h
Control Register Address
Control Register Data
7-Bit Slave Address
S
0
A
A
A
P
R/W
0
74h
00h
74h
DATA
RAM Register Address
RAM Register Data
7-Bit Slave Address
7-Bit Slave Address
S
A
A
Sr
1
A
A
P
Figure 5-32. Reading from a Single RAM Register
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5.11.22 Example – Reading from a Single EEPROM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of EEPROM register (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends EEPROM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
74h
FFh
01h
Control Register Address
Control Register Data
S
7-Bit Slave Address
0
A
A
A
P
74h
00h
74h
DATA
EEPROM Register Address
EEPROM Register Data
S
7-Bit Slave Address
0
A
A
Sr
7-Bit Slave Address
1
A
A
P
Figure 5-33. Reading from a Single EEPROM Register
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5.11.23 Example – Reading from Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of first register to be read (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends contents of first RAM register to be read
18. Bus master acknowledges
19. TPS65642A sends contents of second RAM register to be read
20. Bus master acknowledges
21. TPS65642A sends contents of third (last) RAM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
74h
FFh
00h
7-Bit Slave Address
Control Register Address
Control Register Data
S
0
A
A
A
P
R/W
0
74h
00h
74h
DATA
RAM Register Address (n)
RAM Register Data (n)
7-Bit Slave Address
7-Bit Slave Address
S
A
A
Sr
1
A
A
DATA
DATA
RAM Register Data (n+1)
RAM Register Data (Last)
A
A
P
Figure 5-34. Reading from Multiple RAM Registers
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5.11.24 Example – Reading from Multiple EEPROM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65642A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65642A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65642A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65642A acknowledges
12. Bus master sends address of first EEPROM register to be read (00h)
13. TPS65642A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65642A acknowledges
17. TPS65642A sends contents of first EEPROM register to be read
18. Bus master acknowledges
19. TPS65642A sends contents of second EEPROM register to be read
20. Bus master acknowledges
21. TPS65642A sends contents of third (last) EEPROM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
74h
FFh
01h
Control Register Address
Control Register Data
7-Bit Slave Address
S
0
A
A
A
P
R/W
0
74h
00h
74h
DATA
EEPROM Register Data (n)
EEPROM Register Addr (n)
7-Bit Slave Address
7-Bit Slave Address
S
A
A
Sr
1
A
A
DATA
DATA
EEPROM Register Data (Last)
EEPROM Register Data (n+1)
A
P
A
Figure 5-35. Reading from Multiple EEPROM Registers
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5.11.25 Configuration Parameter VCOM
Figure 5-36. VCOM Register Bit Allocation
7
6
5
4
3
2
1
0
VCOM
R/W-0
P
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-17. VCOM Register Field Descriptions
Bit
Field
Value
Description
7–1
VCOM
During write operations these bits contain the data to be written. During read operations these bits
contain the contents of the EEPROM register.
00h–7F
h
V
VCOM + 1
REF
I
=
´
OUT
R
128
SET
0
P
During write operations this bit configures the destination for data.
Data is written to the DAC register and EEPROM.
Data is written to the DAC register only.
0
1
During read operations this bit indicates whether the contains of the RAM register and EEPROM
are the same or not.
0
1
DAC register and EEPROM contents are the same.
DAC register and EEPROM contents are different.
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5.11.26 Example – Writing a VCOM Value of 77h to RAM Register Only
1. Bus master sends a START condition.
2. Bus master sends 9E hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65642A slave acknowledges.
4. Bus master sends EF hexadecimal (data to be written plus LSB = 1).
5. TPS65642A slave acknowledges.
6. Bus master sends a STOP condition.
4Fh
77h
7-Bit Slave Address
Data to be Written
S
0
A
1
A
P
Figure 5-37. Writing a VCOM Value of 77h to RAM Only
5.11.27 Example – Writing a VCOM Value of 77h to EEPROM and RAM
1. Bus master sends a START condition.
2. Bus master sends 9E hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65642A slave acknowledges.
4. Bus master sends EE hexadecimal (data to be written plus LSB = 0).
5. TPS65642A slave acknowledges.
6. Bus master sends a STOP condition.
4Fh
77h
7-Bit Slave Address
Data to be Written
S
0
A
0
A
P
Figure 5-38. Writing a VCOM Value of 77h to EEPROM and RAM
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5.11.28 Example — Reading a VCOM Value of 77h from EEPROM When RAM Contents are
Identical
1. Bus master sends a START condition.
2. Bus master sends 9F hexadecimal (7-bit slave address plus high R/W bit).
3. TPS65642A slave acknowledges.
4. TPS65642A sends EE hexadecimal from EEPROM (data to be read plus LSB = '0').
5. Bus master does not acknowledge.
6. Bus master sends a STOP condition.
4Fh
77h
S
7-Bit Slave Address
1
A
Data to be Read
0
A
P
Figure 5-39. Reading 77h from EEPROM when RAM Contents are Identical
5.11.29 Example —Reading a VCOM Value of 77h from EEPROM When RAM Contents are
Different
1. Bus master sends a START condition.
2. Bus master sends 9F hexadecimal (7-bit slave address plus high R/W bit).
3. TPS65642A slave acknowledges.
4. TPS65642A sends EF hexadecimal from RAM (data to be read plus LSB = '0').
5. Bus master does not acknowledge.
6. Bus master sends a STOP condition.
4Fh
77h
S
7-Bit Slave Address
1
A
Data to be Read
1
A
P
Figure 5-40. Reading 77h from EEPROM when RAM Contents are Different
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5.11.30 I2C Interface
Configuration parameters and the VCOM voltage setting are programmed through an industry standard I2C
serial interface. The TPS65642A device always works as a slave device and supports standard (100 kbps)
and fast (400 kbps) modes of operation. During write operations, all further attempts to access the slave
addresses are ignored until the current write operation is complete.
NOTE
The I2C interface contains a known bug. If a new start condition appears on the bus
before transfer of the slave address byte from a previously initiated read/write
operation is complete, the I2C interface may hang. Normal operation is recovered after
cycling VIN.
5.12 POWER SEQUENCING
1. Buck converter 1 (VCORE), Buck converter 2 (VIO1), and the linear regulator (VIO2) start as soon as VIN
VUVLO
>
.
2. The reset generator holds RST low until tRESET seconds after VCORE has reached power good status.
3. Boost converter 1 starts tDLY1 milliseconds after EN goes high (or RST has gone high, whichever
occurs later). Once asserted, the EN signal must remain high to ensure normal device operation. Once
disabled (EN = 0), boost converter 1 remains disabled until the device is powered down (even if EN is
re-asserted).
4. Boost converter 2 starts as soon as AVDD has reached power-good status.
5. In non-GIP mode, VGHM is held at high impedance until tDLY6 milliseconds after VGH reaches power-
good status; XAO goes high when VIN > VDET and low when VIN < VDET
.
6. In GIP mode, XAO is held low until tDLY6 milliseconds after VGH reaches power-good status.
Figure 5-41 and Figure 5-42 show the typical power-up or down characteristics of the TPS65642A device
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EN
VIN > VDET
VIN < VDET
VIN > VUVLO
VIN < VUVLO
VIN
tSS1
Actively
discharged
VIO1
Actively discharged
through backgate diode
VIO2
enabled
Discharged
through load
VCORE
tRESET
RST
RMODE=0
Pulled low
Pulled low
tRESET
RST
RMODE=1
tDLY1
AVDD
SMODE=0
Actively
discharged
tSS2
AVDD
SMODE=1
Discharged
through load
tSS2
Discharged
through load
VGH
Discharged
through load
VGL
Held high as long
as possible
tDLY6
VGHM
(tracks VGH
)
Held high as long
as possible
XAO
GIP=1
XAO
GIP=0
Pulled low
VCOM
SMODE=0
Remains active
(tracks AVDD)
VCOM
SMODE=1
POS pin
pulled low
VGAM
AVDD=3V
Pulled low
Figure 5-41. Power-Up or Power-Down Sequencing With EN Connected to VIN
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Detailed Description
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EN
VIN > VDET
VIN > VUVLO
VIN < VDET
VIN < VUVLO
VIN
tSS1
Actively
discharged
VIO1
Actively discharged
through backgate diode
VIO2
enabled
Discharged
through load
VCORE
tRESET
RST
RMODE=0
Pulled low
Pulled low
tRESET
RST
RMODE=1
tDLY1
AVDD
SMODE=0
Actively
discharged
tSS2
AVDD
SMODE=1
Discharged
through load
tSS2
Discharged
through load
VGH
Discharged
through load
VGL
Held high as long
as possible
tDLY6
VGHM
(tracks VGH
)
Held high as long
as possible
XAO
GIP=1
XAO
GIP=0
Pulled low
VCOM
SMODE=0
Remains active
(tracks AVDD)
VCOM
SMODE=1
POS pin
pulled low
VGAM
AVDD=3V
Pulled low
Figure 5-42. Power-Up or Power-Down Sequencing With EN Connected to T-CON Ready
68
Detailed Description
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SLVSC21 –OCTOBER 2013
5.13 UNDERVOLTAGE LOCKOUT
An undervoltage lockout function disables the TPS65642A device when the supply voltage is too low for
proper operation.
6 Application Information
6.1 External Component Selection
Care must be applied to the choice of external components because these components greatly affect
overall performance. The TPS65642A device was developed with the two goals of high performance and
small or low-profile solution size. Because these two goals are often in direct opposition to one another
(for example, larger inductors tend to achieve higher efficiencies), some trade-off is always necessary.
Inductors must have adequate current capability so that the inductors do not saturate under worst-case
conditions. For high efficiency, inductors must also have low DC resistance (DCR).
Capacitors must have adequate effective capacitance under the applicable DC bias conditions they
experience in the application. MLCC capacitors typically exhibit only a fraction of the nominal capacitance
under real-world conditions and this must be taken into consideration when selecting capacitors. This
problem is especially acute in low profile capacitors, in which the dielectric field strength is higher than in
taller components. In general, the capacitance values shown in the circuit diagrams in this data sheet refer
to the effective capacitance after DC bias effects have been taken into consideration. Reputable capacitor
manufacturers provide capacitance-versus-DC-bias curves that greatly simplify component selection.
Table 6-1, Table 6-2,Table 6-3, Table 6-4, and Table 6-5 list some components suitable for use with the
TPS65642A device. The list is not exhaustive — other components may exist that are equally suitable (or
better), however, these components have been proven to work well and were used extensively during the
development of the TPS65642A device.
Table 6-1. Boost Converter 1 External Components
REF.
L
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
Chip Inductor, 4.7 μH, ±20%
1269AS-H-4R7N
Toko
< 1 mm
CIN
Ceramic Capacitor, X5R, 10 µF, 16 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
COUT
Table 6-2. Buck Converter 1 External Component Recommendations
REF.
L
DESCRIPTION
PART NUMBER
1269AS-H-2R2N
MANUFACTURER
Toko
THICKNESS
< 1 mm
Chip Inductor
COUT
Ceramic Capacitor, X5R, 10 = µF, 6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
Table 6-3. Buck Converter 2 External Component Recommendations
REF.
L
DESCRIPTION
PART NUMBER
1269AS-H-2R2
MANUFACTURER
Toko
THICKNESS
< 1 mm
Chip Inductor
COUT
Ceramic Capacitor, X5R, 10 µF, 6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
Table 6-4. LDO Regulator External Component Recommendations
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
THICKNESS
COUT
Ceramic Capacitor, X5R, 10 µF,6.3 V,
±20%
GRM319R61H475MA12
Murata
< 0,85 mm
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Table 6-5. Boost Converter 2 External Components
REF.
DESCRIPTION
Wirewound Inductor, 15 μH, ±20%
PART NUMBER
1156AS-150M
MANUFACTURER
THICKNESS
L
L
Toko
< 1 mm
< 1 mm
Wirewound Inductor, 15 μH, ±20%
LQH3NPN150NG0
GRM319R61H475MA12
Murata
Murata
COUT
Ceramic Capacitor, X5R, 4.7 µF, 50 V,
±20%
< 0,85 mm
D
Switching Diode, 150 mA, 75 V, 350
mW
BAS16W
Infineon
< 1 mm
6.2 Typical Application Circuit
Figure 6-1 and Figure 6-2 show the recommended application circuits for non-GIP and GIP displays
respectively. Minor changes may be required to optimize the circuit for a specific application, however, the
basic circuit is unlikely to change significantly.
70
Application Information
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470nF
BAV99
VGL
2.2µF
4.7R
4.7µH
VIN
AVDD
20µF
10µF
SW1 AVDD
AVDD
VIN
1.5nF
56k
10µF
VIO1
COMP
BOOST
CONVERTER 1
EN
From T-CON
10k
To Level Shifter
To T-CON
RST
CONTROL
XAO
VIO2
VIO2
LDO REGULATOR
10µF
AVDD
BOOST
15µH
TCOMP
CONVERTER 2
VGH
SW4
BAS16W
2.2µF
2.2µH
VCORE
20µF
SW2
BUCK
CONVERTER 1
VCORE
2.2µH
VIO1
10µF
SW3
VIO1
BUCK
CONVERTER 2
GATE
From T-CON
AVDD
FLK
RE
VGH
VOLTAGE
SHAPING
VGHM
VGHM
1k
VGAMH
VGAMI
VGAMA
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
OUTG
AVDD
OUTH
OUTI
VGAMB
VGAMJ
VGAMK
VGAML
VGAMM
VGAMC
VGAMD
VGAME
VGAMF
OUTJ
OUTK
OUTL
OUTM
OUTN
GAMMA
REF
VGAMN
VGAMG
AVDD
1µF
AVDD
SCL
SDA
To/From
T-CON
2
I C INTERFACE
WP
From T-CON
100nF
12.7k
1k
POS1
VCOM1 Feedback
NEG1
OUT1
191R
11.8k
7.5k
VCOM1
PROGRAMMABLE
VCOM
POS2
RSET
1k
100nF
VCOM2 Feedback
24.9k
NEG2
OUT2
7.5k
VCOM2
PGND
AGND
Figure 6-1. Typical Application Circuit for Non-GIP Displays
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Application Information
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470nF
BAV99
VGL
2.2µF
4.7R
4.7µH
VIN
AVDD
20µF
10µF
SW1 AVDD
AVDD
VIN
1.5nF
56k
10µF
VIO1
COMP
BOOST
CONVERTER 1
EN
From T-CON
10k
To Level Shifter
To T-CON
RST
CONTROL
XAO
VIO2
VIO2
LDO REGULATOR
10µF
AVDD
10k@25°C
10.4k
BOOST
15µH
TCOMP
CONVERTER 2
VGH
SW4
10.2k
BAS16W
2.2µF
2.2µH
VCORE
SW2
BUCK
CONVERTER 1
VCORE
20µF
2.2µH
VIO1
10µF
SW3
VIO1
BUCK
CONVERTER 2
GATE
VGH
FLK
RE
VGH
VOLTAGE
SHAPING
VGHM
VGAMH
VGAMI
VGAMA
VGAMB
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
OUTG
AVDD
OUTH
OUTI
VGAMJ
VGAMK
VGAML
VGAMM
VGAMC
VGAMD
VGAME
VGAMF
OUTJ
OUTK
OUTL
OUTM
OUTN
GAMMA
REF
VGAMN
VGAMG
AVDD
1µF
AVDD
SCL
SDA
To/From
T-CON
2
I C INTERFACE
WP
From T-CON
100nF
12.7k
1k
POS1
VCOM1 Feedback
NEG1
OUT1
191R
11.8k
7.5k
VCOM1
PROGRAMMABLE
VCOM
POS2
RSET
1k
100nF
VCOM2 Feedback
24.9k
NEG2
OUT2
7.5k
VCOM2
PGND
AGND
Figure 6-2. Typical Application Circuit for GIP Displays
72
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65642AYFFR
ACTIVE
DSBGA
YFF
56
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS65642A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65642AYFFR
DSBGA
YFF
56
3000
330.0
12.4
3.0
3.55
0.81
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFF 56
SPQ
Length (mm) Width (mm) Height (mm)
335.0 335.0 25.0
TPS65642AYFFR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0056
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
2
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
2.4 TYP
SYMM
H
G
D: Max = 3.478 mm, Min =3.418 mm
E: Max = 3.146 mm, Min =3.086 mm
F
E
D
C
SYMM
2.8
TYP
0.3
0.2
56X
B
A
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
7
0.4 TYP
4219481/A 10/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
56X ( 0.23)
(0.4) TYP
2
4
5
6
7
1
A
B
C
D
E
F
SYMM
G
H
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219481/A 10/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
56X ( 0.25)
(R0.05) TYP
1
2
3
4
5
6
7
A
(0.4)
TYP
B
METAL
TYP
C
D
E
F
SYMM
G
H
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219481/A 10/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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