TPS65982DMC [TI]
坞站管理控制器;
| 型号： | TPS65982DMC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 坞站管理控制器 控制器 |
| 文件： | 总60页 (文件大小：2798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65982DMC
ZHCSLZ6 –SEPTEMBER 2020
TPS65982DMC 对接管理控制器
1 特性
3 描述
• 安全固件更新
TPS65982DMC 是一种坞站管理控制器，用于实现 TI
PD 控制器的坞站、集线器和监视器。TPS65982DMC
包括一个 USB 低速端点，能够接收系统 PD 控制器的
固件更新。固件更新使用 SHA-256 和 RSA-3072 身份
验证安全地执行。此外，端点还提供 USB 广告牌功
能。TPS65982 DMC 集成了背对背 NFET 驱动器，用
于通过外部适配器控制系统电源。DMC 监控通过适配
器输入路径以及系统其他点的电流，并调整受管 PD 控
制器的功率通告，以确保外部适配器不会过载。当包含
在 USB4 系统中时，TPS65982DMC 会监控上行端口
的连接状态并更新下行端口的连接状态，以确保整个系
统的数据行为一致。
– 通过USB 低速安全更新TPS65982DMC 和其他
TI PD 控制器
– SHA-256 和RSA-3072
– I2C 引导适用于TI PD 控制器- 一个闪存适用于
所有器件
– 支持不安全固件更新
• 桶形插孔输入控制
– 具有过压检测的集成式NFET 栅极驱动
– 软启动
• 智能电源策略管理器
– 管理所有坞站电源- USB Type-C、USB Type-
A、系统电源
– 可配置智能电源策略管理器
• USB4 连接管理器
器件信息(1)
封装尺寸（标称值）
器件型号
封装
TPS65982DMC
NFBGA (96)
6.00mm × 6.00mm
– 根据UFP 主机连接更新DFP 端口
– 重新配置PD 控制器并发出正确的连接更改
– 供系统使用的可配置GPIO
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• NFBGA 封装
From external
adapter
To System
– 0.5mm 间距
– 通孔对于所有引脚均兼容
3.3 V
2 应用
TPS65982DMC
PD
Controllers
I2C
Interface
• Thunderbolt 4 设备
• USB4 器件
• 扩展坞
USB2 Endpoint &
Billboard
D+/-
2
External
Memory
SPI
Interface
• 监视器
简化图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFN7
TPS65982DMC
ZHCSLZ6 –SEPTEMBER 2020
www.ti.com.cn
Table of Contents
7 Parameter Measurement Information..........................14
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................32
8.5 Programming............................................................ 37
9 Application and Implementation..................................42
9.1 Application Information............................................. 42
9.2 Typical Application.................................................... 42
10 Power Supply Recommendations..............................47
10.1 3.3 V Power............................................................ 47
10.2 1.8 V Core Power....................................................47
10.3 VDDIO.....................................................................47
11 Layout...........................................................................49
11.1 Layout Guidelines................................................... 49
11.2 Layout Example...................................................... 49
12 Device and Documentation Support..........................53
12.1 接收文档更新通知................................................... 53
12.2 支持资源..................................................................53
12.3 Trademarks.............................................................53
12.4 静电放电警告.......................................................... 53
12.5 术语表..................................................................... 53
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 描述................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Power Supply Requirements and Characteristics.......7
6.6 Power Supervisor Characteristics...............................7
6.7 Adapter Power Switch Characteristics........................8
6.8 USB Endpoint Requirements and Characteristics...... 8
6.9 Analog-to-Digital Converter (ADC) Characteristics.....9
6.10 Input/Output (I/O) Requirements and
Characteristics...............................................................9
6.11 I2C Slave Requirements and Characteristics.......... 11
6.12 SPI Master Characteristics..................................... 12
6.13 Single-Wire Debugger (SWD) Timing
Requirements..............................................................12
6.14 ADP_POWER_CFG Configuration Requirements..13
6.15 Thermal Shutdown Characteristics.........................13
6.16 Oscillator Requirements and Characteristics..........13
Information.................................................................... 53
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
September 2020
*
Initial Release
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5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
GND
LDO_1V8D
SPI_CLK
SPI_MISO
I2C2_SDA
GND
GND
GND
HV_GATE2
SENSE_N
GND
VDDIO
I2C1_IRQz
I2C1_SDA
LDO_BMC
I2C_ADDR
LDO_3V3
VIN_3V3
GND
GPIO_0
GPIO_1
I2C1_SCL
NC
SPI_SSz
SPI_MOSI
I2C2_SCL
I2C2_IRQz
GND
GND
HV_GATE1
SENSE_P
GPIO_4
GPIO_2
GPIO_5
GND
GND
GND
GND
GND
GND
GND
HRESET
GPIO_7
GND
GND
GND
SS
GND
GND
GND
GND
GND
GND
GND
SWD_DATA
SWD_CLK
GND
GND
EXT_MRESET
EXT_RESETZ
GPIO_3
ADP_POWER
_CFG
NC
GND
R_OSC
VOUT_3V3
GND
GND
GPIO_6
GPIO_8
GND
ADP_IN
ADP_IN
ADP_IN
K
L
LDO_1V8A
GPIO_14
GPIO_15
GPIO_12
GPIO_13
GND
GND
GND
GND
UFP_USB2_P DBG_USB2_P
UFP_USB2_N DBG_USB2_N
GND
GND
NC
NC
NC
ADP_IN
GND
NC
NC
Not to scale
图5-1. ZBH Package 96-Pin NFBGA Top View
Pin Functions
BALL NAME
BALL NUMBER
TYPE
Power
POR STATE
N/A
DESCRIPTION
ADP_IN
H11, J10, J11,
K11
Adapter Input to Internal LDO.
ADP_POWER_CFG
DBG_USB2_N
DBG_USB2_P
F10
L7
Analog Input
Analog I/O
Analog I/O
Digital I/O
Input (Hi-Z)
Hi-Z
Sampled by ADC at boot to determine adapter switch behavior.
USB D- Connection for USB Debug.
K7
Hi-Z
USB D+ Connection for USB Debug.
EXT_MRESET
E11
Hi-Z
Forces RESETZ to assert. This pin asserts RESETZ when pulled high. Ground pin with a 1-MΩ
resistor when unused in the application.
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BALL NAME
EXT_RESETZ
BALL NUMBER
F11
TYPE
Digital I/O
POR STATE
DESCRIPTION
Push-Pull Output Active low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused.
(Low)
GND
A1, A11, A6, A7, Ground
A8, B11, B7, B8,
C11, D11, D5, D8,
E4, E5, E6, E7,
E8, F5, F6, F7,
F8, G5, G6, G7,
G8, H10, H4, H5,
H8, J1, J2, K4,
K5, K8, L1, L4,
L5, L8
N/A
Ground. Connect all balls to ground plane.
GPIO_0(1)
GPIO_1(1)
GPIO_2(1)
GPIO_3(1)
GPIO_4(1)
GPIO_5(1)
GPIO_6(1)
GPIO_7(1)
GPIO_8(1)
GPIO_12(1)
GPIO_13(1)
GPIO_14(1)
GPIO_15(1)
HRESET
B2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
General Purpose Digital I/O 0. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
C2
General Purpose Digital I/O 1. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
D10
G11
C10
E10
G10
D7
General Purpose Digital I/O 2. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
General Purpose Digital I/O 3. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
General Purpose Digital I/O 4. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
General Purpose Digital I/O 5. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
General Purpose Digital I/O 6. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
General Purpose Digital I/O 7. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
H6
General Purpose Digital I/O 8. Float pin if it is configured as a push-pull output in the application.
Ground pin with a 1-MΩresistor when unused in the application.
K3
General Purpose Digital I/O 12. Float pin if it is configured as a push-pull output in the
application. Ground pin with a 1-MΩresistor when unused in the application.
L3
General Purpose Digital I/O 13. Float pin if it is configured as a push-pull output in the
application. Ground pin with a 1-MΩresistor when unused in the application.
K2
General Purpose Digital I/O 14. Float pin if it is configured as a push-pull output in the
application. Ground pin with a 1-MΩresistor when unused in the application.
L2
General Purpose Digital I/O 15. Float pin if it is configured as a push-pull output in the
application. Ground pin with a 1-MΩresistor when unused in the application.
D6
Active high hardware reset input. Will re-load settings from external flash memory. Ground pin
when HRESET functionality will not be used.
HV_GATE1
HV_GATE2
I2C1_IRQz
B9
A9
C1
Analog Output
Analog Output
Digital Output
Short to Sense_P External NFET gate control for high voltage power path. Float pin when unused
Short to ADP_IN External NFET gate control for high voltage power path. Float pin when unused
Hi-Z
I2C port 1 interrupt. Active low. Implement externally as an open drain with a pullup resistance.
Float pin when unused.
I2C1_SCL
I2C1_SDA
I2C2_IRQz
I2C2_SCL
I2C2_SDA
I2C_ADDR
LDO_1V8A
LDO_1V8D
LDO_3V3
D2
D1
B6
B5
A5
F1
K1
A2
G1
E1
Digital I/O
Digital I/O
Digital Output
Digital I/O
Digital I/O
Analog I/O
Power
Digital Input
Digital Input
Hi-Z
I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩresistance when used or unused.
I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩresistance when used or unused.
I2C port 2 interrupt. Active low. Implement externally as an open drain with a pullup resistance.
Float pin when unused.
Digital Input
Digital Input
Analog Input
N/A
I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩresistance when used or unused.
I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on
configuration) through a 10-kΩresistance when used or unused.
Sets the I2C address for both I2C ports as well as determine the master and slave devices for
memory code sharing.
Output of the 3.3 V or 1.8 V LDO for Core Analog Circuits. Bypass with capacitance CLDO_1V8A
to GND.
Power
N/A
Output of the 3.3 V or 1.8 V LDO for Core Digital Circuits. Bypass with capacitance CLDO_1V8D
to GND.
Power
N/A
Output of the ADP_IN to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal supply
rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND
LDO_BMC
NC
Power
N/A
N/A
Output of the 1.1V output level LDO. Bypass with capacitance CLDO_BMC to GND.
Populated Ball that must remain unconnected.
E2, F2, K10, K9, Blank
L10, L11, L9
R_OSC
G2
Analog I/O
Hi-Z
External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance
RR_OSC.
SENSE_N
A10
Analog Input
Analog Input
Negative sense for external high voltage power path current sense resistance. Short pin to
ADP_IN when unused.
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BALL NAME
BALL NUMBER
TYPE
POR STATE
DESCRIPTION
SENSE_P
B10
Analog Input
Analog Input
Positive sense for external high voltage power path current sense resistance. Short pin to
ADP_IN when unused.
SPI_CLK
A3
A4
Digital Output
Digital Input
Digital Input
Digital Input
SPI serial clock. Ground pin when unused.
SPI_MISO
SPI serial master input from slave. This pin is used during boot sequence to determine if the
flash memory is valid. Ground pin when unused.
SPI_MOSI
SPI_SSz
SS
B4
B3
H7
G4
Digital Output
Digital Output
Analog Output
Digital Input
Digital Input
Digital Input
Driven Low
SPI serial master output to slave. Ground pin when unused.
SPI slave select. Ground pin when unused.
Soft Start. Tie pin to capacitance CSS to ground.
SWD serial clock. Float pin when unused.
SWD_CLK
Resistive Pull
High
SWD_DATA
F4
Digital I/O
Resistive Pull
High
SWD serial data. Float pin when unused.
UFP_USB2_N
UFP_USB2_P
VDDIO
L6
K6
B1
Analog I/O
Analog I/O
Power
Hi-Z
Hi-Z
N/A
USB D- Connection for USB Endpoint.
USB D+ Connection for USB Endpoint.
VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3.
When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply
input, bypass with capacitance CVDDIO to GND.
VIN_3V3
H1
H2
Power
Power
N/A
N/A
Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VOUT_3V3
Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin
when unused.
(1) GPIO Function is determined by device firmware. Consult device TRM for available GPIO behaviors.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN_3V3
3.6
–0.3
–0.3
–0.3
–0.3
–0.3
VI
Input voltage(2)
SENSEP, SENSEN(3)
24
V
VDDIO
LDO_3V3 + 0.3
LDO_1V8A, LDO_1V8D, LDO_BMC, SS
LDO_3V3
2
3.45
VOUT_3V3, RESETZ, I2C _IRQ1Z, I2C_IRQ2Z, SPI_MOSI, SPI_CLK, SPI_SSZ,
SWD_CLK
LDO_3V3 + 0.3
–0.3
VIO
Output voltage (2)
V
HV_GATE1, HV_GATE2
HV_GATE1 (relative to SENSEP)
HV_GATE2 (relative to ADP_IN)
ADP_IN
30
6
–0.3
–0.3
–0.3
–0.3
6
24
I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_MISO, I2C_SDA2, I2C_SCL2, GPIOn,
MRESET, ADP_POWER_CFG
LDO_3V3 + 0.3
2
–0.3
–0.3
–0.3
R_OSC, I2C_ADDR
HRESET
VIO
I/O voltage (2)
V
LDO_1V8D +
0.3
UFP_USB2_N, UFP_USB2_P, DBG_USB2_N, DBG_USB2_P (Switches Open)
UFP_USB2_N, UFP_USB2_P, DBG_USB2_N, DBG_USB2_P (Switches Closed)
6
–2
–0.3
–10
–55
6
TJ
Operating junction temperature
Storage temperature
125
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(3) The 24 V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (<100 ns) may occur up to 30 V.
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6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX
UNIT
VIN_3V3
2.85
1.7
3.45
3.45
22
Input voltage
range(1)
VI
V
VDDIO
ADP_IN
4
I/O voltage
range(1)
VIO
V
UFP_USB2_N, UFP_USB2_P, DBG_USB2_N, DBG_USB2_P
5.5
–2
–10
–10
–10
TA
TB
TJ
Ambient operating temperature range
Operating board temperature range
Operating junction temperature range
85
°C
°C
°C
100
125
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
6.4 Thermal Information
TPS65982DMC
THERMAL METRIC(1)
ZBH (NFBGA)
UNIT
96 BALLS
42.4
12.4
13
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
13
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Supply Requirements and Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
EXTERNAL
VIN_3V3
Input 3.3-V supply
2.85
4
3.3
5
3.45
22
V
V
V
Input DC bus voltage. Input to the
TPS65982DMC.
ADP_IN
VDDIO(1)
Optional supply for I/O cells.
1.7
3.45
INTERNAL
DC 3.3V generated internally by either a switch
from VIN_3V3, an LDO from PP_CABLE, or an
LDO from ADP_IN
VLDO_3V3
2.7
3.3
3.45
V
VDO_LDO3V3 Drop Out Voltage of LDO_3V3 from PP_CABLE
Drop Out Voltage of LDO_3V3 from ADP_IN
ILOAD = 50 mA
250
750
1.9
1.9
mV
mV
V
250
1.7
1.7
500
1.8
1.8
VLDO_1V8D
VLDO_1V8A
DC 1.8V generated for internal digital circuitry.
DC 1.8V generated for internal analog circuitry.
V
DC voltage generated on LDO_BMC. Setting for
USB-PD.
VLDO_BMC
ILDO_3V3
1.05 1.125
1.2
70
V
DC current supplied by the 3.3V LDOs. This
includes internal core power and external load on
LDO_3V3.
mA
ILDO_3V3EX
IOUT_3V3
External DC current supplied by LDO_3V3
External DC current supplied by VOUT_3V3
30
mA
mA
100
DC current supplied by LDO_1V8D. This is
intended for internal loads only but small external
loads may be added.
ILDO_1V8D
50
5
mA
mA
mA
ILDO_1V8DEX External DC current supplied by LDO_1V8D.
DC current supplied by LDO_1V8A. This is
intended for internal loads only but small external
loads may be added.
ILDO_1V8A
20
ILDO_1V8AEX External DC current supplied by LDO_1V8A.
5
5
mA
mA
mA
mV
DC current supplied by LDO_BMC. This is
ILDO_BMC
intended for internal loads only.
ILDO_BMCEX External DC current supplied by LDO_BMC.
0
Forward voltage drop across VIN_3V3 to
LDO_3V3 switch
VFWD_DROP
ILOAD = 50 mA
VIN_3V3 –VLDO_3V3 > 50 mV
25
60
1.1
90
Input switch resistance from VIN_3V3 to
RIN_3V3
LDO_3V3
0.5
1.75
0.7
V
Ω
Ω
µs
Output switch resistance from VIN_3V3 to
ROUT_3V3
VOUT_3V3
0.35
10-90% rise time on VOUT_3V3 from switch
TR_OUT3V3
enable.
35
120
CVOUT_3V3 = 1 μF
(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before
LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.
6.6 Power Supervisor Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
2.2
20
TYP
2.325
80
MAX
2.45
150
UNIT
V
UV_LDO3V3
Under-voltage threshold for LDO_3V3. Locks out 1.8-V LDOs
Under-voltage hysteresis for LDO_3V3
LDO_3V3 rising
UVH_LDO3V3
LDO_3V3 falling
ADP_IN rising
ADP_IN falling
mV
V
UV_ADP_IN_LDO
UVH_ADP_IN_LDO
Under-voltage threshold for ADP_IN to enable LDO
Under-voltage hysteresis for ADP_IN to enable LDO
3.35
20
3.75
80
3.95
150
mV
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Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Over-voltage threshold for ADP_IN. This value is a 6-bit
programmable threshold
OV_ADP_IN
ADP_IN rising
5
24
V
Over-voltage threshold step for ADP_IN. This value is the LSB of the
programmable threshold
OVLSB_ADP_IN
OVH_ADP_IN
UV_ADP_IN
ADP_IN rising
328
mV
Over-voltage hysteresis for ADP_IN
ADP_IN falling, % of OV_ADP_IN
ADP_IN falling
0.9%
2.5
1.3%
1.7%
18.21
Under-voltage threshold for ADP_IN. This value is a 6-bit
programmable threshold
V
Under-voltage threshold step for ADP_IN. This value is the LSB of the
programmable threshold
UVLSB_ADP_IN
UVH_ADP_IN
ADP_IN falling
249
mV
Under-voltage hysteresis for ADP_IN
ADP_IN rising, % of UV_ADP_IN
Setting 0
0.9%
2.019
2.138
2.256
2.375
2.494
2.613
2.731
2.85
1.3%
2.125
2.25
2.375
2.5
1.7%
2.231
2.363
2.494
2.625
2.756
2.888
3.019
3.15
Setting 1
Setting 2
Setting 3
Configurable under-voltage threshold for VOUT_3V3 rising. De-
asserts RESETZ
UVR_OUT3V3
V
Setting 4
2.625
2.75
2.875
3
Setting 5
Setting 6
Setting 7
UVRH_OUT3V3
TUVRASSERT
TUVRDELAY
Under-voltage hysteresis for VOUT_3V3 falling.
OUT_3V3 falling
30
50
mV
μs
ms
Delay from falling VOUT_3V3 or MRESET assertion to RESETZ
asserting low
75
Configurable delay from VOUT_3V3 to RESETZ de-assertion.
0
161.3
6.7 Adapter Power Switch Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX
UNIT
Active quiescent current from SENSEP pin,
EN_HV = 1
1
mA
Configured as source
IHVEXTACT
IHVEXTSD
Active quiescent current from ADP_IN pin,
EN_HV = 1
3.5
40
mA
Configured as sink
Shutdown quiescent current from SENSEP pin,
EN_HV = 0
μA
3.5
5
6.5
A/V
I = 100 mA , RSENSE = 10 mΩ
Reverse current blocking disabled
PP_EXT current sense accuracy (excluding
RSENSE accuracy)
4
4.4
4.5
4
5
5
5
5
6
5.6
5.5
6
A/V
A/V
A/V
μA
I = 200 mA, RSENSE = 10 mΩ
I = 500 mA, RSENSE = 10 mΩ
I ≥1 A, RSENSE = 10 mΩ
IHVEXT_ACC
IGATEEXT(1)
External Gate Drive Current on HV_GATE1 and
HV_GATE2
VGSEXT
ISS
VGS voltage driving external FETs
Soft start charging current
4.5
5.5
0.6
1.35
68.3
2
7.5
8.5
V
7
1
μA
kΩ
V
1.4
RSS_DIS
VTHSS
TSSDONE
Soft start discharge resistance
Soft start complete threshold
Soft start complete time
1.5
99
6
1.65
129.7
10
CSS = 470 nF
ms
mV
Reverse Current Blocking voltage Threshold for
PP_EXT external switches
VREVPEXT
(1) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1 Ωto provide adequate response time to short
circuit events.
(2) Maximum capacitance on ADP_IN when configured as a source must not exceed 12 µF.
6.8 USB Endpoint Requirements and Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSMITTER(1)
T_RISE_EP
Rising transition time
Low-speed (1.5 Mbps) data rate only
75
300
ns
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Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
75
TYP
MAX
300
25%
2
UNIT
T_FALL_EP
T_RRM_EP
V_XOVER_EP
RS_EP
Falling transition time
Low-speed (1.5 Mbps) data rate only
Low-speed (1.5 Mbps) data rate only
ns
Rise and fall time matching
Output crossover voltage
–20%
1.3
V
Source resistance of driver including 2nd Stage Port
Data Multiplexer
34
Ω
DIFFERENTIAL RECEIVER (1)
VOS_DIFF_EP
VIN_CM_EP
RPU_EP
Input offset
100
2.5
mV
V
–100
0.8
Common Mode Range
Receiving
1.425
1.575
D–Bias Resistance
kΩ
SINGLE ENDED RECEIVER(1)
VTH_SE_EP
Single ended threshold
Single ended threshold hysteresis
Signal rising/falling
Signal falling
0.8
2
V
VHYS_SE_EP
200
mV
(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for
VIN_3V3 ≥3.135 V
6.9 Analog-to-Digital Converter (ADC) Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
bits
RES_ADC
F_ADC
ADC resolution
ADC clock frequency
ADC enable time
1.477
42.14
10.5
1.5
1.523
43.86
10.9
8.12
1.35
1.188
0.65
1.2
MHz
μs
T_ENA
43
T_SAMPLEA
T_CONVERTA
T_INTA
LSB
ADC input sample time
ADC conversion time
ADC interrupt time
Least significant bit
Differential non-linearity
Integral non-linearity
Gain error (divider)
Gain error (no divider)
Buffer offset error
10.67
8
μs
7.88
μs
1.31
1.33
1.17
μs
1.152
–0.65
–1.2
–1.5%
–1
mV
DNL
LSB
LSB
INL
1.5%
1
GAIN_ERR
VOS_ERR
10
mV
°C
–10
THERM_ACC
THERM_GAIN
THERM_V0
Thermal sense accuracy
Thermal slope
8
–8
3.095
0.823
mV/°C
V
Zero degree voltage
6.10 Input/Output (I/O) Requirements and Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI
SPI_VIH
SPI_VIL
SPI_HYS
SPI_ILKG
High-level input voltage
Low-level input voltage
Input hysteresis voltage
Leakage current
LDO_3V3 = 3.3 V
2
V
V
LDO_3V3 = 3.3 V
0.8
1
LDO_3V3 = 3.3 V
0.2
–1
2.9
2.5
V
Output is Hi-Z, VIN = 0 to LDO_3V3
μA
V
IO = –8 mA, LDO_3V3 = 3.3 V
IO = –15 mA, LDO_3V3 = 3.3 V
IO = 10 mA
SPI_VOH
SPI_VOL
SPI output high voltage
SPI output low voltage
0.4
0.8
V
IO = 20 mA
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Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWDIO
SWDIO_VIH
SWDIO_VIL
SWDIO_HYS
SWDIO_ILKG
High-level input voltage
Low-level input voltage
Input Hysteresis Voltage
Leakage current
LDO_3V3 = 3.3 V
2
V
V
LDO_3V3 = 3.3 V
0.8
1
LDO_3V3 = 3.3 V
0.2
–1
2.9
2.5
V
Output is Hi-Z, VIN = 0 to LDO_3V3
μA
V
IO = –8 mA, LDO_3V3 = 3.3 V
IO = –15 mA, LDO_3V3 = 3.3 V
IO = 10 mA
SWDIO_VOH
SWDIO_VOL
Output high voltage
Output low voltage
0.4
0.8
5.2
5
V
IO = 20 mA
2.8
4
SWDIO_RPU
SWDIO_TOS
Pullup resistance
kΩ
ns
SWDIO output skew to falling edge SWDCLK
–5
Input setup time required between SWDIO and rising
edge of SWCLK
6
ns
SWDIO_TIS
SWDIO_TIH
Input hold time required between SWDIO and rising edge
of SWCLK
1
2
ns
SWDCLK
SWDCL_VIH
SWDCL_VIL
SWDCL_THI
SWDCL_TLO
SWDCL_HYS
SWDCL_RPU
High-level input voltage
Low-level input voltage
SWDIOCLK HIGH period
SWDIOCLK LOW period
Input hysteresis voltage
Pullup resistance
LDO_3V3 = 3.3 V
LDO_3V3 = 3.3 V
V
V
0.8
500
500
0.05
0.05
0.2
μs
μs
V
LDO_3V3 = 3.3 V
2.8
4
5.2
kΩ
GPIO, MRESET, RESETZ, ADP_POWER_CFG
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
2
V
GPIO_VIH
GPIO_VIL
GPIO_HYS
High-level input voltage
Low-level input voltage
Input hysteresis Voltage
1.25
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
0.8
V
V
0.63
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
0.2
0.09
–1
50
GPIO_ILKG
GPIO_RPU
GPIO_RPD
GPIO_DG
I/O leakage current
Pullup resistance
INPUT = 0 V to VDD
Pullup enabled
1
150
150
μA
kΩ
kΩ
ns
100
100
20
Pulldown resistance
Digital input path deglitch
Pulldown enabled
50
2.9
IO = –2 mA, LDO_3V3 = 3.3 V
IO = –2 mA, VDDIO = 1.8 V
IO = 2 mA, LDO_3V3 = 3.3 V
IO = 2 mA, VDDIO = 1.8 V
GPIO_VOH
GPIO_VOL
GPIO output high voltage
GPIO output low voltage
V
V
1.35
0.4
0.45
HRESET
HRESET_VIH
HRESET_VIL
HRESET_HYS
HRESET_ILKG
High-level input voltage
Low-level input voltage
Input hysteresis Voltage
I/O leakage current
1.25
V
V
0.63
1
.09
–1
2.0
V
INPUT = 0 V to LDO_1V8D
μA
HRESET_THIGH HRESET minimum high time to assert a reset condition.
ms
HRESET minimum low time to deassert a reset
HRESET_TLOW
condition.
2.0
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Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C_IRQ1Z, I2C_IRQ2Z
OD_VOL
OD_LKG
Low level output voltage
Leakage current
IOL = 2 mA
0.4
1
V
Output is Hi-Z, VIN = 0 to LDO_3V3
–1
μA
6.11 I2C Slave Requirements and Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDA and SCL COMMON CHARACTERISTICS
ILEAK
Input leakage current
Voltage on Pin = LDO_3V3
IOL = 3mA, LDO_3V3 = 3.3 V
IOL = 3mA, VDDIO = 1.8 V
VOL = 0.4 V
-3
3
0.4
μA
VOL
SDA output low voltage
V
0.36
3
6
IOL
SDA max output low current
Input low signal
mA
V
VOL = 0.6 V
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
0.99
0.54
VIL
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
2.31
1.26
0.17
0.09
VIH
Input high signal
V
LDO_3V3 = 3.3 V
VDDIO = 1.8 V
VHYS
Input Hysteresis
V
TSP
CI
I2C pulse width suppressed
Pin Capacitance
50
10
ns
pF
SDA and SCL STANDARD MODE CHARACTERISTICS
FSCL
I2C clock frequency
I2C clock high time
0
4
100
kHz
μs
μs
ns
THIGH
TLOW
I2C clock low time
4.7
250
0
TSUDAT
THDDAT
TVDDAT
I2C serial data setup time
I2C serial data hold time
I2C Valid data time
ns
SCL low to SDA output valid
3.4
3.4
μs
ACK signal from SCL low to SDA (out)
low
TVDACK
I2C Valid data time of ACK condition
μs
TOCF
TBUF
TSTS
TSTH
TSPS
I2C output fall time
10-pF to 400-pF bus
250
ns
I2C bus free time between stop and start
I2C start or repeated Start condition setup time
I2C Start or repeated Start condition hold time
I2C Stop condition setup time
4.7
4.7
4
μs
μs
μs
μs
4
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Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDA and SCL FAST MODE CHARACTERISTICS
FSCL
I2C clock frequency
I2C clock high time
0
0.6
1.3
100
0
400
kHz
μs
μs
ns
THIGH
TLOW
I2C clock low time
TSUDAT
THDDAT
TVDDAT
I2C serial data setup time
I2C serial data hold time
I2C Valid data time
ns
SCL low to SDA output valid
0.9
0.9
μs
ACK signal from SCL low to SDA (out)
low
TVDACK
TOCF
I2C Valid data time of ACK condition
I2C output fall time
μs
10-pF to 400-pF bus, VDD = 3.3 V
10-pF to 400-pF bus, VDD = 1.8 V
12
6.5
1.3
0.6
0.6
0.6
250
250
ns
TBUF
TSTS
TSTH
TSPS
I2C bus free time between stop and start
I2Cstart or repeated Start condition setup time
I2C Start or repeated Start condition hold time
I2C Stop condition setup time
μs
μs
μs
μs
6.12 SPI Master Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
FSPI
Frequency of SPI_CLK
11.82
12 12.18
MHz
ns
TPER
Period of SPI_CLK (1/F_SPI)
82.1 83.33
84.6
TWHI
SPI_CLK High Width
30
30
ns
TWLO
SPI_CLK Low Width
ns
TDACT
TDINACT
TDMOSI
TSUMISO
THDMSIO
SPI_SZZ falling to SPI_CLK rising delay time
SPI_CLK falling to SPI_SSZ rising delay time
SPI_CLK falling to SPI_MOSI Valid delay time
SPI_MISO valid to SPI_CLK falling setup time
SPI_CLK falling to SPI_MISO invalid hold time
30
50
180
5
ns
160
–5
21
ns
ns
ns
0
ns
10% to 90%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
TRSPI
TFSPI
SPI_SSZ/CLK/MOSI rise time
SPI_SSZ/CLK/MOSI fall time
0.1
0.1
8
8
ns
ns
90% to 10%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
6.13 Single-Wire Debugger (SWD) Timing Requirements
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FSWD
TPER
Frequency of SWD_CLK
10 MHz
Period of SWD_CLK (1/FSWD)
SWD_CLK High Width
100
35
35
2
ns
ns
ns
TWHI
TWLO
TDOUT
TSUIN
THDIN
SWD_CLK Low Width
SWD_CLK rising to SWD_DATA valid delay time
SWD_DATA valid to SWD_CLK rising setup time
SWD_DATA hold time from SWD_CLK rising
25
ns
ns
ns
ns
9
3
10% to 90%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
TRSWD
TFSWD
SWD Output rise time
SWD Output fall time
0.1
0.1
8
8
90% to 10%, CL = 5 pF to 50 pF,
LDO_3V3 = 3.3 V
ns
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6.14 ADP_POWER_CFG Configuration Requirements
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VADP_EXT
VADP_DIS
ADP_POWER_CFG Voltage for receiving ADP_IN Power
through the PP_EXT path
0.8
V
ADP_POWER_CFG Voltage for disabling system power from
ADP_IN
2.4
V
6.15 Thermal Shutdown Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TSD_MAIN
Thermal shutdown temperature of the main thermal
shutdown
Temperature rising
145
160
175
°C
TSDH_MAIN Thermal shutdown hysteresis of the main thermal shutdown Temperature falling
20
150
37
°C
°C
°C
ms
TSD_PWR
TSDH_PWR
TSD_DG
Thermal shutdown temperature of the power path block
Thermal shutdown hysteresis of the power path block
Programmable thermal shutdown detection deglitch time
Temperature rising
Temperature falling
135
165
0.1
6.16 Oscillator Requirements and Characteristics
Recommended operating conditions; TA = –10 to +85°C unless otherwise noted
PARAMETER
FOSC_48M 48-MHz oscillator
FOSC_100K 100-kHz oscillator
TEST CONDITIONS
MIN
47.28
95
TYP MAX UNIT
48 48.72
MHz
kHz
kΩ
100
105
14.985
15 15.015
RR_OSC
External oscillator set resistance (0.2%)
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7 Parameter Measurement Information
UVR_OUT3V3 - UVRH_OUT3V3
UVR_OUT3V3
VOUT_3V3
MRESET
TUVRDELAY
TUVRASSERT
TUVRDELAY
TUVRASSERT
RESETZ
图7-1. RESETZ Assertion Timing
T_ENA
T_SAMPLEA
T_CONVERTA
T_INTA
ADC Clock
ADC Enable
ADC Sample
ADC Interrupt
ADC Output
New Valid Output
Previous or Invalid Output
图7-2. ADC Enable and Conversion Timing
T_SAMPA
T_CONVERTA
T_INTA T_SAMPLE
T_CONVERTA
ADC Clock
ADC Sample
ADC Interrupt
ADC Output
New Valid Output
New Valid Output
图7-3. ADC Repeated Conversion Timing
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t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
cont.
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
图7-4. I2C Slave Interface Timing
t
t
t
wlow
per
whigh
SPI_SSZ
SPI_CLK
t
t
dinact
dact
t
t
dmosi
dmosi
SPI_MOSI
SPI_MISO
Valid Data
t
sumiso
Valid Data
t
hdmiso
图7-5. SPI Master Timing
twhigh
tper
twlow
SWD_CLK
tdout
tdout
SWD_DATA (Output)
SWD_DATA (Input)
Valid Data
thdin
tsuin
Valid Data
图7-6. SWD Timing
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8 Detailed Description
8.1 Overview
The TPS65982DMC is a simple dock management controller (DMC) for USB4 devices. The TPS65982 is
capable of managing system power and alternate mode policy for system PD controllers such as the
TPS65988DK. The integrated USB low-speed endpoint allows the TPS6598SDMC to provide in-field firmware
update functionality for system PD controllers as well as billboard support. The TPS65982DMC may also control
an input power adapter switch to soft-start system power and provide input power monitoring.
The TPS65982DMC is divided into four main sections: the adapter power switch, the port-data multiplexer, the
power-management circuitry, and the digital core.
The adapter power switch provides power to the system through external switchec controlled by the integrated
nFET gate drivers. For a high-level block diagram of the adapter power switch, a description of features, and
more detailed circuitry, refer to the Adapter Power Switch section.
The port-data multiplexer connects the internal USB low speed controller to the UFP_USB and DBG_USB pins.
For a high-level block diagram of the port-data multiplexer, a description of features, and more detailed circuitry,
refer to the USB Type-C Port Data Multiplexer section.
The power-management circuitry receives and provides power to the TPS65982DMC internal circuitry and to the
VOUT_3V3 and LDO_3V3 outputs. For a high-level block diagram of the power-management circuitry, a
description of features and, more detailed circuitry, refer to the Power Management section.
The digital core provides the engine for managing system policy, processing firmware updates, as well as
handling control of all other TPS65982DMC functionality. A small portion of the digital core contains non-volatile
memory, called boot code, which is capable of initializing the TPS65982DMC and loading a larger, configurable
portion of application code into volatile memory in the digital core. For a high-level block diagram of the digital
core, a description of features and, more detailed circuitry, refer to the Digital Core section.
The digital core of the TPS65982DMC also interprets and uses information provided by the analog-to-digital
converter ADC (see the ADC section), is configurable to read the status of general purpose inputs and trigger
events accordingly, and controls general outputs which are configurable as push-pull or open-drain types with
integrated pullup or pulldown resistors and can operate tied to a 1.8 V or 3.3-V rail. The TPS65982DMC is an
I2C master to control system PD controllers (see the I2C Slave Interface section), a SPI master to write to and
read from an external flash memory (see the SPI Master Interface section), and is programmed by a single-wire
debugger (SWD) connection (see the Single-Wire Debugger Interface section).
The TPS65982DMC also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs
off of accurate clocks provided by the integrated oscillators (see the Oscillators section).
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8.2 Functional Block Diagram
NMOS
HV_GATE1
HV_GATE2
SENSEN
SENSEP
External FET Control & Sense
Power & Supervisor
ADP_IN
VDDIO
VIN_3V3
VOUT_3V3
HRESET
SS
LDO_3V3
LDO_1V8A
LDO_1V8D
LDO_BMC
R_OSC
I2C_ADDR
ADP_POWER_CFG
EXT_MRESET
EXT_RESETZ
3
I2C_SDA/SCL/IRQ1Z
I2C_SDA/SCL/IRQ2Z
SPI_MOSI/MISO/SSZ/CLK
Digital Core
GPIO_0-15
3
4
2
2
UFP_USB_P/N
DBG_USB_P/N
Port Mux & Endpoint
GND
8.3 Feature Description
8.3.1 Adapter Power Switch
The TPS65982DMC is capable of controlling an external high-voltage, common-drain back-to-back NMOS FET
switch path to sink up to 20 V at 10 A of current. The TPS65982DMC provides external control and sense to
external NMOS power switches for currents greater than 3 A. The external NMOS switches are back-to-back to
protect the system from large voltage differential across the FETs as well as blocking reverse current flow. Each
NFET has a separate gate control. HV_GATE2 is always connected to the ADP_IN side and HV_GATE1 is
always connected to the opposite side, referred to as PP_EXT. Two sense pins, SENSEP and SENSEN, are
used to implement reverse current blocking, over-current protection, and current sensing.
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NMOS
10A
RSENSE
5uQ F 1%
PP_EXT
HV Gate Control and Sense
图8-1. Adapter Power Switch
8.3.1.1 Adapter Switch with RSENSE
图 8-1 shows the configuration when the TPS65982DMC is acting as a sink for the external switch path. The
external FETs must be connected in a common-drain configuration and will not work in a common source
configuration. In this mode, current is sourced from ADP_IN. RSENSE provides an accurate current
measurement and is used to initiate the current limiting feature of the external power path. The voltage between
SENSEP (PP_EXT) and SENSEN (ADP_IN) is sensed to block reverse current flow. This measurement is also
digitally readable via the ADC.
8.3.1.2 Adapter Switch without RSENSE
图 8-2 shows the configuration when the TPS65982DMC is acting as a sink for the external switch path without
an RSENSE resistor. In this mode, current is sunk from ADP_IN to an internal system power node, referred to as
PP_EXT. To block reverse current, the ADP_IN and SENSEP pins monitor the voltage across the NFETs. To
ensure that SENSEN does not float, tie SENSEP to SENSEN in this configuration. When configured in this
mode, the digital readout from current from the ADC will be approximately zero.
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NMOS
10A
PP_EXT
HV Gate Control and Sense
图8-2. Adapter Switch without RSENSE
8.3.1.3 External Current Sense
The current through the external NFETs to ADP_IN is sensed through the RSENSE resistor and is available to
be read digitally through the ADC. When controlling the adapter input, the readout from the ADC will only
accurately reflect the current through the external NFETs when the connection of SENSEP and SENSEN
adheres to 节8.3.1.
8.3.1.4 External Current Limit
The current through the external NFETs to ADP_IN is current limited when enabled. The current is sensed
across the external RSENSE resistance. The current limit is set by a combination of the RSENSE magnitude
and configuration settings for the voltage across the resistance. When the voltage across the RSENSE
resistance exceeds the automatically set voltage limit, the current-limit circuit is activated.
8.3.1.5 Soft Start
When configured as a sink, the SS pin provides a soft start function for each of the high-voltage power path
supplies (P_HV and external PP_EXT path) up to 5.5 V. The SS circuitry is shared for each path and only one
path will turn on as a sink at a time. The soft start is enabled by application code or via the host processor. The
SS pin is initially discharged through a resistance RSS_DIS. When the switch is turned on, a current ISS is
sourced from the pin to a capacitance CSS. This current into the capacitance generates a slow ramping voltage.
This voltage is sensed and the power path FETs turn on and the voltage follows this ramp. When the voltage
reaches the threshold VTHSS, the power path FET will be near being fully turned on, the output voltage will be
fully charged. At time TSSDONE, a signal to the digital core indicates that the soft start function has completed.
The ramp rate of the supply is given by 方程式1:
ISS
Ramp Rate = 17´
CSS
(1)
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8.3.1.6 ADP_POWER_CFG
At power-up, when VIN_3V3 is not present and ADP_IN is present, The TPS65982DMC will power itself from the
ADP_IN rail (see Power Management) and execute boot code (see Boot Code). The boot code will observe the
ADP_POWER_CFG voltage, which will fall into one of two voltage ranges: VBPZ_DIS, and VBPZ_EXT (defined
in ADP_POWER_CFG Configuration Requirements).
When the voltage on ADP_POWER_CFG is in the VBPZ_DIS range (when ADP_POWER_CFG is tied to
LDO_3V3 as in 图 8-3), this indicates that the TPS65982DMC will not close the adapter power switch and route
ADP_IN to the entire system. In this case, the TPS65982DMC will load SPI-connected flash memory and
execute this application code.
LDO_3V3
LDO_1V8D
BUSPOWERZ
ADC
图8-3. ADP_POWER_CFG Configured to Disable Power from ADP_IN
The ADP_POWER_CFG pin can also alternately configure the TPS65982DMC to power the entire system
through the adapter power switch when the voltage on ADP_POWER_CFG is in the VBPZ_EXT range (when
ADP_POWER_CFG is tied to GND as in 图8-4).
LDO_3V3
LDO_1V8D
BUSPOWERZ
ADC
图8-4. ADP_POWER_CFG Configured with PP_EXT as Input Power Path
8.3.2 USB Type-C Port Data Multiplexer
The Port Data Multiplexor routes the internal USB Low Speed endpoint between the endpoint port (UFP_USB_P
and UFP_USB_N) and the debug port (DBG_USB_P and DBG_USB_N). The TPS65982DMC digital core
selects the appropriate connection based on UFP PD state and application firmware configuration.
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UFP_USB_P
UFP_USB_N
DBG_USB_P
DBG_USB_N
USB_EP_P/N
图8-5. Port Data Multiplexers
8.3.2.1 USB2.0 Low-Speed Endpoint
The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based
accesses. The TPS65982DMC supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to
provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for
advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which
cannot be supported by the host, the Billboard class allows a means for the host to report back to the user
without any silent failures.
图 8-6 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the Serial
Interface Engine, and the Endpoint FIFOs and supports low speed operation.
LDO_3V3
USB_EP
UFP_USB_P
UFP_USB_N
RPU_EP
RS_EP
RS_EP
EP_TX_DP
EP_TX_DN
EP0/EP1
TX/RX
FIFO
32
To M0+
EP_RX_RCV
Serial
Interface
Engine
DBG_USB_P
DBG_USB_N
USB_EP
RX/TX
Status
Control
Digital Core
Interrupts
& Control
EP_RX_DP
EP_RX_DN
Transceiver
图8-6. USB Endpoint Phy
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The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and
two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– of the
selected output of the Port Multiplexer. The signals pass through the 2nd Stage Port Data Multiplexer to the port
pins. When driving, the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor
in USB Endpoint Phy but this resistance also includes the resistance of the 2nd Stage Port Data Multiplexer
defined in Port Data Multiplexer Requirements and Characteristics. RPU_EP is disconnected during transmit
mode of the transceiver.
When the endpoint is in receive mode, the resistance RPU_EP is connected to the D– pin of the top or bottom
port (UFP_USB_N or DBG_USB_N) depending on the operating condition. The RPU_EP resistance advertises
low speed mode only.
8.3.3 Power Management
The TPS65982DMC Power Management block receives power and generates voltages to provide power to the
TPS65982DMC internal circuitry. These generated power rails are LDO_3V3, LDO_1V8A, and LDO_1V8D.
LDO_3V3 is also a low power output to load flash memory. VOUT_3V3 is a low power output that does not
power internal circuitry that is controlled by application code and can be used to power other ICs in some
applications. The power supply path is shown in 图8-7.
S1
VIN_3V3
ADP_IN
S2
VOUT_3V3
VREF
To Digital Core
VREF
EN
LDO
LDO_3V3_ADP_EN
LDO_3V3
VREF
EN
LDO_1V8D
LDO
LDO_1V8A_EN
VREF
EN
LDO_1V8A
LDO
LDO_1V8D_EN
图8-7. Power Supply Path
The TPS65982DMC is powered from either VIN_3V3 or ADP_IN. The normal power supply input is VIN_3V3. In
this mode, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and the 3.3-V I/Os. A
second LDO steps the voltage down from LDO_3V3 to LDO_1V8D and LDO_1V8A to power the 1.8-V core
digital circuitry and 1.8-V analog circuits. When VIN_3V3 power is unavailable and power is available on
ADP_IN, the TPS65982DMC will be powered from ADP_IN. In this mode, the voltage on ADP_IN is stepped
down through an LDO to LDO_3V3. Switch S1 in 图 8-7 is unidirectional and no current will flow from LDO_3V3
to VIN_3V3 or VOUT_3V3.
8.3.3.1 Power-On and Supervisory Functions
A power-on-reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present. In addition to the POR and supervisory circuits for the internal supplies, a separate
programmable voltage supervisor monitors the VOUT_3V3 voltage.
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8.3.3.2 Supply Switch-Over
VIN_3V3 takes precedence over ADP_IN, meaning that when both supply voltages are present the
TPS65982DMC will power from VIN_3V3. Refer to The 图 8-7 for a diagram showing the power supply path
block. There are two cases in with a power supply switch-over will occur. The first is when ADP_IN is present
first and then VIN_3V3 becomes available. In this case, the supply will automatically switch-over to VIN_3V3 and
brown-out prevention is verified by design. The other way a supply switch-over will occur is when both supplies
are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65982DMC
occurs prompting a re-boot.
8.3.3.3 RESETZ and MRESET
The VIN_3V3 voltage is connected to the VOUT_3V3 output by a single FET switch (S2 in 图8-7).
The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable. A
supervisor circuit monitors the voltage at VOUT_3V3 for an under-voltage condition and sets the external
indicator RESETZ. The RESETZ pin is active low (low when an under-voltage condition occurs). The RESETZ
output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but is
configurable to be active low. 图 7-1 shows the RESETZ timing with MRESET set to active high. When
VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin.
8.3.4 Digital Core
图 8-8 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital
and analog portions of the TPS65982DMC.
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HRESET
MRESET
RESETZ
GPIO 0-15
I2C1_SDA
I2C1_SCL
I2C1_IRQZ
I2C2_SDA
I2C2_SCL
I2C2_IRQZ
SPI_CLK
I2C
Port 1
I2C
Port 2
Digital Core
USB EP
USB EP Phy
SPI_MOSI
SPI_MISO
SPI_SSZ
SPI
OSC
ADC Read
Temp
Sense
Thermal
Shutdown
ADC
图8-8. Digital Core Block Diagram
8.3.5 System Glue Logic
The system glue logic module performs various system interface functions such as control of the system
interface for RESETZ, MRESET, and VOUT_3V3. This module supports various hardware timers for digital
control of analog circuits.
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8.3.6 Power Reset Congrol Module (PRCM)
The PRCM implements all clock management, reset control, and sleep mode control.
8.3.7 Interrupt Monitor
The Interrupt Control module handles all interrupt from the external GPIO as well as interrupts from internal
analog circuits.
8.3.8 ADC Sense
The ADC Sense module is a digital interface to the SAR ADC. The ADC converts various voltages and currents
from the analog circuits. The ADC converts up to 11 channels from analog levels to digital signals. The ADC can
be programmed to convert a single sampled value.
8.3.9 I2C Slave
Two I2C interfaces provide interface to the digital core from the system. These interfaces are master/slave
configurable and support low-speed and full-speed signaling. See the I2C Slave Interface section for more
information.
8.3.10 SPI Master
The SPI master provides a serial interface to an external flash memory. The recommended memory is the
W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65982DMC is
using the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65982DMC is
using the memory in an shared manner. See theSPI Master Interface section for more information.
8.3.11 Single-Wire Debugger Interface
The SWD interface provides a mechanism to directly master the digital core.
8.3.12 ADC
图 8-9 shows the TPS65982DMC ADC. The ADC is a 10-bit successive approximation ADC. The input to the
ADC is an analog input multiplexer that supports multiple inputs from various voltages and currents in the device.
The output from the ADC is available to be read and used by application firmware. Each supply voltage into the
TPS65982DMC is available to be converted including the port power path inputs and outputs.
GPIO
I2C_ADDR
ADP_POWER_CFG
Buffers
ADP_IN
SENSEP
VIN_3V3
VOUT_3V3
LDO_3V3
10 bits
Voltage
Dividers
Input
Mux
SAR ADC
LDO_1V8A
LDO_1V8D
Thermal
Sense
IPP_ADP
I-to-V
图8-9. SAR ADC
8.3.12.1 ADC Divider Ratios
The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing
elements are not divided.
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表8-1 shows the divider ratios for each ADC input. The table also shows which inputs are auto-sequenced in the
round robin automatic readout mode.
表8-1. ADC Divider Ratios
CHANNEL #
SIGNAL
Thermal Sense
ADP_IN
TYPE
Temperature
Voltage
Voltage
Current
-
AUTO-SEQUENCED
DIVIDER RATIO
BUFFERED
0
1
2
3
4
5
Yes
Yes
Yes
Yes
-
N/A
25
25
N/A
-
No
No
No
No
-
SENSEP
IPP_ADP
Reserved
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
7
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
8
9
10
-
No
-
-
1
-
-
No
-
11
12
GPIO5
Voltage
-
Reserved
13
14
Reserved
Reserved
-
-
-
-
-
-
-
-
15
16
17
VIN_3V3
Voltage
Voltage
-
No
No
-
3
3
-
No
No
-
VOUT_3V3
Reserved
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LDO_1V8A
LDO_1V8D
LDO_3V3
I2C_ADDR
GPIO0
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
No
No
No
No
No
No
No
No
No
No
No
No
No
No
2
2
3
3
3
3
3
3
3
3
3
3
3
3
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
ADP_POWER_CFG
8.3.12.2 ADC Operating Modes
The ADC is configured into one of three modes: single channel readout, round robin automatic readout and one
time automatic readout.
8.3.12.3 Single Channel Readout
In Single Channel Readout mode, the ADC reads a single channel only. Once the channel is selected by
firmware, a conversion takes place followed by an interrupt back to the digital core. 图 7-2 shows the timing
diagram for a conversion starting with an ADC enable. When the ADC is disabled and then enabled, there is an
enable time T_ADC_EN (programmable) before sampling occurs. Sampling of the input signal then occurs for
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time T_SAMPLE (programmable) and the conversion process takes time T_CONVERT (12 clock cycles). After
time T_CONVERT, the output data is available for read and an Interrupt is sent to the digital core for time
T_INTA (2 clock cycles).
In Single Channel Readout mode, the ADC can be configured to continuously convert that channel. 图 7-3
shows the ADC repeated conversion process. In this case, once the interrupt time has passed after a
conversion, a new sample and conversion occurs.
8.3.12.4 Round Robin Automatic Readout
When this mode is enabled, the ADC state machine will read from channel 0 to channel 11 and place the
converted data into registers. The host interface can request to read from the registers at any time. During
Round Robin Automatic Readout, the channel averaging must be set to 1 sample.
When the TPS65982DMC is running a Round Robin Readout, it will take approximately 696 μs (11 channels ×
63.33 μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is
converted, it will overwrite the previous result. Therefore, when all channels are read, any given value may be
649 μs out of sync with any other value.
8.3.12.5 One Time Automatic Readout
The One Time Automatic Readout mode is identical to the Round Robin Automatic Readout except the
conversion process halts after the final channel is converted. Once all 11 channels are converted, an interrupt
occurs to the digital core.
8.3.13 I/O Buffers
表8-2 lists the I/O buffer types and descriptions. 表8-3 lists the pin to I/O buffer mapping for cross-referencing a
pin’s particular I/O structure. The following sections show a simplified version of the architecture of each I/O
buffer type.
表8-2. I/O Buffer Type Description
BUFFER TYPE
IOBUF_GPIOHSSWD
IOBUF_GPIOHSSPI
IOBUF_GPIOLS
IOBUF_GPIOLSI2C
IOBUF_I2C
DESCRIPTION
General Purpose High-Speed I/O
General Purpose High-Speed I/O
General Purpose Low-Speed I/O
General Purpose Low-Speed I/O with I2C deglitch time
I2C Compliant Clock/Data Buffers
Open-Drain Output
IOBUF_OD
IOBUF_UTX
Push-Pull output buffer for UART
Input buffer for UART
IOBUF_URX
IOBUF_PORT
Input buffer between 1st/2nd stage Port Data Mux
表8-3. Pin to I/O Buffer Mapping
I/O GROUP/PIN
DEBUG1/2/3/4
DEBUG_CTL1/2
BUFFER TYPE
IOBUF_GPIOLS
IOBUF_GPIOLSI2C
IOBUF_GPIOLS
IOBUF_GPIOLS
IOBUF_OD
SUPPLY CONNECTION (DEFAULT FIRST)
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3, VDDIO
ADP_POWER_CFG
GPIO0-8
I2C_IRQ1/2Z
I2C_SDA1/2/SCL/1/2
LSX_P2R
IOBUF_I2C
IOBUF_UTX
LSX_R2P
IOBUF_URX
MRESET
IOBUF_GPIOLS
IOBUF_GPIOLS
RESETZ
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表8-3. Pin to I/O Buffer Mapping (continued)
I/O GROUP/PIN
UART_RX
BUFFER TYPE
SUPPLY CONNECTION (DEFAULT FIRST)
IOBUF_URX
LDO_3V3, VDDIO
LDO_3V3, VDDIO
LDO_3V3
UART_TX
IOBUF_UTX
PORT_INT
IOBUF_PORT
SPI_MOSI/MISO/CLK/SSZ
SWD_CLK/DATA
IOBUF_GPIOHSSPI
IOBUF_GPIOHSSWD
LDO_3V3
LDO_3V3
8.3.13.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
图8-10 shows the GPIO I/O buffer for all GPIOn pins listed GPIO0-GPIO17 in Pin Functions. GPIOn pins can be
mapped to application-specific events to control other ICs, interrupt a host processor, or receive input from
another IC. This buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When
configured as an input, the signal can be a deglitched digital input or an analog input to the ADC. The push-pull
output is a simple CMOS output with independent pulldown control allowing open-drain connections. The weak
push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to
this buffer is configurable to be LDO_3V3 by default or VDDIO. For simplicity, the connection to VDDIO is not
shown in 图8-10, but the connection to VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO
in this configuration. The pullup and pulldown output drivers are independently controlled from the input and are
enabled or disabled via application code in the digital core.
LDO_3V3
GPIO_OD_EN
GPIO_OE
GPIO_DO
GPIO_PU_EN
GPIO_RPU
GPIO_RPD
GPIO_PD_EN
20 ns
Deglitch
GPIO
GPIO_DI
GPIO_AI_EN
To ADC
图8-10. IOBUF_GPIOLS (General GPIO) I/O
图8-11 shows the IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended deglitch time.
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LDO_3V3
GPIO_OD_EN
GPIO_OE
GPIO_DO
GPIO_PU_EN
GPIO_RPU
GPIO_RPD
GPIO_PD_EN
50 ns
Deglitch
DEBUG_CTL1/2
GPIO_DI
GPIO_AI_EN
To ADC
图8-11. IOBUF_GPIOLSI2C (General GPIO) I/O with I2C Deglitch
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8.3.13.2 IOBUF_OD
The open-drain output driver is shown in 图 8-12 and is the same push-pull CMOS output driver as the GPIO
buffer. The output has independent pulldown control allowing open-drain connections.
OD
OD_DO
图8-12. IOBUF_OD Output Buffer
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8.3.13.3 IOBUF_I2C
The I2C I/O driver is shown in 图 8-13. This I/O consists of an open-drain output and an input comparator with
deglitching. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. This is not
shown in 图8-13. Parameters for the I2C clock and data I/Os are found in 节6.11.
50 ns
I2C_DI
Deglitch
I2C_IRQnZ
I2C_DO
图8-13. IOBUF_I2C I/O
8.3.13.4 IOBUF_GPIOHSPI
图8-14 shows the I/O buffers for the SPI interface.
SPI_x
SPIin
CMOS
Output
SPIout
SPI_OE
图8-14. IOBUF_GPIOHSSPI
8.3.13.5 IOBUF_GPIOHSSWD
图 8-15 shows the I/O buffers for the SWD interface. The CLK input path is a comparator with a pullup
SWD_RPU on the pin. The data I/O consists of an identical input structure as the CLK input but with a tri-state
CMOS output driver.
LDO_3V3
SWD_RPU
SWD_CLK
SWDCLKin
LDO_3V3
SWD_RPU
SWD_DATA
SWDIOin
CMOS
Output
SWDIOout
SWD_OE
图8-15. IOBUF_GPIOHSSWD
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8.3.14 Thermal Shutdown
The TPS65982DMC has both a central thermal shutdown to the chip and a local thermal shutdown for the power
path block. The central thermal shutdown monitors the temperature of the center of the die and disables all
functions except for supervisory circuitry and halts digital core when die temperature goes above a rising
temperature of TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and when the
temperature falls back below this value, the device resumes normal operation. The power path block has its own
local thermal shutdown circuit to detect an over temperature condition due to over current and quickly turn off the
power switches. The power path thermal shutdown values are TSD_PWR and TSDH_PWR. The output of the
thermal shutdown circuit is deglitched by TSD_DG before triggering. The thermal shutdown circuits interrupt to
the digital core.
8.3.15 Oscillators
The TPS65982DMC has two independent oscillators for generating internal clock domains. A 48-MHz oscillator
generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical layer. An
external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator generates
clocks for various timers and clocking the core during low-power states.
8.4 Device Functional Modes
8.4.1 Boot Code
The TPS65982DMC has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset
signal. The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the
digital core and the boot code starts executing. 图8-16 provides the TPS65982DMC boot code sequence.
The TPS65982DMC boot code is loaded from OTP on POR, and begins initializing TPS65982DMC settings.
This initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values
to settle, and configuring the device I2C addresses.
The unique I2C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor
configuration on the I2C_ADDR pin.
Once initial device configuration is complete the boot code determines if the TPS65982DMC is booting under
dead battery condition (VIN_3V3 invalid, ADP_IN valid). If the boot code determines the TPS65982DMC is
booting under dead battery condition, the ADP_POWER_CFG pin is sampled to determine if the adapter power
switch from ADP_IN should be enabled.
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VIN_3V3 or VBUS
Application
Initialize
Configure I2C
Dead Battery
Check
SPI_MISO High
SPI_MISO Low
Load Appcode
Load from SPI
Flash
Download from
UART
图8-16. Flow Diagram for Boot Code Sequence
8.4.2 Initialization
During initialization the TPS65982DMC enables device internal hardware and loads default configurations. The
48-MHz clock is enabled and the TPS65982DMC persistence counters begin monitoring ADP_IN and VIN_3V3.
These counters ensure the supply powering the TPS65982DMC is stable before continuing the initialization
process. The initialization concludes by enabling the thermal monitoring blocks and thermal shutdown protection,
along with the ADC, CRC, GPIO and NVIC blocks.
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8.4.3 I2C Configuration
The TPS65982DMC features dual I2C busses with configurable addresses. The I2C addresses are determined
according to the flow depicted in 图8-17. The address is configured by reading device GPIO states at boot (refer
to the I2C Pin Address Setting section for details). When the I2C addresses are established the TPS65982DMC
enables a limited host interface to allow for communication with the device during the boot process.
Initialization
Complete
Read state of
DEBUG_CTL1
DEBUG_CTL2
I2C_ADDR
Configure I2C
Address
Initialize Host
Interface
图8-17. I2C Address Configuration
8.4.4 Application Code
The TPS65982DMC application code is stored in an external flash memory. The flash memory used for storing
the TPS65982DMC application code may be shared with other devices in the system. The flash memory
organization shown in 图 8-18 supports the sharing of the flash as well as the TPS65982DMC using the flash
without sharing.
The flash is divided into two separate regions, the Low Region and the High Region. The size of this region is
flexible and only depends on the size of the flash memory used. The two regions are used to allow updating the
application code in the memory without over-writing the previous code. This ensures that the new updated code
is valid before switching to the new code. For example, if a power loss occurred while writing new code, the
original code is still in place and used at the next boot.
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0x000000
0x000004
Region Pointer (RPTR)
Low Header
4k
0x000FFC
0x001000
0x001004
Ace Offset (AOFF)
Region Pointer (RPTR)
High Header
4k
0x001FFC
0x002000
Ace Offset (AOFF)
RPTR+AOFF
Ace Configuration Data
Ace Code
72 kB
图8-18. Flash Memory Organization
There are two 4-kB header blocks starting at address 0x000000h. The Low Header 4-kB block is at address
0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR)
that holds the address of the physical location in memory where the low region application code resides. Each
also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the
TPS65982DMC application code resides. The TPS65982DMC firmware physical location in memory is RPTR +
AOFF. The first sections of the TPS65982DMC application code contain device configuration settings. This
configuration determines the devices default behavior after power-up and can be customized using the
TPS65982DMC Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading
and determining whether a region is valid and contains good application code.
8.4.5 Flash Memory Read
The TPS65982DMC first attempts to load application code from the low region of the attached flash memory. If
any part of the read process yields invalid data, the TPS65982DMC will abort the low region read and attempt to
read from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. 图
8-19 shows the flash memory read flow.
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Enter Flash Read
Read Low Header
Region Pointer
and Application
Code Offset
Read High Header
Region Pointer
and Application
Code Offset
Invalid
Config
Read Config
Area
Read Config
Area
Invalid
Config
Valid Config
Invalid App
Code
Read App
Code and
Read App
Code and
Check CRC
Check CRC
Valid App
Code
Valid App
Code
Invalid App
Code
Reset Core and
Run App Code
Memory Invalid
图8-19. Flash Read Flow
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8.4.6 Invalid Flash Memory
If the flash memory read fails because of invalid data, the TPS65982DMC carries out the memory invalid flow
and presents the SWD interface on the USB Type-C SBU pins.
图8-20 shows the invalid memory process.
Memory Invalid
Enable VOUT_3V3
Release RESETZ
VBUS Invalid
Check VBUS
VBUS Good
Present
Rp/Rp
Rd/Rd Not
Attached
Check for
Rd/Rd
Rd/Rd Attached
Present SWD
Monitor VBUS
图8-20. Memory Invalid Flow
8.5 Programming
8.5.1 SPI Master Interface
The TPS65982DMC loads flash memory during the Boot Code sequence. The SPI master electrical
characteristics are defined in SPI Master Characteristics and timing characteristics are defined in 图 7-5. The
TPS65982DMC is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery
conditions, and therefore pullup resistors used for the flash memory must be tied to LDO_3V3. The flash
memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 1 Mbyte (equivalent
to 8 Mbit) to hold the standard application code outlined in Application Code. The SPI master of the
TPS65982DMC supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same
cycle as chip select (SPI_SSZ pin) becomes active. The chip select polarity is active-low. The clock phase is
defined such that data (on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the clock
(SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined
such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable
sector size of the flash must be 4 kB. The W25Q80 flash memory IC is recommended. Refer to TPS65982DMC
I2C Host Interface Specification for instructions for interacting with the attached flash memory over SPI using the
host interface of the TPS65982DMC.
8.5.2 I2C Slave Interface
The TPS65982DMC has two I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1, I2C_SCL1, and
I2C_IRQ1Z pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces
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provide general status information about the TPS65982DMC, the ability to control the TPS65982DMC behavior,
as well as providing control of system PD controllers.
The two ports can be a master or a slave, but the default behavior is to be a slave. Port 1 and Port 2 are
interchangeable. Each port operates the same way and has the same access in and out of the core. An interrupt
mask is set for each that determines what events are interrupted on that given port.
8.5.2.1 I2C Interface Description
The TPS65982DMC support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the
serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup
resistor. Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high
initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/
output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during
each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as
changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
图 8-21 shows the start and stop conditions of the transfer. 图 8-22 shows the SDA and SCL signals for
transferring a bit. 图8-23 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
SDA
SCL
S
P
Start Condition
Stop Condition
图8-21. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
图8-22. I2C Bit Transfer
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Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
图8-23. I2C Acknowledgment
8.5.2.2 I2C Clock Stretching
The TPS65982DMC features clock stretching for the I2C protocol. The TPS65982DMC slave I2C port may hold
the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more
data. The master communicating with the slave must not finish the transmission of the current bit and must wait
until the clock line actually goes high. When the slave is clock stretching, the clock line will remain low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
8.5.2.3 I2C Address Setting
The boot code sets the hardware configurable unique I2C address of the TPS65982DMC before the port is
enabled to respond to I2C transactions. The unique I2C address is determined by the analog level set by the
analog I2C_ADDR strap pin (three bits) as shown in 表8-4.
表8-4. I2C Default Unique Address
Default I2C Unique Address
Bit 7
0
Bit 6
1
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
0
I2C_ADDR_DECODE[2:0]
Note 1: Any bit is maskable for each port independently providing firmware override of the I2C address.
8.5.2.4 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C master and a single
TPS65982DMC. The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands.
图8-24 and 图8-25 show the write and read protocol for the I2C slave interface, and a key is included in 图8-26
to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated
here in part.
1
7
1
1
8
1
8
1
8
1
Unique Address
Register Number
Byte Count = N
Data Byte 1
S
Wr
A
A
A
A
8
1
8
1
Data Byte 2
Data Byte N
A
A
P
图8-24. I2C Unique Address Write Register Protocol
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1
7
1
1
8
1
1
7
1
1
8
1
S
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
A
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
P
图8-25. I2C Unique Address Read Register Protocol
1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
图8-26. I2C Read/Write Protocol Key
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8.5.2.5 I2C Pin Address Setting
To enable the setting of multiple I2C addresses using a single TPS65982DMC pin, a resistance is placed
externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. 图8-27
shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or
low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address
decoding is done by firmware in the digital core.
5 µA
I2C_ADDR
ADC
R_I2C
To Address
Decoder
DEBUG_CTL1
DEBUG_CTL2
Tristate
Debug Data
To Address
Decoder
图8-27. I2C Address Decode
表 8-5 lists the external resistance needed to set bits [3:1] of the I2C Unique Address. For the master
TPS65982DMC, the pin is grounded.
表8-5. I2C Address Resistance
TPS65982DMC
DEVICE
EXTERNAL
RESISTANCE (1%)
I2C UNIQUE
ADDRESS [3:1]
Master 0
Slave 7
Slave 6
Slave 5
Slave 4
Slave 3
Slave 2
Slave 1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x0F
38.3 k
84.5 k
140 k
205 k
280 k
374 k
Open
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9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The typical applications of the TPS65982DMC is as a system policy manager for USB4 docks and hubs with a
single upstream facing port (UFP) capable of sourcing high voltage, and multiple downstream facing ports
(DFP).
9.2 Typical Application
9.2.1 USB4 Device Application with Host Charging
The figure below shows a USB4 Device application, where there are a total of four Type-C PD Ports. One port is
the main connection to a USB4 Host that is a UFP in terms of data and a source of power. The other three ports
are DFPs in terms of data and source power. Generally the main UFP source Type-C PD port provides the
highest power (up to 100 W) to charge a USB4 Host. The key four devices in the system are the PD Controller
(2), Dock Management Controller, USB4 Hub Controller, and UFP Variable Power Supply.
Type-C Power
Barrel
Jack
I2C Communication
SPI Communication
Data Protocol
SPI
Flash
TPS65982DMC
TPS55288
System 5 V
USB2 UFP
USB2 DFP
I2C Host
USB4 Hub Controller
I2C Host
PPHV1
PPHV2
PPHV1
PPHV2
TPS65988
I2C2
I2C2
TPS65988
I2C1
I2C1
VBUS1
VBUS2
VBUS1
VBUS2
Port B DFP Type-C
(5V @ 3A)
Port C DFP Type-C
(5V @ 3A)
Port D DFP Type-C
(5V @ 3A)
图9-1. USB4 Device Block Diagram
In this application, two dual port TPS65988DK PD controllers are used to determine the connection and provide
power on the Type-C ports. The primary TPS65988DK manages Port A (UFP Source) and Port B (DFP Source).
The secondary TPS65988DK manages the other two, Port C (DFP Source) and Port D (DFP Source). For
systems that do not need all four ports a combination of TPS65988DK and TPS65987DDK may be used to scale
for specific design requirements. The PD controllers have two I2C clients that are controlled by the Dock
Management Controller and the USB4 Hub Controller. The PD controllers have an optional I2C Host that may be
used to control a variable power supply.
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The Dock Management Controller (DMC), TPS65982DMC, main functions are the Connection Manager, Power
Manager, Input Power Control, Secure Firmware Update & booting of the PD controllers. The Connection
Manager determines the capabilities of the UFP connection and sets the DFP capabilities accordingly. The
Power Manager keeps the power allocated to each of the Type-C ports within a specific power budget and also
monitors the entire system power to keep from over loading the Barrel Jack adapter supply. The DMC also
controls the input power to the system and soft starts the power path to prevent large inrush currents when the
Barrel Jack supply is connected. The Secure Firmware Update is accomplished over USB2, the DMC is
connected to one of the USB2 DFP ports on the USB4 Hub Controller or USB2 Hub in the system. The DMC
provides the Secure Firmware Update for itself and the PD controllers. The DMC will boot the PD controllers
over the I2C connection. The I2C connection between the DMC and PD controllers also serves as
communication channel for the Connection and Power Manager.
The USB4 Hub Controller manages the data paths for all of the Type-C ports and determines the required data
protocol by reading the PD controller status over I2C connection. The UFP port is the main connection to the
USB4 Hub Controller from a USB4 host. The other DFP ports act as expansion ports to connect other USB
Type-C & PD devices.
The UFP Variable Power Supply provides 5 V/9 V/15 V/20 V up to 100 W to charge the connected USB4 host.
The TPS55288 is used in this application since it is capable of tightly regulating the output voltage and current.
The TPS55288 is best connected to the I2C Host on the Primary PD controller, to set the output voltage and
current regulation. The other DFP ports generally support 5 V @ 3 A to connect to Type-C & PD devices.
9.2.1.1 Design Requirements
9.2.1.1.1 Power Supply Design Requirements
表9-1 shows the Power Design parameters for the USB4 Device application.
表9-1. Power Supply Design Requirements
Power Design Parameters
Value
Current Path
UFP Source Port A
5 V/9 V/15 V/20 V @ 5 A
5 V @ 9 A (3 A per Port)
5 V @ 2 A (500 mA per Port)
20 V @ 10 A (Imax Sensed)
3.3 V @ 150 mA (50 mA per device)
Host Charging VBUS
DFP VBUS
DFP Source Port B/C/D
PP_CABLE Port A/B/C/D
DMC External Input Path
VIN_3V3 PD Controller & DMC
VCONN Source
USB4 Device Input Power
PD Controller& DMC Power
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 USB Power Delivery Source Capabilities
表9-2 summarizes the source PDOs for all of the ports for the USB4 Device.
表9-2. Source Capabilities
Port
PDO Types
Voltage
Current
Port A
Port B
Port C
Port D
Fixed
5 V/9 V/15 V/20 V
3 A/3 A/3 A/5 A
Fixed
5 V
5 V
5 V
3 A
3 A
3 A
Fixed
Fixed
9.2.1.2.2 USB Power Delivery Sink Capabilities
The UFP Source port is the only DRP port that may connect as a DFP or UFP which means that it should have
at least one sink capability when connected as a UFP. The DFP ports can only connect as a DFP, where they do
not have any sink capabilities.
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表9-3. Sink Capabilities
Port
PDO Types
Voltage
Current
Port A
Fixed
5 V
0 A
9.2.1.2.3 Supported Data Modes
USB4 Hub Controllers may vary on the data supported on the UFP and DFP ports. In this specific example the
USB4 Hub Controllers support USB3, DisplayPort, Thunderbolt, and USB4 on the UFP Port. The DFP Ports will
also support these modes when connected to other Type-C & PD devices.
表9-4. Data Modes
Mode of Operation
USB Data
Data
Data Role
USB3.1 Gen2
DP Video
UFP: Device, DFP: Host
UFP: UFP_D, DFP: DFP_D
UFP: Host/Device, DFP: Host
UFP: Device, DFP Host
DisplayPort
Thunderbolt
USB4
PCIe/DP Video
Tunneled USB3/PCIe/DP
9.2.1.2.4 USB4 Hub Controller & PD Controller I2C Communication
The I2C connection from the PD controllers and the USB4 Hub Controller communicates the connection present
at the Type-C Ports. Each port on the USB4 controller may have its I2C interrupt pin to notify the USB4 Hub
Controller which port has a new connection. The PD controllers have an option to use the shared interrupt for
both ports or to have a separate interrupt for each port that is mapped to a GPIO in its configuration. In the
shared interrupt case, the USB4 Hub Controller will query both port addresses and will determine which port has
a data connection. For the dedicated interrupt the USB4 hub controller will only query the specific port address
and determine the connection present.
图9-2 shows the dedicated GPIO interrupt connection.
PA IRQ
PD IRQ
PC IRQ
USB4 Hub Controller
PB IRQ
I2C Host
PA GPIO IRQ
PB GPIO IRQ
I2C2
Client
PC GPIO IRQ
I2C2
Client
PD GPIO IRQ
TPS65988
TPS65988
I2C Communication
I2C Interrupt
图9-2. Dedicated Interrupts for USB4 Hub
图9-3 shows the shared interrupt connection on I2C2_IRQ.
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PA IRQ
PB IRQ
PD IRQ
PC IRQ
USB4 Hub Controller
I2C Host
PB GPIO IRQ
I2C2_IRQ
I2C2
Client
I2C2
TPS65988
TPS65988
Client
I2C Communication
I2C Interrupt
图9-3. Shared Interrupts for USB4 Hub
表9-5 shows an example of the port I2C addresses for each of the PD controller ports.
表9-5. Recommended I2C Addresses - Hub Controller
Port
I2C Address
Port A
Port B
Port C
Port D
0x38
0x3F
0x48
0x4F
9.2.1.2.5 Dock Management Controller & PD Controller I2C Communication
The I2C connection from the PD controllers and the Dock Management Controller communicates to boot up the
PD controllers and enable the Connection & Power Manager functions. The DMC has two GPIO dedicated for
Port A/B and Port C/D interrupts. The shared interrupt connection to the Dock Management Controller will query
both port addresses and will determine which port has been updated.
PA/PB GPIO IRQ
PC/PD GPIO IRQ
TPS65982DMC
I2C Host
I2C1_IRQ
I2C1 Client
I2C1 Client
I2C1_IRQ
I2C Communication
I2C Interrupt
TPS65988
TPS65988
图9-4. Interupt Configuration for DMC
表9-6 shows and example of the port I2C address for each of the PD controller ports.
表9-6. Recommended I2C Addresses - DMC
Port
I2C Address
Port A
Port B
0x20
0x24
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表9-6. Recommended I2C Addresses - DMC (continued)
Port
I2C Address
Port C
Port D
0x21
0x25
9.2.1.2.6 SPI Flash Options
The TPS65982DMC is connected to the SPI Flash which contains the firmware for the DMC and the PD
controllers connected. 表9-7 shows the supported SPI flash options.
表9-7. SPI Flash Options
Manufacturer
Winbond
Spansion
AMIC
Part Number
Size
8 Mb
8 Mb
8 Mb
8 Mb
8 Mb
8 Mb
W25Q80JVNIQ
S25FL208K
A25L080
Macronix
Micron
MX25L8006EM1I
M25PE80-VMN6TP
M25PX80-VMN6TP
Micron
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10 Power Supply Recommendations
10.1 3.3 V Power
10.1.1 1VIN_3V3 Input Switch
The VIN_3V3 input is the main supply to the TPS65982DMC. The VIN_3V3 switch (S1 in 图 8-7) is a
unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when 3.3 V is available. See 表 10-1 for the recommended external capacitance on
the VIN_3V3 pin.
10.1.2 VOUT_3V3 Output Switch
The VOUT_3V3 output switch (S2 in 图 8-7) enables a low-current auxiliary supply to an external element. This
switch is controlled by and is off by default. The VOUT_3V3 output has a supervisory circuit that drives the
RESETZ output as a POR signal to external elements. RESETZ is also asserted by the MRESET pin or a host
controller. See the RESETZ and MRESET section for more details on RESETZ. See 表 10-1 for the
recommended external capacitance on the VOUT_3V3 pin.
10.1.3 ADP_IN 3.3 V LDO
The 3.3 V LDO from ADP_IN steps down voltage from ADP_IN to LDO_3V3. This allows the TPS65982DMC to
be powered from ADP_IN when VIN_3V3 is not available. This LDO steps down any recommended voltage on
the ADP_IN pin. When ADP_IN is 20 V, the internal circuitry of the TPS65982DMC will operate without triggering
thermal shutdown; however, a significant external load on the LDO_3V3 pin can increase temperature enough to
trigger thermal shutdown. The ADP_IN 3.3 V LDO blocks reverse current from LDO_3V3 back to ADP_IN
allowing ADP_IN to be unpowered when LDO_3V3 is driven from another source. See 表 10-1 for the
recommended external capacitance on the ADP_IN and LDO_3V3 pins.
10.2 1.8 V Core Power
Internal circuitry is powered from 1.8 V. There are two LDOs that step the voltage down from LDO_3V3 to 1.8 V.
One LDO powers the internal digital circuits. The other LDO powers internal low voltage analog circuits.
10.2.1 1.8 V Digital LDO
The 1.8 V Digital LDO provides power to all internal low voltage digital circuits. This includes the digital core,
memory, and other digital circuits. See 表 10-1 for the recommended external capacitance on the LDO_1V8D
pin.
10.2.2 1.8 V Analog LDO
The 1.8 V Analog LDO provides power to all internal low voltage analog circuits. See 表 10-1 for the
recommended external capacitance on the LDO_1V8A pin.
10.3 VDDIO
The VDDIO pin provides a secondary input allowing some I/Os to be powered by a source other than LDO_3V3.
The default state is power from LDO_3V3. The memory stored in the flash will configure the I/O’s to use
LDO_3V3 or VDDIO as a source and application code will automatically scale the input and output voltage
thresholds of the I/O buffer accordingly. See I/O Buffers for more information on the I/O buffer circuitry. See 表
10-1 for the recommended external capacitance on the VDDIO pin.
10.3.1 Recommended Supply Load Capacitance
表 10-1 lists the recommended board capacitances for the various supplies. The typical capacitance is the
nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum
capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum
capacitance allowing for tolerances and voltage de-rating ensuring proper operation.
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表10-1. Recommended Supply Load Capacitance
CAPACITANCE
VOLTAGE
MIN
(ABS
MIN)
TYP
(TYP
PLACED)
PARAMETER
DESCRIPTION
RATING
MAX
(ABS MAX)
CVIN_3V3
Capacitance on VIN_3V3
Capacitance on LDO_3V3
6.3 V
5 µF
5 µF
10 μF
10 µF
1 μF
2.2 µF
2.2 µF
2.2 µF
1 µF
CLDO_3V3
CVOUT_3V3
CLDO_1V8D
CLDO_1V8A
CLDO_BMC
CVDDIO
6.3 V
6.3 V
4 V
25 µF
2.5 μF
12 µF
12 µF
4 µF
Capacitance on VOUT_3V3
Capacitance on LDO_1V8D
Capacitance on LDO_1V8A
Capacitance on LDO_BMC
0.1 μF
500 nF
500 nF
1 µF
4 V
4 V
Capacitance on VDDIO. When shorted to LDO_3V3, the CLDO_3V3
capacitance may be shared.
6.3 V
0.1 µF
CADP_IN
CPP_HVEXT
CSS
Capacitance on ADP_IN
25 V
25 V
6.3 V
0.5 µF
1 µF
47 µF
470 nF
12 µF
Capacitance on external high voltage sink from ADP_IN
Capacitance on soft start pin
120 µF
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11 Layout
11.1 Layout Guidelines
Proper placement and routing will maintain signal integrity for the high speed signals and power integrity for the
external power path. The following guidelines show the recommended methodology to properly route all required
signals. Board manufacturing capabilities must be taken into account with any layout to guarantee
manufacturability.
11.2 Layout Example
The layout example is based on the schematic shown in 图 11-1. Some system components are not shown as
they have their own layout recommendations.
图11-1. Example Schematic
11.2.1 Component Placement
The recommended placement is to have the TPS65982DMC on the Top Layer and have all of the passive
components on the opposite layer of the PCB. This will significantly reduce solution size and allows for more
clearance for the high speed and interface signals. 图11-2 and 图11-3 show the top and bottom placement.
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图11-2. Top Layer Component Placement
图11-3. Bottom Layer Component Placement
11.2.2 Recommended Via Size and Trace Widths
For all LDO voltages, GPIO, Interface (I2C/SPI) and VIN_3V3 a single via connection to the pads on the
TPS65982DMC is sufficient. For ADP_IN the current flowing into the device is less than 50mA but it is important
to reduce the inductance in the trace. The ADP_IN capacitor is best placed close to the TPS65982DMC. The
recommended via is a 16mil diameter / 8mil hole that is filled (epoxy fill or Cu fill) and tented on both sides of the
PCB. The tenting will help reduce solder from wicking and lifting the BGA package. 图 11-4 shows the
recommended via size.
图11-4. Recommended Via Sizing
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表11-1 shows the minimum trace widths. It is recommended to take into account any losses that may be present
such as resistance from system supplies to input supply pins (VIN_3V3).
表11-1. Trace Minimum Widths
Signal
Minimum Width (mil)
LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3,
VOUT_3V3, VDDIO, HV_GATE1, HV_GATE2
6
GPIO, I2C, SPI
4
6
Component GND
11.2.3 Adapter Input Power Routing
The TPS65982DMC Adapter Input Power is the main power input to the system. When placing/routing the
external power path it is important to consider the current handling. It is recommended placing a TVS such as
the TVS2200 close to the Adapter Input Power Jack, to absorb any inductive ringing from a hot plug. The
TPS65982DMC external power path should be placed in the same area as the Adapter Input Power Jack. The
HV_GATE1/2 pins are high voltage nets, so it is recommended to space them from sensitive signals. The
HV_GATE1/2 nets can be route through vias if needed. The SENSE_P/N current sense measures the current
flowing into the system and the routing should be as direct, minimal layer changes, and kept from switching nets/
signals.
11.2.4 USB2 Routing
It is important to reduce the number of vias use when routing USB2 signals for UFP_USB2_P/N and
DBG_USB2_P/N. Routing on the top and bottom layers only will reduce the amount of antenna created when
using a through hole via to connect an outer layer to an inner layer. When fanning out the BGA it is
recommended to use 4mil traces to get enough clearance to route the width and gap requirements for
impedance matching. Follow the USB2 specification and USB Hub requirements for complete routing rules
11.2.5 Oval Pad for BGA Fan Out
The footprint shown in 图 11-5 uses an oval footprint for the outer pads of the BGA. This allows for routing the
inner pads through the outer pads. 图11-6 shows the pad size for the out oval pads.
图11-5. Example Footprint with Oval Pads
图11-6. Oval Pad Sizing
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11.2.6 Top and Bottom Layer Complete Routing
图 11-7 and 图 11-8 incorporate the guidelines to route all of the required TPS65982DMC signals on the top and
bottom layer only. For GND and the external power path, they are connected all with planes/pours. Follow the
amount of vias used and placement to ensure proper grounding and heat dissipation. All vias must be connected
to a GND plane.
图11-7. Top Layer Routing
图11-8. Bottom Layer Routing
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65982DMCZBHR
ACTIVE
NFBGA
ZBH
96
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-10 to 85
T65982DMC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65982DMCZBHR
NFBGA
ZBH
96
2500
330.0
16.4
6.3
6.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZBH 96
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TPS65982DMCZBHR
2500
Pack Materials-Page 2
PACKAGE OUTLINE
ZBH0096A
NFBGA - 1 mm max height
SCALE 2.000
PLASTIC BALL GRID ARRAY
6.1
5.9
B
A
BALL A1 CORNER
INDEX AREA
6.1
5.9
(0.65)
C
1 MAX
SEATING PLANE
0.08 C
BALL TYP
5
0.25
TYP
0.19
TYP
SYMM
(0.5) TYP
L
K
J
(0.5) TYP
H
G
F
SYMM
96X
5
TYP
E
D
C
0.35
0.25
0.15
0.05
C A
C
B
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9 10 11
0.5 TYP
4221754/B 09/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
ZBH0096A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
96X ( 0.25)
(0.5) TYP
1
2
3
4
5
6
7
8
9
10
11
A
B
(0.5) TYP
C
D
E
F
G
H
J
SYMM
K
L
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.25)
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221754/B 09/2018
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZBH0096A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
96X ( 0.25)
(0.5) TYP
(R0.05) TYP
7
1
2
3
5
8
9
4
6
10
11
A
B
(0.5) TYP
C
D
E
F
G
H
J
METAL
TYP
SYMM
K
L
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221754/B 09/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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