TPS7101YPW [TI]
LOW-DROPOUT VOLTAGE REGULATORS; 低压差稳压器
| 型号： | TPS7101YPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-DROPOUT VOLTAGE REGULATORS |
| 文件： | 总33页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
D OR P PACKAGE
(TOP VIEW)
Available in 5-V, 4.85-V, and 3.3-V
Fixed-Output and Adjustable Versions
Very Low-Dropout Voltage . . . Maximum of
GND
EN
IN
PG
1
2
3
4
8
7
6
5
32 mV at I = 100 mA (TPS7150)
†
‡
O
SENSE /FB
OUT
Very Low Quiescent Current – Independent
of Load . . . 285 µA Typ
IN
OUT
Extremely Low Sleep-State Current
0.5 µA Max
PW PACKAGE
(TOP VIEW)
2% Tolerance Over Specified Conditions
For Fixed-Output Versions
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
NC
NC
EN
PG
NC
NC
Output Current Range of 0 mA to 500 mA
TSSOP Package Option Offers Reduced
Component Height for Space-Critical
Applications
‡
FB
NC
Power-Good (PG) Status Output
†
SENSE
NC
IN
OUT
OUT
NC
description
IN
The TPS71xx integrated circuits are a family
of micropower low-dropout (LDO) voltage
regulators. An order of magnitude reduction in
dropout voltage and quiescent current over
conventional LDO performance is achieved by
replacing the typical pnp pass transistor with a
PMOS device.
IN
NC
NC – No internal connection
SENSE – Fixed voltage options only
(TPS7133, TPS7148, and TPS7150)
FB – Adjustable version only (TPS7101)
†
‡
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32
mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see
Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very
low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to
500 mA). These two key specifications yield a significant improvement in operating life for battery-powered
systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down
the regulator, reducing the quiescent current to 0.5 µA maximum at T = 25°C.
J
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
description (continued)
0.25
T
A
= 25°C
0.2
0.15
0.1
TPS7133
TPS7148
TPS7150
0.05
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
– Output Current – A
I
O
Figure 1. Dropout Voltage Versus Output Current
Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery
indicator.
The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP
(8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1.2 mm.
AVAILABLE OPTIONS
OUTPUT VOLTAGE
PACKAGED DEVICES
(V)
CHIP FORM
T
J
(Y)
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
MIN
TYP
MAX
4.9
4.75
3.23
5
4.85
3.3
5.1
4.95
3.37
TPS7150QD
TPS7148QD
TPS7133QD
TPS7150QP
TPS7148QP
TPS7133QP
TPS7150QPW
TPS7148QPW
TPS7133QPW
TPS7150Y
TPS7148Y
TPS7133Y
–40°C to 125°C
†
Adjustable
1.2 V to 9.75 V
TPS7101QD
TPS7101QP
TPS7101QPW
TPS7101Y
†
The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is
programmable using an external resistor divider (see application information). The chip form is tested at 25°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
TPS71xx
8
20
15
14
13
V
IN
PG
PG
I
9
IN
IN
SENSE
OUT
10
V
O
6
0.1 µF
EN
OUT
‡
C
O
+
10 µF
GND
1
2
3
CSR
†
‡
TPS7133, TPS7148, TPS7150 (fixed-voltage options)
Capacitor selection is nontrivial. See application information section
for details.
Figure 2. Typical Application Configuration
TPS71xx chip information
These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(5)
(6)
§
SENSE
(3)
(2)
IN
¶
FB
(4)
(5)
(6)
TPS71xx
(4)
(7)
OUT
PG
EN
(1)
(7)
GND
CHIP THICKNESS: 15 MILS TYPICAL
80
BONDING PADS: 4 × 4 MILS MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
§
¶
SENSE – Fixed voltage options only (TPS7133, TPS7148,
and TPS7150)
FB – Adjustable version only (TPS7101)
(3)
(2)
(1)
NOTE A: For most applications, OUT and SENSE should
betiedtogetherascloseaspossibletothedevice;
for other implementations, refer to SENSE-pin
connection discussion in the Applications
Information section of this data sheet.
92
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
functional block diagram
IN
EN
RESISTOR DIVIDER OPTIONS
†
DEVICE
R1
R2
UNIT
†
†
TPS7101
TPS7133
TPS7148
TPS7150
0
∞
Ω
420
726
756
233
233
233
kΩ
kΩ
kΩ
PG
_
+
NOTE A: Resistors are nominal values only.
OUT
COMPONENT COUNT
‡
1.12 V
SENSE /FB
MOS transistors
Bilpolar transistors
Diodes
464
41
4
+
_
R1
R2
V
ref
= 1.178 V
Capacitors
17
76
Resistors
GND
Switch positions are shown with EN low (active).
For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in Applications Information section.
†
‡
§
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
¶
Input voltage range , V , PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 V
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
§
¶
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
#
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 125°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
PW
725 mW
1175 mW
700 mW
5.8 mW/°C
9.4 mW/°C
5.6 mW/°C
464 mW
752 mW
448 mW
145 mW
235 mW
140 mW
||
#
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)
T
≤ 25°C DERATING FACTOR = 70°C
T
T
= 125°C
C
C
C
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
C
D
P
PW
2188 mW
2738 mW
4025 mW
17.5 mW/°C
21.9 mW/°C
32.2 mW/°C
1400 mW
1752 mW
2576 mW
438 mW
548 mW
805 mW
||
#
||
Dissipation rating tables and figures are provided for maintenance of junction temperature at or below
absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within
recommended operating range, see the Thermal Information section.
Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
DISSIPATION DERATING CURVE
vs
†
DISSIPATION DERATING CURVE
vs
FREE-AIR TEMPERATURE
CASE TEMPERATURE
1400
1200
4800
4400
PW Package
4000
3600
3200
2800
2400
2000
1600
1200
800
R
= 31°C/W
θJC
P Package
R
= 106°C/W
1000
800
θJA
P Package
R
= 46°C/W
θJC
D Package
R
= 172°C/W
θJA
600
400
200
0
PW and PWP
Package
= 178°C/W
D Package
= 57°C/W
R
θJA
400
R
θJC
0
25
50
75
100
125
150
25
50
75
100
125
150
T
A
– Free-Air Temperature – °C
T – Case Temperature – °C
C
Figure 3
Figure 4
†
Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.
recommended operating conditions
MIN
2.5
3.77
5.2
5.33
2
MAX
10
UNIT
TPS7101Q
TPS7133Q
TPS7148Q
TPS7150Q
10
‡
Input voltage, V
V
I
10
10
High-level input voltage at EN, V
V
V
IH
Low-level input voltage at EN, V
0.5
500
125
IL
Output current range, I
0
mA
°C
O
Operating virtual junction temperature range, T
–40
J
‡
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To
calculate the minimum input voltage for your maximum output current, use the following equation: V
= V
+ V
DO(max load)
I(min)
O(max)
beforeapplyingtheaboveequation.Theequationforcalculating
BecausetheTPS7101isprogrammable,r
DS(on)
shouldbeusedtocalculateV
DO
V
from r
is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the
DO
DS(on)
recommended input voltage range for the TPS7101.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE/FB shorted to OUT
O
O
(unless otherwise noted)
TPS7101Q, TPS7133Q
TPS7148Q, TPS7150Q
‡
PARAMETER
T
J
UNIT
TEST CONDITIONS
MIN
TYP
MAX
350
460
0.5
2
25°C
–40°C to 125°C
25°C
285
EN ≤ 0.5 V,
V = V + 1 V,
I O
Ground current (active mode)
Input current (standby mode)
Output current limit
µA
µA
A
0 mA ≤ I ≤ 500 mA
O
EN = V ,
2.7 V ≤ V ≤ 10 V
I
I
–40°C to 125°C
25°C
1.2
2
V
O
= 0,
V = 10 V
I
–40°C to 125°C
25°C
2
0.5
1
Pass-element leakage current in standby
mode
µA
µA
EN = V ,
I
2.7 V ≤ V ≤ 10 V
I
–40°C to 125°C
25°C
0.02
0.5
0.5
Normal operation,
V
PG
= 10 V
PG leakage current
–40°C to 125°C
–40°C to 125°C
Output voltage temperature coefficient
Thermal shutdown junction temperature
61
75 ppm/°C
°C
165
2.5 V ≤ V ≤ 6 V
2
I
–40°C to 125°C
V
EN logic high (standby mode)
6 V ≤ V ≤ 10 V
2.7
I
25°C
–40°C to 125°C
25°C
0.5
V
2.7 V ≤ V ≤ 10 V
EN logic low (active mode)
EN hysteresis voltage
I
0.5
50
mV
25°C
–0.5
–0.5
0.5
µA
0.5
0 V ≤ V ≤ 10 V
0 V ≤ V ≤ 10 V
I
EN input current
I
–40°C to 125°C
25°C
2.05
1.06
2.5
V
Minimum V for active pass element
I
–40°C to 125°C
25°C
2.5
1.5
V
Minimum V for valid PG
I
= 300 µA
I
= 300 µA
I
PG
PG
–40°C to 125°C
1.9
†
‡
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C .
O
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
TPS7101 electrical characteristics at I = 10 mA, V = 3.5 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, FB
shorted to OUT at device leads (unless otherwise noted)
O
I
O
TPS7101Q
‡
T
PARAMETER
UNIT
V
TEST CONDITIONS
J
MIN
TYP
MAX
V = 3.5 V,
I
O
= 10 mA
25°C
1.178
I
Reference voltage (measured at FB
with OUT connected to FB)
2.5 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA,
O
I
–40°C to 125°C 1.143
–40°C to 125°C
1.213
V
See Note 1
Reference voltage temperature
coefficient
61
75 ppm/°C
25°C
–40°C to 125°C
25°C
0.7
1
1
V = 2.4 V,
50 µA ≤ I ≤ 150 mA
O
I
0.83
0.52
1.3
150 mA ≤ I ≤ 500
O
V = 2.4 V,
I
mA
–40°C to 125°C
25°C
1.3
Pass-element series resistance
(see Note 2)
Ω
0.85
V = 2.9 V,
I
50 µA ≤ I ≤ 500 mA
O
–40°C to 125°C
25°C
0.85
V = 3.9 V,
I
50 µA ≤ I ≤ 500 mA
0.32
0.23
O
V = 5.9 V,
I
50 µA ≤ I ≤ 500 mA
25°C
O
25°C
18
25
14
25
22
54
V = 2.5 V to 10 V,
I
50 µA ≤ I ≤ 500 mA,
O
Input regulation
mV
mV
mV
See Note 1
–40°C to 125°C
25°C
I
= 5 mA to 500 mA, 2.5 V ≤ V ≤ 10 V,
I
O
See Note 1
–40°C to 125°C
25°C
Output regulation
I
O
= 50 µA to 500 mA, 2.5 V ≤ V ≤ 10 V,
I
See Note 1
f = 120 Hz
–40°C to 125°C
25°C
–40°C to 125°C
25°C
48
44
45
44
59
54
I
I
= 50 µA
O
Ripple rejection
dB
= 500 mA,
O
See Note 1
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
95
89
74
µV/√Hz
µVrms
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
25°C
O
O
O
10 Hz ≤ f ≤ 100 kHz,
25°C
†
CSR = 1 Ω
25°C
§
V
FB
voltage decreasing from above V
PG
–40°C to 125°C 1.101
1.145
V
PG trip-threshold voltage
§
25°C
25°C
12
mV
Measured at V
PG hysteresis voltage
FB
0.1
0.4
0.4
10
§
I
= 400 µA,
V = 2.13 V
I
V
PG output low voltage
PG
–40°C to 125°C
25°C
–10
–20
0.1
FB input current
nA
–40°C to 125°C
20
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
‡
§
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r
increases (see Figure 27) to a point such that the resulting
I
O
DS(on)
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation:
V
DO
= I
r
O
DS(on)
r
is a function of both output current and input voltage. The parametric table lists r
for V = 2.4 V, 2.9 V, 3.9 V, and
I
DS(on)
DS(on)
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figure 26.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
TPS7133 electrical characteristics at I = 10 mA, V = 4.3 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE
shorted to OUT (unless otherwise noted)
O
I
O
TPS7133Q
‡
T
J
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V = 4.3 V,
I
= 10 mA
25°C
3.3
I
O
Output voltage
V
4.3 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
3.23
3.37
7
I
O
25°C
4.5
47
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 3.23 V
I
–40°C to 125°C
25°C
8
60
V = 3.23 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
80
235
0.47
300
400
0.6
0.8
20
V = 3.23 V
I
–40°C to 125°C
25°C
(3.23 V – V )/I ,
V = 3.23 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 4.3 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
27
21
30
54
49
38
I
= 5 mA to 500 mA, 4.3 V ≤ V ≤ 10 V
I
O
O
–40°C to 125°C
25°C
75
Output regulation
Ripple rejection
60
I
= 50 µA to 500 mA, 4.3 V ≤ V ≤ 10 V
I
–40°C to 125°C
25°C
120
43
40
39
36
I
I
= 50 µA
O
–40°C to 125°C
25°C
f = 120 Hz
dB
= 500 mA
O
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
274
228
159
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
10 Hz ≤ f ≤ 100 kHz,
25°C
†
CSR = 1 Ω
25°C
V
O
voltage decreasing from above V
PG
–40°C to 125°C 2.868
25°C
3
V
PG trip-threshold voltage
PG hysteresis voltage
35
mV
25°C
0.22
0.4
0.4
PG output low voltage
I
= 1 mA,
V = 2.8 V
I
V
PG
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
TPS7148 electrical characteristics at I =10mA, V =5.85V, EN=0V, C =4.7µF/CSR =1Ω,SENSE
shorted to OUT (unless otherwise noted)
O
I
O
TPS7148Q
‡
T
J
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V = 5.85 V,
I
= 10 mA
25°C
4.85
I
O
Output voltage
V
5.85 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
4.75
4.95
6
I
O
25°C
2.9
30
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.75 V
I
–40°C to 125°C
25°C
8
37
V = 4.75 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
54
150
0.32
180
250
0.35
0.52
27
V = 4.75 V
I
–40°C to 125°C
25°C
(4.75 V – V )/I ,
V = 4.75 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 5.85 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
37
12
42
53
50
42
I
= 5 mA to 500 mA, 5.85 V ≤ V ≤ 10 V
I
O
O
–40°C to 125°C
25°C
80
Output regulation
Ripple rejection
60
I
= 50 µA to 500 mA, 5.85 V ≤ V ≤ 10 V
I
–40°C to 125°C
25°C
130
42
39
39
35
I
I
= 50 µA
O
–40°C to 125°C
25°C
f = 120 Hz
dB
= 500 mA
O
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
410
328
212
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
10 Hz ≤ f ≤ 100 kHz,
25°C
†
CSR = 1 Ω
25°C
V
O
voltage decreasing from above V
PG
–40°C to 125°C
25°C
4.5
4.7
V
PG trip-threshold voltage
PG hysteresis voltage
50
mV
25°C
0.2
0.4
0.4
I
= 1.2 mA,
V = 4.12 V
I
V
PG output low voltage
PG
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
TPS7150 electrical characteristics at I = 10 mA, V = 6 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE
shorted to OUT (unless otherwise noted)
O
I
O
TPS7150Q
‡
T
J
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V = 6 V,
I
= 10 mA
25°C
5
I
O
Output voltage
V
6 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
4.9
5.1
6
I
O
25°C
2.9
27
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.88 V
I
–40°C to 125°C
25°C
8
32
V = 4.88 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
47
146
0.29
170
230
0.32
0.47
25
V = 4.88 V
I
–40°C to 125°C
25°C
(4.88 V – V )/I ,
V = 4.88 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 6 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
32
30
45
55
52
45
I
= 5 mA to 500 mA, 6 V ≤ V ≤ 10 V
I
O
O
–40°C to 125°C
25°C
86
Output regulation
Ripple rejection
65
I
= 50 µA to 500 mA, 6 V ≤ V ≤ 10 V
I
–40°C to 125°C
25°C
140
45
40
42
36
I
I
= 50 µA
O
–40°C to 125°C
25°C
f = 120 Hz
dB
= 500 mA
O
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
430
345
220
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
10 Hz ≤ f ≤ 100 kHz,
25°C
†
CSR = 1 Ω
25°C
V
O
voltage decreasing from above V
PG
–40°C to 125°C
25°C
4.55
4.75
V
PG trip-threshold voltage
PG hysteresis voltage
53
mV
25°C
0.2
0.4
0.4
PG output low voltage
I
= 1.2 mA,
V = 4.25 V
I
V
PG
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE/FB
O
O
J
shorted to OUT (unless otherwise noted)
TPS7101Y, TPS7133Y
TPS7148Y, TPS7150Y
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
EN ≤ 0.5 V,
0 mA ≤ I ≤ 500 mA
V = V + 1 V,
I O
Ground current (active mode)
285
µA
O
Output current limit
V
= 0,
V = 10 V
1.2
0.02
165
50
A
µA
°C
mV
V
O
I
Normal operation,
V
PG
= 10 V
PG leakage current
Thermal shutdown junction temperature
EN hysteresis voltage
Minimum V for active pass element
2.05
1.06
I
Minimum V for valid PG
I
= 300 µA
V
I
PG
TPS7101Y
TYP
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
Reference voltage (measured at FB with OUT
connected to FB)
V = 3.5 V,
I
I
O
= 10 mA
1.178
V
V = 2.4 V,
50 µA ≤ I ≤ 150 mA
0.7
0.83
0.52
0.32
0.23
I
O
V = 2.4 V,
I
150 mA ≤ I ≤ 500 mA
O
V = 2.9 V,
I
50 µA ≤ I ≤ 500 mA
Ω
Pass-element series resistance (see Note 2)
O
V = 3.9 V,
I
50 µA ≤ I ≤ 500 mA
O
V = 5.9 V,
I
50 µA ≤ I ≤ 500 mA
O
V = 2.5 V to 10 V,
I
50 µA ≤ I ≤ 500 mA,
O
Input regulation
18
14
22
mV
mV
mV
See Note 1
2.5 V ≤ V ≤ 10 V,
I
= 5 mA to 500 mA,
I
O
O
See Note 1
Output regulation
2.5 V ≤ V ≤ 10 V,
I
= 50 µA to 500 mA,
I
See Note 1
V = 3.5 V,
f = 120 Hz,
I
Ripple rejection
59
dB
I
O
= 50 µA
Output noise-spectral density
V = 3.5 V,
f = 120 Hz
2
95
89
74
12
µV/√Hz
I
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
V = 3.5 V,
I
Output noise voltage
µVrms
10 Hz ≤ f ≤ 100 kHz,
†
CSR = 1 Ω
§
mV
V
V = 3.5 V,
I
Measured at V
FB
PG hysteresis voltage
§
V = 2.13 V,
I
I
= 400 µA
0.1
0.1
PG output low voltage
PG
FB input current
nA
V = 3.5 V
I
V = 3.5 V
I
†
‡
§
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r
increases (see Figure 27) to a point such that the resulting
I
O
DS(on)
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation:
V
DO
= I
r
O
DS(on)
r
is a function of both output current and input voltage. The parametric table lists r
for V = 2.4 V, 2.9 V, 3.9 V, and
I
DS(on)
DS(on)
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figure 26.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE shorted
O
O
J
to OUT (unless otherwise noted) (continued)
TPS7133Y
TYP
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
Output voltage
Dropout voltage
V = 4.3 V,
I
O
I
O
I
O
I
O
= 10 mA
= 10 mA
= 100 mA
= 500 mA
3.3
V
I
V = 3.23 V,
I
0.02
V = 3.23 V,
I
47
mV
V = 3.23 V,
I
235
(3.23 V – V )/I ,
V = 3.23 V,
I
O
O
Pass-element series resistance
Output regulation
0.47
Ω
I
O
= 500 mA
4.3 V ≤ V ≤ 10 V,
I
O
I
O
I
O
I
O
= 5 mA to 500 mA
= 50 µA to 500 mA
= 50 µA
21
30
mV
mV
I
4.3 V ≤ V ≤ 10 V,
I
54
V = 4.3 V,
I
f = 120 Hz
Ripple rejection
dB
= 500 mA
49
Output noise-spectral density
V = 4.3 V,
I
f = 120 Hz
2
µV/√Hz
274
228
159
35
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
V = 4.3 V,
I
10 Hz ≤ f ≤ 100 kHz,
Output noise voltage
µVrms
†
CSR = 1 Ω
mV
V
PG hysteresis voltage
PG output low voltage
V = 4.3 V
I
V = 2.8 V,
I
I
= 1 mA
0.22
PG
TPS7148Y
TYP
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
Output voltage
V = 5.85 V,
I
O
I
O
I
O
I
O
= 10 mA
= 10 mA
= 100 mA
= 500 mA
4.85
V
I
V = 4.75 V,
I
0.08
V = 4.75 V,
I
30
mV
Dropout voltage
V = 4.75 V,
I
150
(4.75 V – V )/I ,
V = 4.75 V,
I
O
O
Pass-element series resistance
Output regulation
0.32
Ω
I
O
= 500 mA
5.85 V ≤ V ≤ 10 V,
I
O
I
O
I
O
I
O
= 5 mA to 500 mA
= 50 µA to 500 mA
= 50 µA
12
42
mV
mV
I
5.85 V ≤ V ≤ 10 V,
I
53
V = 5.85 V,
I
f = 120 Hz
Ripple rejection
dB
= 500 mA
50
Output noise-spectral density
V = 5.85 V,
I
f = 120 Hz
2
µV/√Hz
410
328
212
50
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
V = 5.85 V,
I
10 Hz ≤ f ≤ 100 kHz,
Output noise voltage
µVrms
†
CSR = 1 Ω
mV
V
PG hysteresis voltage
PG output low voltage
V = 5.85 V
I
V = 4.12 V,
I
I
= 1.2 mA
0.2
0.4
PG
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
‡
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
†
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE shorted
O
O
J
to OUT (unless otherwise noted) (continued)
TPS7150Y
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
5
MAX
Output voltage
Dropout voltage
V = 6 V,
I
O
I
O
I
O
I
O
= 10 mA
V
I
V = 4.88 V,
I
= 10 mA
= 100 mA
= 500 µA
0.13
27
V = 4.88 V,
I
mV
V = 4.88 V,
I
146
(4.88 V – V )/I ,
V = 4.88 V,
I
O
O
Pass-element series resistance
Output regulation
0.29
Ω
I
O
= 500 mA
6 V ≤ V ≤ 10 V,
I
O
I
O
I
O
I
O
= 5 mA to 500 mA
= 50 µA to 500 mA
= 50 µA
30
45
mV
mV
I
6 V ≤ V ≤ 10 V,
I
55
V = 6 V,
I
f = 120 Hz
Ripple rejection
dB
= 500 mA
52
Output noise-spectral density
V = 6 V,
I
f = 120 Hz
2
µV/√Hz
430
345
220
53
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
O
O
O
V = 6 V,
I
10 Hz ≤ f ≤ 100 kHz,
Output noise voltage
µVrms
†
CSR = 1 Ω
mV
V
PG hysteresis voltage
PG output low voltage
V = 6 V
I
V = 4.25 V,
I
= 1.2 mA
0.2
PG
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
.
O
‡
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
5
vs Output current
I
Q
Quiescent current
vs Input voltage
6
vs Free-air temperature
vs Output current
7
V
Typical Dropout voltage
Change in dropout voltage
Change in output voltage
Output voltage
8
DO
∆V
∆V
vs Free-air temperature
vs Free-air temperature
vs Input voltage
9
DO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
O
V
O
∆V
Change in output voltage
vs Input voltage
O
V
O
Output voltage
Ripple rejection
vs Output current
vs Frequency
vs Frequency
Output spectral noise density
r
Pass-element resistance
Divider resistance
vs Input voltage
DS(on)
R
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
I
SENSE current
I(SENSE)
FB leakage current
Minimum input voltage for active-pass element
Minimum input voltage for valid PG
Input current (EN)
V
I
I
I(EN)
Output voltage response from Enable (EN)
Power-good (PG) voltage
V
PG
vs Output voltage
vs Output current
34
35
36
37
38
39
40
41
CSR
CSR
CSR
CSR
Compensation Series Resistance
Compensation Series Resistance
Compensation Series Resistance
Compensation Series Resistance
vs Ceramic capacitance
vs Output current
vs Ceramic capacitance
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
QUIESCENT CURRENT
vs
OUTPUT CURRENT
INPUT VOLTAGE
355
345
335
400
350
300
250
200
150
100
T
R
= 25°C
= 10 Ω
A
L
T
= 25°C
A
TPS71xx, V = 10 V
I
TPS7133
TPS7148
325
315
305
295
TPS7150
TPS7101 With V
Programmed to 2.5 V
O
TPS7150, V = 6 V
I
285
275
265
TPS7148, V = 5.85 V
I
50
0
TPS7133, V = 4.3 V
I
0
50 100 150 200 250 300 350 400 450 500
0
1
2
3
4
5
6
7
8
9
10
I
O
– Output Current – mA
V – Input Voltage – V
I
Figure 5
Figure 6
TPS7148Q
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
400
0.3
V = V
+ 1 V
I
O(nom)
= 10 mA
T
A
= 25°C
I
O
0.25
350
300
250
TPS7133
0.2
0.15
TPS7148
TPS7150
0.1
0.05
0
200
150
0
50 100 150 200 250 300 350 400 450 500
–50
–25
0
25
50
75
100
125
T
A
– Free-Air Temperature – °C
I
O
– Output Current – mA
Figure 8
Figure 7
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
CHANGE IN DROPOUT VOLTAGE
vs
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
10
8
20
15
10
5
I
O
= 100 mA
V = V
+ 1 V
I
O(nom)
I
O
= 10 mA
6
4
2
0
0
–2
–4
–5
–10
–15
–20
–6
–8
–10
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 9
Figure 10
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
CHANGE IN OUTPUT VOLTAGE
vs
INPUT VOLTAGE
6
5
4
3
2
1
20
T
R
= 25°C
= 10 Ω
T
R
= 25°C
= 10 Ω
A
L
A
L
TPS7150
15
10
5
TPS7148
TPS7150
TPS7148
0
–5
TPS7133
TPS7133
TPS7101 With V
O
Programmed to 2.5 V
–10
–15
–20
0
0
1
2
3
4
5
6
7
8
9
10
4
5
6
7
8
9
10
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 11
Figure 12
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
TPS7101Q
OUTPUT VOLTAGE
vs
TPS7133Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
2.52
2.515
2.51
3.34
3.33
3.32
3.31
3.3
T
V
= 25°C
Programmed to 2.5 V
A
O
T
A
= 25°C
2.505
2.5
V = 10 V
I
V = 3.5 V
I
V = 4.3 V
I
2.495
2.49
3.29
3.28
V = 10 V
I
2.485
2.48
3.27
3.26
0
100
200
300
400
500
0
100
200
300
400
500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 13
Figure 14
TPS7148Q
TPS7150Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.92
4.91
4.9
5.06
5.05
5.04
5.03
5.02
5.01
5
T
A
= 25°C
T
A
= 25°C
4.89
4.88
4.87
4.86
4.85
4.84
V = 6 V
I
V = 5.85 V
I
4.99
4.98
V = 10 V
I
V = 10 V
I
4.83
4.82
4.81
4.8
4.97
4.96
4.95
4.94
0
100
200
300
400
500
0
100
200
300
400
500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 15
Figure 16
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
TPS7133Q
RIPPLE REJECTION
vs
TPS7101Q
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
70
60
50
70
60
50
R
= 100 kΩ
L
R
= 100 kΩ
L
40
30
40
R
= 500 Ω
L
30
20
10
0
R
= 500 Ω
L
T
= 25°C
20
A
I
V = 3.5 V
R
L
= 10 Ω
C
= 4.7 µF (CSR = 1 Ω)
T
= 25°C
O
10
A
I
No Input Capacitance
Programmed to 2.5 V
V = 3.5 V
V
O
C
= 4.7 µF (CSR = 1 Ω)
O
0
No Input Capacitance
R
= 10 Ω
L
–10
10
100
1K
10K
100K
1M
10M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
TPS7148Q
RIPPLE REJECTION
vs
TPS7150Q
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
70
60
50
70
60
50
40
30
20
10
0
R
= 100 kΩ
L
R
L
= 100 kΩ
L
40
30
R
= 10 Ω
L
R
= 10 Ω
L
R
= 500 Ω
20
R
= 500 Ω
L
10
T
= 25°C
V = 3.5 V
A
I
T
= 25°C
A
V = 3.5 V
I
0
C
= 4.7 µF (CSR = 1 Ω)
No Input Capacitance
O
C
= 4.7 µF (CSR = 1 Ω)
O
No Input Capacitance
–10
10
100 1 k
10 k
100 k
1 M
10 M
10
100 1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 19
Figure 20
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
TPS7101Q
TPS7133Q
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
T
= 25°C
T = 25°C
A
A
No Input Capacitance
V = 3.5 V
V
No Input Capacitance
V = 4.3 V
I
I
O
Programmed to 2.5 V
C
= 10 µF (CSR = 1 Ω)
C
= 4.7 µF (CSR = 1 Ω)
O
O
1
1
C
= 4.7 µF (CSR = 1 Ω)
O
C
= 10 µF (CSR = 1 Ω)
O
C
= 100 µF (CSR = 1 Ω)
O
0.1
0.01
0.1
C
= 100 µF (CSR = 1 Ω)
O
0.01
2
10
3
10
4
10
5
10
2
10
3
10
4
10
5
10
10
10
f – Frequency – Hz
f – Frequency – Hz
Figure 21
Figure 22
TPS7148Q
TPS7150Q
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
T
= 25°C
A
C
= 10 µF (CSR = 1 Ω)
O
No Input Capacitance
V = 5.85 V
I
C
= 4.7 µF (CSR = 1 Ω)
O
C
= 10 µF (CSR = 1 Ω)
O
1
1
C
= 4.7 µF (CSR = 1 Ω)
O
T
A
= 25°C
No Input Capacitance
V = 6 V
I
0.1
0.01
0.1
C
= 100 µF (CSR = 1 Ω)
O
C
= 100 µF (CSR = 1 Ω)
O
0.01
10
100
1 k
10 k
100 k
10
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 23
Figure 24
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
PASS-ELEMENT RESISTANCE
DIVIDER RESISTANCE
vs
FREE-AIR TEMPERATURE
vs
INPUT VOLTAGE
1.1
1
1.2
1.1
1
T
V
= 25°C
V = V
I
I(sense)
+ 1 V
A
O(nom)
= V
= 1.12 V
V
I(FB)
O(nom)
TPS7150
0.9
0.8
0.7
TPS7148
I
O
= 500 mA
0.9
0.6
0.5
0.4
0.8
0.7
I
O
= 100 mA
TPS7133
0.6
0.5
0.4
0.3
0.2
0.1
2
3
4
5
6
7
8
9
10
–50
–25
0
25
50
75
100
125
V – Input Voltage – V
I
T
A
– Free-Air Temperature – °C
Figure 25
Figure 26
FIXED-OUTPUT VERSIONS
SENSE PIN CURRENT
vs
ADJUSTABLE VERSION
FB LEAKAGE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
6
5.8
5.6
5.4
0.6
V = V
+ 1 V
O(nom)
I
V
FB
= 2.5 V
V
= V
I(sense)
O(nom)
0.5
0.4
0.3
5.2
5
0.2
0.1
0
4.8
4.6
4.4
–50
–25
T
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
A
Figure 27
Figure 28
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
MINIMUM INPUT VOLTAGE FOR ACTIVE
MINIMUM INPUT VOLTAGE FOR VALID
POWER GOOD (PG)
vs
PASS ELEMENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.1
2.1
2.09
2.08
2.07
R
= 500 Ω
L
1.09
1.08
1.07
2.06
2.05
2.04
2.03
2.02
1.06
1.05
2.01
2
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 29
Figure 30
EN INPUT CURRENT
vs
FREE-AIR TEMPERATURE
100
V = V
I
= 10 V
I(EN)
90
80
70
60
50
40
30
20
10
0
–40 –20
0
20 40 60
80 100 120 140
T
A
– Free-Air Temperature – °C
Figure 31
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
V
O(nom)
T
R
C
= 25°C
= 500 Ω
= 4.7 µF (ESR = 1Ω)
A
L
O
6
4
No Input Capacitance
2
0
–2
0
20 40 60 80 100 120 140
Time – µs
Figure 32
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE
6
5
4
3
2
1
T
= 25°C
A
PG Pulled Up to 5 V With 5 kΩ
0
93
94
95
96
97
98
) – %
V
O
– Output Voltage (V as a percent of V
O
O(nom)
Figure 33
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
V = V
+ 1 V
I
O(nom)
No Input Capacitance
= 4.7 µF
V = V
+ 1 V
I
O(nom)
No Input Capacitance
= 4.7 µF + 0.5 µF of
C
O
C
O
No Added Ceramic Capacitance
= 25°C
Ceramic Capacitance
= 25°C
T
A
T
A
Region of Instability
10
10
Region of Instability
1
1
Region of Instability
Region of Instability
50 100 150 200 250 300 350 400 450 500
0.1
0.1
0
50 100 150 200 250 300 350 400 450 500
0
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 34
Figure 35
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
100
100
V = V
+ 1 V
V = V
+ 1 V
I
O(nom)
No Input Capacitance
= 100 mA
I
O(nom)
No Input Capacitance
I = 500 mA
O
I
C
T
O
O
A
= 4.7 µF
= 25°C
C
= 4.7 µF
T = 25°C
A
O
10
10
Region of Instability
Region of Instability
1
1
Region of Instability
Region of Instability
0.1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Ceramic Capacitance – µF
Ceramic Capacitance – µF
Figure 36
Figure 37
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
†
TYPICAL REGIONS OF STABILITY
†
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
COMPENSATION SERIES RESISTANCE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
V = V
+ 1 V
I
O(nom)
No Input Capacitance
= 10 µF
V = V
+ 1 V
Region of Instability
I
O(nom)
No Input Capacitance
C = 10 µF + 0.5 µF of
O
C
O
No Ceramic Capacitance
= 25°C
Added Ceramic Capacitance
T = 25°C
A
T
A
10
10
Region of Instability
1
1
0.1
0.1
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 38
Figure 39
†
†
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
100
100
V = V
+ 1 V
V = V
+ 1 V
I
O(nom)
No Input Capacitance
= 10 µF
I
O(nom)
No Input Capacitance
C = 10 µF
O
C
O
I
T
= 100 mA
I
T
= 500 mA
= 25°C
O
O
= 25°C
A
A
10
10
Region of Instability
Region of Instability
1
1
0.1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Ceramic Capacitance – µF
Ceramic Capacitance – µF
Figure 40
Figure 41
†CSR values below 0.1 Ω are not recommended.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
TYPICAL CHARACTERISTICS
To Load
IN
V
I
OUT
+
SENSE
C
†
O
C
cer
R
EN
L
GND
CSR
†
Ceramic capacitor
Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41)
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
APPLICATION INFORMATION
The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of
earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good
indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the
TPS7148(4.85V), andtheTPS7150(5V). Thefamilyalsooffersanadjustabledevice, theTPS7101(adjustable
from 1.2 V to 9.75 V).
device operation
The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even
with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly
proportional to the load current through the regulator (I = I /β). Close examination of the data sheets reveals
B
C
that those devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS
transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low
and invariable over the full load range. The TPS71xx specifications reflect actual performance under load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates
B
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems.
Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular
systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems
specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack
before the device drops out, adding crucial talk minutes between charges.
The TPS71xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 120 µs.
minimum load requirements
The TPS71xx family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection
The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the
regulator. Normally, this connection should be as short as possible; however, the connection can be made near
a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a
high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through
to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an
RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator
to oscillate.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply.
A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients
with fast rise times are anticipated.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
APPLICATION INFORMATION
external capacitor requirements (continued)
As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A low-ESR 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because minimum capacitor ESR is
seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit
ESR to 1.5 Ω maximum. As show in the ESR graphs (Figures 34 through 41), minimum ESR is not a problem
when using 10-µF or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS71xx family. This information (along
with the ESR graphs, Figures 34 through 41) is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines
above.
All load and temperature conditions with up to 1 µF of added ceramic load capacitance:
†
†
†
†
PART NO.
MFR.
VALUE
MAX ESR
0.5
SIZE (H × L × W)
2.8 × 6 × 3.2
T421C226M010AS
593D156X0025D2W
593D106X0035D2W
Kemet
22 µF, 10 V
Sprague 15 µF, 25 V
Sprague 10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
0.3
TPSD106M035R0300 AVX
10 µF, 35 V
0.3
Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
SIZE (H × L × W)
1.2 × 7.2 × 6
592D156X0020R2T
595D156X0025C2T
595D106X0025C2T
293D226X0016D2W
Sprague 15 µF, 20 V
Sprague 15 µF, 25 V
Sprague 10 µF, 25 V
Sprague 22 µF, 16 V
1.1
1
2.5 × 7.1 × 3.2
2.5 × 7.1 × 3.2
2.8 × 7.3 × 4.3
1.2
1.1
Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
1.5
SIZE (H × L × W)
1.3 × 3.5 × 2.7
1.3 × 7 × 2.7
195D106X06R3V2T
195D106X0016X2T
595D156X0016B2T
695D226X0015F2T
695D156X0020F2T
695D106X0035G2T
Sprague 10 µF, 6.3 V
Sprague 10 µF, 16 V
Sprague 15 µF, 16 V
Sprague 22 µF, 15 V
Sprague 15 µF, 20 V
Sprague 10 µF, 35 V
1.5
1.8
1.6 × 3.8 × 2.6
1.8 × 6.5 × 3.4
1.8 × 6.5 × 3.4
2.5 × 7.6 × 2.5
1.4
1.5
1.3
†
Size is in mm. ESR is maximum resistance at 100 kHz and T = 25°C. Listings are sorted by height.
A
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
APPLICATION INFORMATION
external capacitor requirements (continued)
†
TPS71xx
8
20
15
14
13
V
IN
PG
PG
I
9
250 kΩ
IN SENSE
10
V
O
IN
OUT
OUT
C1
0.1 µF
50 V
6
EN
C
+
O
10 µF
GND
CSR
1
2
3
†
TPS7133, TPS7148, TPS7150 (fixed-voltage options)
Figure 43. Typical Application Circuit
programming the TPS7101 adjustable LDO regulator
Programming the adjustable regulators is accomplished using an external resistor divider as shown in
Figure 44. The equation governing the output voltage is:
R1
R2
V
V
1
O
ref
where
V
= reference voltage, 1.178 V typ
ref
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
APPLICATION INFORMATION
programming the TPS7101 adjustable LDO regulator (continued)
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2
is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent
advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at
FB will introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate
resistance:
V
O
R1
1
R2
V
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS7101
OUTPUT
VOLTAGE
R1
R2
UNIT
Power-Good
Indicator
250 kΩ
V
I
IN
PG
OUT
FB
0.1 µF
2.5 V
3.3 V
3.6 V
4 V
191
309
348
402
549
750
169
169
169
169
169
169
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
>2.7 V
EN
V
O
<0.5V
+
R1
5 V
GND
6.4 V
R2
Figure 44. TPS7101 Adjustable LDO Regulator Programming
power-good indicator
The TPS71xx features a power-good (PG) output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup
resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery
indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance,
but instead reports an output voltage low, relative to its nominal regulated value.
regulator protection
The TPS71xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS71xx also features internal current limiting and thermal protection. During normal operation, the
TPS71xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 03/95
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
E. Four center pins are connected to die mount pad.
F. Falls within JEDEC MS-012
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092F – NOVEMBER 1994 – REVISED JANUARY 1997
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,17
0,65
M
0,13
14
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,10 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/D 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1999, Texas Instruments Incorporated
相关型号：
TPS71157YZR
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PBGA8, CSP-8, Fixed Positive Multiple Output LDO Regulator
TI
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