TPS73125DBVRG4 [TI]
Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection; 无电容， NMOS器，150mA低压降稳压器，具有反向电流保护
| 型号： | TPS73125DBVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 文件： | 总18页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS731xx
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SBVS034H–SEPTEMBER 2003–REVISED OCTOBER 2006
Cap-Free, NMOS, 150mA Low Dropout Regulator
with Reverse Current Protection
FEATURES
DESCRIPTION
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
The TPS731xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly
constant over all values of output current.
•
•
•
Input Voltage Range of 1.7V to 5.5V
Ultralow Dropout Voltage: 30mV Typ
Excellent Load Transient Response—with or
without Optional Output Capacitor
•
New NMOS Topology Provides Low Reverse
Leakage Current
The TPS731xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µVRMS with 0.1µF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
•
•
•
Low Noise: 30µVRMS Typ (10kHz to 100kHz)
0.5% Initial Accuracy
1% Overall Accuracy over Line, Load, and
Temperature
•
•
Less Than 1µA Max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
•
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 5.0V
– Adjustable Outputs from 1.20V to 5.5V
– Custom Outputs Available
APPLICATIONS
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Optional
Optional
DBV PACKAGE
SOT23
(TOP VIEW)
VIN
VOUT
IN
OUT
TPS731xx
GND
EN
NR
5
4
IN
GND
EN
1
2
3
OUT
Optional
Typical Application Circuit for Fixed-Voltage Versions
NR/FB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
TPS731xx
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SBVS034H–SEPTEMBER 2003–REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS731xxyyyz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Output voltages from 1.3V to 4V in 100mV increments are available through the use of innovative factory EEPROM programming.
Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
TPS731xx
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
–65 to +150
2
°C
°C
kV
V
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RΘJC
RΘJA
POWER RATING POWER RATING POWER RATING
Low-K(2)
DBV
DBV
64°C/W
64°C/W
255°C/W
180°C/W
3.9mW/°C
5.6mW/°C
390mW
560mW
215mW
310mW
155mW
225mW
(3)
High-K
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
VIN
Input voltage range(1)
Internal reference (TPS73101)
Output voltage range (TPS73101)
Nominal
5.5
1.210
V
V
V
VFB
TJ = 25°C
TJ = 25°C
1.198
VFB
1.20
5.5 – VDO
+0.5
–0.5
VOUT
Accuracy(1)
%
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10 mA ≤ IOUT ≤ 150mA
VIN, IOUT, and T
–1.0
±0.5
+1.0
∆VOUT%/∆VIN
Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 150mA
0.01
0.002
%/V
∆VOUT%/∆IOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 150mA
0.0005
Dropout voltage(2)
VDO
IOUT = 150mA
30
100
500
mV
(VIN = VOUT (nom) – 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
360
200
0.1
Ω
150
mA
mA
µA
ISC
Short-circuit current
IREV
Reverse leakage current(3) (-IIN
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
10
550
750
IOUT = 10mA (IQ)
IOUT = 150mA
400
550
IGND
Ground pin current
µA
V
EN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
ISHDN
IFB
Shutdown current (IGND
)
0.02
1
µA
µA
–40°C ≤ TJ ≤ +100°C
FB pin current (TPS73101)
0.1
58
37
0.3
f = 100Hz, IOUT = 150 mA
f = 10kHz, IOUT = 150 mA
COUT = 10µF, No CNR
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz - 100kHz
VN
µVRMS
µs
COUT = 10µF, CNR = 0.01µF
VOUT = 3V, RL = 30Ω
COUT = 1µF, CNR = 0.01µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5V
0.02
160
140
µA
Shutdown
Reset
Temp increasing
Temp decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
125
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) VDO is not measured for the TPS73115 (VO(nom) = 1.5V) since minimum VIN = 1.7V.
(3) Fixed-voltage versions only; refer to the Applications section for more information.
3
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SBVS034H–SEPTEMBER 2003–REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
Charge Pump
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
Short
Open
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
OUT
FB
Current
Limit
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
R
R
19kΩ for best
1
2
GND
Ω
80k
Ω
8k
accuracy.
R1
R2
Figure 2. Adjustable Voltage Version
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PIN ASSIGNMENTS
DBV PACKAGE
SOT23
(TOP VIEW)
5
4
IN
GND
EN
1
2
3
OUT
NR/FB
TERMINAL FUNCTIONS
TERMINAL
SOT23
DESCRIPTION
NAME
(DBV)
PIN NO.
IN
1
2
3
Input supply
Ground
GND
EN
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
NR
4
4
5
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
FB
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
OUT
Output of the regulator. There are no output capacitor requirements for stability.
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TYPICAL CHARACTERISTICS
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
_
+25
C
_
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40
C
−
−
−
0
15
30 45
60
75
90 105 120 135 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
−
VIN VOUT (V)
IOUT (mA)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
50
40
30
20
10
0
50
40
30
20
10
0
TPS73125DBV
IOUT = 150mA
TPS73125DBV
_
+125
C
_
+25
C
−
_
40 C
−
−
25
0
30
60
IOUT (mA)
90
120
150
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
IOUT = 150mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
30
60
IOUT (mA)
90
120
150
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 9.
Figure 10.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
400
350
300
250
200
150
100
50
1
VENABLE = 0.5V
VIN = VO + 0.5V
ICL
ISC
0.1
TPS73133
0.5
0
0.01
−
−
25
0
1.0
1.5
2.0
2.5
3.0
3.5
50
0
25
50
75
100
125
VOUT (V)
_
Temperature ( C)
Figure 11.
CURRENT LIMIT vs VIN
Figure 12.
CURRENT LIMIT vs TEMPERATURE
500
450
400
350
300
250
200
150
500
450
400
350
300
250
200
150
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
VIN (V)
_
Temperature ( C)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs FREQUENCY
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
IO = 1mA
IO = 100mA
IO = 1mA
CO = Any
CO = 1mF
IO = 1mA
CO = 10mF Tantalum
IO = 100mA
CO = 10mF
CO = 10mF Ceramic
No RSERIES
NrCAP = 0.01mF
IO = 100mA
CO = 1mF
IO = 100mA
CO = 10mF Ceramic
RSERIES = 0.3W
IO = 100mA
CO = Any
NrCAP = 0.01mF
IO = Any
VOUT = 1.25V
VIN = VOUT = 1.25V
100
CO = 0mF
1k
100k
10
10k
1M
10M
1k
100k
10
100
10k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
CNR = 0µF
PSRR (RIPPLE REJECTION) vs VIN - VOUT
40
1
35
30
25
20
15
10
5
µ
COUT = 1
F
µ
COUT = 0
F
0.1
µ
COUT = 10
F
Frequency = 100kHz
µ
COUT = 10
F
IOUT = 150mA
VOUT = 2.5V
0
0.01
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
−
VIN VOUT (V)
Frequency (Hz)
Figure 17.
Figure 18.
NOISE SPECTRAL DENSITY
CNR = 0.01µF
RMS NOISE VOLTAGE vs COUT
1
60
50
40
30
20
10
0
VOUT = 5.0V
µ
COUT = 1 F
0.1
VOUT = 3.3V
VOUT = 1.5V
µ
COUT = 0
F
µ
COUT = 10 F
µ
CNR = 0.01 F
IOUT = 150mA
10 100
10Hz < Frequency < 100kHz
0.01
1k
10k
100k
0.1
1
10
µ
COUT ( F)
Frequency (Hz)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73133
LOAD TRANSIENT RESPONSE
RMS NOISE VOLTAGE vs CNR
140
120
100
80
µ
COUT = 0 F
VIN = 3.8V
VOUT = 5.0V
40mV/tick
40mV/tick
40mV/tick
25mA/tick
VOUT
VOUT
VOUT
IOUT
µ
COUT = 1 F
VOUT = 3.3V
VOUT = 1.5V
µ
COUT = 10 F
60
40
150mA
20
µ
COUT = 0
F
10mA
10Hz < Frequency < 100kHz
0
µ
10 s/div
1p 10p 100p
1n
10n
CNR (F)
Figure 21.
Figure 22.
TPS73133
TPS73133
LINE TRANSIENT RESPONSE
TURN-ON RESPONSE
RL = 1kΩ
IOUT = 150mA
VOUT
µ
COUT = 0
F
µ
COUT = 0 F
Ω
RL = 20
50mV/div
1V/div
1V/div
VOUT
µ
COUT = 1
F
Ω
RL = 20
COUT = 10µF
µ
COUT = 100
5.5V
F
2V
50mV/div
1V/div
VOUT
VEN
dVIN
dt
µ
= 0.5V/
s
0V
4.5V
VIN
µ
10 s/div
100µs/div
Figure 23.
Figure 24.
TPS73133
TURN-OFF RESPONSE
TPS73133
POWER UP / POWER DOWN
6
5
4
3
2
1
0
RL = 20Ω
COUT = 10
µ
F
VIN
Ω
µ
RL = 20
COUT = 1
1V/div
1V/div
F
VOUT
Ω
RL = 1k
COUT = 0µF
VOUT
2V
0V
VEN
−
−
1
2
100µs/div
50ms/div
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73101
RMS NOISE VOLTAGE vs CFB
IENABLE vs TEMPERATURE
60
55
50
45
40
35
30
25
20
10
1
0.1
VOUT = 2.5V
µ
COUT = 0 F
Ω
R1 = 39.2k
10Hz < Frequency < 100kHz
0.01
−
−
10p
100p
1n
10n
50
25
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73101
IFBvs TEMPERATURE
TPS73101
LOAD TRANSIENT, ADJUSTABLE VERSION
160
140
120
100
80
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0 F
VOUT
50mV/div
50mV/div
µ
COUT = 10
F
VOUT
60
40
150mA
20
10mA
IOUT
0
µ
25 s/div
−
−
25
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 29.
Figure 30.
TPS73101
LINE TRANSIENT, ADJUSTABLE VERSION
VOUT = 2.5V
CFB = 10nF
µ
COUT = 0
F
VOUT
100mV/div
100mV/div
µ
COUT = 10
F
VOUT
4.5V
3.5V
VIN
µ
5 s/div
Figure 31.
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APPLICATION INFORMATION
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
The TPS731xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS731xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and
an adjustable output version. All versions have
thermal and over-current protection, including
foldback current limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response,
noise rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
Figure 32 shows the basic circuit connections for the
fixed voltage models. Figure 33 gives the
connections for the adjustable output version
(TPS73101).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
The TPS731xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN – VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
VIN
VOUT
IN
OUT
TPS731xx
GND
EN
NR
Optional bypass
capacitor to reduce
output noise.
OUTPUT NOISE
Figure 32. Typical Application Circuit for
Fixed-Voltage Versions
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS731xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient
noise, or PSRR.
VIN
VOUT
IN
OUT
FB
TPS73101
R1
CFB
EN
GND
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
R2
(1)
Optional capacitor
reduces output noise
and improves
(R1 + R2)
Since the value of VREF is 1.2V, this relationship
reduces to:
VOUT
=
x 1.204
R2
transient response.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
Figure 33. Typical Application Circuit for
Adjustable-Voltage Version
(2)
for the case of no CNR
.
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 33. Sample
resistor values for common output voltages are
shown in Figure 2.
For best accuracy, make the parallel combination of
R1 and R2 approximately euqal to 19kΩ. This 19kΩ,
11
Submit Documentation Feedback
TPS731xx
www.ti.com
SBVS034H–SEPTEMBER 2003–REVISED OCTOBER 2006
DROPOUT VOLTAGE
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
The TPS731xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
(3)
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73101 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB
pin will reduce output noise and improve load
transient performance.
For large step changes in load current, the
TPS731xx requires a larger voltage drop across it to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
insure normal transient response.
The TPS731xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
the gate of the NMOS pass element above VOUT
.
The charge pump generates ~250µV of switching
noise at ~4MHz; however, charge-pump noise
contribution is negligible at the output of the regulator
for most values of IOUT and COUT
.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
the TPS731xx can take
a couple of hundred
microseconds to return to the specified regulation
accuracy.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the PCB be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1µF) from the output pin to ground will reduce
undershoot magnitude but increase duration. In the
INTERNAL CURRENT LIMIT
The TPS731xx internal current limit helps protect the
regulator during fault conditions. Foldback current
helps to protect the regulator from damage during
output short-circuit conditions by reducing current
limit when VOUT drops below 0.5V. See Figure 11 in
the Typical Characteristics section for a graph of IOUT
adjustable version, the addition of a capacitor, CFB
from the output to the adjust pin will also improve the
transient response.
,
The TPS731xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
the load current quickly drops to zero when a
capacitor is connected to the output. The duration of
overshoot can be reduced by adding a load resistor.
The overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
vs VOUT
.
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to VIN. When a pull-up resistor is used,
and operation down to 1.8V is required, use pull-up
resistor values below 50 kΩ.
(Fixed voltage version)
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
12
Submit Documentation Feedback
TPS731xx
www.ti.com
SBVS034H–SEPTEMBER 2003–REVISED OCTOBER 2006
(Adjustable voltage version)
+35°C above the maximum expected ambient
condition of your application. This produces
a
VOUT
dVńdt +
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
(5)
REVERSE CURRENT
The internal protection circuitry of the TPS731xx has
been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS731xx into
thermal shutdown will degrade device reliability.
The NMOS pass element of the TPS731xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass
element, the enable pin must be driven low before
the input voltage is removed. If this is not done, the
pass element may be left on due to stored charge on
the gate.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers will
also improve the heat-sink effectiveness.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current
flowing out of the IN pin due to voltage applied on
the OUT pin. There will be additional current flowing
into the OUT pin due to the 80kΩ internal resistor
divider to ground (see Figure 1 and Figure 2).
For the TPS73101, reverse current may flow when
VFB is more than 1.0V above VIN.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
PD + (VIN * VOUT) IOUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure
the required output voltage.
Package Mounting
Solder pad footprint recommendations for the
TPS731xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
13
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2006
PACKAGING INFORMATION
Orderable Device
TPS73101DBVR
TPS73101DBVRG4
TPS73101DBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73101DBVTG4
TPS731125DBVR
TPS731125DBVRG4
TPS731125DBVT
TPS731125DBVTG4
TPS73115DBVR
TPS73115DBVRG4
TPS73115DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
3000 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73115DBVTG4
TPS73118DBVR
TPS73118DBVRG4
TPS73118DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73118DBVTG4
TPS73125DBVR
TPS73125DBVRG4
TPS73125DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73125DBVTG4
TPS73130DBVR
TPS73130DBVRG4
TPS73130DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73130DBVTG4
TPS73131DBVR
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2006
Orderable Device
TPS73131DBVRG4
TPS73131DBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73131DBVTG4
TPS73132DBVR
TPS73132DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73132DBVTG4
TPS73133DBVR
TPS73133DBVRG4
TPS73133DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73133DBVTG4
TPS73150DBVR
TPS73150DBVRG4
TPS73150DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73150DBVTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2006
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
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Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dsp.ti.com
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www.ti.com/broadband
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www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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power.ti.com
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www.ti.com/opticalnetwork
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Copyright 2006, Texas Instruments Incorporated
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