TPS73218DCQR [TI]
Cap-Free, NMOS, 250mA Low Dropout Regulator with Reverse Current Protection; 无电容， NMOS ， 250毫安低压差稳压器具有反向电流保护
| 型号： | TPS73218DCQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Cap-Free, NMOS, 250mA Low Dropout Regulator with Reverse Current Protection |
| 文件： | 总18页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
Cap-Free, NMOS, 250mA Low Dropout Regulator
with Reverse Current Protection
FEATURES
DESCRIPTION
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
The TPS732xx family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This top-
ology is stable using output capacitors with low ESR,
and even allows operation without a capacitor. It also
provides high reverse blockage (low reverse current)
and ground pin current that is nearly constant over all
values of output current.
•
•
•
Input Voltage Range: 1.7V to 5.5V
Ultralow Dropout Voltage: 40mV Typ at 250mA
Excellent Load Transient Response—with or
without Optional Output Capacitor
•
New NMOS Topology Provides Low Reverse
Leakage Current
The TPS732xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µVRMS with 0.1µF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
•
•
•
Low Noise: 30µVRMS Typ (10kHz to 100kHz)
0.5% Initial Accuracy
1% Overall Accuracy (Line, Load, and
Temperature)
•
•
Less Than 1µA Max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
DCQ PACKAGE
SOT223
•
Available in Multiple Output Voltage Versions
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
– Fixed Outputs of 1.2V, 1.5V, 1.6V, 1.8V, 2.5V,
3.0V, 3.3V, and 5.0V
TAB IS GND
– Adjustable Outputs From 1.20V to 5.5V
– Custom Outputs Available
5
4
IN
GND
EN
1
2
3
OUT
1
2
3
4
5
NR/FB
APPLICATIONS
IN
GND
EN
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
OUT
NR/FB
Optional
Optional
VIN
VOUT
IN
OUT
TPS732xx
EN
GND
NR
Optional
Typical Application Circuit for Fixed-Voltage Versions
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-LEAD
(DESIGNATOR)(2)
PACKAGE
MARKING
ORDERING
NUMBER
(1)
PRODUCT
VOUT
TRANSPORT MEDIA,
QUANTITY
TPS73201DBVT
TPS73201DBVR
TPS73201DCQT
TPS73201DCQR
TPS73215DBVT
TPS73215DBVR
TPS73215DCQT
TPS73215DCQR
TPS73216DBVT
TPS73216DBVR
TPS73218DBVT
TPS73218DBVR
TPS73218DCQT
TPS73218DCQR
TPS73225DBVT
TPS73225DBVR
TPS73225DCQT
TPS73225DCQR
TPS73230DBVT
TPS73230DBVR
TPS73230DCQT
TPS73230DCQR
TPS73233DBVT
TPS73233DBVR
TPS73233DCQT
TPS73233DCQR
TPS73250DBVT
TPS73250DBVR
TPS73250DCQT
TPS73250DCQR
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT223-5 (DCQ)
SOT23-5 (DBV)
SOT223-5 (DCQ)
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PJEQ
PS73201
T38
Adjustable
or 1.2V(3)
TPS73201
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
TPS73215
TPS73216
TPS73218
1.5V
1.6V
1.8V
PS73215
T50
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
T37
PS73218
T36
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
TPS73225
TPS73230
TPS73233
TPS73250
2.5V
3.0V
3.3V
5.0V
PS73225
T39
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
PS73230
T40
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
PS73233
T41
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Tube, 80
PS73250
Tape and Reel, 2500
(1) Custom output voltages from 1.3V to 4V in 100mV increments are available on a quick-turn basis for prototyping. Production quantities
are available; minimum order quantities apply. Contact factory for details and availability.
(2) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet.
(3) For fixed 1.2V operation, tie FB to OUT.
2
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
TPS732xx
-0.3 to 6.0
UNIT
VIN range
V
V
V
VEN range
-0.3 to 6.0
VOUT range
-0.3 to 5.5
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
Internally limited
Indefinite
See Dissipation Ratings Table
-55 to +150
-65 to +150
2
°C
°C
kV
V
ESD rating, CDM
500
(1) Stresses beyond those listedunder absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, andfunctional operation of the device at these or any other conditions beyondthose indicated under the Electrical Characteristics is
not implied. Exposureto absolute maximum rated conditions for extended periods may affect devicereliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RΘJC
RΘJA
POWER RATING POWER RATING POWER RATING
Low-K(2)
DBV
DBV
DCQ
64°C/W
64°C/W
15°C/W
255°C/W
180°C/W
53°C/W
3.9mW/°C
5.6mW/°C
18.9mW/°C
390mW
560mW
1.89W
215mW
310mW
1.04W
155mW
225mW
0.76W
(3)
High-K
Low-K(2)
(1) SeePower Dissipation in theApplications section formore information related to thermal design.
(2) The JEDEC Low-K (1s) boarddesign used to derive this data was a 3 inch x 3 inch, two-layer board with2-ounce copper traces on top of
the board.
(3) The JEDEC High-K (2s2p)board design used to derive this data was a 3 inch x 3 inch, multilayer boardwith 1-ounce internal power and
ground planes and 2-ounce copper traces on thetop and bottom of the board.
3
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
VIN
Input voltage range(1)
Internal reference (TPS73201)
Output voltage range (TPS73201)(2)
Nominal
5.5
1.210
V
V
V
VFB
TJ = 25°C
TJ = 25°C
1.198
VFB
1.20
5.5-VDO
+0.5
-0.5
VOUT
Accuracy(1)
%
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10 mA ≤ IOUT≤ 250mA
VIN, IOUT, and T
-1.0
±0.5
+1.0
∆VOUT%/∆VIN
Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 250mA
0.01
0.002
%/V
∆VOUT%/∆IOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 250mA
0.0005
Dropout voltage(3)
VDO
IOUT = 250mA
40
150
600
mV
(VIN = VOUT (nom) - 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
425
Ω
250
mA
mA
µA
ISC
Short-circuit current
300
IREV
Reverse leakage current(4) (-IIN
)
VEN ≤ 0.5V, 0V≤ VIN ≤ VOUT
0.1
10
550
950
1
IOUT = 10mA (IQ)
IOUT = 250mA
400
IGND
Ground pin current
µA
650
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
0.02
µA
µA
FB pin current (TPS73201)
.1
.3
f = 100Hz, IOUT = 250 mA
f = 10kHz, IOUT = 250 mA
COUT = 10µF, No CNR
58
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz - 100kHz
VN
µVRMS
µs
COUT= 10µF, CNR = 0.01µF
VOUT = 3V, RL = 30Ω
COUT = 1 µF, CNR= 0.01 µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5V
0.02
160
140
µA
Shutdown
Reset
Temp increasing
Temp decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
-40
125
(1) Minimum VIN = VOUT +VDO or 1.7V, whichever isgreater.
(2) TPS73201 is tested atVOUT = 2.5V.
(3) VDO is not measured for the TPS73214, TPS73215 orTPS73216 since minimum VIN =1.7V.
(4) Fixed-voltage versions only;refer to Applicationssection for more information.
4
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
FUNCTIONAL BLOCK DIAGRAMS
IN
Charge
Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
OUT
R
1
R
2
Charge
Pump
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
Short
Open
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
OUT
Current
Limit
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
R
R
19kΩ for best
1
2
GND
Ω
80k
Ω
8k
R1
R2
accuracy.
FB
Figure 2. Adjustable Voltage Version
5
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
PIN ASSIGNMENTS
DBV PACKAGE
SOT23
DCQ PACKAGE
SOT223
(TOP VIEW)
(TOP VIEW)
TAB IS GND
5
4
IN
GND
EN
1
2
3
OUT
NR/FB
1
2
3
4
5
IN
GND
EN
OUT
NR/FB
TERMINAL FUNCTIONS
TERMINAL
SOT23
(DBV)
SOT223
(DCQ)
DESCRIPTION
NAME
PIN NO.
PIN NO.
IN
1
2
3
1
3
5
Unregulated input supply
Ground
GND
EN
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. Refer to the Shutdown section under Applications Information for more details.
EN can be connected to IN if not used.
NR
4
4
5
4
4
2
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap. This allows output noise to be reduced to very low levels.
FB
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to
set the output voltage of the device.
OUT
Output of the Regulator. There are no output capacitor requirements for stability.
6
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40
_
C
+25 C
_
+25
C
_
_
+125
C
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40
C
−
−
−
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
OUT (mA)
200
250
−
I
VIN VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vsOUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
50
20
0
TPS73225DBV
TPS73225DBV
_
+125
C
_
+25
C
−
_
40 C
−
−
25
0
50
100
150
200
250
50
0
25
50
75
100
125
_
IOUT (mA)
Temperature ( C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
7
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
50
100
150
OUT (mA)
200
250
50
0
25
50
75
100
125
_
I
Temperature ( C)
Figure 9.
Figure 10.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
500
450
400
350
300
250
200
150
100
50
1
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
ISC
0.1
TPS73233
0.5
0
0.01
−
−
25
0
1.0
1.5
2.0
2.5
3.0
3.5
50
0
25
50
75
100
125
_
VOUT (V)
Temperature ( C)
Figure 11.
CURRENT LIMIT vs VIN
Figure 12.
CURRENT LIMIT vs TEMPERATURE
600
550
500
450
400
350
300
250
600
550
500
450
400
350
300
250
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 13.
Figure 14.
8
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN - VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1
F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
CO = 1 F
IOUT = 1mA
COUT = Any
IOUT = 100mA
COUT = 10
Frequency = 100kHz
µ
F
C
C
= 10µF
= 0.01µF
IOUT = Any
COUT = 0
OUT
µ
F
NR
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
−
VIN VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
CNR = 0µF
NOISE SPECTRAL DENSITY
CNR = 0.01µF
1
1
µ
COUT = 1
F
µ
COUT = 1
F
µ
COUT = 0
F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0
F
µ
COUT = 10
F
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01
F
µ
COUT = 0
F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p 10p 100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 19.
Figure 20.
9
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73233
LOAD TRANSIENT RESPONSE
TPS73233
LINE TRANSIENT RESPONSE
µ
µ
µ
V
IN = 3.8V
COUT = 0
F
F
F
IOUT = 250mA
50mV/tick
50mV/tick
VOUT
VOUT
VOUT
µ
COUT = 0
F
50mV/div
VOUT
COUT = 1
µ
COUT = 100
F
COUT = 10
50mV/div
1V/div
VOUT
50mV/tick
50mA/tick
dVIN
dt
5.5V
µ
= 0.5V/
s
250mA
4.5V
VIN
10mA
IOUT
µ
µ
10 s/div
10 s/div
Figure 21.
Figure 22.
TPS73233
TURN-ON RESPONSE
TPS73233
TURN-OFF RESPONSE
Ω
RL = 1k
Ω
RL = 20
VOUT
µ
COUT = 0
F
COUT = 10µF
RL = 20Ω
COUT = 1µF
RL = 20Ω
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
Ω
RL = 1k
RL = 20Ω
COUT = 10
µ
COUT = 0
F
µ
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
µ
100 s/div
Figure 23.
Figure 24.
TPS73233
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
0.01
−
−
1
2
50ms/div
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
10
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73101
RMS NOISE VOLTAGE vs CADJ
TPS73201
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0
F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73201
TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0
F
µ
COUT = 0
F
VOUT
VOUT
100mV/div
100mV/div
100mV/div
100mV/div
µ
COUT = 10 F
µ
COUT = 10
F
VOUT
VOUT
4.5V
250mA
3.5V
VIN
10mA
IOUT
µ
5
s/div
µ
10 s/div
Figure 29.
Figure 30.
11
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
APPLICATION INFORMATION
The TPS732xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse cur-
rent blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS732xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback cur-
rent limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for stab-
ility, it is good analog design practice to connect a
0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capaci-
tor may be necessary if large, fast rise-time load
transients are anticipated or the device is located
several inches from the power source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73201).
The TPS732xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN - VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
TPS732xx
GND
EN
NR
Optional bypass
OUTPUT NOISE
capacitor to reduce
output noise.
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS732xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
FB
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
TPS732xx
R1
R2
CFB
R2
(1)
EN
GND
Since the value of VREF is 1.2V, this relationship
reduces to:
Optional capacitor
reduces output noise.
mVRMS
V
(R1 + R2)
×
1.204
VOUT
=
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
R2
(2)
Figure 32. Typical Application Circuit for
Adjustable-Voltage Versions
for the case of no CNR
.
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample re-
sistor values for common output voltages are shown
in Figure 2. For best accuracy, make the parallel
combination of R1 and R2 approximately 19kΩ.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
for CNR = 10nF.
12
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
DROPOUT VOLTAGE
The TPS732xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN - VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
The TPS73201 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin
will reduce output noise and improve load transient
performance.
The TPS732xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250µV of switching noise at
~2MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
For large step changes in load current, the TPS732xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN - VOUT above this line
insure normal transient response.
values of IOUT and COUT
.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available head-
room (VIN to VOUT voltage drop). Under worst-case
conditions [full-scale instantaneous load change with
(VIN - VOUT) close to dc dropout levels], the TPS732xx
can take a couple of hundred microseconds to return
to the specified regulation accuracy.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
VIN and VOUT, with each ground plane connected only
at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect
directly to the GND pin of the device.
TRANSIENT RESPONSE
INTERNAL CURRENT LIMIT
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower configur-
ation allows operation without an output capacitor for
many applications. As with any regulator, the addition
of a capacitor (nominal value 1µF) from the output pin
to ground will reduce undershoot magnitude but
increase duration. In the adjustable version, the
addition of a capacitor, CFB, from the output to the
adjust pin will also improve the transient response.
The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5V. See Figure 11 in the Typical
Characteristics section for a graph of IOUT vs VOUT
.
SHUTDOWN
The TPS732xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as alter-
nate power supplies, to the output. This also results
in an output overshoot of several percent if the load
current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load resist-
ance. The rate of decay is given by:
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown capa-
bility is not required, the Enable pin can be connected
to VIN. When a pull-up resistor is used, and operation
down to 1.8V is required, use pull-up resistor values
below 50 kΩ.
(Fixed voltage version)
VOUT
dVńdt +
COUT 80kW
(4)
13
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
www.ti.com
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
(Adjustable voltage version)
reliability, thermal protection should trigger at least
35°C above the maximum expected ambient con-
dition of your application. This produces a worst-case
junction temperature of 125°C at the highest ex-
pected ambient temperature and worst-case load.
VOUT
dVńdt +
(
)
COUT 80kW ø R1 ) R2
(5)
REVERSE CURRENT
The internal protection circuitry of the TPS732xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS732xx into thermal
shutdown will degrade device reliability.
The NMOS pass element of the TPS732xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the enable pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
POWER DISSIPATION
The ability to remove heat from the die is different for
each package type, presenting different consider-
ations in the PCB layout. The PCB area around the
device that is free of other components moves the
heat from the device to the ambient air. Performance
data for JEDEC low- and high-K boards are shown in
the Power Dissipation Ratings table. Using heavier
copper will increase the effectiveness in removing
heat from the device. The addition of plated
through-holes to heat-dissipating layers will also im-
prove the heat-sink effectiveness.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80kΩ internal resistor divider to
ground (see Figure 1 and Figure 2).
For the TPS73201, reverse current may flow when
VFB is more than 1.0V above VIN.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (VIN to VOUT):
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately 160°C,
allowing the device to cool. When the junction tem-
perature cools to approximately 140°C, the output
circuitry is again enabled. Depending on power dissi-
pation, thermal resistance, and ambient temperature,
the thermal protection circuit may cycle on and off.
This limits the dissipation of the regulator, protecting
it from damage due to overheating.
PD
(VIN VOUT
)
IOUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
Package Mounting
Solder pad footprint recommendations for the
TPS732xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount De-
vices (AB-132), available from the Texas Instruments
web site at www.ti.com.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inad-
equate heatsink. For reliable operation, junction tem-
perature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
(including heatsink), increase the ambient tempera-
ture until the thermal protection is triggered; use
worst-case loads and signal conditions. For good
14
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
TPS73201DBVR
TPS73201DBVT
TPS73201DCQ
TPS73201DCQR
TPS73215DBVR
TPS73215DBVT
TPS73215DCQ
TPS73215DCQR
TPS73216DBVR
TPS73216DBVT
TPS73218DBVR
TPS73218DBVT
TPS73218DCQ
TPS73218DCQR
TPS73225DBVR
TPS73225DBVT
TPS73225DCQ
TPS73225DCQR
TPS73230DBVR
TPS73230DBVT
TPS73230DCQ
TPS73230DCQR
TPS73233DBVR
TPS73233DBVT
TPS73233DCQ
TPS73233DCQR
TPS73250DBVR
TPS73250DBVT
TPS73250DCQ
TPS73250DCQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
DBV
DBV
DCQ
DCQ
DBV
DBV
DCQ
DCQ
DBV
DBV
DBV
DBV
DCQ
DCQ
DBV
DBV
DCQ
DCQ
DBV
DBV
DCQ
DCQ
DBV
DBV
DCQ
DCQ
DBV
DBV
DCQ
DCQ
5
5
6
6
5
5
6
6
5
5
5
5
6
6
5
5
6
6
5
5
6
6
5
5
6
6
5
5
6
6
3000
250
78
2500
3000
250
78
2500
3000
250
3000
250
78
2500
3000
250
78
2500
3000
250
78
2500
3000
250
78
2500
3000
250
78
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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