TPS73718 [TI]
1A Low-Dropout Regulator with Reverse Current Protection; 1A低压降稳压器具有反向电流保护
| 型号： | TPS73718 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A Low-Dropout Regulator with Reverse Current Protection |
| 文件： | 总18页 (文件大小：698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS737xx
www.ti.com
SBVS067C–JANUARY 2006–REVISED AUGUST 2006
1A Low-Dropout Regulator
with Reverse Current Protection
FEATURES
DESCRIPTION
•
Stable with 1.0µF or Larger Ceramic Output
Capacitor
The TPS737xx family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1.0µF ceramic output capacitor. The NMOS
topology also allows very low dropout for the die size
used.
•
•
•
Input Voltage Range: 2.2V to 5.5V
Ultra-Low Dropout Voltage: 130mV typ at 1A
Excellent Load Transient Response—Even
With Only 1.0µF Output Capacitor
•
NMOS Topology Delivers Low Reverse
Leakage Current
The TPS737xx family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under
1µA and ideal for portable applications. These
devices are protected by thermal shutdown and
foldback current limit.
•
•
0.5% Initial Accuracy
3% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 20nA typical IQ in Shutdown Mode
Thermal Shutdown and Current Limit for
Fault Protection
•
Available in Multiple Output Voltage Versions
– Adjustable Output: 1.20V to 5.5V
– Custom Outputs Available Using Factory
Package-Level Programming
APPLICATIONS
•
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
•
•
Post-Regulation for Switching Supplies
Portable/Battery-Powered Equipment
DCQ PACKAGE
SOT223
(TOP VIEW)
Optional
VIN
TAB IS GND
VOUT
IN
OUT
FB
TPS737xx
1.0mF
1
2
3
4
5
EN
GND
IN
GND
EN
Typical Application Circuit
OUT FB/NC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS737xx
www.ti.com
SBVS067C–JANUARY 2006–REVISED AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS737xxyyyz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Most output voltages from 1.5V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory package-level
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS737xx
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +5.5
Internally limited
Indefinite
UNIT
VIN range
V
V
V
VEN range
VOUT range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
°C
°C
kV
V
–65 to +150
2
ESD rating, CDM
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = +25°C POWER RATING POWER RATING POWER RATING
T
A ≤ +25°C
TA = +70°C
TA = +85°C
BOARD
PACKAGE
RθJC
RθJA
Low-K(2)
DCQ
15°C/W
53°C/W
18.9mW/°C 1.89W 1.04W 0.76W
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3-inch × 3-inch, 2-layer board with 2-ounce copper traces on top of
the board.
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 1.0V(1), IOUT = 10mA, VEN = 2.2V, and
COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
Input voltage range(1)(2)
TEST CONDITIONS
MIN
2.2
TYP
MAX
5.5
UNIT
V
VIN
VFB
Internal reference (TPS73701)
TJ = +25°C
1.198
1.20
1.210
V
Output voltage range
(TPS73701)
VFB
–1.0
–3.0
5.5 – VDO
+1.0
V
VOUT
Nominal
TJ = +25°C
Accuracy(1)(3)
%
over VIN, IOUT
and T
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10mA ≤ IOUT ≤ 1A
±0.5
+3.0
∆VOUT%/∆VIN Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 1A
0.01
0.002
0.0005
%/V
∆VOUT%/∆IOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 1A
Dropout voltage(4)
VDO
IOUT = 1A
130
500
2.2
mV
(VIN = VOUT(nom) – 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
2.2V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
1.6
450
0.1
400
800
20
Ω
A
1.05
ISC
Short-circuit current
mA
µA
IREV
Reverse leakage current(5) (–IIN
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
IOUT = 10mA (IQ)
IOUT = 1A
IGND
Ground pin current
µA
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
nA
FB pin current (TPS73701)
0.1
0.6
µA
f = 100Hz, IOUT = 1A,
VIN = VOUT + 1V
58
37
Power-supply rejection ratio
(ripple rejection)
PSRR
VN
dB
f = 10kHz, IOUT = 1A,
VIN = VOUT + 1V
Output noise voltage
BW = 10Hz – 100KHz
COUT = 10µF
27 × VOUT
µVRMS
tSTR
Startup time
VOUT = 3V, RL = 30Ω, COUT = 1µF
600
µs
V
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
Enable low (shutdown)
Enable pin current (enabled)
1.7
0
VIN
0.5
V
VEN = 5.5V
20
nA
Shutdown, temperature increasing
Reset, temperature decreasing
+160
+140
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 2.2V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in an over-voltage condition on the output. To avoid this
situation, disable the device before powering down VIN
.
(3) Tolerance of external resistors not included in this specification.
(4) VDO is not measured for fixed output versions with VOUT(nom) < 2.3V since minimum VIN = 2.2V.
(5) Refer to the Applications section for more information.
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
FUNCTIONAL BLOCK DIAGRAMS
IN
Standard 1% Resistor Values for
Common Output Voltages
4MHz
Charge Pump
VO
R1
R2
EN
Thermal
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Protection
23.2kW
28.0kW
39.2kW
44.2kW
46.4kW
52.3kW
95.3kW
56.2kW
36.5kW
33.2kW
30.9kW
30.1kW
Ref
Servo
27kW
Bandgap
Error
Amp
OUT
FB
Current
Limit
GND
NOTE: VOUT = (R1 + R2)/R2 x 1.204;
R1 || R2 = 19kW for best
accuracy.
80kW
8kW
R1
R2
Figure 1. Adjustable Voltage Version
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
Current
Limit
OUT
8kW
GND
R1
R1 + R2 = 80kW
R2
Figure 2. Fixed-Voltage Version
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
PIN ASSIGNMENTS
DCQ PACKAGE
SOT223
(TOP VIEW)
TAB IS GND
1
2
3
4
5
IN
GND
EN
OUT FB/NC
Table 1. Terminal Functions
SOT223
(DCQ)
NAME
PIN NO.
DESCRIPTION
IN
1
Unregulated input supply
Ground
GND
3, TAB
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
EN
5
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
FB
4
OUT
NC
2
Regulator output. A 1.0µF or larger capacitor of any type is required for stability.
—
Not connected
5
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.3
0.2
+25°C
+125°C
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-40°C
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
V
IN - VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs TEMPERATURE
DROPOUT VOLTAGE vs OUTPUT CURRENT
180
160
140
120
100
80
200
180
160
140
120
100
80
VOUT = 2.5V
+125°C
+25°C
60
60
-40°C
40
40
20
20
0
0
-50
-25
0
25
50
75
100
125
150
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
Temperature (°C)
Figure 5.
OUTPUT VOLTAGE HISTOGRAM
IOUT = 10mA
Figure 6.
DROPOUT VOLTAGE DRIFT HISTOGRAM
30
25
20
15
10
5
18
16
14
12
10
8
IOUT = 10mA
6
4
2
0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 7.
Figure 8.
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
IOUT = 1A
VIN = 5.0V
VIN = 5.0V
VIN = 3.3V
VIN = 3.3V
VIN = 2.2V
VIN = 2.2V
0
0
-50
-25
0
25
50
75
100
125
0
200
400
600
800
1000
Temperature (°C)
IOUT (mA)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VIN
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1
VENABLE = 0.5V
VIN = VOUT + 0.5V
0.1
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
125
VIN (V)
Temperature (°C)
Figure 11.
Figure 12.
PSRR (RIPPLE REJECTION) vs FREQUENCY
CURRENT LIMIT vs TEMPERATURE
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
90
80
70
60
50
40
30
20
10
0
VOUT = 1.2V
IOUT = 100mA
COUT = Any
IOUT = 1mA
COUT = 1mF
IOUT = 1mA
COUT = 10mF
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
IOUT = 100mA
COUT = 10mF
-50
-25
0
25
50
75
100
125
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs
VIN – VOUT
NOISE SPECTRAL DENSITY
1
40
35
30
25
20
15
10
5
COUT = 1mF
0.1
COUT = 10mF
Frequency = 100kHz
COUT = 10mF
IOUT = 150mA
10 100
VOUT = 2.5V
0.01
0
1k
10k
100k
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
IN - VOUT (V)
Frequency (Hz)
V
Figure 15.
Figure 16.
TPS73701
RMS NOISE VOLTAGE vs CFB
TPS73701, VOUT = 1.5V
TURN-ON RESPONSE
60
55
50
45
40
35
30
25
20
VOUT
RL = 20W
1V/div
COUT = 1mF
RL = 20W
COUT = 10mF
2V
VEN
VOUT = 2.5V
1V/div
COUT = 0mF
0V
R1 = 39.2kW
10Hz < Frequency < 100kHz
100ms/div
10p
100p
1n
10n
CFB (F)
Figure 17.
Figure 18.
TPS73701, VOUT = 1.5V
TURN-OFF RESPONSE
TPS73701, VOUT = 3.3V
POWER-UP/POWER-DOWN
6
5
4
3
2
1
0
RL = 20W
COUT = 10mF
VIN
RL = 20W
COUT = 1mF
1V/div
VOUT
VOUT
2V
1V/div
0V
VEN
-1
-2
100ms/div
50ms/div
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2µF, unless otherwise
noted.
TPS73701
IFB vs TEMPERATURE
IENABLE vs TEMPERATURE
10
1
160
140
120
100
80
60
0.1
0.01
40
20
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 21.
Figure 22.
TPS73701
TPS73701
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
VOUT = 2.5V
CFB = 10nF
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
COUT = 10mF
VOUT
VOUT
100mV/div
100mV/div
4.5V
250mA
3.5V
IOUT
VIN
10mA
10ms/div
5ms/div
Figure 23.
Figure 24.
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SBVS067C–JANUARY 2006–REVISED AUGUST 2006
APPLICATION INFORMATION
The TPS737xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features combined with an enable
input make the TPS737xx ideal for portable
applications. This regulator family offers a wide
selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection.
A
higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
Figure 25 shows the basic circuit connections for the
fixed voltage models. Figure 26 gives the
connections for the adjustable output version
(TPS73701).
The TPS737xx requires a 1.0µF output capacitor for
stability. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN – VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
VIN
VOUT
IN
OUT
TPS737xx
EN
GND
Figure 25. Typical Application Circuit for
Fixed-Voltage Versions
OUTPUT NOISE
A precision bandgap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS737xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at its output. The regulator control loop
gains up the reference noise with the same gain as
the reference voltage, so that the noise voltage of
the regulator is approximately given by:
VIN
VOUT
IN
OUT
TPS737xx
R1
R2
CFB
EN
GND
FB
(R1 + R2)
VOUT
=
´ 1.204
R1
(
)
VOUT
VREF
R1 ) R2
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Figure 26. Typical Application Circuit for
Adjustable-Voltage Versions
Since the value of VREF is 1.2V, this relationship
reduces to:
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 26. Sample
resistor values for common output voltages are
shown in Figure 2.
mVRMS
V
ǒ
Ǔ
+ 27ǒ Ǔ
( )
V
VN mVRMS
VOUT
(2)
Connecting a feedback capacitor, CFB, from the
output to the FB pin reduces output noise and
improve load transient performance. This capacitor
should be limited to 0.1µF.
For best accuracy, make the parallel combination of
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
The TPS737xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT
.
The charge pump generates ~250µV of switching
noise at ~2MHz; however, charge-pump noise
contribution is negligible at the output of the regulator
for most values of IOUT and COUT
.
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BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in voltage follower
a
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
bypass capacitor should connect directly to the GND
pin of the device.
configuration allows operation without a 1.0µF output
capacitor. As with any regulator, the addition of
additional capacitance from the output pin to ground
reduces undershoot magnitude but increases
duration. In the adjustable version, the addition of a
capacitor, CFB, from the output to the adjust pin will
also improve the transient response.
The TPS737xx does not have active pull-down when
the output is over-voltage. This architecture allows
applications that connect higher voltage sources,
such as alternate power supplies, to the output. This
architecture also results in an output overshoot of
several percent if the load current quickly drops to
zero when a capacitor is connected to the output.
The duration of overshoot can be reduced by adding
a load resistor. The overshoot decays at a rate
determined by output capacitor COUT and the
internal/external load resistance. The rate of decay is
given by:
INTERNAL CURRENT LIMIT
The TPS737xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5V.
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to VIN. When a pull-up resistor is used,
and operation down to 1.8V is required, use pull-up
resistor values below 50kΩ.
(Fixed voltage version)
VOUT
COUT 80kW ø RLOAD
dV
dT
+
(3)
(4)
(Adjustable voltage version)
VOUT
dV
dT
+
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
DROPOUT VOLTAGE
The TPS737xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the NMOS
pass element.
REVERSE CURRENT
The NMOS pass element of the TPS737xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass
element, the enable pin must be driven low before
the input voltage is removed. If this is not done, the
pass element may be left on because of stored
charge on the gate.
For large step changes in load current, the
TPS737xx requires a larger voltage drop from VIN to
VOUT to avoid degraded transient response. The
boundary of this transient dropout region is
approximately twice the dc dropout. Values of VIN
–
VOUT above this line ensure normal transient
response.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current
flowing out of the IN pin because of voltage applied
on the OUT pin. There will be additional current
flowing into the OUT pin as a result of the 80kΩ
internal resistor divider to ground (see Figure 1 and
Figure 2).
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
For the TPS73701, reverse current may flow when
VFB is more than 1.0V above VIN.
the TPS737xx can take
a couple of hundred
microseconds to return to the specified regulation
accuracy.
11
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TPS737xx
www.ti.com
SBVS067C–JANUARY 2006–REVISED AUGUST 2006
THERMAL PROTECTION
POWER DISSIPATION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage due to
overheating.
The ability to remove heat from the die is different for
each package type, presenting different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers will
also improve the heatsink effectiveness.
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
ǒ
Ǔ
PD + VIN * VOUT IOUT
(5)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure
the required output voltage.
condition of your application. This produces
a
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
Package Mounting
Solder pad footprint recommendations for the
TPS737xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
The internal protection circuitry of the TPS737xx has
been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS737xx into
thermal shutdown will degrade device reliability.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
TPS73701DCQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-223
DCQ
6
6
6
6
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73701DCQG4
TPS73701DCQR
TPS73701DCQRG4
SOT-223
SOT-223
SOT-223
DCQ
DCQ
DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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