TPS7A4701QRGWTQ1 [TI]

具有使能功能的汽车类、1A、36V、低噪声、高 PSRR、低压降稳压器 | RGW | 20 | -40 to 125;


型号：	TPS7A4701QRGWTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的汽车类、1A、36V、低噪声、高 PSRR、低压降稳压器 \| RGW \| 20 \| -40 to 125 稳压器
文件：	总31页 (文件大小：2160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

TPS7A47-Q1 35V、1A、4.2µV_RMS射频 LDO 电压稳压器

1 特性

2 应用

•

符合汽车应用要求

符合 AEC-Q100 标准，其中包括以下内容：

•

电压控制振荡器 (VCO)

Rx、Tx 和 PA 电路

汽车信息娱乐系统与组合仪表

–

器件温度 1 级：–40°C 至 125°C 的环境工作温

度范围

用于运算放大器、

DAC、ADC 和其他高精度模拟电路的电源轨

–

器件 HBM ESD 分类等级 2

器件 CDM ESD 分类等级 C4A

3 说明

•

输入电压范围：3V 至 35V

TPS7A47-Q1 器件是一款正电压 (35V)、超低噪声

(4.2µV_RMS) 低压降线性稳压器 (LDO)，具有 1A 负载电

流灌入能力。

工作结温范围：

–40°C 至 +145°C

•

输出电压噪声：

4.2µV_RMS(10Hz–100kHz)

TPS7A47-Q1 输出电压可通过用户可编程印刷电路板

(PCB) 布局（高达 20.5V）进行配置，也可以使用外部

反馈电阻器进行调节。

电源抑制比：

–

82dB (100Hz)

≥ 55dB (10Hz–10MHz)

TPS7A47-Q1 采用双极技术进行设计，主要用于高精

度、高精密仪表应用，在这些应用中干净的电压轨对

于最大程度地提高系统性能而言至关重要。此特性使得

该器件非常适用于为运算放大器、模数转换器

(ADC)、数模转换器 (DAC) 和其他高性能模拟电路供

电。

•

两个输出电压模式：

–

ANY-OUT™版本（经由 PCB 布局进行配置的

用户可编程输出）：

–

输出电压范围：1.4V 至 20.5V

可调节运行：

输出电压范围：1.4V 至 34V

–

•

输出电流：1A

此外，TPS7A47-Q1 还非常适用于后置直流/直流转换

器稳压。通过滤除直流/直流开关转换所固有的输出电

压纹波，可确保在灵敏仪表、音频和射频应用中实现

最高的系统性能。

热阻：θ_JA= 31.1°C/W

压差：1A 时为 307mV

与 CMOS 逻辑电平兼容的使能引脚

内置固定电流限制和

热关断

器件信息⁽¹⁾

器件型号

封装

VQFN (20)

封装尺寸（标称值）

TPS7A47-Q1

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

8 V

VIN

5 V

OUT

EN1

TPS7A47-Q1

VCC1

High-Performance DAC

VIN

EN1

3.3 V

VDD

OUT

TPS7A47-Q1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS118

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

www.ti.com.cn

特性.......................................................................... 1

Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application ................................................. 15

Power Supply Recommendations...................... 19

9.1 Power Dissipation (P_D)............................................ 19

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 12

7.5 Programming........................................................... 12

10 Layout................................................................... 20

10.1 Layout Guidelines ................................................. 20

10.2 Layout Example .................................................... 20

10.3 Thermal Protection................................................ 21

10.4 Estimating Junction Temperature ......................... 21

11 器件和文档支持 ..................................................... 22

11.1 文档支持................................................................ 22

11.2 接收文档更新通知 ................................................. 22

11.3 社区资源................................................................ 22

11.4 商标....................................................................... 22

11.5 静电放电警告......................................................... 22

11.6 Glossary................................................................ 22

12 机械、封装和可订购信息....................................... 22

4 修订历史记录

日期

修订版本

说明

2017 年 8 月

初始发行版。

TPS7A47-Q1

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ZHCSGI7 –AUGUST 2017

5 Pin Configuration and Functions

RGW Package

5-mm × 5-mm, 20-Pin VQFN

Top View

OUT

PowerPAD

SENSE/FB

6P4V2

0P1V

0P2V

6P4V1

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

NO.

When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

0P1V

When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

0P2V

0P4V

0P8V

1P6V

3P2V

6P4V1

6P4V2

When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.

Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.

Enable pin. The device is enabled when the voltage on this pin exceeds the maximum

enable voltage, V_EN(HI). If enable is not required, tie EN to IN.

GND

—

Ground

Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to

assure stability.

15, 16

A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device

as possible) to reduce circuit sensitivity to printed circuit board (PCB) layout, especially when

long input traces or high source impedances are encountered.

2, 17-19

—

This pin can be left open or tied to any voltage between GND and IN.

Noise-reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be

reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this

pin to ground to assure stability. A 1-µF capacitor is recommended to be connected from NR

to GND (as close to the device as possible) to maximize ac performance and minimize noise.

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to

ground to assure stability. A 47-µF ceramic output capacitor is highly recommended to be

connected from OUT to GND (as close to the device as possible) to maximize ac

performance.

OUT

1, 20

Control-loop error amplifier input.

This pin is the SENSE pin if the device output voltage is programmed using ANY-OUT (no

external feedback resistors). This pin must be connected to OUT. Connect this pin to the

point of load to maximize accuracy.

This pin is the FB pin if the device output voltage is set using external resistors. See the

Adjustable Operation Adjustable Operation section for more details.

SENSE/FB

PowerPAD

Connect the PowerPAD to a large-area ground plane. The PowerPAD™ is internally

connected to GND.

Pad

—

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.4

–36

MAX

0.4

UNIT

IN pin to GND pin

EN pin to GND pin

EN pin to IN pin

OUT pin to GND pin

NR pin to GND pin

SENSE/FB pin to GND pin

–0.4

0P1V pin to GND pin

Voltage⁽²⁾

0P2V pin to GND pin

0P4V pin to GND pin

0P8V pin to GND pin

1P6V pin to GND pin

3P2V pin to GND pin

6P4V1 pin to GND pin

6P4V2 pin to GND pin

Current

Peak output

Internally limited

Operating virtual junction, T_J

Storage, T_stg

–40

–65

145

150

Temperature

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the network ground terminal.

6.2 ESD Ratings

VALUE

±2500

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

TPS7A47-Q1

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ZHCSGI7 –AUGUST 2017

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

MIN

3.0

1.4

NOM

MAX

35.0

34.0

UNIT

V_I

Input voltage

V_O

Output voltage

Output capacitor

Enable pin voltage

Output current

C_OUT

V_EN

I_O

µF

V_IN

1.0

6.4 Thermal Information

TPS7A47-Q1

RGW (VQFN)

20 PINS

31.1

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

21.1

10.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

10.2

R_θJC(bot)

1.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

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6.5 Electrical Characteristics

at –40°C ≤ T_J≤ 145°C; V_I= V_O(nom)+ 1.0 V or V_I= 3.0 V (whichever is greater); V_EN= V_I; I_O= 0 mA; C_IN= 10 µF; C_OUT= 10

µF; C_NR= 10 nF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_I

Input voltage range

V_Irising

2.67

2.5

V_UVLO

Undervoltage lockout threshold

V_Ifalling

V_(REF)

Reference voltage

V_(REF)= V_(FB)

1.4

V_UVLO(HYS)

Under-voltage lockout hysteresis

177

V_OUT

1.4

Using ANY-OUT option

V_NR

Noise reduction pin voltage

Output voltage range

In adjustable mode only

C_OUT= 20 µF, using ANY-OUT option

C_OUT= 20 µF, using adjustable option

T_J= 25°C, C_OUT= 20 µF

1.4

20.5

V_O

Nominal V_Oaccuracy

Overall V_Oaccuracy

–1.0

1.0

%V_O

V_O(nom)+ 1.0 V ≤ V_I≤ 35 V,

0 mA ≤ I_O≤ 1 A, C_OUT= 20 µF

–2.5

2.5

ΔV_O(ΔVI)

ΔV_O(ΔIO)

Line regulation

Load regulation

V_O(nom)+ 1.0 V ≤ V_I≤ 35 V

0 mA ≤ I_O≤ 1 A

V_I= 95% V_O(nom), I_O= 0.5 A

V_I= 95% V_O(nom), I_O= 1 A

V_O= 90% V_O(nom)

I_O= 0 mA

0.092

0.3

%V_O

216

V_(DO)

I_(CL)

Dropout voltage

Current limit

307

450

1.0

1.26

0.58

6.1

I_(GND)

Ground pin current

I_O= 1 A

V_EN= V_I

0.78

0.81

2.55

3.04

I_(EN)

Enable pin current

µA

V_I= V_EN= 35 V

V_EN= 0.4 V

I_(SHDN)

Shutdown supply current

V_EN= 0.4 V, V_I= 35 V

V_I

V_+EN(HI)

V_+EN(LO)

I_(FB)

Enable high-level voltage

Enable low-level voltage

Feedback pin current

2.0

0.4

350

V_I= 16 V, V_O(nom)= 15 V, C_OUT= 50 µF,

I_O= 500 mA, C_NR= 1 µF, f = 1 kHz

PSRR

Power-supply rejection ratio

V_I= 3 V, V_O(nom)= 1.4 V, C_OUT= 50 µF,

C_NR= 1 µF, BW = 10 Hz to 100 kHz

4.17

4.67

V_n

Output noise voltage

µV_RMS

V_IN= 6 V, V_O(nom)= 5 V, C_OUT= 50 µF,

C_NR= 1 µF, BW = 10 Hz to 100 kHz

Shutdown, temperature increasing

Reset, temperature decreasing

170

150

T_sd

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

145

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ZHCSGI7 –AUGUST 2017

6.6 Typical Characteristics

at T_J= 25°C; V_I= V_O(nom)+ 1.0 V or V_I= 3.0 V (whichever is greater); V_EN= V_I; I_O= 0 mA; C_IN= 10 µF; C_OUT= 10 µF; C_NR

1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise

noted)

V_OUT= 1.4 V, V_NOISE= 4.17 mV_RMS

V_OUT= 5 V, V_NOISE= 4.67 mV_RMS

V_OUT= 10 V, V_NOISE= 7.25 mV_RMS

V_OUT= 15 V, V_NOISE= 12.28 mV_RMS

−40°C

0°C

+25°C

+85°C

+125°C

−1

−2

−3

−4

0.1

0.01

100

10k

100k

Frequency (Hz)

Input Voltage (V)

I_OUT= 500 mA, C_OUT= 50 µF, C_NR= 1 µF,

BW_RMSNOISE(10 Hz, 100 kHz)

Figure 1. Noise vs Output Voltage

Figure 2. Line Regulation

−40°C

0°C

UVLO Threshold Off

UVLO Threshold On

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

+25°C

+85°C

+125°C

−1

−2

−3

−4

100 200 300 400 500 600 700 800 900 1000

Output Current (mA)

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 3. Load Regulation

Figure 4. Input Voltage Threshold vs Temperature

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

800

600

400

200

−40°C

0°C

+25°C

+105°C

+125°C

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

Input Voltage (V)

I_OUT= 0 µA

Figure 5. Enable Voltage Threshold vs Temperature

Figure 6. Quiescent Current vs Input Voltage

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Typical Characteristics (continued)

at T_J= 25°C; V_I= V_O(nom)+ 1.0 V or V_I= 3.0 V (whichever is greater); V_EN= V_I; I_O= 0 mA; C_IN= 10 µF; C_OUT= 10 µF; C_NR

1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise

noted)

−40°C

0°C

1.8

1.6

1.4

1.2

+25°C

+85°C

+125°C

0.8

0.6

0.4

0.2

−40°C

0°C

+25°C

+85°C

+125°C

0.1

100

1000

Output Current (mA)

Input Voltage (V)

Figure 7. Ground Current vs Output Current

Figure 8. Enable Current vs Input Voltage

−40°C

0°C

+25°C

2.5

+105°C

+125°C

1.5

−40°C

0°C

+25°C

+85°C

+125°C

0.5

Input Voltage (V)

V_OUT= 90% V_OUT(NOM)

Figure 9. Shutdown Current vs Input Voltage

Figure 10. Current Limit vs Input Voltage

C_NR= 0.01 mF

C_NR= 0.1 mF

C_NR= 1 mF

C_NR= 0.01 mF

C_NR= 0.1 mF

C_NR= 1 mF

C_NR= 2.2 mF

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

I_OUT= 1 A, C_OUT= 50 µF, V_IN= 3 V, V_OUT= 1.4 V

I_OUT= 0.5 A, C_OUT= 50 µF, V_IN= 3 V, V_OUT= 1.4 V

Figure 11. Power-Supply Rejection Ratio vs

Frequency and C_NR

Figure 12. Power-Supply Rejection Ratio vs

Frequency and C_NR

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Typical Characteristics (continued)

at T_J= 25°C; V_I= V_O(nom)+ 1.0 V or V_I= 3.0 V (whichever is greater); V_EN= V_I; I_O= 0 mA; C_IN= 10 µF; C_OUT= 10 µF; C_NR

1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise

noted)

I_OUT= 0 mA

V_DO= 200 mV

V_DO= 300 mV

V_DO= 500 mV

V_DO= 1 V

I_OUT= 50 mA

I_OUT= 500 mA

I_OUT= 1000 mA

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_NR= 1 µF, C_OUT= 50 µF, V_IN= 3 V, V_OUT= 1.4 V

V_OUT= 3.3 V, C_NR= 1 µF, C_OUT= 50 µF, I_OUT= 50 mA

Figure 13. Power-Supply Rejection Ratio vs

Frequency and I_O

Figure 14. Power-Supply Rejection Ratio vs

Frequency and V_DO

V_DO= 200 mV

V_DO= 300 mV

V_DO= 500 mV

V_DO= 1 V

V_DO= 300 mV

V_DO= 500 mV

V_DO= 1 V

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

V_OUT= 3.3 V, C_NR= 1 µF, C_OUT= 50 µF, I_OUT= 500 mA

V_OUT= 3.3 V, C_NR= 1 µF, C_OUT= 50 µF, I_OUT= 1 A

Figure 15. Power-Supply Rejection Ratio vs

Frequency and V_DO

Figure 16. Power-Supply Rejection Ratio vs

Frequency and V_DO

V_OUT= 1.4 V

V_OUT= 3.3 V

V_OUT= 1.4 V

V_OUT= 3.3 V

V_OUT= 5 V

V_OUT= 10 V

V_OUT= 15 V

V_OUT= 10 V

V_OUT= 15 V

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_NR= 1 µF, C_OUT= 50 µF, I_OUT= 500 mA

C_NR= 1 µF, C_OUT= 50 µF, I_OUT= 1000 mA

Figure 17. Power-Supply Rejection Ratio vs

Frequency and V_OUT

Figure 18. Power-Supply Rejection Ratio vs

Frequency and V_OUT

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Typical Characteristics (continued)

at T_J= 25°C; V_I= V_O(nom)+ 1.0 V or V_I= 3.0 V (whichever is greater); V_EN= V_I; I_O= 0 mA; C_IN= 10 µF; C_OUT= 10 µF; C_NR

1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise

noted)

V_IN

I_OUT

(10 V/div)

(1 A/div)

V_OUT

(10 mV/div)

Time (500 ms/div)

Time (5 ms/div)

V_IN= 5 V, V_OUT= 3.3 V, I_OUT= 10 mA to 845 mA

V_IN= 5 V to 15 V, V_OUT= 3.3 V, I_OUT= 845 mA

Figure 19. Load Transient

Figure 20. Line Transient

I_OUT= 50 mA, V_NOISE= 5 mV_RMS

I_OUT= 20 mA, V_NOISE= 5.9 mV_RMS

V_EN

(2 V/div)

V_OUT

(2 V/div)

I_OUT

(200 mA/div)

0.1

0.01

100

10k

100k

Time (50 ms/div)

Frequency (Hz)

Startup time = 65 ms, V_IN= 6 V, V_OUT= 5V, I_OUT= 500 mA,

C_IN= 10 µF, C_OUT= 50 µF

V_OUT= 4.7 V, C_OUT= 10 µF, C_NR= 1 µF, BW_RMSNOISE(10 Hz,

100 kHz)

Figure 21. Startup

Figure 22. Noise vs Output Current

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ZHCSGI7 –AUGUST 2017

7 Detailed Description

7.1 Overview

The TPS7A47-Q1 is a positive voltage (35 V), ultralow-noise (4.2 µV_RMS) LDO capable of sourcing a 1-A load.

The TPS7A47-Q1 is designed with bipolar technology primarily for high-accuracy, high-precision instrumentation

applications where clean voltage rails are critical to maximize system performance. This feature makes the

device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters

(DACs), and other high-performance analog circuitry.

7.2 Functional Block Diagram

OUT

Thermal

Shutdown

UVLO

C_IN

C_OUT

Current

Limit

100 kW

Band

Gap

265.5 kW

SENSE/FB

3.2 MW

0P1V

0P2V

0P4V

0P8V

1.6 MW

800 kW

400 kW

1.572 MW

Fast

Charge

Enable

TI Device

1P6V 3P2V 6P4V 6P4V

C_NR

7.3 Feature Description

7.3.1 Internal Current Limit (I_CL

)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The

LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases. Also, when a current limit

occurs while the resulting output voltage is low, excessive power is dissipated across the LDO, which results in a

thermal shutdown of the output.

7.3.2 Enable (EN) And Undervoltage Lockout (UVLO)

The TPS7A47-Q1 only turns on when both EN and UVLO are above the respective voltage thresholds. The

UVLO circuit monitors input voltage (V_I) to prevent device turn-on before V_Irises above the lockout voltage. The

UVLO circuit also causes a shutdown when V_Ifalls below lockout. The EN signal allows independent logic-level

turn-on and shutdown of the LDO when the input voltage is present. EN can be connected directly to V_Iif

independent turn-on is not needed.

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

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Feature Description (continued)

7.3.3 Soft-Start And Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have

achieved the threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output

noise reduction and programming the soft-start ramp during turn-on.

Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up.

Inrush current then consists primarily of the sum of load and charge current to the output capacitor. Use

Equation 1 to estimate in-rush current:

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

where:

•

V_OUT(t) is the instantaneous output voltage of the turn-on ramp

dV_OUT(t) / dt is the slope of the V_Oramp

R_LOADis the resistive load impedance

(1)

7.4 Device Functional Modes

The TPS7A47-Q1 has the following functional modes:

1. Enabled: when EN goes above V_+EN(HI), the device is enabled.

2. Disabled: when EN goes below V_+EN(LO), the device is disabled. During this time, OUT is high impedance,

and the current into IN does not exceed I_(SHDN)

7.5 Programming

7.5.1 ANY-OUT Programmable Output Voltage

For ANY-OUT operation, do not use external resistors to set the output voltage, but use device pins 4, 5, 6, 8, 9,

10, 11, and 12 to program the regulated output voltage. Each pin is either connected to ground (active) or is left

open (floating). The ANY-OUT programming is set by Equation 2 as the sum of the internal reference voltage

(V_(REF)= 1.4 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 100 mV

(pin 12), 200 mV (pin 11), 400 mV (pin 10), 800 mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V

(pin 4). Table 1 summarizes these voltage values associated with each active pin setting for reference. By

leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output

voltage equal to V_(REF)

V_OUT= V_REF+ (S ANY-OUT Pins to Ground)

(2)

Table 1. ANY-OUT Programmable Output Voltage

ANY-OUT PROGRAM PINS (Active Low)

Pin 4 (6P4V2)

ADDITIVE OUTPUT VOLTAGE LEVEL

6.4 V

Pin 5 (6P4V1)

Pin 6 (3P2)

3.2 V

Pin 8 (1P6)

1.6 V

Pin 9 (0P8)

800 mV

400 mV

200 mV

100 mV

Pin 10 (0P4)

Pin 11 (0P2)

Pin 12 (0P1)

TPS7A47-Q1

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Table 2 shows a list of the most common output voltages and the corresponding pin settings. The voltage setting

pins have a binary weight; therefore, the output voltage can be programmed to any value from 1.4 V to 20.5 V in

100-mV steps.

Table 2. Common Output Voltages and Corresponding Pin Settings

PIN NAMES AND VOLTAGE PER PIN

0P1V

(100 mV)

0P2V

(200 mV)

0P4V

(400 mV)

0P8V

(800 mV)

1P6V

(1.6 V)

3P2V

(3.2 V)

6P4V1

(6.4 V)

6P4V2

(6.4 V)

V_O(V)

1.4

1.5

1.8

2.5

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

Open

GND

3.3

4.5

20.5

7.5.2 Adjustable Operation

The TPS7A47-Q1 has an output voltage range of 1.4 V to 34 V. For adjustable operation, set the nominal output

voltage of the device (as shown in Figure 23) using two external resistors.

V_IN

V_OUT

OUT

C_IN

R₁

R₂

TPS7A4701-Q1

10 mF

C_OUT

47 mF

GND

C_NR/SS

1 mF

Figure 23. Adjustable Operation for Maximum AC Performance

R₁and R₂can be calculated for any output voltage within the operational range. The current through feedback

resistor R₂must be at least 5 µA to ensure stability. Additionally, the current into the FB pin (I_(FB), typically

350 nA) creates an additional output voltage offset that depends on the resistance of R₁. For high-accuracy

applications, select R₂such that the current through R₂is at least 35 µA to minimize any effects of I_(FB)variation

on the output voltage; 10 kΩ is recommended. Equation 3 calculates R₁.

V_OUT- V_REF

R₁=

V_REF

I_FB

R₂

where

•

V_REF= 1.4 V

I_FB= 350 nA

(3)

Use 0.1% tolerance resistors to minimize the effects of resistor inaccuracy on the output voltage.

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

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Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially available 1%

tolerance resistors. The resulting output voltages yield a nominal error of < 0.5%.

Table 3. Suggested Resistors for Common Voltage Rails

V_OUT

1.4 V

1.8 V

3.3 V

5 V

R₁, CALCULATED

0 Ω

R₁, CLOSEST 1% VALUE

R₂

0 Ω

∞

2.782 kΩ

2.8 kΩ

13.3 kΩ

25.5 kΩ

76.8 kΩ

102 kΩ

118 kΩ

165 kΩ

9.76 kΩ

10 kΩ

10.2 kΩ

10.5 kΩ

10 kΩ

10.2 kΩ

13.213 kΩ

25.650 kΩ

77.032 kΩ

101.733 kΩ

118.276 kΩ

164.238 kΩ

12 V

15 V

18 V

24 V

To achieve higher nominal accuracy, two resistors can be used in the place of R₁. Select the two resistor values

such that the sum results in a value as close as possible to the calculated R₁value.

There are several alternative ways to set the output voltage. The program pins can be pulled low using external

general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board

(PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for purchase from the

TI eStore, allows the output voltage to be programmed using jumpers.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A47-Q1 is a high-voltage, low-noise, 1-A LDO. Low-noise performance makes this LDO ideal for

providing rail voltages to noise-sensitive loads, such as PLLs, oscillators, and high-speed ADCs.

8.2 Typical Application

As shown in Figure 24, output voltage is set by grounding the appropriate control pins. When grounded, all

control pins add a specific voltage on top of the internal reference voltage (V_(REF)= 1.4 V). For example, when

grounding pins 0P1V, 0P2V, and 1P6V, the voltage values 0.1 V, 0.2 V, and 1.6 V are added to the 1.4-V

internal reference voltage for V_O(nom)equal to 3.3 V, as described in the Programming section.

V_IN= 5 V

V_OUT= 3.3 V

OUT

10 mF

47 mF

SENSE

GND

Load

TPS7A4701-Q1

1 mF

0P1V

0P2V

0P4V 0P8V 1P6V 3P2V 6P4V1 6P4V2

Figure 24. Typical Application, V_OUT= 3.3 V

8.2.1 Design Requirements

PARAMETER

Input voltage

Output voltage

Output current

DESIGN REQUIREMENT

5.0 V, ±10%

3.3 V, ±3%

500 mA

Peak-to-peak noise, 10 Hz to 100 kHz

50 µV_PP

8.2.2 Detailed Design Procedure

8.2.2.1 Capacitor Recommendations

This LDO is designed to be stable using low equivalent series resistance (ESR), ceramic capacitors at the input,

output, and at the noise-reduction pin (NR, pin 14). Multilayer ceramic capacitors have become the industry

standard for these types of applications and are recommended here, but must be used with good judgment.

Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good

capacitive stability across temperature, but the use of Y5V-rated capacitors is discouraged precisely because the

capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating voltage and the

design engineer must be aware of these characteristics. TI recommends applying a 50% derating of the nominal

capacitance in the design.

TPS7A47-Q1

ZHCSGI7 –AUGUST 2017

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Attention must be given to the input capacitance to minimize transient input droop during load current steps

because the TPS7A47-Q1 has a very fast load transient response. Large input capacitors are necessary for good

transient load response, and have no detrimental influence on the stability of the device. However, using large

ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor, in combination

with the wire lead inductance, creates a high-Q peaking effect during transients. For example, a 5-nH lead

inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of 712 kHz at the edge of

the control loop bandwidth. Short, well-designed interconnect leads to the up-stream supply minimize this effect

without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with

a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.

8.2.2.1.1 Input and Output Capacitor Requirements

The TPS7A47-Q1 is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the

input and output. Optimal noise performance is characterized using a total output capacitor value of 50 µF. Input

and output capacitances must be located as near as practical to the respective input and output pins.

8.2.2.1.2 Noise-Reduction Capacitor (C_NR

)

The noise-reduction capacitor, connected to the NR pin of the LDO, forms an RC filter for filtering out noise that

might ordinarily be amplified by the control loop and appear on the output voltage. Larger capacitances, up to

1 µF, affect noise reduction at lower frequencies and also tend to further reduce noise at higher frequencies. C_NR

also serves a secondary purpose in programming the turn-on rise time of the output voltage and thereby controls

the turn-on surge current.

8.2.2.2 Dropout Voltage (V_DO

)

Generally speaking, the dropout voltage often refers to the voltage difference between the input and output

voltage (V_(DO)= V_I– V_O). However, in the Electrical Characteristics V_(DO)is defined as the V_I– V_Ovoltage at the

rated current (I_(RATED)), where the main current pass-FET is fully on in the Ohmic region of operation and is

characterized by the classic R_DS(on)of the FET. V_(DO)indirectly specifies a minimum input voltage above the

nominal programmed output voltage at which the output voltage is expected to remain within its accuracy

boundary. If the input falls below this V_(DO)limit (V_I< V_O+ V_(DO)), then the output voltage decreases in order to

follow the input voltage.

Dropout voltage is always determined by the R_DS(on)of the main pass-FET. Therefore, if the LDO operates below

the rated current, then V_(DO)is directly proportional to the output current and can be reduced by the same factor.

Use Equation 4 to calculate R_DS(on)for the TPS7A47-Q1:

V_DO

R_DS(ON)

I_RATED

(4)

8.2.2.3 Output Voltage Accuracy

The output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected

nominal output voltage stated as a percent. This accuracy error typically includes the errors introduced by the

internal reference and the load and line regulation across the full range of rated load and line operating

conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage

accuracy also accounts for all variations between manufacturing lots.

8.2.2.4 Startup

The startup time for the TPS7A47-Q1 depends on the output voltage and the capacitance of the C_NRcapacitor.

Equation 5 calculates the startup time for a typical device.

V + 5

≈

’

t_SS= 100,000 • C_NR• ln

∆

◊

where

•

C_NR= capacitance of the C_NRcapacitor

V_R= V_Ovoltage if using the ANY-OUT configuration, or 1.4 V if using the adjustable configuration

(5)

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8.2.2.5 AC Performance

AC performance of the LDO is typically understood to include power-supply rejection ratio, load step transient

response, and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase

margin, and reference noise.

8.2.2.5.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc

output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 6

gives the PSRR calculation as a function of frequency where input noise voltage [V_S(IN)(f)] and output noise

voltage [V_S(OUT)(f)] are understood to be purely ac signals.

V_S(IN)(f)

PSRR (dB) = 20 Log₁₀

V_S(OUT)(f)

(6)

Noise that couples from the input to the internal reference voltage for the control loop is also a primary

contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise-

reduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (R_SS) for optimal

PSRR.

The LDO is often employed not only as a dc/dc regulator, but also to provide exceptionally clean power-supply

voltages that are free of noise and ripple to power-sensitive system components. This usage is especially true for

the TPS7A47-Q1.

8.2.2.5.2 Load Step Transient Response

The load step transient response is the output voltage response by the LDO to a step change in load current

whereby output voltage regulation is maintained. The worst-case response is characterized for a load step of

10 mA to 1 A (at 1 A per microsecond) and shows a classic, critically-damped response of a very stable system.

The voltage response shows a small dip in the output voltage when charge is initially depleted from the output

capacitor and then the output recovers as the control loop adjusts itself. The depth of the charge depletion

immediately after the load step is directly proportional to the amount of output capacitance. However, to some

extent, the speed of recovery is inversely proportional to that same output capacitance. In other words, larger

output capacitances act to decrease any voltage dip or peak occurring during a load step but also decrease the

control-loop bandwidth, thereby slowing response.

The worst-case, off-loading step characterization occurs when the current step transitions from 1 A to 0 mA.

Initially, the LDO loop cannot respond fast enough to prevent a small increase in output voltage charge on the

output capacitor. Because the LDO cannot sink charge current, the control loop must turn off the main pass-FET

to wait for the charge to deplete, thus giving the off-load step its typical monotonic decay (which appears

triangular in shape).

8.2.2.5.3 Noise

The TPS7A47-Q1 is designed, in particular, for system applications where minimizing noise on the power-supply

rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking

circuits for instance, where minimum phase noise is all important, or in-test and measurement systems where

even small power-supply noise fluctuations can distort instantaneous measurement accuracy. Because the

TPS7A47-Q1 is also designed for higher voltage industrial applications, the noise characteristic is well designed

to minimize any increase as a function of the output voltage.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This

noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,

thermal noise caused by thermal agitation of charge carriers, flicker or 1/f noise that is a property of resistors and

dominates at lower frequencies as a function of 1/f, burst noise, and avalanche noise).

To calculate the LDO RMS output noise, a spectrum analyzer must first measure the spectral noise across the

bandwidth of choice (typically 10 Hz to 100 kHz in units of µV/√Hz). The RMS noise is then calculated in the

usual manner as the integrated square root of the squared spectral noise over the band, then averaged by the

bandwidth.

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8.2.3 Application Curves

V_OUT(10 µV/DIV)

V_EN(2 V/DIV)

V_OUT(1 V/DIV)

I_LOAD(500 mA/DIV)

Figure 25. Startup With EN Pin Rising

(10 ms per Division)

Figure 26. Output Noise Voltage, 10 Hz to 100 kHz

(10 ms per Division)

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9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range of 3 V to 35 V. If the input supply is noisy,

additional input capacitors with low ESR can help improve the output noise performance.

9.1 Power Dissipation (P_D)

Power dissipation must be considered in the PCB design. In order to minimize risk of device operation above

145°C, use as much copper area as available for thermal dissipation. Do not locate other power-dissipating

devices near the LDO.

Power dissipation in the regulator depends on the input to output voltage difference and load conditions.

Equation 7 calculates P_D:

P_D= (V_OUT- V_IN) ´ I_OUT

(7)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input voltage necessary for output regulation to be obtained.

The primary heat conduction path for the VQFN (RGW) package is through the PowerPAD to the PCB. The

PowerPAD must be soldered to a copper pad area under the device. Thermal vias are recommended to improve

the thermal conduction to other layers of the PCB.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to Equation 8, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (θ_JA) of the combined PCB and device package and the temperature of the ambient

air (T_A).

T_J= T_A+ (q_JA´ P_D)

(8)

Unfortunately, this thermal resistance (θ_JA) depends primarily on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

spreading planes. The θ_JArecorded in the Thermal Information table is determined by the JEDEC standard, PCB,

and copper-spreading area and is to be used only as a relative measure of package thermal performance. For a

well-designed thermal layout, θ_JAis actually the sum of the VQFN package junction-to-case (bottom) thermal

resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper. By knowing θ_JCbot, the minimum

amount of appropriate heat sinking can be used with Figure 27 to estimate θ_JA. θ_JCbotcan be found in the

Thermal Information table.

120

100

q_JA(RGW)

Board Copper Area (in²)

NOTE: θ_JAvalue at a board size of 9-in²(that is, 3-in × 3-in) is a JEDEC standard.

Figure 27. θ_JAvs Board Size

TPS7A47-Q1

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10 Layout

10.1 Layout Guidelines

For best overall performance, all circuit components are recommended to be located on the same side of the

circuit board and as near as practical to the respective LDO pin connections. Ground return connections to the

input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and

connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit

connections is strongly discouraged and negatively affects system performance. This grounding and layout

scheme minimizes inductive parasitics and thereby reduces load-current transients, minimizes noise, and

increases circuit stability.

A ground reference plane is also recommended. This reference plane serves to assure accuracy of the output

voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when

connected to the PowerPAD. In most applications, this ground plane is necessary to meet thermal requirements.

Use the TPS7A4701 evaluation module (EVM), available for purchase from the TI eStore, as a reference for

layout and application design.

10.2 Layout Example

Signal Ground

R₁

R₂

Use R₁and R₂

with adjustable

operation

SN/FB

C_NR

Connect if

ANYOUT

operation is

used.

Power

Ground

Input

Output

C_OUT

C_IN

Orient input and output capacitors

vertically, so that the grounds are

separated.

Figure 28. Layout Example

TPS7A47-Q1

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ZHCSGI7 –AUGUST 2017

10.3 Thermal Protection

The TPS7A47-Q1 contains a thermal shutdown protection circuit to turn off the output current when excessive

heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (T_J) of the main

pass-FET exceeds 170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)

when the temperature falls to 145°C (typical). Because the TPS7A47-Q1 is capable of supporting high input

voltages, a great deal of power can be expected to be dissipated across the device at low output voltages, which

causes a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the

output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.

For reliable operation, the junction temperature must be limited to a maximum of 145°C. To estimate the thermal

margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered

using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must be

designed to occur at least 45°C above the maximum expected ambient temperature condition for the application.

This configuration produces a worst-case junction temperature of 145°C at the highest expected ambient

temperature and worst-case load.

The internal protection circuitry of the TPS7A47-Q1 is designed to protect against thermal overload conditions.

The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A47-Q1 into thermal

shutdown degrades device reliability.

10.4 Estimating Junction Temperature

JEDEC standards recommend the use of PSI thermal metrics to estimate the junction temperatures of the LDO

when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances,

but rather offer practical and relative means of estimating junction temperatures. These PSI metrics are

determined to be significantly independent of copper-spreading area. The key thermal metrics (Ψ_JTand Ψ_JB) are

given in the Thermal Information table and are used in accordance with Equation 9.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in Equation 7

T_Tis the temperature at the center-top of the device package

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(9)

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11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

《TPS7A33 –36V、1A、超低噪声负电压稳压器》

《TPS7A47XXEVM-094 评估模块用户指南》

《使用前馈电容器和低压降稳压器的优缺点》

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到所有的

产品更改信息每周摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

ANY-OUT, PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A4701QRGWRQ1

TPS7A4701QRGWTQ1

ACTIVE

VQFN

RGW

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

7A4701Q

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A4701QRGWRQ1

TPS7A4701QRGWTQ1

VQFN

RGW

3000

250

330.0

180.0

12.4

5.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A4701QRGWRQ1

TPS7A4701QRGWTQ1

VQFN

RGW

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGW 20

5 x 5, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4227157/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

5.1

4.9

PIN 1 INDEX AREA

5.1

4.9

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.15±0.1

2X 2.6

(0.1) TYP

16X 0.65

SYMM

2.6

0.36

0.26

20X

PIN1 ID

(OPTIONAL)

0.1

C A B

0.05

SYMM

0.65

0.45

20X

4219039/A 06/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

3.15)

(2.6)

(

16X (0.65)

(1.325)

SYMM

(4.65) (2.6)

(R0.05) TYP

20X (0.31)

20X (0.75)

(Ø0.2) VIA

TYP

(1.325)

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219039/A 06/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

4X ( 1.37)

2X (0.785)

16X (0.65)

2X (0.785)

SYMM

(4.65) (2.6)

(R0.05) TYP

20X (0.31)

20X (0.75)

METAL

TYP

SYMM

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED COVERAGE BY AREA

SCALE: 15X

4219039/A 06/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A4701QRGWTQ1 [TI]

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