TPS7A88 [TI]

1A、低噪声、高 PSRR、双通道可调节超低压降稳压器;


型号：	TPS7A88
厂家：	TEXAS INSTRUMENTS
描述：	1A、低噪声、高 PSRR、双通道可调节超低压降稳压器稳压器
文件：	总36页 (文件大小：2314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

TPS7A88 双路 1A 低噪声 (3.8 µV_RMS)、LDO 稳压器

1 特性

3 说明

•

两个独立的 LDO 通道

TPS7A88 是一款双路、低噪声 (3.8 µV_RMS)、低压降

(LDO) 稳压器，每通道具有 1A 的拉电流能力，其最高

压降仅为 200mV。

低输出噪声：< 3.8µV_RMS(10Hz–100kHz)

低压降：1A 电流时为 200mV（最大值）

宽输入电压范围：1.4V 至 6.5V

宽输出电压范围：0.8V 至 5.0V

高电源纹波抑制：

TPS7A88 提供两个独立的 LDO，极具灵活性，解决方

案尺寸要比两个单通道 LDO 小 50% 左右。每个输出

可通过外部电阻在 0.8V 至 5.0V 范围内进行调节。

TPS7A88 的宽输入电压范围支持其在 1.4V 至 6.5V 范

围内的电压下工作。

–

直流时为 75dB

100kHz 时为 40dB

1MHz 时为 40dB

TPS7A88 的输出电压精度（整个线路、负载和温度范

围内）达 1%，并且可通过软启动功能减少涌入电流，

因此非常适合为敏感类模拟低压器件 [例如，压控振荡

器 (VCO)、模数转换器 (ADC)、数模转换器 (DAC)、

高端处理器和现场可编程门阵列 (FPGA)] 供电。

•

整个线路、负载和温度范围内的精度达 1.0%

出色的负载瞬态响应

可调节的启动浪涌控制

可选软启动充电电流

独立开漏电源正常 (PG) 输出

与 10µF 或更大的陶瓷输出电容一起工作时保持稳

定

TPS7A88 旨在为噪声敏感类组件供电，广泛适用于高

速通信、视频、医疗或测试和测量等应用。此器件具

有 4 µV_RMS的超低输出噪声和宽带电源抑制比 (PSRR)

（1MHz 时为 40dB），最大限度减少了相位噪声和时

钟抖动。这些特性最大限度提升了计时器件、ADC

和 DAC 的性能。

•

4mm × 4mm 20 引脚超薄型四方扁平无引线

(WQFN) 封装

2 应用

•

高速模拟电路：

器件信息⁽¹⁾

–

压控振荡器 (VCO)、模数转换器 (ADC)、数模

转换器 (DAC) 以及低压差分信令 (LVDS)

器件型号

TPS7A88

封装

WQFN (20)

封装尺寸（标称值）

4.00mm x 4.00mm

•

成像：互补金属氧化物半导体 (CMOS) 传感器，视

频专用集成电路 (ASIC)

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

•

测试和测量

仪器仪表、医疗和音频

数字负载：串化解串器 (SerDes)，现场可编程栅极

阵列 (FPGA)， DSP™

典型应用图

ENABLE

Clock

LMK03328

LMX2581

PG1

VIN1

EN1

IN1

EN1

OUT1

OUT2

VDD_VCO

TPS7A88

VIN2

EN2

IN2

EN2

PG2

VDD

SCLK

ADC

ADC3xxx

ADC3xJxx

ADS4xJBxx

ADC5xJxx

ADC12Jxxxx

ENABLE

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS248

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 13

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application .................................................. 22

8.3 Do's and Don'ts....................................................... 23

Power Supply Recommendations...................... 24

10 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 24

10.2 Layout Example .................................................... 25

11 器件和文档支持 ..................................................... 26

11.1 器件支持 ............................................................... 26

11.2 文档支持 ............................................................... 26

11.3 社区资源................................................................ 26

11.4 商标....................................................................... 27

11.5 静电放电警告......................................................... 27

11.6 Glossary................................................................ 27

12 机械、封装和可订购信息....................................... 27

4 修订历史记录

Changes from Original (November 2015) to Revision A

Page

•

已发布为“量产数据”................................................................................................................................................................. 1

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

5 Pin Configuration and Functions

RTJ Package

4-mm × 4-mm 20-Pin WQFN

Top View

20 19 18 17 16

IN1

15 OUT1

OUT1

GND

IN2

Thermal Pad

OUT2

IN2

11 OUT2

Pin Functions

NAME

NO.

I/O

DESCRIPTION

EN1

EN2

Enable pin for each channel. These pins turn the regulator on and off. If V_ENx⁽¹⁾≥ V_IH(ENx), the regulator is enabled.

If V_ENx≤ V_IL(ENx), the regulator is disabled. The ENx pin must be connected to INx if the enable function is not

used.

FB1

FB2

GND

IN1

Feedback pin for each channel. These pins are the inputs to the control loop error amplifier and are used to set

the output voltage of the device.

—

3, 13

1, 2

4, 5

Device GND. Connect both pins to the device thermal pad.

Input pin for LDO1. A 10 µF or greater input capacitor is required to assure robust operation.

Input pin for LDO2. A 10 µF or greater input capacitor is required to assure robust operation.

IN2

NR/SS1

NR/SS2

Noise reduction pin for each channel. Connect these pins to an external capacitor to bypass the noise generated

by the internal band-gap reference. The capacitor reduces the output RMS noise to very low levels and sets the

output ramp rate to limit inrush current.

—

OUT1

OUT2

PG1

14, 15

11, 12

Regulated output 1. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability.

Regulated output 2. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability.

Open-drain power-good indicator pins for the LDO1 and LDO2 output voltages. A 10-kΩ to 100-kΩ external pullup

resistor is required. These pins can be left floating or connected to GND if not used.

PG2

SS_CTRL1

Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of

the NR/SSx capacitor. If a C_NR/SSxcapacitor is not used, SS_CTRLx must be connected to GND to avoid output

overshoot.

SS_CTRL2

Thermal pad

—

Connect the thermal pad to the printed circuit board (PCB) ground plane.

(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

INx, PGx, ENx⁽²⁾

7.0

7.5

V_INx+ 0.3⁽³⁾

3.6

INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs)

Voltage

Current

OUTx

SS_CTRLx

NR/SSx, FBx⁽²⁾

OUTx⁽²⁾

PGx (sink current into device)⁽²⁾

Internally limited

°C

Operating junction temperature, T_J

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.

(3) The absolute maximum rating is V_INx+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

1.4

0.8

MAX

6.5

5.0

UNIT

V_INx

Input supply voltage range

Output voltage range

V_OUTx

I_OUTx

C_INx

Output current

Input capacitor, each input

Output capacitor

µF

kΩ

°C

C_OUTx

C_NR/SSx

R_PG

Noise-reduction capacitor

Power-good pullup resistance

Junction temperature range

100

125

T_J

–40

6.4 Thermal Information

TPS7A88

THERMAL METRIC⁽¹⁾

RTJ (WQFN)

UNIT

20 PINS

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.8

8.0

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

8.0

R_θJC(bot)

2.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

6.5 Electrical Characteristics

over operating temperature range (T_J= –40°C to +125°C), V_INx= 1.4 V, V_OUTx(TARGET)= 0.8 V, I_OUTx= 50 mA, V_ENx= 1.4 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, SS_CTRLx = GND, PGx pin pulled up to V_INxwith 100 kΩ, and for each channel

(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

V_INx

Input supply voltage range

Reference voltage

Input supply UVLO

V_UVLO

1.4

6.5

V_REF

V_UVLO

V_HYS

0.8

1.31

290

V_INxrising

1.39

Output voltage range

Output voltage accuracy⁽²⁾⁽³⁾

Line regulation

0.8 – 1.0%

–1.0%

5.0 + 1.0%

1.0%

V_OUTx

0.8 V ≤ V_OUTx≤ 5 V, 5 mA ≤ I_OUTx≤ 1 A

I_OUTx= 5 mA, 1.4 V ≤ V_INx≤ 6.5 V

5 mA ≤ I_OUTx≤ 1 A

ΔV_OUTx(ΔVINx)

ΔV_{OUTx(ΔIOUTx)}

0.003

0.03

%/V

%/A

Load regulation

V_INx≥ 1.4 V, 0.8 V ≤ V_OUTx≤ 5.0 V,

I_OUTx= 1 A, V_FBx= 0.8 V – 3%

V_DO

I_LIM

Dropout voltage

200

1.9

3.5

V_OUTxforced at 0.9 × V_OUTx(TARGET)

Output current limit

1.5

1.7

2.1

V_INx= V_OUTx(TARGET)+ 300 mV

Both channels enabled, per channel,

V_INx= 6.5 V, I_OUTx= 5 mA

I_GND

GND pin current

Both channels enabled, per channel,

V_INx= 1.4 V, I_OUTx= 1 A

Both channels shutdown, per channel, PGx = (open),

V_INx= 6.5 V, V_ENx= 0.5 V

I_SDN

Shutdown GND pin current

ENx pin current

0.1

0.2

0.4

μA

I_ENx

V_INx= 6.5 V, 0 V ≤ V_ENx≤ 6.5 V

–0.2

ENx pin low-level input voltage

(device disabled)

V_IL(ENx)

ENx pin high-level input voltage

(device enabled)

V_IH(ENx)

I_{SS_CTRLx}

V_IT(PGx)

1.1

–0.2

82%

6.5

0.2

SS_CTRLx pin current

PGx pin threshold

V_INx= 6.5 V, 0 V ≤ V_{SS_CTRLx}≤ 6.5 V

μA

For PGx transitioning low with falling V_OUTx

expressed as a percentage of V_OUTx(TARGET)

88.9%

93%

For PGx transitioning high with rising V_OUTx

expressed as a percentage of V_OUTx(TARGET)

V_hys(PGx)

PGx pin hysteresis

V_OL(PGx)

I_lkg(PGx)

PGx pin low-level output voltage V_OUTx< V_IT(PGx), I_PGx= –1 mA (current into device)

0.4

PGx pin leakage current

V_OUTx> V_IT(PGx), V_PGx= 6.5 V

µA

V_NR/SSx= GND, 1.4 V ≤ V_INx≤ 6.5 V,

V_{SS_CTRLx}= GND

4.0

6.2

9.0

I_NR/SSx

NR/SSx pin charging current

µA

V_NR/SSx= GND, 1.4 V ≤ V_INx≤ 6.5 V, V_{SS_CTRLx}= V_INx

100

150

100

I_FBx

FBx pin leakage current

V_INx= 6.5 V, V_FBx= 0.8 V

–100

f = 500 kHz, V_INx= 3.8 V, V_OUTx= 3.3 V,

I_OUTx= 750 mA, C_NR/SSx= 10 nF, C_FFx= 10 nF

PSRR

Power-supply ripple rejection

3.8

BW = 10 Hz to 100 kHz, V_INx= 1.8 V, V_OUTx= 0.8 V,

I_OUTx= 1.0 A, C_NR/SSx= 1 µF, C_FFx= 100 nF

V_n

Output noise voltage

Noise spectral density

μV_RMS

nV/√Hz

f = 10 kHz, V_INx= 1.8 V, V_OUTx= 0.8 V,

I_OUTx= 1.0 A, C_NR/SSx= 10 nF, C_FFx= 10 nF

Output active discharge

resistance

R_diss

V_ENx= GND

250

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_sd

Thermal shutdown temperature

°C

(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.

(2) When the device is connected to external feedback resistors at the FBx pin, external resistor tolerances are not included.

(3) The device is not tested under conditions where V_INx> V_OUTx+ 2.5 V and I_OUTx= 1 A because the power dissipation is higher than the

maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power

dissipation limit of the package under test.

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

6.6 Typical Characteristics

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

I_OUTx= 1 A

C_NR/SSx= Open

C_NR/SSx= 0.01 mF

C_NR/SSx= 0.1 mF

C_NR/SSx= 1 mF

C_NR/SSx= 10 mF

I_OUTx= 0.75 A

I_OUTx= 0.5 A

I_OUTx= 0.25 A

I_OUTx= 0.1 A

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_OUTx= 1.2 V, V_INx= V_ENx= 1.7 V, I_OUTx= 1 A, C_OUTx= 10 µF,

C_NR/SSx= C_FFx= 10 nF

V_OUTx= 1.2 V, V_INx= V_ENx= 1.7 V, I_OUTx= 1.0 A, C_OUTx= 10 µF,

C_FFx= 10 nF

图 1. Power-Supply Rejection vs Output Current

图 2. Power-Supply Rejection vs C_NR/SSx

V_INx= 1.5 V

V_INx= 1.7 V

I_OUTx= 1 A

V_INx= 1.8 V

V_INx= 2.5 V

I_OUTx= 0.75 A

I_OUTx= 0.5 A

I_OUTx= 0.25 A

I_OUTx= 0.1 A

V_INx= 3.3 V

V_INx= 5.0 V

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_OUTx= 1.2 V, I_OUTx= 1.0 A, C_OUTx= 10 µF,

C_NR/SSx= C_FFx= 10 nF

V_OUTx= 3.3 V, V_INx= V_ENx= 3.8 V, I_OUTx= 1 A, C_OUTx= 10 µF,

C_NR/SSx= C_FFx= 10 nF

图 4. Power-Supply Rejection vs Output Current

图 3. Power-Supply Rejection vs Input Voltage

C_OUTx= 10 mF

V_INx= 6.0 V

V_INx= 5.0 V

V_INx= 3.8 V

C_OUTx= 22 mF

C_OUTx= 100 mF

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_OUTx= 1.2 V, V_INx= V_ENx= 1.7 V, I_OUTx= 1.0 A,

C_OUTx= ceramic, C_FFx= 10 nF

V_OUTx= 3.3 V, I_OUTx= 1.0 A, C_OUTx= 10 µF,

C_NR/SSx= C_FFx= 10 nF

图 5. Power-Supply Rejection vs Output Capacitance

图 6. Power-Supply Rejection vs Input Voltage

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

110

100

V_OUTx= 0.8 V, 3.94 mV_RMS

V_OUTx= 1.2 V, 4.31 mV_RMS

V_OUTx= 1.8 V, 5.1 mV_RMS

V_OUTx= 2.5 V, 6.03 mV_RMS

V_OUTx= 3.3 V, 7.43 mV_RMS

V_OUTx= 5.0 V, 10.3 mV_RMS

0.1

0.01

V_OUT1to V_OUT2

V_OUT2to V_OUT1

0.001

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_OUTx= 1.8 V, I_OUTx= 100 mA, C_OUTx= 10 µF,

C_NR/SSx= C_FFx= 10 nF

V_INx= V_OUTx+ 1.0 V, I_OUTx= 1.0 A, V_RMSBW = 10 Hz to 100 kHz,

C_OUTx= 10 µF, C_NR/SSx= C_FFx= 10 nF

图 8. Spectral Noise Density vs Output Voltage

图 7. Channel-to-Channel Output Voltage Isolation vs

Frequency

C_NR/SSx= None, 11.43 mV_RMS

C_NR/SSx= 0.01 mF, 4.94 mV_RMS

C_NR/SSx= 0.1 mF, 4.24 mV_RMS

C_FFx= 0 mF

C_FFx= 0.01 mF

C_FFx= 0.1 mF

C_NR/SSx= 1.0 mF, 4.22 mV_RMS

0.1

0.01

0.001

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_INx= 1.7 V, V_OUTx= 1.2 V, I_OUTx= 1.0 A, V_RMSBW = 10 Hz to

100 kHz, C_OUTx= 10 µF, C_FFx= 10 nF

V_INx= 3.8 V, V_OUTx= 3.3 V, I_OUTx= 1.0 A, V_RMSBW = 10 Hz to

100 kHz, C_OUTx= 10 µF, C_NR/SSx= 10 nF

图 9. Spectral Noise Density vs C_NR/SSx

图 10. Spectral Noise Density vs C_FFx

V_INx= 1.5 V

V_INx= 1.8 V

V_INx= 2.5 V

C_OUTx= 10 mF, 4.94 mV_RMS

C_OUTx= 22 mF, 5.05 mV_RMS

C_OUTx= 100 mF, 5.66 mV_RMS

V_INx= 3.3 V

0.1

0.01

0.001

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

V_OUTx= 1.2 V, I_OUTx= 1.0 A, C_OUTx= 10 µF, C_NR/SSx= 10 nF

V_OUTx= 1.8 V, I_OUTx= 1.0 A, V_RMSBW = 10 Hz to 100 kHz,

C_FFx= 0.01 µF

图 12. Spectral Noise Density vs C_OUTx

图 11. Spectral Noise Density vs V_INx

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

1E-6

1E-5 0.0001 0.001

0.01

0.1

1E-6

1E-5

0.0001

0.001

0.01

0.1

Noise Reduction Capacitor [C_NR/SSx] (mF)

Feed-Forward Capacitor [C_FFx] (mF)

V_OUTx= 1.8 V, I_OUTx= 1.0 A, C_FFx= 0.01 µF,

BW = 10 Hz to 100 kHz

V_OUTx= 1.8 V, I_OUTx= 1.0 A, C_NR/SSx= 1 µF,

BW = 10 Hz to 100 kHz

图 13. RMS Output Noise vs C_NR/SSx

图 14. RMS Output Noise vs C_FFx

V_OUT2

50 mV/div

20 mV/div

V_OUT1

20 mV/div

V_OUT1

50 mV/div

I_OUT1

500 mA/div

I_OUT1

500 mA/div

Time (10 ms/div)

V_INx= 5.5 V, I_OUTx= 100 mA to 1 A to 100 mA at 1 A/µs,

C_OUTx= 10 µF

V_INx= 1.5 V, I_OUTx= 100 mA to 1 A to 100 mA at 1 A/µs,

C_OUTx= 10 µF

图 16. Load Transient Response (V_OUTx= 5.0 V)

图 15. Load Transient Response (V_OUTx= 1.2 V)

2.2

-40èC

0èC

25èC

85èC

125èC

V_INx

2 V/div

1.8

1.6

1.4

1.2

V_OUTx

20 mV/div

V_PGx

1 V/div

0.25

0.5

0.75

1.25

1.5

Output Voltage (V)

Time (200 ms/div)

V_INx= 1.4 V to 6.5 V to 1.4 V at 2 V/µs, V_OUTx= 0.8 V,

I_OUTx= 1 A, C_NR/SSx= C_FFx= 10 nF

D001

V_INx= 1.8 V, V_OUTx= 1.5 V

图 17. Line Transient

图 18. Current Limit Foldback

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Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

V_ENx

1 V/div

V_EN1

1 V/div

V_OUTx

200 mV/div

V_OUT1

200 mV/div

V_PGx

200mV/div

V_PG1

200 mV/div

Time (50 ms/div)

V_INx= 1.4 V

Time (500 ms/div)

V_INx= 1.4 V

图 19. Start-Up (SS_CTRLx = GND, C_NR/SSx= 0 nF)

图 20. Start-Up (SS_CTRLx = GND, C_NR/SSx= 10 nF)

V_EN1

1 V/div

V_OUT1

1 V/div

200 mV/div

V_PG1

200 mV/div

V_PG1

200 mV/div

Time (50 ms/div)

Time (2 ms/div)

V_INx= 1.4 V

图 22. Start-Up (SS_CTRLx = V_INx, C_NR/SSx= 1 µF)

图 21. Start-Up (SS_CTRLx = V_INx, C_NR/SSx= 10 nF)

180

550

-40èC

500

160

140

120

100

0èC

25èC

85èC

125èC

25èC

450

85èC

125èC

400

350

300

250

200

150

100

100 200 300 400 500 600 700 800 900 1000

Load Current (mA)

1.5

2.5

3.5

4.5

5.5

6.5

Input Voltage (V)

V_INx= 5.5 V

I_OUTx= 1 A

图 23. Dropout Voltage vs Output Current

图 24. Dropout Voltage vs Input Voltage

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Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

0.5

0.25

0.5

0.25

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.25

-0.5

-0.25

-0.5

100 200 300 400 500 600 700 800 900 1000

Output Current (mA)

1.5

2.5

3.5

4.5

5.5

6.5

Input Voltage (V)

V_INx= 1.4 V

I_OUTx= 50 mA

图 25. Load Regulation (V_OUTx= 0.8 V)

图 26. Line Regulation (V_OUTx= 0.8 V)

0.5

0.25

0.5

0.25

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.25

-0.5

-0.25

-0.5

100 200 300 400 500 600 700 800 900 1000

Output Current (mA)

3.5

4.5

5.5

6.5

Input Voltage (V)

V_INx= 3.8 V

I_OUTx= 5 mA

图 27. Load Regulation (V_OUTx= 3.3 V)

图 28. Line Regulation (V_OUTx= 3.3 V)

0.5

-40èC

0èC

25èC

85èC

125èC

0èC

25èC

85èC

125èC

0.25

-0.25

-0.5

1.5

2.5

3.5

4.5

5.5

6.5

100 200 300 400 500 600 700 800 900 1000

Output Current (mA)

Input Voltage (V)

D001

V_INx= 5.5 V

Both channels

图 29. Load Regulation (V_OUTx= 5.0 V)

图 30. Shutdown Current vs Input Voltage

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Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

5.2

4.5

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

4.8

4.6

4.4

4.2

3.8

3.6

3.4

3.2

3.5

100 200 300 400 500 600 700 800 900 1000

0.5

1.5

2.5

3.5

4.5

5.5

6.5

Output Current (mA)

Input Voltage (V)

D001

V_INx= 1.4 V, both channels enabled

Both channels enabled

图 31. Ground Current vs Output Current

图 32. Ground Current vs Input Voltage

500

400

300

200

100

500

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

400

300

200

100

0.5

1.5

2.5

0.5

1.5

2.5

PG Current (mA)

图 33. PG Low Level vs PG Current (V_INx= 1.4 V)

图 34. PG Low Level vs PG Current (V_INx= 6.5 V)

90.6

90.2

89.8

89.4

0.03

0.025

0.02

0.015

0.01

0.005

Rising Threshold

Falling Threshold

88.6

88.2

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

V_INx= 6.5 V

V_INx= V_PGx= 6.5 V

图 35. PG Threshold vs Temperature

图 36. PG Leakage Current vs Temperature

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Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_INx< 6.5 V, V_INx≥ V_OUTx(TARGET)+ 0.3 V, V_OUTx= 0.8 V, SS_CTRLx = GND, I_OUTx= 5 mA, V_ENx= 1.1 V,

C_OUTx= 10 μF, C_NR/SSx= 0 nF, C_FFx= 0 nF, PGx pin pulled up to V_OUTxwith 100 kΩ, and SS_CTRLx = GND (unless otherwise

noted)

115

110

105

100

7.5

VIN = 6.5 V

VIN = 1.4 V

6.5

5.5

VIN = 6.5 V

VIN = 1.4 V

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

图 37. Soft-Start Current vs Temperature

图 38. Soft-Start Current vs Temperature

(SS_CTRLx = GND)

(SS_CTRLx = V_INx

)

900

850

800

750

700

650

600

550

900

850

800

750

700

650

600

550

Enable Rising

Enable Falling

Enable Rising

Enable Falling

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

图 39. Enable Threshold vs Temperature (V_INx= 1.4 V)

图 40. Enable Threshold vs Temperature (V_INx= 6.5 V)

1.4

Rising Threshold

Falling Threshold

1.35

1.3

1.25

1.2

1.15

1.1

1.05

0.95

0.9

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

图 41. Input UVLO Threshold vs Temperature

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7 Detailed Description

7.1 Overview

The TPS7A88 is a dual-channel, low-noise, high PSRR, low dropout (LDO) regulator capable of sourcing a 1-A

load with only 200 mV of maximum dropout. The TPS7A88 can operate down to a 1.4-V input voltage and a 0.8-

V output voltage. This combination of low-noise, high PSRR, and low dropout voltage makes the device an ideal

LDO to power a multitude of loads from noise-sensitive communication components in high-speed

communications applications to high-end microprocessors or field-programmable gate arrays (FPGAs).

As shown in the Functional Block Diagram section, each linear regulator features a low-noise, 0.8-V internal

reference that can be filtered externally to obtain even lower output noise. The internal protection circuitry (such

as the undervoltage lockout) prevents the device from turning on before the input is high enough to ensure

accurate regulation. Foldback current limiting is also included that allows each output to source the rated output

current when the output voltage is in regulation but reduce the allowable output current during short-circuit

conditions. The internal power-good detection circuit allows users to sequence down-stream supplies and be

alerted if the output voltage is below a regulation threshold.

7.2 Functional Block Diagram

Current

Limit

IN1

OUT1

Charge

Pump

Active

Discharge

0.8-V

V_REF

Error

Amp

Softstart

Control

I_NR/SSx

SS_CTRL1

NR/SS1

FB1

PG1

0.89 x V_REF

UVLO

Internal

Enable

Control

Thermal

Shutdown

EN1

IN2

Current

Limit

OUT2

Charge

Pump

Active

Discharge

0.8-V

V_REF

Error

Amp

Softstart

Control

I_NR/SSx

SS_CTRL2

NR/SS2

FB2

PG2

0.89 x V_REF

UVLO

Internal

Enable

Control

Thermal

Shutdown

EN2

GND

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7.3 Feature Description

7.3.1 Independent Dual-Channel LDO

The TPS7A88 consists of two completely independent linear regulators that can be used to replace two stand-

alone LDOs, or to provide channel isolation for the same voltage input and outputs. Regardless of the

implementation, the TPS7A88 provides excellent regulation to 1% accuracy, excellent dropout voltage, and high

output current. If desired, the LDOs can be cascaded to achieve even higher PSRR by connecting the output of

one channel to the input of the other channel.

Both channels of the TPS7A88 have an on-board charge pump that is always running to power the error

amplifier to drive the gate of the n-channel pass-FET higher than the input voltage. The integrated charge pump

allows the low dropout characteristics of the device to be maintained over the entire input voltage range of 1.4 V

to 6.5 V.

7.3.2 Output Enable

The enable pins for the TPS7A88 are both active high. The output voltage for each channel is enabled when the

corresponding enable pin voltage is greater than V_IH(ENx)and disabled with the enable pin voltage is less than

V_IL(ENx). If control of the output voltage with the enable pin is not needed, then connect the enable pin to the

corresponding input.

The TPS7A88 has an internal pulldown MOSFET that connects a 250-Ω resistor to ground when the device is

disabled to actively discharge the output voltage.

7.3.3 Dropout Voltage (V_DO

)

Dropout voltage (V_DO) is defined as the V_INx– V_OUTxvoltage at the rated current (I_RATED), where the main current

pass-FET is fully on and in the ohmic region of operation. V_DOindirectly specifies a minimum input voltage above

the nominal programmed output voltage at which the output voltage is expected to remain in regulation. If the

input falls below the nominal output regulation, then the output follows the input.

Dropout voltage is determined by the R_DS(ON)of the main pass-FET. Therefore, if the LDO operates below the

rated current, then the V_DOfor that current scales accordingly. The R_DS(ON)for the TPS7A88 can be calculated

using 公式 1:

V_DO

R_DS(ON)

I_RATED

(1)

7.3.4 Output Voltage Accuracy

Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal

output voltage stated as a percent. The TPS7A88 features an output voltage accuracy of 1% that includes the

errors introduced by the internal reference, load regulation, and line regulation variance across the full range of

rated load and line operating conditions over temperature, as specified by the Electrical Characteristics table.

Output voltage accuracy also accounts for all variations between manufacturing lots.

7.3.5 Low Output Noise

Each channel of the TPS7A88 includes a low-noise reference ensuring minimal output noise in normal operation.

Adding a capacitor to the NR/SSx pins provides additional filtering to the internal reference, thus reducing the

total output noise. The maximum value recommended for the NR/SSx capacitor is 1 µF. Further output noise

reduction can be achieved by adding an external C_FFbetween the SNS pin and the FBx pin.

7.3.6 Internal Protection Circuitry

7.3.6.1 Undervoltage Lockout (UVLO)

Each input of the TPS7A88 has an independent undervoltage lockout (UVLO) circuit that monitors the input

voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from

turning off if the input droops during turn on, the UVLO has approximately 285 mV of hysteresis.

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Feature Description (接下页)

7.3.6.2 Internal Current Limit (I_CL

)

The internal current limit circuit is used to protect the LDO against transient high-load current faults or shorting

events. The LDO is not designed to operate in current limit under steady-state conditions. During an overcurrent

event where the output voltage is pulled 10% below the regulated output voltage, the LDO sources a constant

current as specified in the Electrical Characteristics table. When the output voltage falls, the amount of output

current is reduced to better protect the device. During a hard short-circuit event, the current is reduced to

approximately 1.25 A. See 图 18 in the Typical Characteristics section for more information about the current limit

foldback behavior. Note also that when a current-limit event occurs, the LDO begins to heat up because of the

increase in power dissipation. The increase in heat can trigger the integrated thermal shutdown protection circuit.

7.3.6.3 Thermal Protection

Each LDO channel of the TPS7A88 contains a thermal shutdown protection circuit to turn off the output current

when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature

(T_J) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO again

resets (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor

die is fairly short, and thus the output turns on and off at a high rate when thermal shutdown is reached until

power dissipation is reduced. Because there are two independent thermal shutdown circuits, one channel can be

in thermal shutdown when the other channel is not.

The internal protection circuitry of the TPS7A88 is designed to protect against thermal overload conditions. The

circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A88 into thermal shutdown

degrades device reliability.

For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a

given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-

case load and highest input voltage conditions. For good reliability, thermal shutdown must occur at least 40°C

above the maximum expected ambient temperature condition for the application. This configuration produces a

worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

7.3.7 Output Soft-Start Control

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after the ENx and UVLO

thresholds are exceeded. The noise-reduction capacitor (C_NR/SSx) serves a dual purpose of both governing output

noise reduction and programming the soft-start ramp during turn-on. Larger values for the noise-reduction

capacitors decrease the noise but also result in a slower output turn-on ramp rate.

The TPS7A88 features an SS_CTRLx pin for each output. When this pin connected to INx the charging current

for the NR/SSx pin is increased to 100 µA (typ). The higher current allows use of a much larger noise-reduction

capacitor and still maintains a faster soft-start time. When the SS_CTRLx pin is connected to GND the charging

current is reduced to 6.2 µA (typ), allowing a slower startup ramp rate. If a noise-reduction capacitor is not used

on the NR/SSx pin, tying the SS_CTRLx pin to VIN can result in output voltage overshoot of approximately

10%. Any overshoot is minimized by connecting the SS_CTRLx pin to GND or using a capacitor on the NR/SSx

pin. To achieve the lowest possible output noise, values for the noise-reduction capacitor can be as high as

10 µF. In this case, if a faster soft-start time is needed, connect the SS_CTRLx pin to VDD.

7.3.8 Power-Good Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.

When the feedback pin voltage falls below the PG threshold voltage (V_IT(PG)), the PGx pin open-drain output

engages and pulls the PGx pin close to GND. When the feedback voltage exceeds the V_IT(PG)threshold by an

amount greater than V_HYS(PG), the PGx pin becomes high impedance. By connecting a pullup resistor to an

external supply, any downstream device can receive power good as a logic signal that can be used for

sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving

device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external reset device

such as the TPS3780 is also recommended in applications where high accuracy is needed or in applications

where microprocessor resets are needed.

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Feature Description (接下页)

When employing the feed-forward capacitor (C_FF), the turn-on time constant for the LDO is increased whereas

the power-good output time constant stays the same, resulting in an invalid status of the LDO. To avoid this

issue and to receive a valid PG output, ensure that the time constant of both the LDO and the power-good output

are matching by adding a capacitor in parallel with the power-good pullup resistor. The state of PG is only valid

when the device is operating above the minimum input voltage of the device and power good is asserted

regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO

hysteresis. When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to

keep the open-drain, power-good device turned on and the power-good output is falsely pulled high. Connecting

the power-good pullup resistor to the output voltage can help minimize this effect.

7.4 Device Functional Modes

表 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.

表 1. Device Functional Modes Comparison

PARAMETER

OPERATING MODE

V_INx

ENx

I_OUTx

I_OUTx< I_CL

—

T_J

Normal⁽¹⁾

Dropout⁽¹⁾

Disabled⁽²⁾

V_INx> V_OUTx(nom)+ V_DO

V_INx< V_OUTx(nom)+ V_DO

UVLO

V_ENx> V_IH(ENx)

V_ENx< V_IL(ENx)

T_J< T_sd

T_J> T_sd

(1) All table conditions must be met.

(2) The device is disabled when any condition is met.

7.4.1 Normal Operation

The device regulates to the nominal output voltage when all of the following conditions are met.

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUTx(nom)+ V_DO)

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

below the enable falling threshold

•

The output current is less than the current limit (I_OUTx< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_sd)

)

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks

the input voltage. During this mode, the transient performance of the device becomes significantly degraded

because the pass device is in a triode state and no longer controls the current through the LDO. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_INx< V_OUTx(NOM)+ V_DO

right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible

when the control loop is out of balance. During the normal time required for the device to regain regulation, V_INx

V_OUTx(NOM)+ V_DO, V_OUTxovershoots if the input voltage slew rate is 0.1 V/µs or faster.

≥

7.4.3 Disabled

The outputs of the TPS7A88 can be shutdown by forcing the enable pins below 0.4 V. When disabled, the pass

device is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an

internal switch from the output to ground.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A88 is a linear voltage regulator operating from 1.4 V to 6.5 V on the input and regulates voltages

between 0.8 V to 5.0 V within 1% accuracy and a 1-A maximum output current. Efficiency is defined by the ratio

of output voltage to input voltage because the TPS7A88 is a linear voltage regulator. To achieve high efficiency,

the dropout voltage (V_INx– V_OUTx) must be as small as possible, thus requiring a very low dropout LDO.

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Adjustable Outputs

The output voltages of the TPS7A8801 can be adjusted from 0.8 V to 5.0 V by using resistor divider networks as

shown in 图 42.

TPS7A8801

V_IN1

IN1

V_OUT1

C_OUT1

OUT1

FB1

R₁

C_IN1

EN1

SS_CTRL1

R₂

NR/SS1

C_NR/SS1

PG1

V_IN2

V_OUT2

C_OUT2

OUT2

IN2

R₃

C_IN2

EN2

FB2

SS_CTRL2

NR/SS2

R₄

C_NR/SS2

PG2

GND

图 42. Adjustable Operation

R₁, R₃and R₂, R₄can be calculated for any output voltage range using 公式 2. This resistive network must

provide a current equal to or greater than 5 μA for optimum noise performance.

V_REF(max)

R₂, R₄

≈

∆

’

V_OUTx

V_REF

R₁, R₃= R₂, R₄

-1 , where

> 5 mA

◊

(2)

If greater voltage accuracy is required, take into account the output voltage offset contributions resulting from the

feedback pin current (I_FB) and use 0.1% tolerance resistors.

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Application Information (接下页)

表 2 shows the resistor combination required to achieve a few of the most common rails using commercially-

available, 0.1%-tolerance resistors to maximize nominal voltage accuracy and also abiding to the formula given

in 公式 2.

表 2. Recommended Feedback-Resistor Values

FEEDBACK RESISTOR VALUES⁽¹⁾

V_OUTx(TARGET)

(V)

R₁, R₃(kΩ)

Short

2.55

R₂, R₄(kΩ)

Open

10.2

11.8

10.7

1.5

0.8

1.00

1.20

1.50

1.80

1.90

2.50

3.00

3.30

5.00

5.9

9.31

1.87

15.8

11.5

1.15

2.43

3.16

3.57

10.5

(1) R₁, R₃are connected from OUTx to FBx; R₂, R₄are connected from FBx to GND; see 图 42.

8.1.2 Start-Up

8.1.2.1 Enable (ENx) and Undervoltage Lockout (UVLO)

The TPS7A88 only turns on when ENx and UVLO are above their respective voltage thresholds. Each input to

the TPS7A88 has an independent UVLO circuit that monitors the input voltage to allow a controlled and

consistent turn on and off. To prevent the device from turning off if the input droops during turn on, the UVLO has

approximately 285 mV of hysteresis. The ENx signal for each output allows independent logic-level turn-on and

shutdown of the LDO when the input voltage is present. It is recommended to connect ENx directly to INx if

independent turn-on is not needed.

8.1.2.2 Noise-Reduction and Soft-Start Capacitor (C_NR/SSx

)

Each output of the TPS7A88 features a programmable, monotonic, voltage-controlled soft-start that is set with an

external capacitor (C_NR/SSx). This soft-start eliminates power-up initialization problems when powering FPGAs,

digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces

peak inrush current during start-up, thus minimizing start-up transients to the input power bus.

To achieve a linear and monotonic start-up, the TPS7A88 error amplifier tracks the voltage ramp of the external

soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-

start charging current (I_NR/SSx), the soft-start capacitance (C_NR/SSx), and the internal reference (V_REF). The

approximate soft-start ramp time (t_SSx) can be calculated with 公式 3:

t_SSx= (V_REF× C_NR/SSx) / I_NR/SSx

(3)

Note that the value for I_NR/SSxis determined by the state of the SS_CTRLx pin. When the SS_CTRLx pin is

connected to GND, the typical value for the I_NR/SSxcurrent is 6.2 µA. Connecting the SS_CTRLx pin to INx

increases the typical soft-start charging current to 100 µA. The larger charging current for I_NR/SSxis useful if

smaller start-up ramp times are needed or when using larger noise reduction capacitors. Values for the soft-start

charging currents are provided in the Electrical Characteristics table.

For low-noise applications, the noise-reduction capacitor (connected to the NR/SSx pin of the LDO) forms an RC

filter for filtering out noise that is ordinarily amplified by the control loop and appears on the output voltage. For

low-noise applications, a 10-nF to 1-µF C_NR/SSxis recommended. Larger values for C_NR/SSxcan be used;

however, above 1-µF there is little benefit in lowering the output voltage noise.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

8.1.2.3 Soft-Start and Inrush Current

Soft-start refers to the gradual ramp-up characteristic of the output voltage after the ENx and UVLO thresholds

are exceeded. The noise-reduction capacitor serves a dual purpose of both governing output noise reduction and

programming the soft-start ramp during turn-on.

Inrush current is defined as the current into the LDO at the INx pin during start-up. Inrush current then consists

primarily of the sum of load and current used to charge the output capacitor. This current is difficult to measure

because the input capacitor must be removed, which is not recommended. However, the inrush current can be

estimated by 公式 4:

≈

∆

’

◊

_OUTxì dV_OUTx(t)

V_OUTx(t)

R_LOADx

≈

’

I_OUTx(t) =

∆

◊

where:

•

V_OUTx(t) is the instantaneous output voltage of the turn-on ramp

dV_OUTx(t) / dt is the slope of the V_OUTxramp and

R_LOADis the resistive load impedance

(4)

8.1.3 Capacitor Recommendation

The TPS7A88 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

inputs, outputs, and noise-reduction pins. Multilayer ceramic capacitors have become the industry standard for

these types of applications and are recommended, but must be used with good understanding of their limitations.

Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good

capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged precisely

because the capacitance varies so widely. In all cases, ceramic capacitors vary a great deal with operating

voltage and temperature and the design engineer must be aware of these characteristics. As a rule of thumb,

ceramic capacitors are recommended to be derated by 50%. To compensate for this derating, increase the

capacitor value by 100%. The input and output capacitors recommended herein account for a capacitance

derating of 50%.

Attention must be given to the input capacitance to minimize transient input droop during load current steps. An

input capacitor of 10 µF or greater provides the desired effect and does not affect stability. Note that simply using

large ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor (in

combination with the wire-lead inductance) creates a high-Q peaking effect during transients. For example, a

5-nH lead inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of 712 kHz that is

near the edge of the open-loop bandwidth. Short, well-designed interconnect traces to the upstream supply

minimize this effect without adding damping. Damping of unwanted ringing can be accomplished by using a

tantalum capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.

8.1.3.1 Input and Output Capacitor Requirements (C_INxand C_OUTx

)

The TPS7A88 is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the

input and output. Locate the input and output capacitors as near as practical to the respective input and output

pins to minimize the trace inductance from the capacitor to the device.

8.1.3.2 Feed-Forward Capacitor (C_FFx

)

Although a feed-forward capacitor (C_FFx), from the FBx pin to the OUTx pin is not required to achieve stability, a

10-nF, feed-forward capacitor optimizes the noise and PSRR performance. A higher capacitance C_FFcan be

used; however, the startup time is longer and the power-good signal can incorrectly indicate that the output

voltage has settled. For a detailed description, see application report Pros and Cons of Using a Feed-Forward

Capacitor with a Low Dropout Regulator, SBVA042.

8.1.4 AC Performance

LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output

isolation, load step transient response, and output noise. These metrics are primarily a function of open-loop gain

and bandwidth, phase margin, and reference noise.

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

8.1.4.1 Power-Supply Ripple Rejection (PSRR)

PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc

output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Even though

PSRR is a loss in noise signal amplitude, the PSRR curves in the Electrical Characteristics table are shown as

positive values in decibels (dB) for convenience. 公式 5 gives the PSRR calculation as a function of frequency

where input noise voltage [V_S(INx)(f)] and output noise voltage [V_S(OUTx)(f)] are understood to be purely sinusoidal

signals.

≈

∆

’

◊

_INx(f)

PSRR (dB) = 20 Log₁₀

V_OUTx(f)

(5)

Noise that couples from the input to the internal reference voltage for the control loop is also a primary

contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise-

reduction capacitor at the NR/SSx pin of the LDO in combination with an internal filter resistor for improved

PSRR at lower frequencies.

The LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply

voltages that exhibit ultra-low noise and ripple to power-sensitive system components. This usage is especially

true for the TPS7A88.

The TPS7A88 features an innovative circuit to boost the PSRR between 200 kHz and 1 MKz; see 图 4. To

achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the

100-kHz to 1-MHz band is recommended.

8.1.4.2 Channel-to-Channel Output Isolation and Crosstalk

Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting

the other output. This attenuation appears in load transient tests on the other output; however, to numerically

quantify the rejection, the output channel isolation is expressed in decibels (dB). In order to characterize the

output channel isolation both ac disturbances in output voltages are understood to be purely sinusoidal signals.

Output isolation performance is a strong function of the PCB layout. See the Layout section on how to best

optimize the isolation performance.

8.1.4.3 Load-Step Transient Response

The load-step transient response is the output voltage response by the LDO to a step change in load current,

whereby output voltage regulation is maintained. The depth of charge depletion immediately after the load step is

directly proportional to the amount of output capacitance. However, larger output capacitances function to

decrease any voltage dip or peak occurring during a load step but also decrease the control-loop bandwidth,

thereby slowing response.

The LDO cannot sink charge, therefore the control loop must turn off the main pass-FET to wait for the charge to

deplete when the output load is removed.

8.1.4.4 Noise

The TPS7A88 is designed for system applications where minimizing noise on the power-supply rail is critical to

system performance. This scenario is the case for phase-locked loop (PLL)-based clocking circuits where

minimum phase noise is all important, or in test and measurement systems where even small power-supply

noise fluctuations can distort instantaneous measurement accuracy.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This

noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,

thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower

frequencies as a function of 1/f).

See the marketing white paper, How to Measure LDO Noise, SLYY076 for further details.

Noise is affected by the choice of noise reduction capacitor C_NR/SSxand feedforward capacitor C_FFx.. See the

Noise-Reduction and Soft-Start Capacitor (C_NR/SSx) and Feed-Forward Capacitor (C_FFx) sections for additional

design information.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

8.1.5 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. P_Dcan be calculated using 公式 6:

P_D= (V_OUTx– V_INx) × I_OUTx

(6)

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper

selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output

regulation to be obtained.

The primary heat conduction path for the RTJ package is through the thermal pad to the PCB. Solder the thermal

pad to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to

any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(θ_JA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to 公式 7.

T_J= T_A+ (q_JA´ P_D)

(7)

Unfortunately, the thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The θ_JArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area and is only used as a relative measure of package thermal performance.

8.1.6 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are given in the Thermal Information table and are used in accordance with 公式 8.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in 公式 6

T_Tis the temperature at the center-top of the device package and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(8)

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

8.2 Typical Application

This section discusses the implementation of the TPS7A88 to regulate from a common input voltage to two

output voltages of the same value. This is a common application where two noise-sensitive loads must have the

same supply voltage but have high channel-to-channel isolation. The schematic for this application circuit is

provided in 图 43.

TPS7A8801

1.8 V

IN1

OUT1

FB1

1.2 V

C_OUT1

10 ꢀF

C_IN1

10 mF

R₁5.9 kW

EN1

SS_CTRL1

NR/SS1

C_FF110 nF

V_OUT1

R₂

11.8 kW

C_NR/SS1

0.1 mF

R_PG1

20 kW

PG1

IN2

OUT2

FB2

1.2 V

C_IN2

10 mF

R₃5.9 kW

C_OUT2

EN2

10 ꢀF

SS_CTRL2

NR/SS2

C_FF210 nF

V_OUT2

R₄

11.8 kW

C_NR/SS2

R_PG2

0.1 mF

20 kW

PG2

GND

图 43. Application Example

8.2.1 Design Requirements

For the design example shown in 图 43, use the parameters listed in 表 3 as the input parameters.

表 3. Design Parameters

PARAMETER

DESIGN REQUIREMENT

1.8 V, ±3%, provided by the dc-dc converter switching at 750 kHz

55°C

Input voltages (V_IN1and V_IN2

)

Maximum ambient operating temperature

Output voltages (V_OUT1and VOUT2)

1.2 V, ±1%, output voltages are isolated

1.0 A (maximum), 10 mA (minimum)

Isolation greater than 50 dB at 100 kHz

< 5 µV_RMS, bandwidth = 10 Hz to 100 kHz

> 40 dB

Output currents (I_OUT2and I_OUT2

Channel-to-channel isolation

RMS noise

)

PSRR at 750 kHz

Startup time

< 5 ms

8.2.2 Detailed Design Procedure

The output voltages can be set to 1.2 V by selecting the correct values for R₁, R₃and R₂, R₄; see 公式 2.

Input and output capacitors are selected in accordance with the Capacitor Recommendation section. Ceramic

capacitances of 10 µF for both inputs and outputs are selected.

To satisfy the required startup time (t_SSx) and still maintain low-noise performance, a 0.1-µF C_NR/SSxis selected

for both channels with SS_CTRL1 and SS_CTRL2 connected to V_IN1and V_IN2, respectively. This value is

calculated with 公式 9.

t_SSx= (V_REF× C_NR/SSx) / I_NR/SSx

(9)

With a 1.0-A maximum load, the internal power dissipation is 600 mW per channel or 1.2 W total, which

corresponds to a 40°C junction temperature rise. With an 55°C maximum ambient temperature, the junction

temperature is at 95°C. To minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

Channel-to-channel isolation depends greatly on the layout of the design. To minimize crosstalk between the

outputs, keep the output capacitor grounds on separate sides of the design. See the Layout section for an

example of how to layout the TPS7A88 to achieve best PSRR, channel-to-channel isolation, and noise.

8.2.3 Application Curves

110

100

V_INx= 1.8 V

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

Frequency (Hz)

图 44. Power-Supply Rejection

图 45. Channel-to-Channel Isolation

0.5

V_INx= 1.8 V, V_RMS= 4.26 mV

0.3

0.2

0.1

0.05

0.03

0.02

0.01

0.005

0.003

0.002

0.001

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

图 46. Output Noise

8.3 Do's and Don'ts

表 4 lists the recommended guidelines for the TPS7A88.

表 4. Recommended Guidelines for Designing with the TPS7A88

DO'S

DON'TS

Do place at least one 10-µF ceramic capacitor as close as possible

to each output of the device.

Do not place either output capacitor more than 10 mm away from the

regulator.

Do connect a 10-μF or larger low equivalent series resistance (ESR)

capacitor across each input pin to GND.

Do not exceed the absolute maximum ratings.

Do not leave the enable pins floating.

Do follow the recommended layout in 图 47

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

9 Power Supply Recommendations

Both inputs of the TPS7A88 are designed to operate from an input voltage range between 1.4 V and 6.5 V. The

input voltage range must provide adequate headroom in order for the device to have a regulated output. This

input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help

improve the output noise performance.

10 Layout

10.1 Layout Guidelines

General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit

board and as near as practical to the respective LDO pin connections. Place ground return connections to the

input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide,

component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly

discouraged and negatively affects system performance.

10.1.1 Board Layout

To maximize the ac performance of the TPS7A88, following the layout example illustrated in 图 47 is

recommended. This layout isolates the analog ground (AGND) from the noisy power ground. Components that

must be connected to the quiet analog ground are the noise reduction capacitors (C_NR/SSx) and the lower

feedback resistors (R₂, R₄). These components must have a separate connection back to the power pad of the

device. To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite

sides of the layout and only connect back to the device at opposite sides of the thermal pad. TI recommends

connecting the GND pins directly to the thermal pad and not to any external plane.

To maximize the output voltage accuracy, the connection from each output voltage back to top output divider

resistors (R₁and R₃) must be made as close as possible to the load. This method of connecting the feedback

trace eliminates the voltage drop from the device output to the load.

To improve thermal performance, a 3 × 3 thermal via array must connect the thermal pad to internal ground

planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating

temperature of the device.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

10.2 Layout Example

Power Ground

R_PG1

AGND

R₂

PGOOD1

R₁

C_NR/SS1

C_FF1

V_OUT1SENSE

on Bottom

Layer

C_IN1

C_OUT1

IN1

OUT1

V_IN1

V_OUT1

OUT1

GND

IN2

OUT2

V_OUT2

V_IN2

C_IN2

C_OUT2

V_OUT2SENSE

on Bottom

Layer

C_FF2

C_NR/SS2

R₃

PGOOD2

R₄

AGND

R_PG2

Circles denote PCB via connections.

Power Ground

图 47. TPS7A88 Example Layout

TPS7A88

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

评估模块 (EVM) 可与 TPS7A88 配套使用，帮助评估初始电路性能。有关此固定装置的相关摘要信息，请参见表

4。

表 5. 设计套件与评估模块⁽¹⁾

名称

器件号

TPS7A88 低压降稳压器评估模块

TPS7A88EVM-776

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。

在德州仪器 (TI) 网站 (www.ti.com) 上，可通过 TPS7A88 产品文件夹获取 EVM。

11.1.1.2 Spice 模型

分析模拟电路和系统的性能时，使用 spice 模型对电路性能进行计算机仿真非常有用。可以从 TPS7A88 产品文件

夹中的仿真模型下获取 TPS7A88 的 spice 模型。

11.1.2 器件命名规则

表 6. 订购信息⁽¹⁾

产品

说明

YYY 为封装标识符。

TPS7A88xxYYYZ

XX 表示输出电压。01 为可调输出版本。

Z 为封装数量。

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。

11.2 文档支持

11.2.1 相关文档ꢀ

《TPS3780 数据表》，SBVS250

《TPS7A88EVM 用户指南》，SBVU027

使用前馈电容器和低压降稳压器的优缺点， SBVA042

《如何测量 LDO 噪声》，SLYY076

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

TPS7A88

www.ti.com.cn

ZHCSEP2A –NOVEMBER 2015–REVISED NOVEMBER 2015

11.4 商标

DSP, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A8801RTJR

TPS7A8801RTJT

ACTIVE

QFN

RTJ

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

TPS7A88

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2021

OTHER QUALIFIED VERSIONS OF TPS7A88 :

Automotive : TPS7A88-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

GENERIC PACKAGE VIEW

RTJ 20

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224842/A

www.ti.com

DATA BOOK

PACKAGE OUTLINE

LEADFRAME EXAMPLE

4222370

DRAFTSMAN:

DATE:

H. DENG

09/12/2016

DESIGNER:

CHECKER:

ENGINEER:

APPROVED:

RELEASED:

CODE IDENTITY

NUMBER

H. DENG

01295

SEMICONDUCTOR OPERATIONS

V. PAKU & T. LEQUANG

T. TANG

ePOD, RTJ0020D / WQFN,

20 PIN, 0.5 MM PITCH

09/12/2016

10/06/2016

10/24/2016

E. REY & D. CHIN

WDM

SCALE

SIZE

REV

PAGE

TEMPLATE INFO:

4219125

15X

04/07/2016

EDGE# 4218519

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

RTJ0020D

4.1

3.9

PIN 1 INDEX AREA

4.1

3.9

DIM A

OPT 1

(0.1)

OPT 2

(0.2)

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

16X 0.5

(A) TYP

EXPOSED

THERMAL PAD

SYMM

ꢀꢁꢂꢃꢁꢄ

4X 2

0.5

0.3

20X

PIN 1 ID

(OPTIONAL)

SYMM

0.29

0.19

0.1

20X

C A B

0.05

4219125 / A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

RTJ0020D

PLASTIC QUAD FLATPACK - NO LEAD

2.7)

SYMM

20X (0.6)

20X (0.24)

(1.1)

TYP

SYMM

(3.8)

(0.5)

TYP

ꢅꢃꢁꢀꢆꢇ7<3

VIA

(R0.05)

TYP

(3.8)

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219125 / A 10/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their

locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

RTJ0020D

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.69)

TYP

20X (0.6)

20X (0.24)

(0.69)

TYP

SYMM

(3.8)

(0.5)

TYP

(R0.05)

TYP

4X ( 1.19)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

4219125 / A 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

R E V I S I O N S

REV

DESCRIPTION

ECR

DATE

ENGINEER / DRAFTSMAN

T. TANG / H. DENG

RELEASE NEW DRAWING

2160736

10/24/2016

SCALE

SIZE

REV

PAGE

4219125

5 _OF5

NTS

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