TPS7B4253QDDARQ1 [TI]
汽车类 300mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DDA | 8 | -40 to 125;
| 型号： | TPS7B4253QDDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 300mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DDA | 8 | -40 to 125 电池 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总35页 (文件大小：2400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7B4253-Q1
ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
TPS7B4253-Q1 具有 4mV 跟踪容差的 300mA 40V 低压降电压跟踪 LDO
1 特性
3 说明
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
对于汽车非板载传感器和小电流非板载模块，电源通过
一条长电缆连接主板。 在这类情况下，电源器件需要
为非板载负载提供保护，防止板载组件在接地短路或者
电缆破损造成的电池短路期间受损。 非板载传感器需
要与板载组件采用相同的电源，以确保数据采集的高精
度。
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 3A
器件组件充电模式 (CDM) ESD 分类等级 C6
TPS7B4253-Q1 器件设计用于具有 45V 负载突降问题
的汽车类应用。 该器件可用作一个跟踪低压降 (LDO)
稳压器或者电压跟踪器，通过板载主电源为非板载传感
器构建一个封闭电源环路。 该器件的输出由 ADJ 引脚
的基准电压精准调节。
•
•
–40V 至 45V 宽输入电压范围（最大值）
可调节输出电压范围：
–
–
1.5V 至 40V (HTSSOP)
2V 至 40 V (SO PowerPAD™)
•
•
•
•
300mA 输出电流能力
为了给非板载模块提供精确的电源，该器件的 ADJ 与
FB 引脚间在运行温度范围内具有 4mV 超低跟踪容
差。 PMOS 背靠背拓扑消除了反极性条件下对外部二
极管的需求。 TPS7B4253-Q1 器件还包括热关断、感
性钳位、过载和电池短路保护，防止板载组件在极限条
件下受损。
±4mV 超低输出跟踪容差
320mV 低压降 (IOUT = 200mA 时)
分别用于使能和跟踪输入的单独引脚（仅限
HTSSOP）
•
低静态电流 (IQ)：
–
–
< 4µA（EN = 低电平时）
轻负载时典型值为 60µA
器件信息(1)
•
超宽等效串联电阻 (ESR) 范围。
器件型号
封装
封装尺寸（标称值）
4.89mm × 3.90mm
6.50mm x 4.40mm
–
与 10µF 至 500µF 范围内的陶瓷输出电容
SO PowerPAD (8)
HTSSOP (20)
TPS7B4253-Q1
（ESR 为 1mΩ 至 20Ω）搭配使用时可保持稳
定
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
•
反极性保护
限流和热关断保护
对接地和电源的输出短路保护
输出引脚感性钳位
提供以下封装：
典型应用电路原理图
Automotive
Battery
Main Board
DC-DC or LDO
–
–
8 引脚小外形尺寸 (SO) PowerPAD 封装
V
IN
OUT
Long Cable
20 引脚散热薄型小外形尺寸 (HTSSOP) 封装
ADJ
OUT
TPS7B4253-Q1
GND
Off-Board
Sensor
2 应用
C
(OUT)
•
•
•
非板载传感器电源
MCU
ADC
高精度电压跟踪
非板载负载的电源开关
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCP3
TPS7B4253-Q1
ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 15
8
9
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
10.3 Power Dissipation and Thermal Considerations... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持................................................................ 22
11.2 文档支持................................................................ 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2015) to Revision A
Page
•
已更改 器件状态，从产品预览更改为量产数据....................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
TPS7B4253-Q1
www.ti.com.cn
ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
OUT
NC
NC
NC
NC
GND
NC
NC
NC
FB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IN
OUT
NC
1
2
3
4
8
7
6
5
IN
EN
NC
NC
NC
GND
NC
NC
NC
ADJ
NC
Thermal
Pad
GND
FB
GND
ADJ
Thermal
Pad
NC — No internal connection
NC — No internal connection
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
SO PowerPAD
HTSSOP
Connect the reference to this pin. A low signal disables the device and a high signal
enables the device. The reference voltage can be connected directly or by a voltage
divider for lower output voltages. To compensate for line influences, connect a
capacitor close to the device pins.
ADJ
5
11
I
This pin is the enable pin. The device goes to the STANDBY state when the enable
pin goes lower than the threshold value.
EN
FB
—
4
19
10
I
I
This pin is the feedback pin which can connect to the external resistor divider to
select the output voltage.
3
6
6
GND
IN
G
I
Ground reference
15
This pin is the device supply. To compensate for line influences, connect a
capacitor close to the device pins.
8
2
20
2
3
4
5
7
8
NC
9
NC
Not connected
12
13
14
16
17
18
7
1
Block to GND with a capacitor close to the device pins with respect to the
capacitance and ESR requirements listed in the Output Capacitor section.
OUT
1
O
Exposed thermal pad
—
Connect the thermal pad to the GND pin or leave it floating.
(1) I = input, O = output, G = ground, NC = no connect
Copyright © 2015, Texas Instruments Incorporated
3
TPS7B4253-Q1
ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–40
–40
–1
MAX
45
UNIT
Unregulated input voltage
Enable input voltage
IN(2)(3)
V
V
V
Enable input voltage(2)(3)
Regulated output voltage(2)(4)
45
Regulated output voltage
45
Voltage difference between the input and
output
IN – OUT
–40
45
V
Reference voltage
ADJ(2)(3)
FB(2)(3)
–0.3
–1
45
45
V
V
Feedback input voltage for the tracker
Reference voltage minus the input voltage ADJ – IN(5)
18
V
Operating junction temperature, TJ
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND pin.
(3) Absolute maximum voltage.
(4) An internal diode is connected between the OUT and GND pins with 600-mA DC current capability for inductive clamp protection.
(5) The ADJ voltage cannot be 18 V higher than the IN voltage, otherwise the device can be damaged.
6.2 ESD Ratings
VALUE
UNIT
NC pins
±2000
kV
Human body model (HBM), per AEC
Q100-002(1)
All pins except for NC
pins
V(ESD)
Electrostatic discharge
±4000
±1000
kV
kV
Charged device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
4
MAX
UNIT
VIN
Unregulated input voltage(2)
Enable input voltage
40
40
V
V
VEN
0
VADJ
VFB
Adjust and enable input voltage
Feedback input voltage for the tracker
Output voltage
Output capacitor requirements(3)
Output ESR requirements(4)
Operating junction temperature range
1.5
1.5
1.5
10
18
V
18
V
VOUT
C(OUT)
40
V
500
20
µF
Ω
0.001
–40
TJ
150
°C
(1) Within the functional range the device operates as described in the circuit description. The electrical characteristics are specified within
the conditions given in the related Electrical Characteristics table.
(2) VIN > VADJ + V(DROPOUT)
(3) The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%, when a resistor divider is
connected between the OUT and FB pins (the output voltage is higher than reference voltage), a 47-nF feedforward capacitor is
required to be connected between the OUT and FB pins for loop stability, and the ESR range of the output capacitor is required to be
from 0.001 to 10 Ω.
(4) Relevant ESR value at f = 10 kHz
4
Copyright © 2015, Texas Instruments Incorporated
TPS7B4253-Q1
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ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
6.4 Thermal Information
TPS7B4253-Q1
THERMAL METRIC(1)
DDA (SO PowerPAD)
PWP (HTSSOP)
UNIT
8 PINS
45.4
51.1
27.0
8.2
20 PINS
45.9
29.2
24.7
1.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
26.9
6.4
24.5
3.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 13.5 V, VADJ ≥ 1.5 V for HTSSOP, VADJ ≥ 2 V for SO PowerPAD, VEN ≥ 2 V, TJ = –40ºC to 150ºC unless otherwise
stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.65
2.8
UNIT
V
VIN rising
VIN falling
VI(UVLO)
IN undervoltage detection
V
IOUT = 100 µA to 300 mA, VIN = 4 to 40 V
VADJ < VIN – 1 V
1.5 V < VADJ < 18 V for HTSSOP
2 V < VADJ < 18 V for SO PowerPAD
ΔVO
Output voltage tracking accuracy(1)
–4
4
mV
ΔVO(ΔIO)
ΔVO(ΔVI)
Load regulation steady-state
Line regulation steady-state
IOUT = 0.1 to 300 mA, VADJ= 5 V
4
4
mV
mV
IOUT= 10 mA, VIN = 6 to 40 V, VADJ = 5 V
ƒrip = 100 Hz, Vrip = 0.5 VPP, C(OUT) = 10 µF,
IOUT = 100 mA
PSRR
Power supply ripple rejection
Dropout voltage
70
dB
V(DROPOUT)
IOUT = 200 mA, VIN = VADJ ≥ 4 V(2)
320
450
520
mV
(V(DROPOUT) = VIN – VOUT
Output current limitation
Reverse current at IN
)
IO(lim)
IR(IN)
VADJ = 5 V, OUT short to GND
301
–2
520
0
mA
µA
µA
VIN = 0 V, VOUT = 40 V, VADJ = 5 V
VIN = –40 V, VOUT = 0 V, VADJ = 5 V
IR(–IN)
Reverse current at negative IN
Thermal shutdown temperature
Thermal shutdown hysteresis
–10
0
TJ increases because of power dissipation
generated by the IC
TSD
175
°C
°C
TSD_hys
15
2
4 V ≤ VIN ≤ 40 V, VADJ = 0 V; VEN = 0 V
4 V ≤ VIN ≤ 40 V, VEN ≥ 2 V, VADJ < 0.8 V
4 V ≤ VIN ≤ 40 V, IOUT < 100 µA, VADJ = 5 V
4 V ≤ VIN ≤ 40 V, IOUT < 300 mA, VADJ = 5V
VIN = VADJ = 5 V, IOUT = 100 µA
HTSSOP package, VADJ = VFB = 5 V
SO PowerPAD package, VADJ = VFB = 5 V
VOUT = 0 V
4
18
7
IQ
Current consumption
µA
60
350
70
100
400
140
0.5
5.5
0.8
18
IQ(DROPOUT)
II(ADJ)
Current consumption in dropout region
Adjust input current
µA
µA
V(ADJ_LOW)
V(ADJ_HIGH)
V(EN_LOW)
V(EN_HIGH)
IEN
Adjust low signal valid
Adjust high signal valid
Enable low signal valid
Enable high Signal Valid
Enable pulldown current
FB bias current
0
1.5
0
V
V
|VOUT – VADJ| < 5 mV
VOUT = 0 V
0.7
40
V
OUT settled
2
V
2V < VEN < 40 V
5
µA
µA
IFB
VADJ = VFB = 5 V
0.5
(1) The tracking accuracy is specified when the FB pin is directly connected to the OUT pin which means VADJ = VOUT, external resistor
divider variance is not included.
(2) Measured when the output voltage, VOUT has dropped 10 mV from the nominal value.
Copyright © 2015, Texas Instruments Incorporated
5
TPS7B4253-Q1
ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
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6.6 Typical Characteristics
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
4
4
3
IOUT = 70 mA
IOUT = 300 mA
IOUT = 10 mA
IOUT = 100 mA
3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
35
40
Ambient Temperature (qC)
Input Voltage (V)
D004
D005
图 1. Tracking Accuracy vs Ambient Temperature
图 2. Line Regulation
800
700
600
500
400
300
200
100
0
4
3
TA = ꢀ40qC
TA = 25qC
TA = 125qC
TA = 25qC
TA = 125qC
2
1
0
-1
-2
-3
-4
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Current (mA)
Output Current (mA)
D006
D007
VIN = VADJ = 4 V
图 3. Load Regulation
图 4. Dropout Voltage vs Output Current
800
700
600
500
400
300
200
100
0
500
490
480
470
460
450
440
430
420
410
400
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (qC)
Ambient Temperature (qC)
D008
D003
VIN = VADJ = 4 V
IOUT = 200 mA
图 5. Dropout Voltage vs Ambient Temperature
图 6. Current Limit (IO(lim)) vs Ambient Temperature
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ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
Typical Characteristics (接下页)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
450
400
350
300
250
200
150
100
50
20
TA = ꢀ40qC
IQ (VEN = VADJ = 0 V)
IQ (VEN = 5 V, VADJ = 0 V)
18
TA = 25qC
TA = 125qC
16
14
12
10
8
6
4
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
50
100
150
200
250
300
Ambient Temperature (qC)
Output Current (mA)
D009
D010
图 7. Shutdown Current vs Ambient Temperature
图 8. Quiescent Current vs Output Current
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
IOUT = 300 mA
IOUT = 0.1 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
35
40
Ambient Temperature (qC)
Input Voltage (V)
D011
D012
VADJ = VEN = 5 V
图 9. Quiescent Current vs Ambient Temperature
图 10. Quiescent Current vs Input Voltage
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+8
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+8
Frequency (Hz)
Frequency (Hz)
D013
D014
C(OUT) = 10 µF
IOUT = 1 mA
TA = 25°C
C(OUT) = 10 µF
IOUT = 100 mA
TA = 25°C
图 11. PSRR
图 12. PSRR
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Typical Characteristics (接下页)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
500
500
400
300
200
100
10
400
300
Stable Region
Stable Region
200
100
10
0.001
5
10
ESR of C(OUT) (Ω)
15
20
0.001
2.5
5
ESR of C(OUT) (Ω)
7.5
10
D002
D002
VFB = VOUT
VFB < VOUT
图 13. ESR Stability vs Load Capacitance
图 14. ESR Stability vs Load Capacitance
500
400
300
200
100
10
10 V/div
Stable Region
V
IN
100 mV/div
(OUT_AC)
V
100 mA/div
OUT
I
0.001
0.75
1.5
ESR of C(OUT) (Ω)
2.25
3
VIN = 6 to 40 V
VADJ = 5 V
C(OUT) = 10 µF
D015
IOUT = 100 mA, 20 µs/div
图 15. ESR Stability vs Load Capacitance (Multiple Output
图 16. 6- to 40-V Line Transient
Capacitors)
10 V/div
10 V/div
V
IN
V
IN
100 mV/div
100 mV/div
V
(OUT_AC)
V
(OUT_AC)
100 mA/div
100 mA/div
OUT
I
I
OUT
VIN = 40 to 6 V
VADJ = 5 V
C(OUT) = 10 µF
VIN = 6 to 40 V
VADJ = 5 V
C(OUT) = 10 µF
IOUT = 100 mA, 20 µs/div
IOUT = 10 mA, 20 µs/div
图 17. 40- to 6-V Line Transient
图 18. 6- to 40-V Line Transient
8
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ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
Typical Characteristics (接下页)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
10 V/div
5 V/div
100 mV/div
V
IN
V
(OUT_AC)
100 mV/div
(OUT_AC)
V
IN
V
50 mA/div
100 mA/div
OUT
I
I
OUT
VIN = 14 V
VADJ = 5 V
C(OUT) = 10 µF
VIN = 40 to 6 V
VADJ = 5 V
C(OUT) = 10 µF
IOUT = 10 to 100 mA, 40 µs/div
IOUT = 10 mA, 20 µs/div
图 20. 10- to 100-mA Load Transient
图 19. 40- to 6-V Line Transient
5 V/div
100 mV/div
V
(OUT_AC)
V
IN
50 mA/div
I
OUT
VIN = 14 V
VADJ = 5 V
C(OUT) = 10 µF
IOUT = 100 to 10 mA, 40 µs/div
图 21. 100- to 10-mA Load Transient
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7 Detailed Description
7.1 Overview
The TPS7B4253-Q1 device is a monolithic integrated low-dropout voltage tracker with an ultralow tracking
tolerance. Key protection circuits are integrated in the device, including output current limitation, reverse polarity
protection, inductive load clamp, output short-to-battery protection, and thermal shutdown in case of an
overtemperature event.
7.2 Functional Block Diagram
IN
OUT
V(BAT)
Load
Reverse
Current
Protection
Internal
Supply
Current
Limit
UVLO
EN
Logic
Control
±
Thermal
Shutdown
ADJ
FB
Vref
GND
7.3 Feature Description
7.3.1 Short Circuit and Overcurrent Protection
The TPS7B4253-Q1 device features integrated fault protection which makes the device ideal for automotive
applications. To keep the device in a safe area of operation during certain fault conditions, internal current-limit
protection is used to limit the maximum output current. This protection protects the device from excessive power
dissipation. For example, during a short-circuit condition on the output, the current through the pass element is
limited to IO(lim) to protect the device from excessive power dissipation.
7.3.2 Integrated Inductive Clamp Protection
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp at the OUT pin to help to dissipate the inductive energy stored in the cable.
An internal diode is connected between the OUT and GND pins with a DC-current capability of 600 mA for
inductive clamp protection.
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Feature Description (接下页)
7.3.3 OUT Short to Battery and Reverse Polarity Protection
The TPS7B4253-Q1 device can withstand a short to battery when the output is shorted to the battery, as shown
in 图 22. Therefore, no damage to the device occurs.
Short to Battery
TPS7B4253-Q1
IN
Automotive
Battery
OUT
Load
14 V (Typical)
1 µF
10 µF
FB
EN
ADJ
GND
5 V
100 nF
图 22. OUT Short to Battery, VIN = V(BAT)
A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as
shown in 图 23. In this case, the TPS7B4253-Q1 supply-input voltage is set to 7 V when a short to battery (14 V
typical) occurs on the OUT pin which operates at 5 V. The internal back-to-back PMOS remains on for 1 ms
during which the input voltage of the TPS7B4253-Q1 device charges up to the battery voltage. A diode
connected between the output of the DC-DC converter and the input of the TPS7B4253-Q1 device is required in
case the other loads connected behind the DC-DC converter cannot withstand the voltage of an automotive
battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be
eliminated if the output of the DC-DC converter and the loads connect behind it withstand automotive battery
voltage.
The internal back-to-back PMOS is switched to OFF when reverse polarity or short to battery occur for 1 ms.
After that, the reverse current flows out through the IN pin with less than 10 µA. In the meanwhile, a special ESD
structure implemented at the input ensures the device can withstand –40 V.
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Feature Description (接下页)
Short to Battery
TPS7B4253-Q1
Automotive
Battery
14 V (Typical)
IN
7 V
OUT
DC-DC
Load
1 µF
10 µF
FB
EN
Other Loads
ADJ
GND
5 V
100 nF
图 23. OUT Short to Battery, VIN < V(BAT)
In most cases, the output of the TPS7B4253-Q1 device is shorted to the battery through an automotive cable.
The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4253-Q1 device when
the short to battery occurs. Ideally, the peak voltage at the output of the TPS7B4253-Q1 device should be lower
than the absolute-maximum voltage rating (45 V) during LC oscillation.
7.3.4 Undervoltage Shutdown
The device has an internally fixed undervoltage-shutdown threshold. Undervoltage shutdown activates when the
input voltage on IN drops below UVLO. This activation ensures the regulator is not latched into an unknown state
during a low input-supply voltage. If the input voltage has a negative transient that drops below the UVLO
threshold and then recovers, the regulator shuts down and then powers up with a standard power-up sequence
when the input voltage is above the required levels.
7.3.5 Thermal Protection
The device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. During continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature decreases to 15°C (typical) lower
than the TSD trip point, the output turns on.
注
The purpose of the design of the internal protection circuitry of the TPS7B4253-Q1 device
is to protect against overload conditions and is not intended as a replacement for proper
heat-sinking. Continuously running the device into thermal shutdown degrades device
reliability.
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Feature Description (接下页)
7.3.6 Regulated Output (OUT)
The OUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has an incorporated soft-start feature to control the initial current through the pass
element.
7.3.7 Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input on the EN pin acitvates the device and turns on the
regulator. The device consumes a maximum of shutdown current 4 µA when the EN pin is low. The EN pin has a
maximum internal pulldown of 5 µA.
7.3.8 Adjustable Output Voltage (FB and ADJ)
7.3.8.1 OUT Voltage Equal to the Reference Voltage
With the reference voltage applied directly at the ADJ pin and the FB pin connected to the OUT pin, the voltage
at the OUT pin equals to the reference voltage at the ADJ pin, as shown in 图 24.
VOUT = VADJ
(1)
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
22 µF
10 µF
FB
EN
ADJ
GND
Vref
图 24. OUT Voltage Equal to the Reference Voltage
7.3.8.2 OUT Voltage Higher Than Reference Voltage
By using an external resistor divider connected between the OUT and FB pins, an output voltage higher than
reference voltage can be generated as shown in 图 25. Use 公式 2 to calculate the value of the output voltage.
The recommended range for R1 and R2 is from 10 kΩ to 100 kΩ.
VADJ ´ (R1+ R2)
=
R2
VOUT
(2)
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Feature Description (接下页)
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
1 µF
10 µF
R1
47 nF
FB
EN
R2
ADJ
GND
Vref
图 25. OUT Voltage Higher Than the Reference Voltage
7.3.8.3 Output Voltage Lower Than Reference Voltage
By using an external resistor divider connected at the ADJ pin, an output voltage lower than reference voltage
can be generated as shown in 图 26. Use 公式 3 to calculate the output voltage. The recommended value for
both R1 and R2 is less than 100 kΩ.
V
´ R2
ref
VOUT
=
R1+ R2
(3)
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
1 µF
10 µF
FB
EN
Vref
R1
R2
ADJ
GND
图 26. OUT Voltage Lower Than the Reference Voltage
14
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7.4 Device Functional Modes
7.4.1 Operation With VIN < 4 V
The maximum UVLO voltage is 3.65 V, and the device generally operates at an input voltage above 4 V. The
device can also operate at a lower input voltage; no minimum UVLO voltage is specified. At an input voltage
below the actual UVLO voltage, the device does not operate.
7.4.2 Operation With EN Control
The enable rising edge threshold is 2 V (maximum). With the EN pin held above that voltage and the input
voltage above 4 V, the device becomes active. The falling edge of the EN pin is 0.7 V (minimum). Holding the
EN pin below that voltage disables the device, thus reducing the quiescent current of the device.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B4253-Q1 device is a 300-mA low-dropout tracking regulator with ultralow tracking tolerance. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.2 Typical Application
8.2.1 Application With Output Voltage Equal to the Reference Voltage
图 27 shows the typical application circuit for the TPS7B4253-Q1 device. Different values of external components
can be used depending on the end application. An application may require a larger output capacitor during fast
load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with
a dielectric of type X5R or X7R.
IN
OUT
Load
Battery
(sensor)
1 µF
10 µF
Reverse
Current
Protection
Internal
Supply
Current
Limit
UVLO
EN
MCU I/O
Logic
Control
±
Thermal
Shutdown
ADJ
FB
V
ref
(5 V)
100 nF
GND
图 27. Output Voltage Equals the Reference Voltage
16
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Typical Application (接下页)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表 1 as the design parameters.
表 1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
4 to 40 V
Output voltage
1.5 to 40 V
Enable voltage
2 to 40 V
ADJ voltage
1.5 to 18 V
Output capacitor
Output capacitor ESR range
10 to 500 µF
0.001 to 20 Ω
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
•
Input voltage range
Output voltage
Reference voltage
Output current
Current limit
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 2.2 µF. The voltage rating must be greater than the
maximum input voltage.
8.2.1.2.2 Output Capacitor
To ensure the stability of the TPS7B4253-Q1 device, the device requires an output capacitor with a value in the
range from 10 µF to 500 µF and with an ESR range from 0.001 Ω to 20 Ω when the FB pin is directly connected
to the OUT pin. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient
response.
To achieve an output voltage higher than the reference voltage, a resistor divider is connected between the OUT
pin and the FB pin. In this case, a 47-nF feed forward capacitor must be connected between the OUT and FB
pins for loop stability. The ESR of the output capacitor must be from 0.001 Ω to 10 Ω.
When multiple capacitors (two or more) are connected in parallel at the OUT pin, the ESR range of each output
capacitor must be from 0.001 Ω to 3 Ω for loop stability.
In case the FB pin is shorted to ground, the TPS7B4253-Q1 device functions as a power switch with no need for
the output capacitor.
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8.2.1.3 Application Curves
10 V/div
V
IN
100 mV/div
(OUT_AC)
V
100 mA/div
OUT
I
VIN = 6 to 40 V
IOUT = 100 mA, 20 µs/div
图 28. 6- to 40-V Line Transient
VADJ = 5 V
C(OUT) = 10 µF
8.2.2 High-Side Switch Configuration
As shown in 图 29, by connecting the FB pin to the GND pin, the TPS7B4253-Q1 device can be used as a high-
side switch with current-limit, thermal shutdown, output short-to-battery, and reverse polarity protection. The
switching on and off of the device is then controlled through the EN and ADJ pins.
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
1 µF
10 µF
FB
EN
ADJ
GND
MCU I/O
图 29. High-Side Switch Application
18
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8.2.3 High Accuracy LDO
With an accurate voltage rail, the TPS7B4253-Q1 device can be used as an LDO with ultrahigh-accuracy output
voltage by configuring the device as shown in 图 30.
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
1 µF
10 µF
FB
EN
Accurate reference rail
For example: TLV431
ADJ
GND
Vref
图 30. High-Accuracy LDO Application
For example, assume the reference voltage is a 5-V rail with 0.5% accuracy. Because the tracking accuracy
between the ADJ and OUT pins is specified below 4 mV across temperature, the output accuracy of the
TPS7B4253-Q1 device can be calculated with 公式 4.
VADJ ´ 0.5% + 4 mV
5 ´ 0.5% + 0.004
Accuracyof VOUT
=
´ 100% =
´ 100% = 0.58%
VADJ
5
(4)
9 Power Supply Recommendations
The device is designed to operate with an input voltage supply from 4 V to 40 V. This input supply must be well
regulated. If the input supply is more than a few inches away from the TPS7B4253-Q1 device, TI recommends
adding an electrolytic capacitor with a value of 2.2 µF and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For the layout of the TPS7B4253-Q1 device, place the input and output capacitors close to the devices as shown
in the Functional Block Diagram. To enhance the thermal performance, TI recommends surrounding the device
with some vias.
Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure stability. Place
every capacitor as close as possible to the device and on the same side of the PCB as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces for the path between the output capacitor and the OUT pins
because vias can negatively impact system performance and even cause instability.
If possible, and to ensure the maximum performance specified in this data sheet, use the same layout pattern
used for the TPS7B4253-Q1 evaluation board, TPS7B4253EVM, which is available at
www.ti.com/tool/TPS7B4253EVM.
10.2 Layout Example
HTSSOP 20
62ꢀ3RZHU3$'-8
OUT
IN
OUT
IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
8
1
2
7
6
5
Thermal
Pad
GND
FB
GND
3
4
ADJ/EN
Thermal Pad
GND
GND
ADJ
6
7
8
9
FB
10
图 31. SO PowerPAD Package TPS7B4253-Q1
图 32. HTSSOP Package TPS7B4253-Q1 Layout
Layout Example
Example
20
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ZHCSE23A –JANUARY 2015–REVISED AUGUST 2015
10.3 Power Dissipation and Thermal Considerations
Use 公式 5 to calculate the device power dissipation.
PD = IO ´ V - V + I ´ V
(
)
I
O
Q
I
where
•
•
•
•
•
PD = continuous power dissipation
IO = output current
VI = input voltage
VO = output voltage
IQ = quiescent current
(5)
As IQ « IO, the term IQ × VI in 公式 5 can be ignored.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with
公式 6.
T = T + q ´ PD
(
)
J
A
JA
where
•
θJA = junction-to-junction-ambient air thermal impedance
(6)
(7)
A rise in junction temperature because of power dissipation can be calculated with 公式 7.
DT = T - T = q ´ PD
(
)
J
A
JA
For a given maximum junction temperature (TJmax), the maximum ambient air temperature (TAmax) at which the
device can operate can be calculated with 公式 8.
TA max = TJ max- (qJA ´ PD )
(8)
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
如需 TPS7B4253 PSpice 瞬态模型，请访问 www.ti.com.cn/product/cn/TPS7B4253-Q1/toolssoftware。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
《TPS7B4253-Q1 评估模块》，SLVUAE3
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B4253QDDARQ1
TPS7B4253QPWPRQ1
ACTIVE SO PowerPAD
DDA
PWP
8
2500 RoHS & Green
2000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 125
-40 to 125
4253
7B4253Q
ACTIVE
HTSSOP
20
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2000
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B4253QDDARQ1
SO
Power
PAD
DDA
8
330.0
330.0
12.8
16.4
6.4
5.2
7.1
2.1
1.6
8.0
8.0
12.0
16.0
Q1
Q1
TPS7B4253QPWPRQ1 HTSSOP PWP
20
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B4253QDDARQ1
TPS7B4253QPWPRQ1
SO PowerPAD
HTSSOP
DDA
PWP
8
2500
2000
366.0
350.0
364.0
350.0
50.0
43.0
20
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.1
2.5
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.6
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.1)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
0.125
0.150
0.175
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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