TPS7B4254QDDARQ1 [TI]
汽车类 150mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DDA | 8 | -40 to 125;
| 型号： | TPS7B4254QDDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 150mA、电池供电运行 (40V)、可调节电压跟踪低压降稳压器 | DDA | 8 | -40 to 125 电池 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总28页 (文件大小：2157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
TPS7B4254-Q1 跟踪容差为 4mV 的 150mA、40V 电压跟踪 LDO
1 特性
2 应用
1
•
适用于汽车电子 应用
•
•
•
非板载传感器电源
•
符合 AEC-Q100 标准的下列结果
高精度电压跟踪
非板载负载的电源开关
–
–
–
器件温度等级 1：环境运行温度范围为 -40°C
至 125°C
3 说明
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 3A
对于汽车非板载传感器和低电流非板载模块，电源通过
一条长电缆连接主板。在这类情况下，电源器件需要为
非板载负载提供保护，防止板载组件在接地短路或者电
缆破损造成的电池短路期间受损。非板载传感器需要与
板载组件采用相同的电源，以确保数据采集的高精度。
器件组件充电模式 (CDM) ESD 分类等级 C6
•
•
•
•
•
•
–40V 至 45V 宽输入电压范围（最大值）
可调输出电压范围：2V 到 40V
150mA 输出电流能力
±4mV 超低输出跟踪容差
TPS7B4254-Q1 器件设计用于 具有 45V 负载突降问
题的汽车类应用。该器件可用作一个跟踪低压降
(LDO) 稳压器或者电压跟踪器，通过板载主电源为非
板载传感器构建一个封闭电源环路。该器件的输出由
ADJ 引脚的基准电压精准调节。
160mV 低压降 (IOUT = 100mA 时)
低静态电流 (IQ)：
–
–
< 4µA（ADJ = 低电平时）
轻负载时的典型值为 60µA
•
超宽等效串联电阻 (ESR) 范围
为了给非板载模块提供精确的电源，该器件的 ADJ 与
FB 引脚间在运行温度范围内具有 4mV 超低跟踪容
差。PMOS 背靠背拓扑消除了反极性条件下对外部二
极管的需求。TPS7B4254-Q1 器件还包括热关断、感
性钳位、过载和电池短路保护，防止板载组件在极限条
件下受损。
–
–
10µF 至 500µF 的陶瓷输出电容
等效串联电阻 (ESR) 范围为 1mΩ 至 20Ω
•
•
•
•
•
反极性保护
限流和热关断保护
针对接地和电源的输出短路保护
输出引脚感性钳位
器件信息(1)
8 引脚小外形尺寸 (SO) PowerPAD™封装，带外露
散热焊盘
器件型号
封装
封装尺寸（标称值）
TPS7B4254-Q1
SO PowerPAD (8)
4.89mm × 3.90mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
典型应用电路原理图
Automotive
Battery
IN
OUT
CIN
COUT
DC-DC or
LDO
TPS7B4254-Q1
ADJ
Off-Board
Sensor
FB
GND
MCU
ADC
Main Board
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDI1
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 社区资源................................................................ 19
11.2 商标....................................................................... 19
11.3 静电放电警告......................................................... 19
11.4 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
Changes from Original (April 2016) to Revision A
Page
•
已将数据表状态由“产品预览”改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP With Exposed Thermal Pad
Top View
OUT
NC
1
2
3
4
8
7
6
5
IN
NC
Thermal
Pad
GND
FB
GND
ADJ
NC – No internal connection
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Connect the reference to this pin. A low signal disables the device and a high signal enables
the device. The reference voltage can be connected directly or by a voltage divider for lower
output voltages. To compensate for line influences, connect a capacitor close to the device
pin.
ADJ
5
I
This pin is the feedback pin, which can connect to the external resistor divider to select the
output voltage.
FB
4
3, 6
8
I
G
GND
IN
Ground reference
This pin is the device supply. To compensate for line influences, connect a capacitor close to
the device pin.
I
NC
2, 7
1
NC
O
Not internally connected.
Block to GND with a capacitor close to the device pins with respect to the capacitance and
ESR requirements listed in the Output Capacitor section.
OUT
Exposed thermal pad
—
Connect the thermal pad to the GND pin or leave it floating.
(1) I = input, O = output, G = ground, NC = no internal connection
Copyright © 2016, Texas Instruments Incorporated
3
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–40
–1
MAX
45
UNIT
V
Unregulated input voltage
Regulated output voltage
IN(2)
OUT(2)(3)
45
V
Voltage difference between the input
and output
IN – OUT
–40
45
V
Reference voltage
ADJ(2)
FB(2)
–0.3
–1
45
45
V
V
Feedback input voltage for the tracker
Reference voltage minus the input
voltage
ADJ – IN(4)
18
V
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
ºC
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND pin.
(3) An internal diode is connected between the OUT and GND pins with 600-mA dc current capability for inductive clamp protection.
(4) When the (ADJ – IN) voltage is higher than 18 V, the (ADJ – OUT) voltage should be maintained lower than 18 V, otherwise the device
can be damaged.
6.2 ESD Ratings
VALUE
±4000
±2000
±1000
UNIT
All pins except NC
NC pins
Human-body model (HBM), per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)(1)
MIN
4
MAX
40
UNIT
V
VIN
Unregulated input voltage(2)
Reference input voltage
VADJ
VFB
1.5
1.5
1.5
10
18
V
Feedback input voltage for the tracker
Regulated output voltage
Output capacitor requirements(3)
Output ESR requirements(4)
Operating junction temperature
18
V
VOUT
COUT
40
V
500
20
µF
Ω
0.001
–40
TJ
150
ºC
(1) Within the functional range the device operates as described in the circuit description. The electrical characteristics are specified within
the conditions given in the related Electrical Characteristics table.
(2) VIN > VADJ + VDROPOUT
(3) The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%. When a resistor divider is
connected between the OUT and FB pins (the output voltage is higher than reference voltage), a 47-nF feedforward capacitor is
required to be connected between the OUT and FB pins for loop stability, and the ESR range of the output capacitor is required to be
from 0.001 to 10 Ω.
(4) Relevant ESR value at f = 10 kHz
4
Copyright © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
6.4 Thermal Information
TPS7B4254-Q1
THERMAL METRIC(1)
DDA (HSOP)
8 PINS
45.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.1
27
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.2
ψJB
26.9
RθJC(bot)
6.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 13.5 V, VADJ ≥ 2 V, TJ = –40ºC to 150ºC, over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIN rising
MIN
TYP
MAX
3.65
2.8
UNIT
V
VIN(UVLO)
IN undervoltage detection
VIN falling
V
IOUT = 100 μA to 150 mA, VIN = 4 to
40 V
VADJ < VIN – 1 V
ΔVOUT
Output voltage tracking accuracy(1)
–4
4
mV
2 V < VADJ < 18 V
ΔVOUT(ΔIO) Load regulation, steady-state
ΔVOUT(ΔVI) Line regulation, steady-state
IOUT = 0.1 to 150 mA, VADJ= 5 V
4
4
mV
mV
IOUT = 10 mA, VIN = 6 to 40 V, VADJ
= 5 V
frip = 100 Hz, Vrip = 0.5 VPP, COUT
10 μF, IOUT = 100 mA
=
PSRR
Power-supply ripple rejection
70
dB
Dropout voltage (VDROPOUT = VIN
–
VDROPOUT
IOUT = 100 mA, VIN = VADJ ≥ 4 V(2)
160
450
260
mV
VOUT
)
IOUT(LIM)
IR(IN)
IR(–IN)
TSD
Output current limitation
VADJ = 5 V, OUT short to GND
151
–2
520
0
mA
µA
µA
ºC
Reverse current at IN
VIN = 0 V, VOUT = 40 V, VADJ = 5 V
VIN = –40 V, VOUT = 0 V, VADJ = 5 V
Reverse current at negative IN
Thermal shutdown temperature
Thermal shutdown hysteresis
–10
175
15
2
TSD_hys
ºC
4 V ≤ VIN ≤ 40 V, VADJ = 0 V
4
µA
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT
100 µA
<
<
60
210
70
100
µA
µA
µA
IQ
Current consumption
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT
150 mA
260
140
IQ(DROPOUT Current consumption in dropout
VIN = VADJ = 5 V, IOUT = 100 μA
region
)
IADJ
Reference input current
VADJ = VFB = 5 V
VOUT = 0 V
5.5
0.7
18
µA
V
VADJ(LOW) Reference low signal valid
VADJ(HIGH) Reference high signal valid
0
2
|VOUT – VADJ| < 4 mV
VADJ = VFB = 5 V
V
IFB
FB bias current
0.5
µA
(1) The tracking accuracy is specified when the FB pin is directly connected to the OUT pin which means VADJ = VOUT, external resistor
divider variance is not included.
(2) Measured when the output voltage, VOUT, has dropped 10 mV from the nominal value.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
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6.6 Typical Characteristics
4
3
4
3
IOUT = 0.1 mA
IOUT = 70 mA
IOUT = 150 mA
IOUT = 10 mA
IOUT = 100 mA
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
-40
-20
0
20
40
60
80
100
120
0
5
10
15
20
25
30
35
40
Temp (èC)
DVin (V)
D001
D002
V
V
Figure 1. Tracking Accuracy vs Ambient Temperature
Figure 2. Line Regulation
400
350
300
250
200
150
100
50
4
-40 C
25 C
125 C
Ta = 25 èC
Ta = 125 èC
3
2
1
0
-1
-2
-3
-4
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
IOUT (mA)
IOUT (mA)
D003
D004
V
VIN = VADJ = 4 V
Figure 3. Load Regulation
Figure 4. Dropout Voltage vs Output Current
400
350
300
250
200
150
100
50
500
490
480
470
460
450
440
430
420
410
400
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
D005
D006
VIN = VADJ = 4 V
IOUT = 100 mA
V
Figure 5. Dropout Voltage vs Ambient Temperature
Figure 6. Current Limit (IOUT(LIM)) vs Ambient Temperature
6
Copyright © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
Typical Characteristics (continued)
250
200
150
100
50
4
3.5
3
-40 èC
25 èC
125 èC
2.5
2
1.5
1
0.5
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
25
50
75
100
125
150
Temperature (èC)
IOUT (mA)
D007
D008
V
V
Figure 7. Shutdown Current vs Ambient Temperature
Figure 8. Quiescent Current vs Output Current
500
500
450
400
350
300
250
200
150
100
50
IOUT = 300 mA
IOUT = 0.1 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
450
400
350
300
250
200
150
100
50
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
35
40
Temperature (èC)
VIN (V)
D009
D010
V
VADJ = 5 V
Figure 10. Quiescent Current vs Input Voltage
Figure 9. Quiescent Current vs Ambient Temperature
140
120
100
80
60
40
20
0
120
100
80
60
40
20
0
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
IOUT = 1 mA
VADJ = 5 V
Frequency (Hz)
IOUT = 100 mA
VADJ = 5 V
D011
D012
COUT = 10 µF
VIN = 14 V
TA = 25°C
COUT = 10 µF
VIN = 14 V
TA = 25°C
Figure 11. PSRR
Figure 12. PSSR
Copyright © 2016, Texas Instruments Incorporated
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Typical Characteristics (continued)
500
500
400
300
200
400
300
Stable Region
Stable Region
200
100
10
100
10
0.001
5
10
ESR of COUT (W)
15
20
0.001
2.5
5
7.5
10
ESR of COUT (W)
D013
D014
VFB = VOUT
VFB < VOUT
Figure 14. ESR Stability vs Load Capacitance
Figure 13. ESR Stability vs Load Capacitance
500
VOUT (1 V/div)
400
300
200
VIN (10 V/div)
Stable Region
VOUT(AC) (50 mV/div)
100
10
IOUT (10 mA/div)
0.001
0.5
1
1.5
ESR of COUT (W)
2
2.5
3
D015
V
VIN = 6 to 40 V
IOUT = 10 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
V
Figure 15. ESR Stability vs Load Capacitance (Multiple
Output Capacitors in parallel)
Figure 16. 6-V to 40-V Line Transient
VIN (10 V/div)
VOUT (1 V/div)
VIN (10 V/div)
VOUT (1 V/div)
VOUT(AC) (50 mV/div)
IOUT (100 mA/div)
VOUT(AC) (50 mV/div)
IOUT (10 mA/div)
VIN = 40 to 6 V
IOUT = 10 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
VIN = 6 to 40 V
IOUT = 100 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
Figure 17. 40-V to 6-V Line Transient
Figure 18. 6-V to 40-V Line Transient
8
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
Typical Characteristics (continued)
VIN (10 V/div)
VIN (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
VOUT(AC) (100 mV/div)
VOUT(AC) (50 mV/div)
IOUT (100 mA/div)
IOUT (50 mA/div)
VIN = 40 to 6 V
IOUT = 100 mA
VADJ = 5 V
40 µs/div
COUT = 10 µF
VIN = 14 V
VADJ = 5 V
COUT = 10 µF
100 µs/div
IOUT = 10 mA to 100 mA
Figure 19. 40-V to 6-V Line Transient
VIN (5 V/div)
Figure 20. 10-V to 100-mA Load Transient
VOUT (1 V/div)
VOUT(AC) (100 mV/div)
IOUT (50 mA/div)
VIN = 14 V
VADJ = 5 V
COUT = 10 µF
100 µs/div
IOUT = 100 mA to 10 mA
Figure 21. 100-mA to 10-mA Load Transient
Copyright © 2016, Texas Instruments Incorporated
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TPS7B4254-Q1
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7 Detailed Description
7.1 Overview
The TPS7B4254-Q1 device is a monolithic integrated low-dropout voltage tracker with an ultralow tracking
tolerance. Key protection circuits are integrated in the device, including output current limitation, reverse polarity
protection, inductive load clamp, output short-to-battery protection, and thermal shutdown in case of an
overtemperature event.
7.2 Functional Block Diagram
OUT
IN
VBAT
Load
Reverse
Current
Protection
Internal
Supply
Current
Limit
UVLO
Logic
Control
–
Thermal
Shutdown
FB
ADJ
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Short-Circuit and Overcurrent Protection
The TPS7B4254-Q1 device features integrated fault protection, which makes the device ideal for automotive
applications. To keep the device in a safe area of operation during certain fault conditions, internal current-limit
protection is used to limit the maximum output current. This protection protects the device from excessive power
dissipation. For example, during a short-circuit condition on the output, the current through the pass element is
limited to IOUT(LIM) to protect the device from excessive power dissipation.
7.3.2 Integrated Inductive Clamp Protection
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp at the OUT pin to help to dissipate the inductive energy stored in the cable.
An internal diode is connected between the OUT and GND pins with a dc-current capability of 600 mA for
inductive clamp protection.
7.3.3 OUT Short-to-Battery and Reverse-Polarity Protection
The TPS7B4254-Q1 device can withstand a short to battery on the output, as shown in Figure 22. Therefore, no
damage to the device occurs.
10
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF00A –APRIL 2016–REVISED MAY 2016
Feature Description (continued)
IN
OUT
Automotive Battery
14 V (Typical)
Load
10 µF
TPS7B4254-Q1
ADJ
FB
5 V
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 22. OUT Short to Battery, VIN = VBAT
A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as
shown in Figure 23. In this case, the TPS7B4254-Q1 supply-input voltage is set to 7 V when a short to battery
(14 V typical) occurs on the OUT pin, which operates at 5 V. The internal back-to-back PMOS remains on for
1 ms, during which the input voltage of the TPS7B4254-Q1 device charges up to the battery voltage. A diode
connected between the output of the dc-dc converter and the input of the TPS7B4254-Q1 device is required in
case the other loads connected behind the dc-dc converter cannot withstand the voltage of an automotive
battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be
eliminated if the output of the dc-dc converter and the loads connected behind it withstand automotive battery
voltage.
The internal back-to-back PMOS is switched to OFF when reverse polarity or a short to battery occurs for 1 ms.
After that, the reverse current that flows out through the IN pin is less than 10 μA. Meanwhile, a special ESD
structure implemented at the input ensures the device can withstand –40 V.
Short to Battery
Automotive Battery
14 V (Typical)
7 V
IN
OUT
DC-DC
Load
10 µF
Other
Loads
TPS7B4254-Q1
ADJ
FB
5 V
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 23. OUT Short to Battery, VIN < VBAT
In most cases, the output of the TPS7B4254-Q1 device is shorted to the battery through an automotive cable.
The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4254-Q1 device when
the short to battery occurs. The peak voltage at the output of the TPS7B4254-Q1 device must be lower than the
absolute-maximum voltage rating (45 V) during LC oscillation.
Copyright © 2016, Texas Instruments Incorporated
11
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
www.ti.com.cn
Feature Description (continued)
7.3.4 Undervoltage Shutdown
The device has an internally fixed undervoltage-shutdown threshold. Undervoltage shutdown activates when the
input voltage on IN drops below UVLO. This activation ensures the regulator is not latched into an unknown state
during a low input-supply voltage. If the input voltage has a negative transient that drops below the UVLO
threshold and then recovers, the regulator shuts down and then powers up with a standard power-up sequence
when the input voltage is above the required level.
7.3.5 Thermal Protection
The device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. During continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature decreases to 15°C (typical) lower
than the TSD trip point, the output turns on.
NOTE
The purpose of the internal protection circuitry of the TPS7B4254-Q1 device is to protect
against overload conditions and is not intended as a replacement for proper heat-sinking.
Continuously running the device into thermal shutdown degrades device reliability.
7.3.6 Regulated Output (OUT)
The OUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has an incorporated soft-start feature to control the initial current through the pass
element.
7.3.7 Adjustable Output Voltage (FB and ADJ)
7.3.7.1 OUT Voltage Equal to the Reference Voltage
With the reference voltage applied directly at the ADJ pin and the FB pin connected to the OUT pin, the voltage
at the OUT pin equals to the reference voltage at the ADJ pin, as shown in Figure 24.
VOUT = VADJ
(1)
IN
OUT
VBAT
Load
10µF
TPS7B4254-Q1
ADJ
FB
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 24. OUT Voltage Equal to the Reference Voltage
7.3.7.2 OUT Voltage Higher Than Reference Voltage
By using an external resistor divider connected between the OUT and FB pins, an output voltage higher than
reference voltage can be generated as shown in Figure 25. Use Equation 2 to calculate the value of the output
voltage. The recommended range for R1 and R2 is from 10 kΩ to 100 kΩ.
R1
æ
ö
VOUT = VADJ ´ 1+
ç
÷
R2
è
ø
(2)
12
Copyright © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
www.ti.com.cn
ZHCSF00A –APRIL 2016–REVISED MAY 2016
Feature Description (continued)
IN
OUT
VBAT
Load
10µF
47nF
FB
R1
R2
TPS7B4254-Q1
ADJ
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 25. OUT Voltage Higher Than the Reference Voltage
7.3.7.3 Output Voltage Lower Than Reference Voltage
By using an external resistor divider connected at the ADJ pin, an output voltage lower than reference voltage
can be generated as shown in Figure 26. Use Equation 3 to calculate the output voltage. The recommended
value for both R1 and R2 is less than 100 kΩ.
R2
VOUT = VREF
´
R1+ R2
(3)
IN
OUT
VBAT
Load
10 μF
TPS7B4254-Q1
VREF
R1
R2
ADJ
FB
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. OUT Voltage Lower Than the Reference Voltage
7.4 Device Functional Modes
7.4.1 Operation With VIN < 4 V
The maximum UVLO voltage is 3.65 V, and the device generally operates at an input voltage above 4 V. The
device can also operate at a lower input voltage; no minimum UVLO voltage is specified. At an input voltage
below the actual UVLO voltage, the device does not operate.
Copyright © 2016, Texas Instruments Incorporated
13
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B4254-Q1 device is a 150-mA low-dropout tracking regulator with ultralow tracking tolerance. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.2 Typical Applications
8.2.1 Application With Output Voltage Equal to the Reference Voltage
Figure 27 shows a typical application circuit for the TPS7B4254-Q1 device. Different values of external
components can be used, depending on the end application. An application may require a larger output capacitor
during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic
capacitor with a dielectric of type X5R or X7R.
IN
OUT
VBAT
Load
1μF
to
10 μF
0.1 μF
22μF
TPS7B4254-Q1
ADJ
0.1 μF
FB
VREF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Output Voltage Equals the Reference Voltage
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
4 V to 40 V
Output voltage
2 V to 40 V
ADJ voltage
2 V to 18 V
Output capacitor
10 µF to 500 µF
0.001 Ω to 20 Ω
Output capacitor ESR range
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
Input voltage range
Output voltage
Reference voltage
Output current
14
Copyright © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
www.ti.com.cn
ZHCSF00A –APRIL 2016–REVISED MAY 2016
•
Current limit
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 μF with a 0.1 µF ceramic bypass capacitor in parallel. The
voltage rating must be greater than the maximum input voltage.
8.2.1.2.2 Output Capacitor
To ensure the stability of the TPS7B4254-Q1 device, the device requires an output capacitor with a value in the
range from 10 μF to 500 μF and with an ESR range from 0.001 Ω to 20 Ω when the FB pin is directly connected
to the OUT pin. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient
response.
To achieve an output voltage higher than the reference voltage, a resistor divider is connected between the OUT
pin and the FB pin. In this case, a 47-nF feedforward capacitor must be connected between the OUT and FB
pins for loop stability. The ESR of the output capacitor must be from 0.001 Ω to 10 Ω.
When multiple capacitors (two or more) are connected in parallel at the OUT pin, the ESR range of each output
capacitor must be from 0.001 Ω to 3 Ω for loop stability.
In case the FB pin is shorted to ground, the TPS7B4254-Q1 device functions as a power switch with no need for
the output capacitor.
8.2.1.3 Application Curve
VOUT (1 V/div)
VIN (10 V/div)
VOUT(AC) (50 mV/div)
IOUT (100 mA/div)
Figure 28. 6-V to 40-V Line Transient
8.2.2 High-Accuracy LDO
With an accurate voltage rail, the TPS7B4254-Q1 device can be used as an LDO with ultrahigh-accuracy output
voltage by configuring the device as shown in Figure 29.
Copyright © 2016, Texas Instruments Incorporated
15
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
www.ti.com.cn
IN
OUT
VBAT
Load
1 μF
to
0.1 μF
10 μF
22μ F
TPS7B4254-Q1
ADJ
Accurate Reference Rail
For Example: REF5050A-Q1
FB
VREF
0.1 μF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 29. High-Accuracy LDO Application
For example, assume the reference voltage is a 5-V rail with 0.1% accuracy. Because the tracking accuracy
between the ADJ and OUT pins is specified below 4 mV across temperature, the output accuracy of the
TPS7B4254-Q1 device can be calculated with Equation 4.
V
ADJ ´ 0.1% + 4 mV
5´ 0.1% + 0.004
Accuracy of VOUT
=
´100 % =
´100 % = 0.18 %
VOUT
5
(4)
16
Copyright © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
www.ti.com.cn
ZHCSF00A –APRIL 2016–REVISED MAY 2016
9 Power Supply Recommendations
The device is designed to operate with an input voltage supply from 4 V to 40 V. This input supply must be well
regulated. If the input supply is more than a few inches away from the TPS7B4254-Q1 device, TI recommends
adding an electrolytic capacitor with a value of 10 μF and a ceramic bypass capacitor at the input.
Copyright © 2016, Texas Instruments Incorporated
17
TPS7B4254-Q1
ZHCSF00A –APRIL 2016–REVISED MAY 2016
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For the layout of the TPS7B4254-Q1 device, place the input and output capacitors close to the devices as shown
in the Functional Block Diagram. To enhance the thermal performance, TI recommends surrounding the device
with some vias. Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure
stability. Place every capacitor as close as possible to the device and on the same side of the PCB as the
regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces for the path between the output capacitor and the OUT pins
because vias can negatively impact system performance and even cause instability.
10.2 Layout Example
OUT
IN
VOUT
VIN
1
2
3
4
8
7
6
5
Thermal
Pad
GND
FB
GND
ADJ
ADJ
Figure 30. TPS7B4254-Q1 Layout Example
18
版权 © 2016, Texas Instruments Incorporated
TPS7B4254-Q1
www.ti.com.cn
ZHCSF00A –APRIL 2016–REVISED MAY 2016
11 器件和文档支持
11.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。本数据随时可能发生变更并且
不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
版权 © 2016, Texas Instruments Incorporated
19
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B4254QDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4254
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B4254QDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS7B4254QDDARQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.1
2.5
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.6
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.1)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
0.125
0.150
0.175
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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