TPS7B7701-Q1 [TI]
汽车类 300mA、电池供电运行 (40V)、可调节天线低压降稳压器;型号: | TPS7B7701-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 汽车类 300mA、电池供电运行 (40V)、可调节天线低压降稳压器 电池 稳压器 |
文件: | 总29页 (文件大小:1393K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
具有电流检测功能的 TPS7B770x-Q1 车用单通道和双通道天线 LDO
1 特性
3 说明
1
•
符合汽车类应用的 要求
TPS7B770x-Q1 系列器件采用具有电流检测功能的单
通道和双通道高电压低压差稳压器 (LDO),适合在
4.5V 至 40V(45V 负载突降保护)的宽输入电压范围
内工作。这些器件通过一条每通道电流为 300mA 的同
轴电缆为有源天线的低噪声放大器供电。每条通道还可
提供 1.5V 至 20V 的可调节输出电压。
•
具有符合 AEC-Q100 标准的下列特性:
–
–
–
器件温度 1 级:–40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
器件组件充电模式 (CDM) ESD 分类等级 C4B
这些器件通过电流检测和错误引脚提供诊断。为监视负
载电流,高侧电流检测电路提供了与检测的负载电流成
比例的模拟输出。电流检测功能非常精确,无需进一步
校正即可检测开路、正常和短路条件。可以在通道和器
件间对电流检测进行多路复用,以节省模数转换器
(ADC) 资源。每个通道还通过外部电阻实现了可调节
限流功能。
•
具有电流检测和可调节限流功能的单通道和双通道
低压降稳压器 (LDO)
•
•
•
•
•
•
4.5V 至 40V 宽输入电压范围,45V 负载突降保护
FB 接至 GND 时进入电源开关模式
1.5V 至 20V 可调节输出电压
每通道输出电流高达 300mA
可通过外部电阻实现可调节限流功能
高精度电流检测功能,无需进一步校准即可在低电
流下检测天线开路情况
集成了反极性二极管,因此无需使用外部二极管。这些
器件具有标准热关断功能、输出端电池短路保护功能以
及反向电流保护功能。各通道可在电感式开关断开期间
为输出端提供内部电感式钳位保护。
•
•
•
•
高电源抑制比:100Hz 时的典型值为 73dB
集成反向极性保护,低至 -40V 且无需外部二极管
负载电流为 100mA 时,最大压降电压为 500mV
这些器件的工作环境温度范围为 -40°C 至 +125°C。
与 2.2µF 至 100µF(ESR 为 1mΩ 至 5Ω)范围内
的输出电容器搭配使用时可保持稳定
器件信息(1)
•
集成了保护和诊断功能
器件型号
TPS7B7701-Q1
TPS7B7702-Q1
封装
HTSSOP (16)
HTSSOP (16)
通道
–
–
–
–
–
–
–
–
–
热关断
单通道
双通道
欠压锁定 (UVLO)
短路保护
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
反向电池极性保护
反向电流保护
703A I2C
Active
IN
Battery
Input
输出端电池短路保护
输出端感性负载钳位
多通道/器件间的电流检测功能复用
能够通过电流检测功能区分所有故障
Antenna
Filter Coil
Filter Coil
10 ꢀF
OUT1/2
FB1/2
Cable
10 ꢀF
10 ꢀF
SENSE_EN
MCU I/O
MCU I/O
SENSE_SEL
SENSE1/2
•
16 引脚 HTSSOP PowerPAD™封装
TPS7B770x-Q1
R
1 ꢀF
(SENSE)
2 应用
EN1/2
ERR
ILIM1/2
MCU I/O
MCU I/O
•
•
•
信息娱乐系统有源天线电源
R
(LIM)
V
环视摄像头电源
CC
1 ꢀF
适用于小电流应用的高侧电源 开关
GND
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSCE8
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 文档支持................................................................ 20
11.2 相关链接................................................................ 20
11.3 接收文档更新通知 ................................................. 20
11.4 社区资源................................................................ 20
11.5 商标....................................................................... 20
11.6 静电放电警告......................................................... 20
11.7 术语表 ................................................................... 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2015) to Revision C
Page
•
•
•
Changed NC pin description in Pin Functions table to clarify which pins are internally connected ...................................... 3
Added row to Recommended Operating Conditions for OUT1, OUT2, and OUT regarding switched-mode operation ....... 4
已更改 Current-Limit Resistor Selection section for clarity................................................................................................... 17
Changes from Revision A (May 2015) to Revision B
Page
•
•
Deleted the min and max limits of –4% and 4% from the current-limit threshold voltage parameter in the Electrical
Characteristics table ............................................................................................................................................................... 6
Added to the current-limit accuracy table note for the programmable current-limit accuracy parameter in the
Electrical Characteristics table ............................................................................................................................................... 6
•
•
•
已添加 graphs for the TPS7B7701-Q1 device in the Typical Characteristics section ........................................................... 7
已删除 the channel 2 PSRR graph in the Typical Characteristics section ............................................................................. 7
已添加 additional test conditions for the 9- to 16-V Line Transient and Power Up graphs in the Typical
Characteristics section .......................................................................................................................................................... 9
•
已添加 additional test conditions of the Power Up graphs in the Application Curves section ............................................. 18
Changes from Original (January 2015) to Revision A
Page
•
发布了完整版数据表 ............................................................................................................................................................... 1
2
Copyright © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
Single-Channel TPS7B7701-Q1 PWP Package
16-Pin HTSSOP With PowerPAD
Top View
Dual-Channel TPS7B7702-Q1 PWP Package
16-Pin HTSSOP With PowerPAD
Top View
IN
EN1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
FB1
IN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
FB
EN2
OUT2
FB2
NC
NC
VCC
NC
VCC
PowerPAD (GND)
PowerPAD (GND)
SENSE
NC
GND
NC
SENSE1
SENSE2
SENSE_SEL
SENSE_EN
GND
LIM2
LIM1
ERR
NC
LIM
ERR
SENSE_EN
Not to scale
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
SINGLE-
CHANNEL
DUAL-
CHANNEL
NAME
EN
2
—
—
9
—
2
Input
Input
Input
Active-high enable input for the OUT pin with internal pulldown.
Active-high enable input for the OUT1 pin with internal pulldown.
Active-high enable input for the OUT2 pin with internal pulldown.
EN1
EN2
ERR
FB
3
9
Output This pin is an open-drain fault indicator for general faults.
15
—
—
12
1
—
15
13
12
1
Input
Input
Input
Feedback input for setting OUT voltage. Connect FB to GND for current-limited switch operation.
Feedback input for setting OUT1 voltage. Connect FB1 to GND for current-limited switch operation.
Feedback input for setting OUT2 voltage. Connect FB2 to GND for current-limited switch operation.
FB1
FB2
GND
IN
Ground Ground reference
Power
Output
Input power-supply voltage
Programmable current-limit pin. Connect a resistor to GND to set the current limitation level. This pin
does not need an external capacitor. To set to internal current limit, short this pin to GND.
LIM
10
—
—
Programmable current-limit pin for channel 1. Connect a resistor to GND to set the current limitation
LIM1
10
Output level for channel 1. This pin does not need an external capacitor. To set to internal current limit, short
this pin to GND.
Programmable current-limit pin for channel 2. Connect a resistor to GND to set the current limitation
Output level for channel 2. This pin does not need an external capacitor. To set to internal current limit, short
this pin to GND.
LIM2
NC
—
11
3, 13, 14
6, 7, 11
16
—
—
—
16
14
—
Not connected. Connect the NC pins to ground or leave floating.
—
Internally connected. These pins must either be floated or connected to GND.
OUT
Power
Power
Power
Output voltage
OUT1
OUT2
—
Output voltage 1
—
Output voltage 2
Output of current sense for sensing. To set the SENSE output voltage level, connect a resistor
SENSE
5
—
5
Output between this pin and GND. In addition, connect a 1-µF capacitor from this pin to GND for frequency
compensation of the current-sense loop. Short this pin to GND if not used.
SENSE1
—
Output Output of current sense for sensing. SENSE1 current is proportional to the current flow through OUT1
and SENSE 2 current is proportional to OUT2 current when SENSE_SEL and SENSE_EN are low. To
set the SENSEx output voltage level, connect a resistor between this pin and GND. In addition,
SENSE2
—
6
Output
connect a 1-µF capacitor from the SENSEx pin to GND for frequency compensation of the current-
sense loop. Short the SENSEx pin to GND if not used.
SENSE_EN
SENSE_SEL
8
8
7
Input
Input
This pin is the enable and disable of the current-sense pin for multiplexing, active-low enable.
—
This pin selects the current sense between channel 1 and channel 2. See 表 2 for details.
Internal 4.5-V regulator. Connect 1-μF ceramic capacitor between VCC and GND for frequency
compensation.
VCC
4
4
Output
Copyright © 2015–2018, Texas Instruments Incorporated
3
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–40
MAX
UNIT
Unregulated input, IN
Input voltage
45
V
V
V
V
V
EN, EN1, and EN2
–0.3
–0.3
–0.3
–0.3
45
(3)(4)
VCC
6
45
Regulated output(2)
OUT1 and OUT2
SENSE, SENSE1, and SENSE2(3)(4)
VCC + 0.3
Low-voltage pins
LIM, LIM1, LIM2, SENSE_EN , SENSE_SEL, ERR, FB, FB1, and
FB2(3)(4)
–0.3
7
V
Operating junction temperature, TJ
Operating ambient temperature, TA
Storage Temperature, Tstg
–40
–40
–65
150
125
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) There is an internal diode connects between the OUT and GND pins with 300-mA DC current capability for inductive clamp protection.
(3) All voltage values are with respect to GND.
(4) Absolute maximum voltage.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Corner pins (1, 8, 9, and 16)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VI
Unregulated input
EN, EN1, and EN2
4.5
0
40
40
V
SENSE, SENSE1, SENSE2, SENSE_EN , SEN_SEL ,
ERR , FB, FB1, FB2, LIM, LIM1, LIM2, and VCC
Low-voltage pins
0
5.3
V
V
Normal-mode operation
Switched-mode operation
1.5
1.5
20
35
OUT1, OUT2, and OUT
CO
Output capacitor stability range
2.2
100
5
µF
Ω
CO(ESR)
TJ
Output capacitor ESR stability range
Junction temperature
0.001
–40
150
125
°C
°C
TA
Ambient temperature
–40
4
Copyright © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
6.4 Thermal Information
TPS7B7701-Q1
TPS7B7702-Q1
PWP
(HTSSOP)
PWP
(HTSSOP)
THERMAL METRIC(1)
UNIT
16 PINS
45.9
29.2
24.7
1.3
16 PINS
40.3
27.7
22.3
0.8
(2)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
24.5
3.7
22
RθJC(bot)
2.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The thermal data is based on JEDEC standard high K profile – JESD 51-7. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated
6.5 Electrical Characteristics
at VI = 14 V and TJ = –40ºC to +150ºC (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VI
Input voltage
4.5
40
1
V
TPS7B7701-Q1: VI = 4.5 to 40 V, V(EN) ≥ 2 V,
I(OUT) = 0.1 mA
0.6
0.6
IQ
Quiescent current
mA
µA
TPS7B7702-Q1: VI = 4.5 to 40 V, V(EN1) and
1
V(EN2) ≥ 2 V, I(OUT1) and I(OUT2) = 0.1 mA
TPS7B7701-Q1: EN = GND
5
5
I(shutdown)
Shutdown current
Operating current
TPS7B7702-Q1: EN1 = EN2 = GND
TPS7B7701-Q1: V(EN) ≥ 2 V, I(OUT) ≤ 300 mA,
GND current
4.5
6
Inom
mA
TPS7B7702-Q1: V(EN1) and V(EN2) ≥ 2 V, I(OUT1)
and I(OUT2) ≤ 300 mA, GND current
V(BG)
V(UVLO)
Vhys
Bandgap
Reference voltage for FB
–2%
1.233
0.4
2%
4
V
V
V
Undervoltage lockout falling
Hysteresis
Ramp IN down until the output turns off
INPUT CONTROL PINS (EN, EN1, EN2, SENSE_EN, AND SENSE_SEL)
For EN, EN1, EN2, SENSE_EN, and
SENSE_SEL
VIL
Logic input low level
0
2
0.7
V
V
For EN, EN1, EN2, SENSE_EN, and
SENSE_SEL
VIH
Logic input high level
II(SENSE_EN)
SENSE_EN input current
V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V
V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V
10
10
10
µA
µA
µA
II(SENSE_SEL) SENSE_SEL input current
II(EN) Enable input current
REGULATED OUTPUT (OUT, OUT1, AND OUT2)
V(ENx) ≤ 40 V
40 V ≥ VI ≥ VO + 1.5 V and VI ≥ 4.5 V, IO = 1 to
VO
Regulated output
Line regulation
Load regulation
–2%
2%
10
20
300 mA(1)
VI = VO + 1.5 V to 40 V and VI ≥ 6 V, IO = 10
mA, voltage variation on FB pin
ΔVO(ΔVI)
ΔVO(ΔIO)
mV
mV
IO = 1 mA to 200 mA, voltage variation on FB
pin
V(DROPOUT)
IO
Dropout voltage
Measured between IN and OUTx, IO = 100 mA
VO in regulation
500
300
mV
mA
dB
Output current
Power supply ripple rejection(2)
0
PSRR
IO = 100 mA, CO = 2.2 µF, ƒ = 100 Hz
73
CURRENT SENSE AND CURRENT-LIMIT
IO/ISENSE
OUTx to SENSEx current ratio (IO / ISENSEx
)
VI = 4.5 V to 40 V, 5 mA ≤ IO ≤ 300 mA
198
(1) External feedback resistor is not considered.
(2) Design information; specified by design, not production tested.
Copyright © 2015–2018, Texas Instruments Incorporated
5
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
at VI = 14 V and TJ = –40ºC to +150ºC (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
–3%
TYP
MAX
UNIT
IO = 100 to 300 mA
3%
5%
IO = 50 to 100 mA
–5%
OUTx to SENSEx current ratio accuracy
IO = 10 to 50 mA
–10%
–20%
10%
20%
IO = 5 to 10 mA
IO/ILIM
I(LIMx)
IL(LIMx)
OUTx to LIMx current ratio (IO / ILIM
Programmable current-limit accuracy(3)
)
VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA
VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA
LIMx shorted to GND
198
–8%
340
8%
Internal current-limit
550
mA
µA
SENSE, SENSE1, SENSE2, LIM, LIM1,
and LIM2 leakage current
Ilkg
ENx = GND, TA = 25°C
2
Voltage on the LIM, LIM1, and LIM2 pins when
output current is limited
V(LIMx_th)
Current-limit threshold voltage
1.233
3.2
V
V
When short-to-battery or reverse current
conditions are detected
V(SENSEx_stb) Current-sense short-to-battery fault voltage
3.05
3.3
Current-sense thermal shutdown fault
V(SENSEx_tsd)
voltage
When thermal shutdown is detected
2.7
2.4
2.85
2.55
3
V
V
V(SENSEx_cl)
Current-sense current-limit fault voltage
When current-limit conditions are detected
2.65
When short-to-battery, reverse current, thermal
shutdown, or current-limit conditions are
detected
I(SENSEx_H)
Current-sense fault condition current
3.3
mA
FAULT DETECTION
V(stb_th) Short-to-battery threshold
I(REV)
V(OUTx) – VI, checked during turnon sequence
Power FET on (SW or LDO mode)
Junction temperature
–500
–100
–55
–40
175
15
110
–1
mV
mA
°C
Reverse current detection level
Thermal shutdown
TSD
TSD(hys)
Thermal shutdown hysteresis
°C
INTERFACE CIRCUITRY
VOL ERR output low
I(SINK) = 5 mA
0.4
1
V
ERR high impedance, 5-V external voltage is
applied at ERR
Ilkg
ERR open-drain leakage current
µA
R(OUTx-off)
IR(lkg)
OUT pulldown resistor(2)
ENx = GND
50
0.6
4.5
kΩ
mA
V
Reverse leakage current
–40 V < VI < 0 V, reverse current to IN
VI = 5.5 to 40 V, ICC = 0 mA
VCC
Internal voltage regulator
4.25
15
4.75
70
ICC(lim)
Internal voltage-regulator current-limit
mA
(3) The current-limit accuracy is maintained when the current limit is set between 50 mA and 300 mA, and it includes the deviation of the
current-limit threshold voltage V(LIMx_th)
.
6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE AND CURRENT-LIMIT
Current-sense delay time from the rising edge
V
(ENx) ≥ 2 V, SENSE_EN = GND,
td(SENSE_SEL_r)
td(SENSE_SEL_f)
td(SENSE_EN_r)
td(SENSE_EN_f)
10
10
10
10
µs
µs
µs
µs
of SENSE_SEL(1)
SENSE_SEL rise from 0 to 5 V
Current-sense delay time from the falling edge
of SENSE_SEL(1)
V(ENx) ≥ 2 V, SENSE_EN = GND,
SENSE_SEL fall from 5 to 0 V
V(ENx) ≥ 2 V, SENSE_EN rise from 0 to
Current-sense delay time from rising edge of
SENSE_EN(1)
5 V
Current-sense delay time from falling edge of
SENSE_EN(1)
V(ENx) ≥ 2 V, SENSE_EN fall from 5 to
0 V
FAULT DETECTION
Delay to shut down the switch or LDO
after a drop over ron becomes negative,
I(OUTx) = –200 mA (typical), TA = 25°C
Reverse current (Short-to-BAT) shutdown
deglitch time
t(PD_RC)
5
20
µs
Blanking time for reverse-current
detection after power up, the rising
edge of the ENx pin, or the current
limiting event is over
t(BLK_RC)
Reverse current blanking time
16
ms
(1) Design information; specified by design; not production tested.
6
Copyright © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
6.7 Typical Characteristics
at VI = 14 V (unless otherwise specified)
4.5
4
3
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
-40èC
25èC
125èC
-40èC
25èC
125èC
0.5
0
0.5
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Current (mA)
Output Current (mA)
D001
D012
图 1. Quiescent Current vs Output Current
图 2. Quiescent Current vs Output Current
(TPS7B7702-Q1)
(TPS7B7701-Q1)
3.5
3
0.8
0.75
0.7
2.5
2
0.65
0.6
1.5
1
0.55
0.5
0
I(shutdown) (VI = 13.5 V)
I(shutdown) (VI = 40 V)
0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
Ambient Temperature (èC)
D002
D003
IO = 0.1 mA
图 3. Shutdown Current vs Ambient Temperature
图 4. Quiescent Current vs Ambient Temperature
(TPS7B7702-Q1)
(TPS7B7702-Q1)
0.6
0.55
0.5
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
0.45
0.4
0.35
1.19
1.18
0.3
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
Ambient Temperature (èC)
D013
D004
IO = 0.1 mA
IO = 10 mA
图 5. Quiescent Current vs Ambient Temperature
图 6. FB Voltage vs Ambient Temperature
(TPS7B7701-Q1)
版权 © 2015–2018, Texas Instruments Incorporated
7
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at VI = 14 V (unless otherwise specified)
1500
306
304
302
300
298
296
294
292
290
-40èC
25èC
125èC
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
D005
D006
ILIM = 300 mA
图 7. Dropout Voltage vs Output Current
图 8. Current Limit vs Ambient Temperature
120
100
80
60
40
20
0
0.52
0.516
0.512
0.508
0.504
0.5
-40èC
25èC
125èC
0.496
0.492
0.488
0.484
0.48
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6 5E+6
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
Frequency (Hz)
D007
D009
CO = 10 µF
IO = 10 mA
图 9. PSRR TPS7B770x-Q1
图 10. Current Sense Ratio vs Output Current, TPS7B7702-
Q1 Channel 1
0.52
-40èC
0.516
0.512
0.508
0.504
0.5
10 V/div
5 V/div
25èC
125èC
IN
OUT1
OUT1
0.496
0.492
0.488
0.484
0.48
200 mV/div AC
100 mA/div
IO
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
D010
VO = 8.5 V
CO = 10 µF
IO = 1 to 170 mA
图 11. Current Sense Ratio vs Output Current, TPS7B7702-
图 12. 1-mA to 170-mA Load Transient
Q1 Channel 2
8
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
Typical Characteristics (接下页)
at VI = 14 V (unless otherwise specified)
10 V/div
5 V/div
IN
IN
5 V/div
20 mV/div AC
OUT2
OUT1
100 mV/div AC
OUT2
20 mV/div AC
OUT2
100 mA/div
IO
VO = 5 V
CO = 10 µF
IO = 1 to 100 mA
VO = 8.5 V
IO = 50 mA
图 13. 1-mA to 100-mA Load Transient
图 14. 9-V to 16-V Line Transient (1 V/µs)
5 V/div
IN
5 V/div
5 V/div
20 mV/div AC
IN
OUT1
OUT1
20 mV/div AC
5 V/div
OUT2
OUT2
VO = 5 V
IO = 50 mA
VO = 8.5 V
IO = 100 mA
VI = 0 to 14 V
图 15. 9-V to 16-V Line Transient (1 V/µs)
图 16. Power Up (1 V/µs)
100
80
60
40
20
5 V/div
5 V/div
Stable Region
IN
OUT1
5 V/div
OUT2
2.2
0.001
1
2
3
4
5
ESR of Output Capacitance (W)
VO = 5 V
IO = 100 mA
VI = 0 to 14 V
图 17. Power Up (1 V/µs)
图 18. Load Capacitance vs ESR of Output Capacitance
版权 © 2015–2018, Texas Instruments Incorporated
9
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS7B770x-Q1 family of devices feature a single- or dual-channel, high voltage LDO with a current-sense
function. These devices operate with a wide input-voltage range of 4.5 V to 40 V (45-V load dump protection).
These devices also offers protection of antenna lines against electrostatic discharge (ESD) and from short-to-
ground, short-to-battery, and thermal overstress. Device output voltage is adjustable from 1.5 V to 20 V through
an external resistor divider. Alternatively, each channel can be configured as a switch.
These devices monitor the load. Accurate current sense allows for detection of open, normal, and short-circuit
conditions without the need of further calibration. The current sense can also be multiplexed between channels
and devices to save ADC resources. Each channel also provides an adjustable current limit with external
resistor.
7.2 Functional Block Diagram
Reverse polarity
OUT1
OUT2
IN
Reverse
current
monitor
Current
sense
EA
FB1
FB2
LIM
ref
1.233 V
FB
V
Current
sense
SENSE_EN
SENSE_SEL
EN1
EN2
Logic control
SENSE1
SENSE2
ERR
Open and
short
protection
LIM1
LIM2
Temperature
sense
UVLO
Internal
reference
Reverse
current
protection
V
CC
Regulator
GND
10
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
7.3 Feature Description
7.3.1 Fault Detection and Protection
The device includes both analog current sense and digital fault pins for full diagnostics of different fault
conditions.
The current-sense voltage scale is selected based on the output-current range of interest. 图 19 shows a
recommended setting that allows for full diagnostics of each fault. Before the device goes into current-limit mode,
the output current-sense voltage is linearly proportional to the actual load current. During a thermal-shutdown
(TSD) and short-to-battery (STB) condition, the current-sense voltage is set to the fault voltage level that is
specified in the Electrical Characteristics table.
3.3
Reverse Current and Short to Battery
3.2 V (Typical)
3.05
3.0
Thermal Shutdown
2.85 V (Typical)
2.7
2.65
2.4
Short Circuit and Current limit
(2.55 V Typical)
Linear Current Sense
Band Up to 2.4 V
Overcurrent
Open load
Normal
Short Circuit
Operating Range
图 19. Functionality of the Current-Sense Output
7.3.2 Short-Circuit and Overcurrent Protection
The current limit on each channel is programmed by selecting the external resistor. The voltage on LIMx pin is
compared with an internal voltage reference. When the threshold is exceeded, the current limit is triggered. The
output of the current limited channel continues to remain on and the current is limited.
Under current-limit status, the ERR pin asserts low and the SENSE voltage of the fault channel is internally
pulled up to a voltage rail between 2.4 V and 2.65 V as shown in 图 19. At this moment, the output voltage is not
disabled. The microcontroller (MCU) should monitor the voltage at the SENSEx pin or ERR pin to disable the
faulted channel by pulling the ENx pin low. If a current-limit condition exists for a long period of time, thermal
shutdown can be triggered and shutdown the output.
7.3.3 Short-to-Battery and Reverse Current Detection
Shorting the OUT pin to the battery because of a fault in the system is possible. Each channel detects this failure
by comparing the voltage at the OUT and IN pins before the switch turns on. Each time the LDO switch is
enabled on the rising edge of the EN pin or during the exiting of the thermal shutdown, the short-to-battery
detection occurs. At this moment, if the device detects the short-to-battery fault, the LDO switch is latched off, the
ERR pin is asserted low, and the fault-channel SENSE voltage is pulled up internally to a voltage rail between
3.05 V and 3.3 V. The device operates normally when the short-to-battery is removed and the EN pin is toggled.
版权 © 2015–2018, Texas Instruments Incorporated
11
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Feature Description (接下页)
During normal operation if a short-to-battery fault results in reverse current for more than 5 µs (typical), the LDO
switch is latched off and the ERR pin is asserted low. To remove the latched condition after a short-to-battery
(reverse current) fault, the condition must first be removed and then the EN pin must be toggled.
Series inductance and the output capacitor can produce ringing during power up or recovery from current limit,
resulting in an output voltage that temporarily exceeds the input voltage. The 16-ms (typical) reverse-current
blanking can help filter this ringing.
For the dual-channel antenna LDO application, if both channels are enabled and one channel is shorted to
ground after power up, the current drawn from the input capacitor can result in a temporary dip in the input
voltage, which can trigger the reverse-current detection fault. To avoid this false trigger event, care must be
taken when selecting the input capacitor; an increase of the input capacitor value is recommended.
7.3.4 Thermal Shutdown
The device incorporates a TSD circuit as a protection from overheating. For continuous normal operation, the
junction temperature should not exceed the TSD trip point. If the junction temperature exceeds the TSD trip
point, the output is turned off. When the junction temperature decreases by 15°C (typical) than the TSD trip point,
the output is turned on again. The SENSE voltage is internally pulled up to a voltage rail between 2.7 V and 3 V
during TSD status.
注
The purpose of the design of the internal protection circuitry of the TPS7B770x-Q1 family
of devices is to protect against overload conditions and is not intended as a replacement
for proper heat-sinking. Continuously running the device into thermal shutdown degrades
device reliability.
7.3.5 Integrated Reverse-Polarity Protection
The device integrates a reverse-connected PMOS to block the reverse current during reverse polarity at the input
and output short-to-battery condition. A special ESD structure at the input is specified to withstand –40 V.
7.3.6 Integrated Inductive Clamp
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp to help dissipate the inductive energy stored in the cable. An internal diode
is connected between OUT and GND pins with a DC-current capability of 300 mA for inductive clamp protection.
7.3.7 Undervoltage Lockout
The device includes an undervoltage lockout (UVLO) threshold that is internally fixed. The undervoltage lockout
activates when the input voltage on the IN pin drops below V(UVLO). The UVLO makes sure that the regulator is
not latched into an unknown state during low input-supply voltage. If the input voltage has a negative transient
that drops below the UVLO threshold and then recovers, the regulator shuts down and powers up with a normal
power-up sequence when the input voltage is above the required levels.
表 1. Fault Table
FAILURE MODE
Open load
V(SENSE)
ERR
HIGH
HIGH
HIGH
LDO SWITCH OUTPUT
Enabled
LATCHED
No
No
No
I
ì R
(SENSE)
O
Normal
Enabled
198
Overcurrent
Enabled
Short-circuit or current
limit
2.4 to 2.65 V
LOW
Enabled
No
Thermal shutdown
Output short-to-battery
Reverse current
2.7 to 3 V
3.05 to 3.3 V
3.05 to 3.3 V
LOW
LOW
LOW
Disabled
Disabled
Disabled
No
Yes
Yes
12
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
7.3.8 Enable (EN, EN1, and EN2)
The TPS7B7702-Q1 device features two active-high enable inputs, EN1 and EN2. The EN1 pin controls output
voltage 1, OUT1, and the EN2 pin controls output voltage 2, OUT2. The devices consumes a maximum of
shutdown current 5-µA when the ENx pins are low. Both the EN1 and EN2 pins have a maximum internal
pulldown of 10 µA.
The TPS7B7701-Q1 device features one active-high enable input. The device consumes a maximum shutdown
current of 5 µA when the EN pin is low. The EN pin has a maximum internal pull down of 10 µA.
7.3.9 Internal Voltage Regulator (VCC
)
The device features an internal regulator that regulates the input voltage to 4.5 V to power all internal circuitry.
Bypass a 1-µF ceramic capacitor from the VCC pin to the GND pin for frequency compensation. The VCC pin can
be used as a power supply for external circuitry with up to 15-mA current capability.
7.3.10 Current Sense Multiplexing
The two, independent current sense pins (one for each channel) provide flexibility in the system design. When
the ADC resource is limited, the device allows the multiplexing of the current sense pins by only using one
current sense pin and one ADC to monitor all the antenna outputs.
The SENSE_SEL pin (TPS7B7702-Q1 only) selects the channels to monitor the current. The SENSE_EN pin
enables and disables the SENSE pin, allowing multiplexing between chips. Therefore, only one ADC and one
resistor is needed for current-sense diagnostics of multiple outputs. When the SENSE1 pin is connected to an
ADC, the current flow through both channels can be sensed by changing the electrical level at the SENSE_SEL
pin.
表 2 lists the selection logic for the current sense.
表 2. SENSE_EN and SEN_SEL Logic Table
SENSE_EN
LOW
SEN_SEL
LOW
SENSE1 Status
CH1 current
SENSE2 Status
CH2 current
LOW
HIGH
—
CH2 current
HIGH impedance
HIGH impedance
HIGH
HIGH impedance
图 20 shows the application of four antenna channels sharing one ADC resource.
Current
Sense
SENSE_EN
Antenna AM/FM
SENSE_SEL
SENSE2
Antenna FM2
SENSE1
MCU
Current
Sense
SENSE_EN
ADC
Antenna DAB
Antenna GPS
R(SENSE)
SENSE_SEL
SENSE2
SENSE1
图 20. Current Multiplexing Application Block
版权 © 2015–2018, Texas Instruments Incorporated
13
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
7.3.11 Adjustable Output Voltage (FB, FB1, and FB2)
Using an external resistor divider selects an output voltage between 1.5 V and 20 V. Use 表 2 to calculate the
output voltage (VO). The recommended value for both R1 and R2 is less than 100 kΩ.
V
ì (R1+ R2)
(FB)
V
=
O
R2
where
•
V(FB) = 1.233 V
(1)
OUT
R1
R2
TPS7B770x-Q1
FB
图 21. TPS7B770x-Q1 Output Voltage Setting Connection
The TPS7B770x-Q1 family of devices can also be used as a current-limited switch by connecting the FB pin to
the GND pin.
7.4 Device Functional Modes
7.4.1 Operation With IN < 4.5 V
The maximum UVLO voltage is 4 V and the device operates at an input voltage above 4.5V. The device can also
operate at lower input voltage. No minimum UVLO voltage is specified. At an input voltage below the actual
UVLO voltage, the device does not operate.
7.4.2 Operation With EN Control
The threshold of EN rising edge is 2 V (maximum). With the EN pin held above that voltage and the input voltage
above 4.5 V, the device becomes active. The EN falling edge is 0.7 V (minimum). Holding the EN pin below that
voltage disables the device which therefore reduces the quiescent current of the device.
14
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B770x-Q1 family of devices is a single- or dual-channel 300-mA LDO regulator with high, accurate
current sense and a programmable current-limit function. Use the PSPICE transient model to evaluate the base
function of the devices. Go to www.ti.com to download the PSPICE model and user's guide for the devices.
8.2 Typical Application
图 22 shows the typical application circuit for the TPS7B770x-Q1 family of devices. Different values of external
components can be used depending on the end application. An application can require a larger output capacitor
during fast load steps to prevent large drops on output voltage. TI recommends a low-ESR ceramic capacitor
with a dielectric of type X5R or X7R.
Active antenna
Filter coil
Reverse polarity
Filter coil
OUT1
OUT2
IN
Battery
Input
Cable
10 µF
10 µF
Reverse
current
monitor
Current
sense
EA
FB1
FB2
LIM
FB
V
ref
Current
sense
SENSE_EN
MCU I/O
1.233 V
SENSE_SEL
MCU I/O
EN1
EN2
Logic control
MCU I/O
MCU I/O
SENSE1
SENSE2
ERR
R
Open and
short
(SENSE)
1 µF
protection
LIM1
LIM2
Temperature
sense
UVLO
R
(LIM)
Internal
reference
Reverse
current
protection
V
CC
Regulator
1 µF
GND
图 22. TPS7B770x-Q1 Typical Application
版权 © 2015–2018, Texas Instruments Incorporated
15
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Typical Application (接下页)
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 3 as the design parameters.
表 3. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 40 V
Output voltage
1.5 to 20 V
Output capacitor range
Output Capacitor ESR range
SENSE resistor
2.2 to 100 µF
0.001 to 5 Ω
See the Current Sense Resistor Selection section
Programmable current limit
50 to 300 mA
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
•
•
Input voltage
Output voltage
Output current
Current limit
ADC voltage rating
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value should be between
2.2 µF and 100 µF. The ESR range should be between 1 mΩ and 5 Ω. TI recommends selecting a ceramic
capacitor with low ESR to improve the load transient response.
8.2.2.3 Current Sense Resistor Selection
The current-sense outputs, SENSEx (SENSE, SENSE1, and SENSE2), are proportional to the output current at
the OUT, OUT1, and OUT2 pins with a factor of 1/198. An output resistor, R(SENSE), must be connected between
the SENSEx pin and ground to generate a current sense voltage to be sampled by ADC. Use 公式 2 to calculate
the voltage at SENSEx pin (V(SENSEx)).
V
= I(SENSEx) ì R(SENSEx)
(SENSEx)
where
I(OUTx)
I(SENSEx)
=
198
•
(2)
For this example, select 1.5 kΩ as a value for R(SENSEx). Do not consider the resistor and current-sense accuracy.
For a load current of 198 mA, use 公式 3 to calculate the value of V(SENSEx)
.
198 mA
I(SENSEx)
=
= 1mA ç V
= 1mA ì 1.5 kW = 1.5 V
(SENSEx)
198
(3)
16
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
To avoid any overlap between normal operation and current-limit or short-to-ground phase, using 公式 4 to select
the value of the SENSE resistor is recommended.
198 ì 2.4 V
R(SENSEx)
Ç
IOmax
where
•
•
•
198 is the output current to current-sense ratio
2.4 V is the minimum possible voltage at the SENSEx pin under a short-circuit fault case
IOmax is the maximum possible output current under normal operation
(4)
To stabilize the current-sense loop, connecting a 1-µF ceramic capacitor at the SENSE, SENSE1, or SENSE2
pin is required. 表 4 lists the current sense accuracy across temperature.
表 4. Current Sense Accuracy
OUTPUT CURRENT
5 mA to 10 mA
CURRENT SENSE ACCURACY
20%
10%
5%
10 mA to 50 mA
50 mA to 100 mA
100 mA to 300 mA
3%
8.2.2.4 Current-Limit Resistor Selection
The current at the LIMx pins (LIM, LIM1, and LIM2) is proportional to the load current at the OUTx (OUT, OUT1,
and OUT2) pins and is internally connected to a current-limit comparator referenced to 1.233 V. The current limit
is programmable through the external resistor connected at LIMx pin. Use 公式 5 to calculate the value of the
external resistor, R(LIMx). The programmable current limit accuracy is 8% maximum across all conditions. The
internal current limit of the device is set by shorting the LIM pin to ground. Because the current limit varies by
8%, 公式 6 shows how to calculate the minimum current limit value, and 公式 7 shows how to calculate the
maximum current limit value.
1.233 V
R(LIMx)
=
ì 198
I(LIMx)
where
1.233 V
I(LIMx)(typ)
=
ì 198
R(LIMx)
•
(5)
(6)
(7)
≈
’
1.233 V
R(LIMx)
I(LIMx)(min) = I(LIMx)(typ) ì0.92 = 0.92
ì198
ì198
∆
∆
«
÷
÷
◊
(
)
≈
’
1.233 V
R(LIMx)
I(LIMx)(max) = I(LIMx)(typ) ì1.08 = 1.08
∆
∆
«
÷
÷
◊
(
)
Select a maximum current-limit value of 200 mA and use 公式 8 to calculate the value of R(LIMx)
.
1.08ì198ì1.233 V
R(LIMx)
=
I(LIMx)(max)
(8)
Using 公式 8 yields a RLIMx value of 1.318 kΩ. The closest 1% resistor that can be selected is 1.33 kΩ. Now
using 公式 7 and plugging in 1.33 kΩ for RLIMx yields a maximum current of 198.2 mA. Keep in mind this result
does not include resistor tolerance in the calculation. To make sure that the current does not exceed the set
amount, resistor tolerance must also be included in the equation.
版权 © 2015–2018, Texas Instruments Incorporated
17
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
8.2.3 Application Curves
5 V/div
5 V/div
5 V/div
IN
IN
5 V/div
OUT1
OUT1
5 V/div
OUT2
5 V/div
OUT2
VO = 8.5 V
IO = 100 mA
VI = 0 to 14 V
VO = 5 V
IO = 100 mA
VI = 0 to 14 V
图 23. Power Up (1 V/µs)
图 24. Power Up (1 V/µs)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply with a range between 4.5 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B770x-Q1
device, TI recommends adding an 10-µF electrolytic capacitor and a ceramic bypass capacitor at the input.
10 Layout
10.1 Layout Guidelines
For the layout of TPS7B770x-Q1 device, place the input and output capacitors close to the device as shown in 图
25. To enhance the thermal performance, TI recommends surrounding the device with some vias.
Minimize equivalent-series inductance (ESL) and ESR to maximize performance and provide stability. Place
every capacitor as close as possible to the device and on the same side of the PCB as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use long traces because they can negatively impact system performance and cause
instability.
If possible, and to maintain the maximum performance specified in this device data sheet, use the same layout
pattern used for the TPS7B770x-Q1 evaluation board, available online at www.ti.com/tool/TPS7B7702EVM.
18
版权 © 2015–2018, Texas Instruments Incorporated
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com.cn
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
10.2 Layout Example
VIN
OUT1
OUT2
GND
Thermal Pad
(GND)
图 25. TPS7B770x-Q1 Layout Example
版权 © 2015–2018, Texas Instruments Incorporated
19
TPS7B7701-Q1, TPS7B7702-Q1
ZHCSDQ2C –JANUARY 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档:
《TPS7B7702-Q1 评估模块用户指南》
11.2 相关链接
表 5 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPS7B7701-Q1
TPS7B7702-Q1
11.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
20
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B7701QPWPRQ1
TPS7B7702QPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
7B7701
7B7702
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B7701QPWPRQ1 HTSSOP PWP
TPS7B7702QPWPRQ1 HTSSOP PWP
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B7701QPWPRQ1
TPS7B7702QPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明