TPS7B8233QDRVRQ1 [TI]
TPS7B82-Q1 Automotive 300-mA, High-Voltage, Ultra-Low-IQ Low-Dropout Regulator;
| 型号： | TPS7B8233QDRVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS7B82-Q1 Automotive 300-mA, High-Voltage, Ultra-Low-IQ Low-Dropout Regulator |
| 文件： | 总34页 (文件大小：3029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B82-Q1
SLVSDQ0I – SEPTEMBER 2017 – REVISED AUGUST 2021
TPS7B82-Q1 Automotive 300-mA, High-Voltage, Ultra-Low-IQ Low-Dropout Regulator
1 Features
3 Description
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C ≤ TA ≤ 125°C
– Temperature grade 0: –40°C ≤ TA ≤ 150°C
Extended junction temperature range:
– Grade 1: –40°C ≤ TJ ≤ 150°C
– Grade 0: –40°C ≤ TJ ≤ 165°C
Low quiescent current IQ:
– 300-nA shutdown IQ
– 2.7 µA typical at light loads
– 5 µA maximum at light loads
3-V to 40-V wide VIN input voltage range with up to
45-V transient
In automotive battery-connected applications, low
quiescent current (IQ) is important to save power and
extend battery lifetime. Ultra-low IQ must be included
for always-on systems.
The TPS7B82-Q1 is a low-dropout linear regulator
designed to operate with a wide input-voltage range
from 3 V to 40 V (45-V load dump protection).
Operation down to 3 V allows the TPS7B82-Q1 to
continue operating during cold-crank and start and
stop conditions. With only 2.7-µA typical quiescent
current at light load, this device is an optimal solution
for powering microcontrollers (MCUs) and CAN/LIN
transceivers in standby systems.
•
•
•
•
Maximum output current: 300 mA
2% output-voltage accuracy
The device features integrated short-circuit and
overcurrent protection. This device operates in
ambient temperatures from –40°C to +125°C and
with junction temperatures from –40°C to +150°C.
Additionally, this device uses a thermally conductive
package to enable sustained operation despite
significant dissipation across the device. Because of
these features, the device is designed as a power
supply for various automotive applications.
Maximum dropout voltage: 700 mV at 200-mA load
current for fixed 5-V output version
Stable with low-ESR (0.001-Ω to 5-Ω) ceramic
output-stability capacitor (1 µF to 200 µF)
Fixed 2.5-V, 3.3-V, and 5-V output voltage
Packages:
– 8-pin HVSSOP, RθJA = 63.9°C/W
– 6-pin WSON, RθJA = 72.8°C/W
– 5-pin TO-252, RθJA = 31.1°C/W
– 14-pin HTSSOP, RθJA = 52.0°C/W
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
6.10 mm × 6.60 mm
5.00 mm x 4.40 mm
2 Applications
HVSSOP (8)
•
•
•
•
•
Automotive head units
Telematics control units
Headlights
Body control modules
Inverter and motor controls
WSON (6)
TPS7B82-Q1
TO-252 (5)
HTSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B82-Q1
SLVSDQ0I – SEPTEMBER 2017 – REVISED AUGUST 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Grade 1 Options................ 5
6.6 Electrical Characteristics: Grade 0 Options................ 6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................15
10 Layout...........................................................................15
10.1 Layout Guidelines................................................... 15
10.2 Layout Example...................................................... 15
11 Device and Documentation Support..........................16
11.1 Receiving Notification of Documentation Updates..16
11.2 Support Resources................................................. 16
11.3 Trademarks............................................................. 16
11.4 Electrostatic Discharge Caution..............................16
11.5 Glossary..................................................................16
12 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2021) to Revision I (August 2021)
Page
•
•
•
Changed IQ parameter maximum specifications from 3.5 μA to 5 μA and from 4.5 μA to 6.5 μA in the
Electrical Characteristics: Grade 0 Options table............................................................................................... 6
Changed V(Load-Reg) parameter maximum specification from 10 mV to 20 mV in the Electrical Characteristics:
Grade 0 Options table.........................................................................................................................................6
Changed VOUT parameter test condition from 40 V to 14 V in the Electrical Characteristics: Grade 0 Options
table....................................................................................................................................................................6
Changes from Revision G (July 2020) to Revision H (March 2021)
Page
•
•
•
•
•
•
•
•
Added PWP (HTSSOP) package to document...................................................................................................1
Added grade 0 information to Features section..................................................................................................1
Deleted Thermal resistance bullet from Features section.................................................................................. 1
Changed RθJA rating from 38.8°C/W to 31.1°C/W in TO-252 Packages sub-bullet............................................1
Added grade 0 information to junction temperature parameter in Absolute Maximum Ratings .........................4
Added grade 0 information to Recommended Operating Conditions table........................................................ 4
Added grade 1 options to condition statement of Electrical Characteristics table.............................................. 5
Added Electrical Characteristics: Grade 0 Options table....................................................................................6
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5 Pin Configuration and Functions
IN
EN
1
2
3
6
5
4
OUT
DNC
GND
IN
EN
1
2
3
4
8
7
6
5
OUT
NC
Thermal
Pad
Thermal
Pad
NC
GND
GND
GND
GND
Not to scale
Not to scale
Figure 5-2. DRV Package, 6-Pin WSON
PowerPAD™, Top View
Figure 5-1. DGN Package, 8-Pin HVSSOP
PowerPAD™, Top View
IN
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT
NC
GND
EN
NC
Thermal
Pad
NC
NC
GND
NC
DNC
NC
NC
8
NC
Not to scale
Not to scale
Figure 5-4. PWP Package, 14-Pin HTSSOP, Top
View
Figure 5-3. KVU Package, 5-Pin TO-252, Top View
NC – No internal connection
Table 5-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DGN
DRV
KVU
PWP
Do not connect to a biased voltage. Tie this pin to ground or leave
floating.
DNC
—
5
4
10
—
EN
2
4, 5, 6
1
2
3,4
1
2
3, TAB
1
3
5
1
I
—
I
Enable input pin
GND
IN
Ground reference
Input power-supply pin
2, 4, 6, 7,
8, 9, 11,
12, 13
NC
3, 7
8
—
6
—
5
—
Not internally connected
OUT
14
O
Regulated output voltage pin
Connect the thermal pad to a large-area GND plane for improved
thermal performance.
Thermal pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–40
–40
–40
MAX
45
UNIT
VIN
Unregulated input(3)
V
V
V
VEN
VOUT
Enable input(3)
VIN
7
Regulated output
Junction temperature (grade 1)
Junction temperature (grade 0)
Storage temperature range
150
165
150
TJ
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to GND.
(3) Absolute maximum voltage, withstand 45 V for 200 ms.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level H2
±2000
V(ESD)
Electrostatic discharge
Corner pins
(1, 4, 5, and 8)
V
±750
±500
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C3B
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
3
MAX
40
UNIT
V
VIN
Unregulated input voltage
VEN
COUT
ESR
Enable input voltage
0
VIN
200
5
V
Output capacitor requirements(1)
Output capacitor ESR requirements(2)
Ambient temperature (grade 1)
Ambient temperature (grade 0)
Junction temperature (grade 1)
Junction temperature (grade 0)
1
µF
Ω
0.001
–40
–40
–40
–40
125
150
150
165
TA
TJ
°C
°C
(1) The output capacitance range specified in the table is the effective value.
(2) Relevant equivalent series resistance (ESR) value at f = 10 kHz.
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6.4 Thermal Information
TPS7B82-Q1
DGN
(HVSSOP)
DRV
(WSON)
KVU
(TO-252)
PWP
(HTSSOP)
THERMAL METRIC(1)
UNIT
8 PINS
63.9
50.2
22.6
1.8
6 PINS
72.8
85.8
37.4
2.7
5 PINS
31.1
39.9
9.9
14 PINS
52.0
48.2
28.2
2.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.2
ψJB
22.3
12.1
37.3
13.8
9.9
28.1
10.7
RθJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Grade 1 Options
VIN = 14-V, 10-µF ceramic output capacitor, grade 1 options, TJ = –40°C to +150°C, over operating ambient temperature
range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VOUT(NOM)
+ V(Dropout)
VIN
Input voltage
40
1
V
I(SD)
Shutdown current
EN = 0 V
0.3
1.9
1.9
2.7
2.7
µA
DRV and KVU
packages
3.5
5
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0 mA
DGN package
I(Q)
Quiescent current
DRV and KVU
packages
4.5
µA
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0.2 mA
DGN package
6.5
2.7
Ramp VIN down until the output turns OFF
Hysteresis
V
V(IN, UVLO) VIN undervoltage detection
200
mV
ENABLE INPUT (EN)
VIL
VIH
Logic-input low level
Logic-input high level
0.7
V
V
2
REGULATED OUTPUT (OUT)
DRV and KVU
packages
–1.5%
–2%
1.5%
VIN = VOUT + V(Dropout) to 40 V,
IOUT = 1 mA to 300 mA
VOUT
Regulated output
DGN package
2%
10
V(Line-Reg) Line regulation
V(Load-Reg) Load regulation
VIN = 6 V to 40 V, IOUT = 10 mA
mV
mV
DRV and KVU
packages
10
20
VIN = 14 V, IOUT = 1 mA to 300 mA
DGN package
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6.5 Electrical Characteristics: Grade 1 Options (continued)
VIN = 14-V, 10-µF ceramic output capacitor, grade 1 options, TJ = –40°C to +150°C, over operating ambient temperature
range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRV and KVU
packages
630
1170
IOUT = 300 mA
DGN package
1000
DRV and KVU
packages
420
400
210
200
730
780
VOUT(NOM) = 5 V
IOUT = 200 mA
IOUT = 100 mA
IOUT = 300 mA
DGN package
700
DRV and KVU
packages
390
V(Dropout) Dropout voltage(1)
mV
DGN package
350
DRV and KVU
packages
1350
1250
900
DGN package
VOUT = 3.3 V
DRV and KVU
packages
475
IOUT = 200 mA
IOUT = 100 mA
DGN package
850
450
IOUT
I(CL)
Output current
VOUT in regulation
0
300
690
mA
mA
Output current limit
VOUT short to 90% × VOUT
310
510
60
Power-supply ripple
rejection
V(Ripple) = 0.5 VPP, IOUT = 10 mA, frequency = 100 Hz,
COUT = 2.2 µF
PSRR
dB
OPERATING TEMPERATURE RANGE
Junction shutdown
temperature
T(SD)
175
20
°C
°C
Hysteresis of thermal
shutdown
T(HYST)
(1) Dropout is not valid for the 2.5-V output because of the minimum input voltage limits.
6.6 Electrical Characteristics: Grade 0 Options
VIN = 14-V, 10-µF ceramic output capacitor, grade 0 options (PWP package), TJ = –40°C to +165°C, over operating ambient
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VOUT(NOM)
+ V(Dropout)
VIN
Input voltage
40
1
V
I(SD)
Shutdown current
EN = 0 V
0.3
1.9
µA
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0 mA
5
I(Q)
Quiescent current
VIN = 6 V to 40 V, EN ≥ 2 V,
IOUT = 0.2 mA
2.7
6.5
2.7
µA
Ramp VIN down until the output turns OFF
Hysteresis
V
V(IN, UVLO) VIN undervoltage detection
200
mV
ENABLE INPUT (EN)
VIL
VIH
Logic-input low level
Logic-input high level
0.7
V
V
2
REGULATED OUTPUT (OUT)
VIN = VOUT + V(Dropout) to 14 V,
IOUT = 1 mA to 300 mA
VOUT
Regulated output
–1.5%
1.5%
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6.6 Electrical Characteristics: Grade 0 Options (continued)
VIN = 14-V, 10-µF ceramic output capacitor, grade 0 options (PWP package), TJ = –40°C to +165°C, over operating ambient
temperature range (unless otherwise noted)
PARAMETER
V(Line-Reg) Line regulation
V(Load-Reg) Load regulation
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN = 6 V to 40 V, IOUT = 10 mA
10
20
mV
mV
VIN = 14 V, IOUT = 1 mA to 300 mA
IOUT = 300 mA
630
420
210
730
475
1170
780
390
1350
900
450
300
690
VOUT(NOM) = 5 V
IOUT = 200 mA
IOUT = 100 mA
IOUT = 300 mA
IOUT = 200 mA
IOUT = 100 mA
V(Dropout) Dropout voltage(1)
mV
VOUT = 3.3 V
IOUT
I(CL)
Output current
VOUT in regulation
0
mA
mA
Output current limit
VOUT short to 90% × VOUT
310
510
60
Power-supply ripple
rejection
V(Ripple) = 0.5 VPP, IOUT = 10 mA, frequency = 100 Hz,
COUT = 2.2 µF
PSRR
dB
OPERATING TEMPERATURE RANGE
Junction shutdown
temperature
T(SD)
185
20
°C
°C
Hysteresis of thermal
shutdown
T(HYST)
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6.7 Typical Characteristics
VIN = 14 V, VEN ≥ 2 V, TJ = –40°C to 150°C (unless otherwise noted)
750
3000
2500
2000
1500
1000
500
IOUT = 1 mA
IOUT = 100 mA
IOUT = 200 mA
600
450
300
150
-40°C
25°C
125°C
0
0
-500
0
50
100
150
Output Current (mA)
200
250
300
0
5
10
15
Input Voltage (V)
20
25
30
35
40
D001
D002
VOUT = 5 V
VOUT = 5 V
Figure 6-1. Quiescent Current vs Output Current
Figure 6-2. Quiescent Current vs Input Voltage
0.5
500
IOUT = 1 mA
IOUT = 100 mA
400
0.4
0.3
0.2
0.1
0
300
200
100
0
-100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D003
D004
VEN = 0 V
VOUT = 5 V
Figure 6-3. Shutdown Current vs Ambient Temperature
Figure 6-4. Quiescent Current vs Ambient Temperature
800
700
600
500
400
300
800
700
600
500
400
300
200
100
0
200
-40°C
25°C
125°C
100
0
0
50
100
150
Output Current (mA)
200
250
300
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D005
D006
VIN = 5 V, 5-V fixed output, V(Dropout) = VIN – VOUT
VIN = 5 V, 5-V fixed output, V(Dropout) = VIN – VOUT
Figure 6-5. Dropout Voltage vs Output Current
Figure 6-6. Dropout Voltage vs Ambient Temperature
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6.7 Typical Characteristics (continued)
VIN = 14 V, VEN ≥ 2 V, TJ = –40°C to 150°C (unless otherwise noted)
5.1
5.5
5
4.5
4
5.05
5
3.5
3
2.5
2
1.5
1
4.95
-40èC
25èC
125èC
0.5
0
4.9
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
0
5
10
15
20
25
Input Voltage (V)
30
35
40
D007
D008
VOUT = 5 V
Figure 6-7. Output Voltage vs Ambient Temperature
VOUT = 5 V, IOUT = 1 mA
Figure 6-8. Output Voltage vs Input Voltage
700
1
0.8
0.6
0.4
0.2
0
-40°C
25°C
125°C
600
500
400
300
200
100
0
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
150
Output Current (mA)
200
250
300
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D010
D009
VOUT = 5 V
VIN = 14 V, VOUT is shorted to 90% × VOUT
Figure 6-10. Load Regulation
Figure 6-9. Output Current Limit vs Ambient Temperature
1
125
100
75
-40°C
25°C
125°C
0.8
0.6
0.4
0.2
0
50
-0.2
-0.4
-0.6
-0.8
-1
25
0
-25
0
5
10
15
Input Voltage (V)
20
25
30
35
40
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
D011
D012
VOUT = 5 V, IOUT = 10 mA
IOUT = 10 mA
Figure 6-11. Line Regulation
Figure 6-12. PSRR vs Frequency
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6.7 Typical Characteristics (continued)
VIN = 14 V, VEN ≥ 2 V, TJ = –40°C to 150°C (unless otherwise noted)
125
200
100
100
75
50
25
0
10
-25
10
1
0.001
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
0.01
0.1
ESR (W)
1
5
D013
D014
IOUT = 100 mA
Figure 6-13. PSRR vs Frequency
Figure 6-14. Output Capacitance vs ESR Stability
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7 Detailed Description
7.1 Overview
The TPS7B82-Q1 is a 40-V, 300-mA low-dropout (LDO) linear regulator with ultra-low quiescent current. This
voltage regulator consumes only 3 μA of quiescent current at light load, and is designed for the automotive
always-on application.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Device Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulation ON. Connect
this pin to an external microcontroller or a digital circuit to enable and disable the device, or connect to the IN pin
for self-bias applications.
7.3.2 Undervoltage Shutdown
This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage
(VIN) falls below an internal UVLO threshold (V(UVLO)). This threshold limit ensures that the regulator does not
latch into an unknown state during low-input-voltage conditions. If the input voltage has a negative transient that
drops below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up
sequence when the input voltage is above the required level.
7.3.3 Current Limit
This device features current-limit protection to keep the device in a safe operating area when an overload
or output short-to-ground condition occurs. This limit protects the device from excessive power dissipation.
For example, during a short-circuit condition on the output, fault protection limits the current through the pass
element to I(LIM) to protect the device from excessive power dissipation.
7.3.4 Thermal Shutdown
This device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature must not exceed the TSD trip point. The junction temperature
exceeding the TSD trip point causes the output to turn off. When the junction temperature falls below the TSD
trip point minus thermal shutdown hysteresis, the output turns on again.
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7.4 Device Functional Modes
7.4.1 Operation With VIN Lower Than 3 V
The device normally operates with input voltages above 3 V. The device can also operate at lower input
voltages; the maximum UVLO voltage is 2.7 V. At input voltages below the actual UVLO voltage, the device does
not operate.
7.4.2 Operation With VIN Larger Than 3 V
When VIN is greater than 3 V, if VIN is also higher than the output set value plus the device dropout voltage, VOUT
is equal to the set value. Otherwise, VOUT is equal to VIN minus the dropout voltage.
Copyright © 2021 Texas Instruments Incorporated
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TPS7B82-Q1
SLVSDQ0I – SEPTEMBER 2017 – REVISED AUGUST 2021
www.ti.com
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS7B82-Q1 is a 300-mA, 40-V low-dropout linear regulator with ultra-low quiescent current. The PSpice
transient model is available for download on the product folder and can be used to evaluate the basic function of
the device.
8.2 Typical Application
Figure 8-1 shows a typical application circuit for the TPS7B82-Q1. Different values of external components can
be used, depending on the end application. An application may require a larger output capacitor during fast load
steps to prevent a large drop on the output voltage. Use a low-ESR ceramic capacitor with a dielectric of type
X5R or X7R.
Figure 8-1. TPS7B82-Q1 Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1.
Table 8-1. Design Requirements Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
3 V to 40 V
5 V or 3.3 V
Output current
300 mA maximum
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
•
Input voltage range
Output voltage
Output current
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8.2.2.1 Input Capacitor
Although an input capacitor is not required for stability, good analog design practice is to connect a 10-µF to
22-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple rejection, and PSRR. The voltage rating must be greater than the maximum input voltage.
8.2.2.2 Output Capacitor
To ensure the stability of the TPS7B82-Q1, the device requires an output capacitor with a value in the range from
1 μF to 200 μF and with an ESR range between 0.001 Ω and 5 Ω. Select a ceramic capacitor with low ESR to
improve the load transient response.
8.2.3 Application Curve
Figure 8-2. TPS7B82-Q1 Power-Up Waveform (5 V)
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www.ti.com
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 3 V to 40 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the TPS7B82-Q1, add a capacitor
with a value greater than or equal to 10 μF with a 0.1-μF bypass capacitor in parallel at the input.
10 Layout
10.1 Layout Guidelines
For LDO power supplies, especially high-voltage and large output current supplies, layout is an important step.
If layout is not carefully designed, the regulator can fail to deliver enough output current because of thermal
limitation. To improve the thermal performance of the device, and to maximize the current output at high ambient
temperature, spread the copper under the thermal pad as far as possible and place enough thermal vias on the
copper under the thermal pad. Figure 10-1 shows an example layout.
10.2 Layout Example
GND
IN
1
2
3
4
8
7
6
5
OUT
EN
GND
Figure 10-1. TPSB82-Q1 Example Layout Diagram
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B8225QDGNRQ1
TPS7B8233EPWPRQ1
TPS7B8233QDGNRQ1
TPS7B8233QDRVRQ1
TPS7B8233QKVURQ1
TPS7B8250EPWPRQ1
TPS7B8250QDGNRQ1
TPS7B8250QDRVRQ1
TPS7B8250QKVURQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HTSSOP
HVSSOP
WSON
DGN
PWP
DGN
DRV
KVU
PWP
DGN
DRV
KVU
8
14
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
1QFX
NIPDAU
NIPDAUAG
NIPDAU
SN
7B8233E
1GGX
6
1ORH
TO-252
5
7B8233Q1
7B8250E
19TX
HTSSOP
HVSSOP
WSON
14
8
NIPDAU
NIPDAUAG
NIPDAU
SN
6
1UFH
TO-252
5
7B8250Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7B8225QDGNRQ1 HVSSOP DGN
TPS7B8233EPWPRQ1 HTSSOP PWP
TPS7B8233QDGNRQ1 HVSSOP DGN
8
14
8
2500
2500
2500
3000
2500
2500
2500
3000
2500
330.0
330.0
330.0
180.0
330.0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
8.4
5.3
6.9
5.3
2.3
6.9
6.9
5.3
2.3
6.9
3.4
5.6
1.4
1.6
8.0
8.0
8.0
4.0
8.0
8.0
8.0
4.0
8.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
3.4
1.4
TPS7B8233QDRVRQ1
WSON
DRV
KVU
6
2.3
1.15
2.7
TPS7B8233QKVURQ1 TO-252
5
16.4
12.4
12.4
8.4
10.5
5.6
16.0
12.0
12.0
8.0
TPS7B8250EPWPRQ1 HTSSOP PWP
TPS7B8250QDGNRQ1 HVSSOP DGN
14
8
1.6
3.4
1.4
TPS7B8250QDRVRQ1
WSON
DRV
KVU
6
2.3
1.15
2.7
TPS7B8250QKVURQ1 TO-252
5
16.4
10.5
16.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7B8225QDGNRQ1
TPS7B8233EPWPRQ1
TPS7B8233QDGNRQ1
TPS7B8233QDRVRQ1
TPS7B8233QKVURQ1
TPS7B8250EPWPRQ1
TPS7B8250QDGNRQ1
TPS7B8250QDRVRQ1
TPS7B8250QKVURQ1
HVSSOP
HTSSOP
HVSSOP
WSON
DGN
PWP
DGN
DRV
KVU
PWP
DGN
DRV
KVU
8
14
8
2500
2500
2500
3000
2500
2500
2500
3000
2500
366.0
853.0
366.0
210.0
340.0
853.0
366.0
210.0
340.0
364.0
449.0
364.0
185.0
340.0
449.0
364.0
185.0
340.0
50.0
35.0
50.0
35.0
38.0
35.0
50.0
35.0
38.0
6
TO-252
5
HTSSOP
HVSSOP
WSON
14
8
6
TO-252
5
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
(1.846)
SYMM
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(2.15)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
0.125
0.15
0.175
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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具有快速瞬态响应的汽车类 150mA、40V 低压降 (LDO) 线性稳压器 | DCY | 4 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS7B84-Q1
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TPS7B84-Q1_V01
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