TPS7B8333QDCYRQ1 [TI]
具有快速瞬态响应的汽车类 150mA、40V 低压降 (LDO) 线性稳压器 | DCY | 4 | -40 to 125;
| 型号： | TPS7B8333QDCYRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有快速瞬态响应的汽车类 150mA、40V 低压降 (LDO) 线性稳压器 | DCY | 4 | -40 to 125 稳压器 |
| 文件： | 总29页 (文件大小：2581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B83-Q1
ZHCSMC8 – NOVEMBER 2020
TPS7B83-Q1 150mA、40V 低压降稳压器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准：
TPS7B83-Q1 是一款低压降线性稳压器，专用于连接
汽 车 应 用 中 的 电 池 。 该 器 件 的 输 入 电 压 范 围 高 达
40V，因此可承受汽车系统可能发生的瞬变（如负载突
降）。此器件的静态电流仅为 18µA，
是为备用系统中微控制器 (MCU) 和控制器局域网
(CAN) 收发器等常开型器件供电的出色解决方案。
– 温度等级 1：–40°C 至 +125°C，TA
– 结温：–40°C 至 +150°C，TJ
输入电压范围：3V 至 40V（最大 42V）
输出电压范围：3.3V 和 5V（固定）
输出电流：高达 150mA
输出电压精度：±1%（最大值）
低压降：
– 150 mA 时为 230 mV（最大值）(VOUT ≥ 3.3V)
低静态电流：
– 18µA（典型值）
•
•
•
•
•
该器件具有先进的瞬态响应，因此输出端可对负载或线
路变化（例如，在冷启动条件下）作出迅速响应。此
外，该器件架构新颖，可在从电压跌落恢复过程中最大
限度降低输出过冲幅度。正常运行时，该器件可在整个
线路、负载和温度范围内维持 ±1% 的直流精度。
•
•
出色的线路瞬态响应：
器件信息(1)
– 冷启动时出现 ±2% VOUT 偏差
– ±2% VOUT 偏差（VIN 压摆率 1V/µs）
与 2.2µF 或更高的电容器搭配使用时可保持稳定
提供功能安全
器件型号
封装
封装尺寸（标称值）
TPS7B83-Q1
SOT-223 (3)
6.50mm × 3.50mm
•
•
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 可帮助进行功能安全系统设计的文档
封装：3 引脚 SOT-223
•
2 应用
•
•
•
可重新配置仪表组
车身控制模块 (BCM)
常开型电池连接应用：
– 汽车网关
– 远程免钥匙进入 (RKE)
45
40
35
30
25
20
15
10
5
0.25
0.2
IN
OUT
VIN
VOUT
TPS7B83-Q1
GND
0.15
0.1
0.05
0
典型应用原理图
-0.05
-0.1
-0.15
-0.2
0
0
500
1000
1500
Time (ms)
2000
2500
3000
线路瞬态响应
（VIN 压摆率 3V/µs）
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS376
TPS7B83-Q1
ZHCSMC8 – NOVEMBER 2020
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 接收文档更新通知................................................... 22
11.3 支持资源..................................................................22
11.4 Trademarks............................................................. 22
11.5 静电放电警告...........................................................22
11.6 术语表..................................................................... 22
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 3
6.1 Absolute Maximum Ratings ....................................... 3
6.2 ESD Ratings .............................................................. 3
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................4
6.6 Typical Characteristics................................................6
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2020
*
Initial release.
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5 Pin Configuration and Functions
IN
GND
OUT
1
2
3
4
GND
Not to scale
图 5-1. DCY Package, 3-Pin SOT-223, Top View
表 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
GND
DCY
2, 4
G
P
Ground pin. Connect this pin to the thermal pad with a low-impedance connection.
Input power-supply voltage pin. For best transient response and to minimize input
impedance, use the recommended value or larger ceramic capacitor from IN to ground, as
listed in the Recommended Operating Conditions table and the Input Capacitor section.
Place the input capacitor as close to the input of the device as possible.
IN
1
3
Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For
best transient response, use the nominal recommended value or larger ceramic capacitor
from OUT to ground; see the Recommended Operating Conditions table and the Output
Capacitor section. Place the output capacitor as close to output of the device as possible. If
using a high ESR capacitor, decouple the output with a 100-nF ceramic capacitor.
OUT
O
(1) I = input; O = output; P = power; G = ground.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–40
–40
–65
MAX UNIT
IN
Unregulated input
42
VIN + 0.3(2)
125
V
OUT
TA
Regulated output
V
Operating ambient temperature
Operating junction temperature
Storage temperature
°C
°C
°C
TJ
150
Tstg
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
(2) The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
MAX
40
UNIT
V
VIN
Input voltage
VOUT
IOUT
COUT
ESR
CIN
Output voltage
1.2
18
V
Output current
0
150
220
2
mA
µF
Output capacitor(2)
2.2
Output capacitor ESR requirements(3)
Input capacitor(1)
0.001
0.1
Ω
1
µF
TJ
Operating junction temperature
150
°C
–40
(1) For robust EMI performance the minimum input capacitance is 500 nF.
(2) Effective output capacitance of 1 µF minimum required for stability.
(3) If using a large ESR capacitor it is recommended to decouple this with a 100-nF ceramic capacitor to improve transient performance.
6.4 Thermal Information
TPS7B83-Q1
THERMAL METRIC(1) (2)
DCY
3 PINS
77.1
41.7
11.7
UNIT
RθJA
RθJC(top) Junction-to-case (top) thermal resistance
Junction-to-ambient thermal resistance(3)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.3
11.5
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
11.5
(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
(3) The 1s0p RθJA is 154.6℃/W for the DCY package.
6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
TJ = 25ºC
MIN TYP MAX
UNIT
–
0.75
0.75
VIN = VOUT + 500 mV to
Regulated output accuracy DCY 40 V,
IOUT = 100 µA to 150 mA (1)
VOUT
%
TJ = –40°C to +150º
C
1
–1
VIN = VOUT + 500 mV
to 40 V,
IOUT = 100 µA
Change in percent of output
voltage
Line regulation
Load regulation
0.2
ΔVOUT(ΔVIN)
%
VIN = VOUT + 500 mV,
IOUT = 100 µA to
150 mA
Change in percent of output
voltage
0.2
ΔVOUT(ΔIOUT)
Load transient response settling
time(2) (3)
COUT = 10 µF
100
µs
IOUT = 45 mA to 105
mA
COUT = 10 µF
10%
ΔVOUT
–2%
Load transient response
overshoot, undershoot(3)
%VOUT
IOUT = 0 mA to 150
mA
–
10%
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF typical
values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
TJ = 25ºC
18
21
26
35
VIN = VOUT + 500 mV to
40 V, IOUT = 0 mA
TJ = –40°C to +150º
C
IQ
Quiescent current
µA
TJ = –40°C to +150º
C
IOUT = 500 µA
47
180
230
2.82
2.6
I
OUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
Dropout voltage
130
160
2.7
mV
IOUT = 105 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT = 150 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
VUVLO(RISING) Rising input supply UVLO
VUVLO(FALLING) Falling input supply UVLO
VIN rising
VIN falling
2.6
V
V
2.38
2.5
VUVLO(HYST)
ICL
VUVLO hysteresis
230
mV
VIN = VOUT(nom) + 1 V, VOUT short to
90% x VOUT(NOM)
Output current limit
180
220
55
260
mA
dB
VIN - VOUT = 500 mV, frequency = 1 kHz,
IOUT = 150 mA
PSRR
Vn
Power-supply ripple rejection
Output noise voltage
VOUT = 3.3 V, BW = 10 Hz to 100 kHz
280
175
20
µVRMS
°C
TSD(SHUTDOWN) Junction shutdown temperature
TSD(HYST) Hysteresis of thermal shutdown
°C
(1) Power dissipation is limited to 2W for IC production testing purposes. The power dissipation can be higher during normal operation.
Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
(2) The settling time is measured from when IOUT is stepped from 45mA to 105 mA to when the output voltage recovers to
VOUT = VOUT(nom) - 5 mV.
(3) This specification is specified by design.
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6.6 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
0.1
0.05
0
5.015
5.01
5.005
5
150 mA
100 mA
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
4.995
4.99
4.985
4.98
4.975
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
图 6-2. Line Regulation vs VIN
图 6-1. Accuracy vs Temperature
5.015
5.015
5.01
5.005
5
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
5.01
5.005
5
4.995
4.99
4.985
4.98
4.975
4.995
4.99
4.985
4.98
4.975
5
10
15
20 25
Input Voltage (V)
30
35
40
5
10
15
20 25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 5 mA
图 6-3. Line Regulation vs VIN
VOUT = 5 V, IOUT = 1 mA
图 6-4. Line Regulation vs VIN
5.015
5.01
5.005
5
5.01
5.0075
5.005
5.0025
5
-40 èC
25 èC
85 èC
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
4.995
4.99
4.985
4.98
4.975
4.9975
4.995
4.9925
4.99
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
25
50 75
Output Current (mA)
100
125
150
COUT = 10 µF
图 6-6. Line Regulation at 50 mA
VOUT = 5 V
图 6-5. Load Regulation vs IOUT
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
5.01
5.0075
5.005
5.0025
5
275
250
225
200
175
150
125
100
75
-55èC
-40èC
0èC
85èC
150èC
-40 èC
25 èC
85 èC
25èC
125èC
4.9975
4.995
4.9925
4.99
50
25
0
0
30
60 90
Output Current (mA)
120
150
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VIN = 3 V
COUT = 10 µF
图 6-7. Line Regulation at 100 mA
图 6-8. Dropout Voltage (VDO) vs IOUT
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
IOUT = 150 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 10 mA
IOUT = 1mA
VIN = 5.5 V
VIN = 6 V
VIN = 7 V
VIN = 10 V
VIN = 13.5 V
0
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
COUT = 10 µF (X7R 50 V), IOUT = 150 mA, VOUT = 5 V
图 6-9. PSRR vs Frequency and IOUT
图 6-10. PSRR vs Frequency and VIN
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
IOUT
10 mA, 252.5 mVRMS
150 mA, 267.6 mVRMS
IOUT
10 mA, 364.8 mVRMS
150 mA, 391.4 mVRMS
0.005
0.005
0.002
0.001
0.002
0.001
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VOUT = 3.3 V, COUT = 10 µF
VOUT = 5 V, COUT = 10 µF
图 6-12. Noise vs Frequency at 5.0 V
图 6-11. Noise vs Frequency at 3.3 V
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
45
40
35
30
25
20
15
10
5
0.25
0.2
10
8
300
240
180
120
60
VIN
VOUT
VIN
VOUT
6
0.15
0.1
4
2
0.05
0
0
0
-2
-4
-6
-8
-10
-60
-0.05
-0.1
-0.15
-0.2
-120
-180
-240
-300
0
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
500
1000
1500
Time (ms)
2000
2500
3000
VOUT = 5 V, VIN = 5.5 V to 6.5 V, trise = 1 µs, COUT = 10 µF
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 40 V,
slew rate = 2.7 V/µs, VEN = 3.3 V, COUT = 10 µF
图 6-14. Line Transients at 5.5 V to 6.5 V
图 6-13. Line Transients at 13.5 V to 40 V
150
100
50
300
200
100
0
150
100
50
300
-40èC
-40èC
25èC
150èC
IOUT
25èC
150èC
IOUT
200
100
0
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
图 6-15. Load Transient, No Load to 100 mA
图 6-16. Load Transient, No Load to 100-mA Rising Edge
50
300
240
180
120
60
50
40
30
20
10
0
200
150
100
50
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
40
30
20
10
0
0
0
-50
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-100
-150
-200
-250
-120
-180
-240
-300
0
40
80
120
Time (ms)
160
200
240
280
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
图 6-17. Load Transient, 45 mA to 105 mA
图 6-18. Load Transient, 45-mA to 105-mA Rising Edge
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
150
100
50
300
200
100
0
150
100
50
300
200
100
0
-40èC
25èC
150èC
IOUT
-40èC
25èC
150èC
IOUT
0
0
-50
-100
-150
-100
-200
-300
-50
-100
-150
-100
-200
-300
0
0.25
0.5
0.75
1
Time (ms)
1.25
1.5
1.75
2
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs, VEN
3.3 V, COUT = 10 µF
=
图 6-19. Load Transient, No Load to 150 mA
图 6-20. Load Transient, No Load to 150-mA Rising Edge
228
227
226
225
224
223
222
221
220
40
-55èC
-40èC
0èC
85èC
150èC
25èC
125èC
35
30
25
20
15
10
219
Current Limit
218
-75
-45
-15
15
45
75
105
135
Temperature (èC)
5
10
15
20 25
Input Voltage (V)
30
35
40
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
VOUT = 5 V
图 6-22. Quiescent Current (IQ) vs VIN
图 6-21. Output Current Limit vs Temperature
175
450
400
350
300
250
200
150
100
50
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55 èC
-40 èC
0 èC
25 èC
85 èC
125 èC
150 èC
150
125
100
75
50
25
0
0
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
25
50
75
Output Current (mA)
100
125
150
VOUT = 5 V
图 6-23. Quiescent Current (IQ) vs VIN
图 6-24. Ground Current (IGND) vs IOUT
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
281
280
279
278
277
276
275
274
273
272
271
26
25
24
23
22
21
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Ambient Temperature (èC)
IOUT = 100 mA
IOUT = 500 µA
图 6-25. Ground Current
图 6-26. Ground Current
20
15
10
5
200
2.8
Input Voltage
Output Voltage
Output Current
Falling Threshold
Rising Threshold
2.75
2.7
150
100
50
2.65
2.6
2.55
2.5
0
0
2.45
2.4
-5
-50
10
0
1
2
3
4
5
Time (ms)
6
7
8
9
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
COUT = 10 µF
图 6-27. Undervoltage Lockout (UVLO) Threshold vs
图 6-28. Startup Plot
Temperature
20
18
16
14
12
10
8
OFF
ON
6
4
0.2
-50 -25
0
25
50
75 100 125 150 175 200
0.4
0.6
0.8
1
1.2
Injected current (mA)
1.4
1.6
1.8
Temperature (èC)
图 6-30. Thermal Shutdown
图 6-29. Output Voltage vs Injected Current
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6.6 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, and CIN = 1 µF
(unless otherwise noted)
10
5
2
1
0.5
0.2
0.1
0.05
Stable region
0.02
0.01
0.005
0.002
0.001
0.0005
0.0002
0.0001
1
2
3
4 5 67810
20 30 50 70 100 200300 500
COUT (mF)
图 6-31. Stability ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS7B83-Q1 is a low-dropout linear regulator (LDO) designed to connect to the battery in automotive
applications. The device has an input voltage range extending to 40 V, which allows the device to withstand
transients (such as load dumps) that are anticipated in automotive systems. With only a 18-µA quiescent current
at light loads, the device is an optimal solution for powering always-on components.
The device has a state-of-the-art transient response that allows the output to quickly react to changes in the load
or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that
minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC
accuracy of ±1% over line, load, and temperature.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
Thermal
Shutdown
œ
+
UVLO
R2
Bandgap
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.2 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns
off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output
current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application report.
图 7-1 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
0 V
IOUT
IRATED
0 mA
ICL
图 7-1. Current Limit
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
表 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
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8 Application and Implementation
Note
以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B83-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an
equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For the best transient performance, use X5R-
and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
8.1.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
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8.1.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.4.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter, RθJA, is highly dependent on the heat-spreading capability built
into the particular PCB design, and therefore varies according to the total copper area, copper weight, and
location of the planes. The RθJA recorded in the Thermal Information table in the Specifications section is
determined by the JEDEC standard (see 图 8-1), PCB, and copper-spreading area, and is only used as a
relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum
of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by
the PCB copper.
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Mold
Compound
Die
Wire
Die
Attach
2oz
Signal
Trace
Lead
Frame
Internal Signal
or power plane
1oz copper
Thermal
Pad or Tab
of the LDO
Internal
GND plane
1oz copper
Bottom
Relief
2oz copper
Thermal
Vias
图 8-1. JEDEC Standard 2s2p PCB
图 8-2 and 图 8-3 depict the functions of RθJA and ψJB versus copper area and thickness. These plots are
generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the four-layer board, the inner
planes use a 1-oz copper thickness. Outer layers are simulated with both a 1-oz and 2-oz copper thickness. A 4
x 4 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the thermal pad of the
device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first
inner GND plane. Each of the layers has a copper plane of equal area.
20
115
105
95
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
4 Layer PCB, 1 oz copper
4 Layer PCB, 2 oz copper
2 Layer PCB, 1 oz copper
2 Layer PCB, 2 oz copper
19
18
17
16
15
14
13
85
75
65
55
45
35
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Cu Area Per Layer (cm2)
Cu Area Per Layer (cm2)
图 8-2. RθJA vs Copper Area 2s2p DCY Package
图 8-3. ψJB vs Copper Area 2s2p DCY Package
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8.1.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-
to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to
calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB
surface temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(4)
where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(5)
where
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
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8.2 Typical Application
图 8-4 shows a typical application circuit for the TPS7B83-Q1. Use different values of external components,
depending on the end application. An application may require a larger output capacitor during fast load steps in
order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type
X5R or X7R.
VI
Vo
V
V
reg
bat
0.1 …F
10 …F
TPS7B83-Q1
GND
图 8-4. Typical Application Schematic for the TPS7B83-Q1
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters.
表 8-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
6 V to 40 V
5 V
Output current
100 mA
10 µF
Output capacitor
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between
2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design a low ESR, 10-µF
ceramic capacitor was used to improve transient performance.
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8.2.3 Application Curves
20
15
10
5
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
Input Voltage
Output Voltage
Output Current
0
0
IOUT = 150 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 10 mA
IOUT = 1mA
-5
-50
10
0
1
2
3
4
5
Time (ms)
6
7
8
9
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
图 8-5. Power-Up Waveform
图 8-6. PSRR
50
40
300
-40èC
25èC
150èC
IOUT
240
180
120
60
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-120
-180
-240
-300
0
40
80
120
160
200
240
280
Time (ms)
图 8-7. Transient Response
9 Power Supply Recommendations
This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B83-Q1, add
an electrolytic capacitor and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. TI also recommends a ground reference plane either embedded in the
PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to
assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)
heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is
necessary to meet thermal requirements.
10.1.1 Package Mounting
Solder pad footprint recommendations for the TPS7B83-Q1 are available at the end of this document and at
www.ti.com.
10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
As depicted in 图 10-1, place the input and output capacitors close to the device for the layout of the TPS7B83-
Q1. In order to enhance the thermal performance, place as many vias as possible around the device. These vias
improve the heat transfer between the different GND planes in the PCB.
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces to connect the capacitors because these can negatively
impact system performance and may even cause instability.
If possible, and to ensure the maximum performance specified in this document, use the same layout pattern
used for the TPS7B83-Q1 evaluation board, available at www.ti.com.
10.2 Layout Example
GND
VIN
VOUT
图 10-1. SOT-223 (DCY) Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
表 11-1. Device Nomenclature(1)
PRODUCT
VOUT
xx is the nominal output voltage (for example, 33 = 3.3 V V; 50 = 5.0 V).
TPS7B83xxQDCYRQ1
Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard.
Q1 indicates that this device is an automotive grade (AEC-Q100) device.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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TPS7B83-Q1
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PACKAGE OUTLINE
DRC0010U
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
S
C
A
S
E
C
30.0
OI
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
4X (0.25)
(0.2) TYP
EXPOSED
THERMAL PAD
5
6
(0.16) TYP
A
A
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
4225163/A 07/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.25)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225163/A 07/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010U
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.25)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4225163/A 07/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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11-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7B8333QDCYRQ1
TPS7B8333QDCYRQ1M3
TPS7B8350QDCYRQ1
TPS7B8350QDCYRQ1M3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
DCY
DCY
DCY
DCY
4
4
4
4
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7B8333
Samples
Samples
Samples
Samples
SN
NIPDAU
SN
7B8333
7B8350
7B8350
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
DCY (R-PDSO-G4)
PLASTIC SMALL-OUTLINE
6,70 (0.264)
6,30 (0.248)
3,10 (0.122)
2,90 (0.114)
4
0,10 (0.004)
M
3,70 (0.146)
3,30 (0.130)
7,30 (0.287)
6,70 (0.264)
Gauge Plane
1
2
3
0,25 (0.010)
0,84 (0.033)
0,66 (0.026)
0°–10°
2,30 (0.091)
0,10 (0.004)
M
4,60 (0.181)
0,75 (0.030) MIN
1,70 (0.067)
1,50 (0.059)
1,80 (0.071) MAX
0,35 (0.014)
0,23 (0.009)
Seating Plane
0,08 (0.003)
0,10 (0.0040)
0,02 (0.0008)
4202506/B 06/2002
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
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