TPS7H3302-SEP [TI]
耐辐射、2.3V 至 3.5V 输入、3A 灌电流和拉电流 DDR 终端 LDO 稳压器;
| 型号： | TPS7H3302-SEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射、2.3V 至 3.5V 输入、3A 灌电流和拉电流 DDR 终端 LDO 稳压器 双倍数据速率 稳压器 |
| 文件： | 总37页 (文件大小：2205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
TPS7H3302-SP 和TPS7H3302-SEP 3A DDR 耐辐射终端稳压器
1 特性
3 说明
• 提供QMLP TPS7H3302-SP 标准微电路图
(SMD)，5962R14228
TPS7H3302 是一款具有内置 VTTREF 缓冲器的耐辐
射双倍数据速率 (DDR) 3A 终端稳压器。该稳压器专门
设计用于为单板计算机、固态记录器和有效载荷处理等
航天 DDR 端接应用提供完整的紧凑型低噪声解决方
案。
• 提供增强型航天塑料封装供应商项目图，VID
V62/22615
• 电离辐射总剂量(TID) 特性
– 耐辐射保障(RHA)，耐受高达100krad(Si) 或
50krad(Si) 的电离辐射总剂量(TID)
• 单粒子效应(SEE) 特性
TPS7H3302 支持使用 DDR、DDR2、DDR3、DDR3L
和 DDR4 的 DDR VTT 端接应用。凭借快速瞬态响
应，TPS7H3302 VTT 稳压器可在读取/写入状态下提
供非常稳定的电源。TPS7H3302 还包含一个用于跟踪
VTT 的内置 VTTREF 电源，以进一步减小解决方案尺
寸。为了实现简单的电源时序，TPS7H3302 中集成了
使能输入和电源正常输出 (PGOOD)。使能信号还可用
于在挂起至RAM (S3) 断电模式时使VTT 放电。
– 单粒子锁定(SEL)、单粒子栅穿(SEGR)、单粒
子烧毁(SEB) 对于LET 的抗扰度= 70MeV-
cm2/mg
– 单粒子瞬变(SET)、单粒子功能中断(SEFI) 和
单粒子翻转(SEU) 特性值高达70MeVcm2/mg
• 支持DDR、DDR2、DDR3、DDR3L 和DDR4 端
接应用
• 输入电压：支持2.5V 和3.3V 电源轨
• 低至
0.9V 的独立低压输入(VLDOIN)，可提高电源效率
• 3A 灌电流和拉电流终端稳压器
• 可实现电源时序的使能输入和电源正常输出
• VTT 终端稳压器
器件信息
等级
器件型号(1)
封装(2)
HTSSOP (32)
5962R142280PYE(3)
QMLP-RHA
6.10mm × 11.00mm
质量= 0.184g
TPS7H3302MDAPTSEP
TPS7H3302EVM
9 月
EVM
评估板
(1) 有关更多信息，请查看Device Options 表。
(2) 尺寸和质量值为标称值。
(3) 产品预发布。
– 输出电压范围：0.5 至1.75 V
– 3A 灌电流和拉电流
• 具有检测输入的精密集成分压器网络
• 遥感(VTTSNS)
TPS7H3302
VIN (2.5 V or 3.3 V supply)
VDD
VTTSNS
VTT = VDDQ / 2
VDDQ
• VTTREF 缓冲基准
VDDQSNS
VLDOIN
EN
VTT
VTTREF
PGOOD
AGND
– 相对于VDDQSNS (±3mA) 的精度为49% 至
VDDQ
VTTREF = VDDQSNS / 2
51%
DDR - 2.5 V
DDR2 - 1.8 V
DDR3 - 1.5 V
DDR 3L - 1.375 V
DDR4 - 1.2 V
– ±10mA 灌电流和拉电流
• 集成了欠压锁定(UVLO) 和过流限制(OCL) 功能
• 塑料封装
VDD
ENABLE
100 k
PGND
2 应用
• 卫星电力系统(EPS)
• 命令和数据处理(C&DH)
• 光学成像有效载荷
• 雷达成像有效载荷
图3-1. DDR 应用的简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
9.3 Power Supply Recommendations.............................25
9.4 Layout....................................................................... 25
10 Device and Documentation Support..........................27
10.1 Device Support....................................................... 27
10.2 Documentation Support.......................................... 27
10.3 Receiving Notification of Documentation Updates..27
10.4 Support Resources................................................. 27
10.5 Trademarks.............................................................27
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics..............................................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2023) to Revision A (May 2023)
Page
• 将TPS7H3302-SEP 状态从“预告信息”更改为“量产数据”......................................................................... 1
• 为QMLP 版本TPS7H3302-SP 添加了“产品预发布”说明..............................................................................1
• 在“特性”部分和“器件选项”表中添加了TPS7H3302-SP（产品预发布）辐射等级.....................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
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ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
5 Device Options
Device Options
Grade2
Generic Part Number
Radiation Rating(1)
Package
Orderable Part Number
TPS7H3302-SP
QMLP-RHA
32-Pin HTSSOP DAP
5962R142280PYE(3)
TID of 100 krad(Si) RLAT,
DSEE free to 70 MeV-
cm2/mg
TPS7H3302-SEP
TPS7H3302EVM
TID of 50 krad(Si) RLAT,
DSEE free to 48 MeV-
cm2/mg
Space Enhanced Plastic
Evaluation Board
32-Pin HTSSOP DAP
EVM
TPS7H3302MDAPTSEP
TPS7H3302EVM
None
(1) TID is total ionizing dose and DSEE is destructive single event effects. Additional information is available in the associated TID reports
and SEE reports for each product.
(2) For additional information about part grade, view SLYB235.
(3) Product preview.
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
6 Pin Configuration and Functions
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
NC
NC
NC
3
NC
4
VTTSNS
AGND
NC
VTTREF
VDDQSNS
NC
5
6
7
VTT
VTT
VTT
VTT
PGOOD
VDD
EN
VLDOIN
VLDOIN
PGND
PGND
PGND
NC
8
Thermal Pad
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC
NC
图6-1. DAP Package 32-Pin HTSSOP Top View
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
VTTREF
VDDQSNS
4
5
O
I
Reference output. Connect to GND through 0.1-µF ceramic capacitor.
VDDQ sense input. Reference input for VTTREF.(2)
7
VLDOIN
I
Supply voltage for the LDO. Connect to VDDQ voltage or an alternate voltage source.
8
9
PGND
10
11
Power ground. Connect to system ground.
—
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the
device.
EN
20
21
22
I
I
2.5- or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1 and 10 µF is
required.
VDD
PGOOD output pin. PGOOD pin is an open drain output to indicate the output voltage is within
specification.
PGOOD
O
23
24
25
26
28
29
VTT
O
Power output for VTT LDO.
AGND
VTTSNS
NC
Signal ground. Connect to system ground.
—
I
Voltage sense for VTT. Place capacitor close to pin. Route sense line to VTT near load.
1-3, 6,
12-19,
27, 30-32
No connect. These pins are not internally connected. It is recommended to connect these pins to ground
to prevent charge buildup; however, these pins can also be left open or tied to any voltage between
ground and VDD.
—
Thermal Pad
Connect to PGND. This is internally floating.
(1) I = Input, O = Output, —= Other
(2) VDDQSNS shall be connected to the regulated voltage supplying VDDQ. If the VDDQ supply is also used for VLDOIN, an RC filter is
recommended to isolate transients from VLDOIN to VDDQ.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
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ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range and all voltages with respect to AGND (unless otherwise noted)(1)
MIN
–0.36
–0.3
–0.3
–0.3
–0.3
–55
MAX
3.6
UNIT
VDD, VLDOIN, VTTSNS, VDDQSNS
Input voltage
EN
3.6
V
PGND to AGND
VTT, VTTREF
PGOOD
TJ
0.3
3.6
Output voltage
V
3.6
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
–55
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
±4000
±750
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
all voltages with respect to AGND (unless otherwise noted)
MIN
2.375
1
NOM
MAX
UNIT
VDD
3.5
3.5
3.5
3.5
0.1
3.5
1.8
4
VDDQSNS
VLDOIN
EN, VTTSNS, PGOOD
PGND
0.9
Input voltage
V
–0.1
–0.1
–0.1
–0.1
0
VTT
Output voltage
Input current
V
mA
A
VTTREF
PGOOD
VTT
3
–3
Output current
Junction temperature
VTTREF
TJ
0.01
125
–0.01
–55
°C
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
UNIT
7.4 Thermal Information
TPS7H3302-SEP
THERMAL METRIC(1)
HTSSOP DAP
32-PINS
25.9
15.9
7.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
7.9
ΨJB
RθJC(bot)
1.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
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7.5 Electrical Characteristics
Over 2.375 ≤VDD ≤3.5 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, EN = VDD, TA = –55°C to 125°C; Standard DDR
Application; all voltages with respect to AGND, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY CURRENTS
IVDD
Quiescent current
Shutdown current
EN = 3.3 V, no load
18
1.75
5
30 mA
VDDQSNS = 0 V
3
IVDD(SHDN)
EN = 0 V, no load
mA
6
VDDQSNS > 0.78 V
IVLDOIN
Quiescent current of VLDOIN
Shutdown current of VLDOIN
VDDQSNS input current
EN = 3.3 V, no load
EN = 0 V, no load
EN = 3.3 V
450 1200 µA
IVLDOIN(SHDN)
IVDDQSNS
0.5
4
1
6
µA
µA
VTT OUTPUT
VDDQSNS = VLDOIN
= 2.5 V (DDR1)
1.24
0.89
1.25
0.9
1.26
0.91
VDDQSNS = VLDOIN
= 1.8V (DDR2)
VDDQSNS = VLDOIN
= 1.5 V (DDR3)
IVTT = 5 mA
0.745 0.752 0.759
0.67 0.677 0.684
0.596 0.602 0.608
V
V
V
VDDQSNS = VLDOIN
= 1.35 V (DDR3L)
VDDQSNS = VLDOIN
= 1.2 V (DDR4)
VDDQSNS = VLDOIN
= 2.5 V (DDR1)
1.25
0.9
1.26
0.91
1.27
0.92
VDDQSNS = VLDOIN
= 1.8V (DDR2)
VDDQSNS = VLDOIN
= 1.5 V (DDR3)
VTTSNS
Output DC voltage, VTT
0.752
0.76 0.768
IVTT = –5 mA
VDDQSNS = VLDOIN
= 1.35 V (DDR3L)
0.675 0.685 0.692
VDDQSNS = VLDOIN
= 1.2 V (DDR4)
0.602
1.24
0.61 0.618
VDDQSNS = VLDOIN
= 2.5 V (DDR1)
1.26
1.28
0.93
0.78
0.72
0.63
VDDQSNS = VLDOIN
= 1.8V (DDR2)
0.885 0.910
VDDQSNS = VLDOIN
= 1.5 V (DDR3)
0.735
0.66
0.76
0.69
0.6
–1 A ≤IVTT ≤1 A
VDDQSNS = VLDOIN
= 1.35 V (DDR3L)
VDDQSNS = VLDOIN
= 1.2 V (DDR4)
0.585
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
Over 2.375 ≤VDD ≤3.5 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, EN = VDD, TA = –55°C to 125°C; Standard DDR
Application; all voltages with respect to AGND, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
IVTT = 0.5 A
5
60
190
8
60
180
465
70
VDDQSNS = 2.5 V
(DDR1)
IVTT = 1 A
IVTT = 2 A
IVTT = 0.5 A
IVTT = 1 A
IVTT = 2 A
IVTT = 0.5 A
IVTT = 1 A
IVTT = 2 A
IVTT = 0.5 A
IVTT = 1 A
IVTT = 2 A
IVTT = 0.5 A
IVTT = 1 A
IVTT = 2 A
VDDQSNS = 1.8 V
(DDR2)
65
190
5
200
475
65
Dropout voltage,
VDO = VLDOIN –VTTREF
VDO recorded when VTT –
VTTREF = 50 mV
VDDQSNS = 1.5 V
(DDR3)
VDO
60
180
4
180 mV
420
60
VDDQSNS = 1.35 V
(DDR3L)
60
175
4
180
420
60
VDDQSNS = 1.2 V
(DDR4)
60
175
18
-15
180
420
IVTT = -3 A
IVTT = 3 A
1
30
mV
-1
VTT Tolerance to VTTREF
(VTT –VTTREF)
VTT(TOL)
-30
Ramp output 0 A to 10 A, record current when
VTT reaches lowest value
ILIM_SRC_VTT
ILIM_SNK_VTT
VTT sourcing current limit
5
5
9
A
Ramp output 0 A to -10 A, record current when
VTT reaches highest value
VTT sinking current limit
VTT discharge resistance
10
25
A
RDSCHRG
VDDQSNS = 0 V, VTT = 0.3 V, EN = 0 V
7
Ω
POWER GOOD
VPG(LOW, Falling)
VPG(LOW, Rising)
VPG(HI, Falling)
VPG(HI, Rising)
VPG(HYST)
PGOOD window lower falling threshold
PGOOD window lower rising threshold
PGOOD window High falling threshold
PGOOD window High rising threshold
-21% -20% -18%
-17% -15% -13%
VTT PGOOD threshold with
respect to VTTREF
13%
18%
15%
20%
17%
21%
VTT PGOOD threshold with
respect to VTTREF
VTT PGOOD hysteresis
PGOOD startup delay
5%
Startup rising edge, VTTSNS within 20% of
VTTREF
tPG(delay)
4
ms
tPG_BAD(delay)
VPG(OL)
PGOOD bad delay
VTTSNS outside of the ±20% PGOOD window
IPGOOD(SINK) = 4 mA
1.95
µs
V
Power good output low
0.4
1
VTTSNS = VTTREF (PGOOD high impedance),
PGOOD = VDD + 0.2 V
IPG(LKG)
Power good leakage
0.07
µA
VDDQSNS AND VTTREF
VDDQSNS UVLO turn-on
threshold
VDDQSNSUVLO(HYST) VDDQSNS UVLO hysteresis
VTTREF VTTREF voltage
VDDQSNSUVLO
VDDQSNS rising
750
75
900 mV
150
V
VDDQSNS / 2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
8
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ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
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Over 2.375 ≤VDD ≤3.5 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V, EN = VDD, TA = –55°C to 125°C; Standard DDR
Application; all voltages with respect to AGND, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
49%
49%
49%
49%
49%
49%
49%
49%
TYP MAX UNIT
VDDQSNS = 2.5 V
51%
51%
VDDQSNS = 1.8 V
VDDQSNS = 1.5 V
VDDQSNS = 1.35 V
VDDQSNS = 1.2 V
VDDQSNS = 1.5 V
VDDQSNS = 1.35 V
VDDQSNS = 1.2 V
-10 mA ≤IVTTREF ≤10
51.25%
51.5%
51.5%
51%
mA
VTTREF voltage tolerance to
VDDQSNS
VTTREF
-3 mA ≤IVTTREF ≤3
51%
mA
51%
Sourcing current ramped from 0 to 55mA. Find
when VTTREF drops to half its original value
ILIM_SRC_VTTREF
VTTREF sourcing current limit
35
12
45
mA
Sinking current ramped from 0 to 16.5mA. Find
when VTTREF hits peak value
ILIM_SNK_VTTREF
IVTTREF(dis)
VTTREF sinking current limit
VTTREF discharge current
15
EN = 0 V, VDDQSNS = 0 V, VTTREF = 0.5 V
1.3
mA
UVLO AND ENABLE
VDDUVLO
VDD UVLO turn-on threshold
VDD UVLO hysteresis
2.18
40
2.3
1.7
V
VDDUVLO(HYST)
mV
Enable high-level input voltage
(turn-on)
VIH_EN
VIL_EN
V
V
Enable low-level input voltage
(turn-off)
0.3
-1
VEN(HYS)
IEN(LKG)
Enable hysteresis voltage
700
mV
µA
Enable input leakage current
1
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Product Folder Links: TPS7H3302-SP TPS7H3302-SEP
English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
7.6 Typical Characteristics
For Fig 7-1 through Fig 7-11, (3 × 150-µF tantalum + 4 × 4.7-µF MLCC) or equivalent capacitance/ESR are used
on VTT output
1.278
1.275
1.272
1.269
1.266
1.263
1.26
1.257
1.254
1.251
1.248
1.245
1.242
1.239
1.236
0.927
0.924
0.921
0.918
0.915
0.912
0.909
0.906
0.903
0.9
0.897
0.894
0.891
0.888
0.885
25C
125C
-55C
25C
125C
-55C
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
3
3
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
VDD = 3.6 V
VDDQSNS = 2.5
VDD = 3.6 V
VDDQSNS = 1.8 V
图7-1. Output Voltage vs Output Current
图7-2. Output Voltage vs Output Current
0.777
0.702
25C
125C
-55C
25C
125C
-55C
0.774
0.771
0.768
0.765
0.762
0.759
0.756
0.753
0.75
0.747
0.744
0.741
0.738
0.735
0.699
0.696
0.693
0.69
0.687
0.684
0.681
0.678
0.675
0.672
0.669
0.666
0.663
0.66
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Output Current (A)
VDD = 3.6 V
VDDQSNS = 1.5 V
VDD = 3.6 V
VDDQSNS = 1.35 V
图7-3. Output Voltage vs Output Current
图7-4. Output Voltage vs Output Current
0.625
1.2605
25C
125C
-55C
25C
125C
-55C
1.26
1.2595
1.259
0.62
0.615
0.61
1.2585
1.258
0.605
0.6
1.2575
1.257
0.595
0.59
1.2565
1.256
0.585
0.58
1.2555
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-10
-8
-6
-4
-2
0
2
4
6
8
10
Output Current (A)
VTTREF Current (mA)
VDD = 3.6 V
VDDQSNS = 1.2 V
VDDQSNS = 2.5 V
图7-5. Output Voltage vs Output Current
图7-6. VTTREF Voltage vs VTTREF Current
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0.9105
0.91
0.76
0.7595
0.759
25C
125C
-55C
25C
125C
-55C
0.9095
0.909
0.9085
0.908
0.9075
0.907
0.9065
0.906
0.7585
0.758
0.7575
0.757
0.7565
0.756
0.7555
0.755
0.9055
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
VTTREF Current (mA)
VTTREF Current (mA)
VDDQSNS = 1.8V
VDDQSNS = 1.5 V
图7-7. VTTREF Voltage vs VTTREF Current
图7-8. VTTREF Voltage vs VTTREF Current
0.685
0.61
25C
25C
0.6845
0.6095
125C
125C
-55C
-55C
0.684
0.609
0.6835
0.683
0.6825
0.682
0.6815
0.681
0.6805
0.68
0.6085
0.608
0.6075
0.607
0.6065
0.606
0.6055
0.605
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
VTTREF Current (mA)
VTTREF Current (mA)
VDDQSNS = 1.35 V
VDDQSNS = 1.2V
图7-9. VTTREF Voltage vs VTTREF Current
图7-10. VTTREF Voltage vs VTTREF Current
180
160
140
120
100
80
60
1.25 V
0.9 V
0.75 V
0.675 V
0.6 V
40
20
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Output Current (A)
VDD = 3.6 V
图7-11. Dropout Voltage vs Output Current
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8 Detailed Description
8.1 Overview
The TPS7H3302-SEP device is a sink and source double data rate (DDR) termination regulator specifically
designed for low input voltage, low-noise systems where space and mass are a key consideration.
8.2 Functional Block Diagram
VDDQSNS
5
7, 8
4
VLDOIN
VTTREF
+
–
2.25V
-
UVLO
+
VDD
21
29
DchgREF
Gm
GND
-
VTTSNS
+
23, 24, 25, 26
VTT
20
28
EN
DchgVTT
REFINOK
Gm
9, 10, 11
PGND
AGND
GND
-
GND
22
PGOOD
+
+
+
Startup
Delay
-
+
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8.3 Feature Description
8.3.1 VTT Sink and Source Regulator
The TPS7H3302 is a 3-A sink and source tracking termination regulator incorporating a high performance, low-
dropout (LDO) linear regulator specifically designed for low input voltage, and low external component count
systems where board area is a key application parameter. The LDO regulator employs a fast feedback loop so
that ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing pin (VTTSNS) should be connected to the positive pin of
the output capacitor(s) as a separate trace from the high-current path of VTT.
The TPS7H3302 has a dedicated pin (VLDOIN) for connection to the VTT power supply, in order to minimize the
LDO power dissipation. The minimum VLDOIN voltage is highlighted in Electrical Characteristics : TPS7H3302
(VLDOIN to VTT headroom) for various load conditions.
8.3.2 Reference Input (VDDQSNS)
The output voltage, VTT, is regulated to VTTREF. VDDQSNS incorporates an integrated resistor divider network.
VDDQSNS should be connected to the memory supply bus (VDDQ). The TPS7H3302 supports VDDQSNS
voltage from 1 V to 3.5 V, making it versatile and ideal for many types of low-power LDO applications.
8.3.3 Reference Output (VTTREF)
When it is configured for DDR termination applications, VTTREF buffers the DDR VTT reference voltage for the
memory application. The VTTREF block consists of an on-chip 1/2 resistor divider and a low-pass filter (LPF).
VTTREF tracks 1/2 of VDDQSNS typically within ±1%. It is typically capable of supporting a ±10 mA sink/source
load current. VTTREF becomes active when VDDQSNS reaches 0.75V and VDD is above the UVLO threshold.
When VTTREF is less than 0.675 V, VTTREF is disabled and subsequently discharges to GND through an
internal MOSFET. VTT is also discharged following the discharge of VTTREF. VTTREF is independent of the EN
pin state. To meet stability criteria, a ceramic capacitor of 0.1-µF minimum must be installed close to VTTREF
(pin 4). Capacitor value at VTTREF (pin 4) must not exceed 2.2 µF.
8.3.4 EN Control (EN)
When EN is driven high, the TPS7H3302 VTT regulator begins normal operation. When EN is driven low, VTT
discharges to GND through an internal 18-Ω (typical) MOSFET. VTTREF remains on when EN is driven low. EN
is not tied high internally to prevent power sequencing issues with an external signal that may be controlling the
enable. EN is a floating input and not internally tied, thus the user can have complete control over where and
when the EN signal is generated. EN feeds directly into power-good (PGOOD). When enable is low, PGOOD is
low.
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8.3.5 Power-Good Function (PGOOD)
The TPS7H3302 provides an open-drain PGOOD output that goes high when the VTT output is within 20% of
VTTREF (typ). PGOOD deasserts within 1.95 μs after the output exceeds the size of the power-good window.
During initial VTT startup, PGOOD asserts high 4 ms (typ) after the VTT enters power-good window. Because
PGOOD is an open-drain output, a 100-kΩ pullup resistor between PGOOD and a stable active supply voltage
rail is recommended for proper operation.
8.3.6 VTT Current Protection
The LDO has a constant overcurrent limit (OCL).
8.3.7 VIN UVLO Protection
For VDD undervoltage lockout (UVLO) protection, the TPS7H3302 monitors VDD voltage. When the VDD
voltage is lower than the UVLO threshold voltage, both the VTT and VTTREF regulators are powered off. This
shutdown is a non-latch protection.
8.3.8 Thermal Shutdown
The TPS7H3302 includes thermal shutdown circuitry that typically activates at 210ºC with a 12ºC hysterysis;
when engaged the VTT and VTTREF regulators are both shutoff and discharged by the internal discharge
MOSFET. This description is only provided in order to provide a complete description of the TPS7H3302; the
thermal shutdown feature is not included in the product specification as the plastic package is not designed for
use at 210ºC.
8.4 Device Functional Modes
The TPS7H3302 is a 3-A sink and source LDO provides low output noise to meet system needs. In order to
improve efficiency in the LDO, the TPS7H3302 LDO can operate from low VLDOIN voltage rail, thus using dual
voltage source one for the VLDOIN that supports high-current and an alternate voltage sources that enables the
VDDQSNS pin to track VDDQ.
In some cases VLDOIN and VDDQSNS pins are tied together. In the memory system, VDDQ is a high-current
supply that powers the core, the I/O, and the logic of the memory. VTTREF is a low-current, precision reference
voltage that provides a threshold between a logic high (one) and a logic low (zero) that adapts to changes in the
I/O supply voltage. By providing a precision threshold that adapts to the supply voltage, VTTREF realizes wider
noise margins than those possible with a fixed threshold and normal variations in termination and drive
impedance. Specifications vary for different DDR technologies. For example DDR3 JEDEC JESD79-3F specifies
0.49 to 0.51 times VDDQ and draws only tens to hundreds of microamps. The TPS7H3302 VTTREF is designed
to sink and source up to 10 mA.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS7H3302 device is a highly-integrated sink and source LDO. The device is targeted to support VTT
voltage for DDR memory applications and is capable of sourcing and sinking 3-A load current. The
TPS7H3302EVM user’s guide is available on www.ti.com, SLVUCK2. The guide highlights standard EVM test
results, schematic, and bill of materials (BOM) for reference.
9.2 Typical Application
The design example describes a 2.5-V VIN, DDR3 configuration.
VDD
R5
R2
TPS7H3302
PGOOD
VTTSNS
AGND
VTT
PGOOD
C2
VTTREF = VDDQSNS/2
C14
VTTREF
VDDQSNS
VLDOIN
PGND
GND
VTT = 0.75V
C9 C18
C7
C16
C8
C17
C15
C10
VDDQ
DDR3 1.5V
EN
C4 C11 C5 C12 C6 C13
GND
R1
ENABLE
2.5V SUPPLY
VDD
C1
GND
GND
图9-1. Typical Application Schematic
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9.2.1 Design Requirements
See the Recommended Operating Conditions for recommended limits.
9.2.2 Detailed Design Procedure
表9-1. Design Example 1 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
RC0603JR-0720KL
RC0603FR-07392RL
GCM31CR71C106KA64K
CC0603KRX7R7BB102
1210ZC475KAT2A
R1, R5
Yageo
Yageo
Murata
Yageo
AVX
20 kΩ
Resistor
R2
392 Ω
C1, C4, C5, C6, C11, C12,
10 µF, 16 V
1000 pF, 10 V
4.7 µF, 10 V
1000 pF, 100 V
150 µF, 10 V
2.2 µF, 25 V
C2
C7, C8, C9, C18
C10
Capacitor
06031C102KAT2A
AVX
C13, C15, C16, C17
C14
T530D157M010ATE005
08053C225KAT2A
Kemet
AVX
9.2.2.1 VDD Capacitor
Add a ceramic capacitor, with a value between 1- and 10-μF, placed close to the VDD pin to minimize high
frequency noise from the supply.
9.2.2.2 VLDO Input Capacitor
Depending on the trace impedance between the VLDOIN/VDDQ bulk power supply to the device, a transient
increase of source current is supplied mostly by the charge from the VLDOIN/VDDQ input capacitor. Use a 150-
μF (or greater) tantalum capacitor in parallel with a 4.7-µf ceramic capacitor to supply this transient charge.
Provide more input capacitance as more output capacitance is used at VTT.
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9.2.2.3 VTT Output Capacitor
For stable operation, the total capacitance of the VTT output pin must be greater than 470 μF. Attach three, 3 ×
150-μF low-ESR tantalum capacitors in parallel with four 4.7 μF ceramic capacitors to minimize the effect of
equivalent series resistance (ESR) and equivalent series inductance (ESL). If the total parallel ESR is greater
than 2 mΩ, insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter
time constant should be almost the same as or slightly lower than the time constant of the output capacitor and
its ESR.
9.2.2.4 VTTSNS Connection
To achieve tight regulation with minimum effect of trace resistance, a remote sensing pin (VTTSNS) should be
connected to the positive pin of the VTT pin output capacitor or capacitors as a separate trace from the high-
current path from VTT. Consider adding a low-pass R-C filter at the VTTSNS pin in case the ESR of the VTT
output capacitor or capacitors is larger than 2 mΩ. The R-C filter time constant should be approximately the
same or slightly lower than the time constant of the VTT output capacitance and ESR.
TPS7H3302-SEP
26
25
24
23
VTT
VTT
VTT
VTT
RC
29
VTTSNS
CC
470 μF
PGND
PGND
PGND
9
GND
10
11
GND
图9-2. RC Filter for VTTSNS
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9.2.2.5 Low VDD Applications
TPS7H3302 can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. The
TPS7H3302 minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute
minimum voltage (both DC and transient) at the device pin is 2.375 V or greater. The voltage tolerance for a 2.5-
V rail input is between ±5% accuracy, or better.
9.2.2.6 S3 and Pseudo-S5 Support
The TPS7H3302 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in
the end application. Both VTTREF and VTT are on when EN = high (S0 state). VTTREF is maintained while VTT
is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). Please notice that the
EN signal controls only the output buffer for VTT and therefore, while in S3 state, VDDQSNS is present in order
to maintain data in volatile memory. As a result, when EN is set high to exit the S3 state, it is desired to bring
VTT into regulation as fast as possible. This causes an output current controlled by the current limit of the device
and the output capacitors.
When EN = low and the VDDQSNS voltage is less than 0.75 V(typically), TPS7H3302 enters pseudo-S5 state.
Both VTT and VTTREF outputs are turned off and discharged to GND through internal MOSFETs when pseudo-
S5 support is engaged (S4/S5 state). 图 9-3 shows a typical startup and shutdown timing diagram for an
application that uses S3 and pseudo-S5 support.
VDD
VDDQ = 1.5 V
VLDOIN
0.75 V
0.675 V
0.37 V
VDDQSNS
VTTREF
EN
(S3_SLP)
trise
VTT = 0.75 V
VTT
COUT x VTT
IVOSRCL
trise
=
PGOOD
4 ms
图9-3. Typical Timing Diagram for S3 and Pseudo-S5 Support
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9.2.2.7 Tracking Startup and Shutdown
The TPS7H3302 supports tracking startup of VDDQ and shutdown when EN is tied directly to the system bus
and not used to turn on or turn off the device. During tracking startup, VTT follows VTTREF once VDDQSNS
voltage is greater than 0.75 V. VDDQSNS incorporates a resistor divider network and a time constant of about
445 µs. The rise time of the VTT output is then a function of the rise time of VDDQSNS. If the VDDQSNS rise
time is larger than 445 µs. Typically PGOOD is asserted 4 ms after VTT is within ±20% of VTTREF. During
tracking shutdown, VTT falls following VTTREF until VTTREF reaches 0.37 V (typically). Once VTTREF falls
below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both VTTREF and VTT to
GND. PGOOD is deasserted once VTT is beyond the ±20% range of VTTREF. 图 9-4 shows the typical timing
diagram for an application that uses tracking startup and shutdown.
There are no sequencing requirements between VDD and VLDOIN. If VLDOIN is applied first followed by VDD
there is no issue. VDD UVLO protection monitors VDD voltage. When VDD is lower than UVLO threshold both
VTT and VTTREF regulators are powered off.
VDD
EN
VLDOIN
VDDQSNS
VTTREF
EN
(S3_SLP)
VTT = 0.75 V
Trise determined by the
rise time of VDDQSNS
VTT
PGOOD
4 ms
图9-4. Typical Timing Diagram of Tracking Startup and Shutdown
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9.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
The TPS7H3302 is specifically designed to power up the memory termination rail (as shown in 图9-5). The DDR
memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and
source current while maintaining acceptable VTT tolerance. See 图 9-6 for typical characteristics for a single
memory cell.
TPS7H3302-SEP
VTTREF
VTT
Cref
0.1 - 2.2 μF
GND
150 μF
150 μF
150 μF
GND
图9-5. Typical Application Diagram for DDR3 VTT DIMM/Module Using TPS7H3302
In 图9-6, when Q1 is on and Q2 is off:
• Current flows from VDDQ via the termination resistor to VTT.
• VTT sinks current.
In 图9-6, when Q2 is on and Q1 is off:
• Current flows from VTT via the termination resistor to GND.
• VTT sources current.
V
V
TT
DDQ
Q1
Q2
25 W
R
S
20 W
Receiver
Ouput
Buffer
(Driver)
V
V
IN
OUT
V
SS
UDG-08023
图9-6. DDR Physical Signal System SSTL Signaling
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Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the
tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2. See 表 9-2 for detailed
information and JEDEC relevant specifications.
VTTREF –40 mV < VTT < VTTREF + 40 mV, for both DC and AC conditions
The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.
The TPS7H3302 specifies the regulator output voltage to be:
VTTREF –30 mV < VTT < VTTREF + 30 mV, for both DC and AC conditions and –3 A < IVTT < 3 A.
The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to
DDR, DDR2, DDR3 and low-power DDR3/DDR4 applications (see 表 9-2 for detailed information). To meet the
stability requirement, a minimum output capacitance of 470 μF is needed, combination of both tantalum and
ceramic capacitors. Considering the actual tolerance on the MLCC capacitors, four 4.7-μF ceramic capacitors in
parallel with 3 × 150-µF low-ESR tantalum capacitor are sufficient to meet the above requirement. Higher ESR
tantalum capacitors will require multiple tantalum capacitors in parallel with ceramic capacitors to meet system
needs.
表9-2. DDR, DDR2, DDR3, and LP DDR3 Termination Technology and Differences
LOW POWER DDR3
DDR
DDR2
DDR3
(DDR3L)
FSB data rates 200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz
On-die termination for data
800, 1066, 1330 and 1600 MHz Same as DDR3
On-die termination for data
Motherboard termination to group. VTT used for termination group. VTT used for termination
Termination
Same as DDR3
Same as DDR3
VTT for all signals
of address, command and
control signals.
of address, command and
control signals.
Not as demanding
Not as demanding
•
Only 34 signals (address,
command, control) tied to
VTT
•
Only 34 signals (address,
command, control) tied to
VTT
Max sink and source
transient currents of up to
2.6 A to 2.9 A
Termination
current demand
•
ODT handles data signals
•
ODT handles data signals
Less than 1 A of burst current
1.8-V core and I/O 0.9-V VTT
Less than 1 A of burst current
1.5-V core and I/O 0.75-V VTT
2.5-V core and I/O 1.25-V
VTT
1.35-V core and I/O
0.68-V VTT
Voltage level
Relevant
JEDEC
specification
JESD79F (SSTL_2
JESD8-9B)
DDR2 JESD79-2F (SSTL_18
JESD8-15)
DDR3L
JESD79-3-1A.01
DDR3 JESD79-3F
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The TPS7H3302 is designed as a Gm-driven LDO. The voltage droop between the reference input and the
output regulator is determined by the transconductance and output current of the device. The typical Gm is 250
S at 3 A and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very
low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage
loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm. (See below)
Gm
F
=
UGBW
2´ p´ C
OUT
(1)
where
• FUGBW is the unity gain bandwidth
• Gm is transconductance
• COUT is the output capacitance
There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. To
maintain stability, the zero location contributed by the ESR of the output capacitors should be greater than the –
3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the
design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to
prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor, and
parasitic inductance of the VTT trace.
图9-7 shows the bode plot simulation for a typical DDR3 configuration of the TPS7H3302, where:
• VDD = 2.4 V
• VVLDOIN = 1.5 V
• VTT = 0.75 V
• IIO = 3 A
• 3 × 150-μF low-ESR tantalum capacitors (T530D157M010ATE005) in parallel with 4 × 4.7-µF ceramic
capacitor
• ESR = 1.66 mΩ
• ESL = 800 pH
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
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The unity-gain bandwidth is approximately 85 kHz and the phase margin is 92°. The 0-dB level is crossed, the
gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
Bode Plot for DDR3 VDDQSNS = 1.5V
VTT load 3 A
100
90
80
70
60
200
180
160
140
120
100
80
Gain
Phase
50
40
30
60
20
40
10
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
10 20 50 100200
1000
10000
100000
1000000 5000000
Frequency
图9-7. Bode Plot for a Typical DDR3 Configuration
The figure below shows the Load Regulation and Transient Plot shows the transient response for a typical DDR3
configuration. When the regulator is subjected to a ±1.875-A load step. The current shown only represents the
device sourcing 1.875 A due to location of current probe.
图9-8. Transient Plot
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
9.2.2.9 LDO Design Guidelines
For TPS7H3302, a minimum of 420 mV (VLDOINMIN – VTTMAX) is needed in order to support a Gm driven
sourcing current of 2 A based on the specified dropout voltage maximum at VDDQSNS = 1.5 V. Because the
TPS7H3302 is essentially a Gm-driven LDO, its impedance characteristics are both a function of the 1/Gm and
RDS(on) of the sourcing MOSFET (see TPS7H3302 Impedance Characteristics). The current inflection point of
the design is between 3 A and 4 A. When ISRC is less than the inflection point, the LDO is considered to be
operating in the Gm region; when ISRC is greater than the inflection point but less than the overcurrent limit point,
the LDO is operating in the RDS(on) region. The typical sourcing RDS(on) is 154 mΩ with VIN = 3 V and TJ = 125°C.
1/Gm
Inflection
Point
1/R
DS(on)
(between
2 A and 3 A)
Overcurrent
Limit
I
- Source Current - A
SRC
UDG-08026
图9-9. TPS7H3302 Impedance Characterisitcs
9.2.3 Application Curve
Bode Plot for DDR3 VDDQSNS = 1.5V
VTT load 1 A
100
90
80
70
60
200
180
160
140
120
100
80
Gain
Phase
50
40
30
60
20
40
10
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
10 20 50 100200
1000
10000
100000
1000000 5000000
Frequency
图9-10. DDR2 2-A Load VDD = 2.4 V, VTT = 0.9 V
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
9.3 Power Supply Recommendations
TPS7H3302 is designed to support DDR, DDR2, DDR3, DDR3L, and DDR4 VTT applications. TPS7H3302
VLDOIN supports voltage range from 0.9 V to 3.5 V. The supply must be well regulated. Having a separate
VLDOIN supply from DDR VDDQ allows designer to optimize system efficiency. VDD is used to bias the
TPS7H3302 IC and its voltage range from 2.375 V to 3.5 V. This supply must be well regulated and bypassed
with a ceramic capacitor with a value of 1 µF and 10 µF. TI recommends that VLDOIN and DDR supply VDDQ
be isolated from each other. If this is not possible then an RC filter must be used to isolate VLDOIN and
VDDQSNS. However, in so doing the dynamic tracking of VTT and VTTREF will be reduced. See the EVM
user's guide SLVUCK2 for additional details.
9.4 Layout
9.4.1 Layout Guidelines
Consider the following points before starting the TPS7H3302 layout design.
• The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide
connections.
• The output capacitor for VTT should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL trace inductance.
• VTTSNS should be connected to the positive node of VTT output capacitors as a separate trace from the
high-current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If
sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor or
capacitors at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace
between the GND pin and the output capacitor or capacitors.
• Consider adding low-pass filter at VTTSNS if the ESR of the VTT output capacitor or capacitors is larger than
2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the
reference voltage of VTTREF. Avoid any noise-generating lines.
• The negative node of the VTT output capacitor or capacitors and the VTTREF capacitor should be tied
together by avoiding common impedance to the high-current path of the VTT sink and source current.
• The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.
Also, place bulk caps close to the DIMM/module or memory load point and route the VTTSNS to the DIMM/
module load sense point.
• In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package’s thermal pad. Numerous vias, 0.33 mm in diameter or smaller, connected from the thermal
land to the internal/solder side ground plane or planes should also be used to help dissipation.
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
9.4.2 Layout Example
To VTTREF Host
To VDDQ Source
Vias from top layer thermal pad to GND (PGND)
NC
NC
NC
NC
NC
NC
Cap
VTTREF
VDDQSNS
NC
VTTSNS
AGND
NC
VLDOIN PLANE
VLDOIN
VLDOIN
VTT
VTT
VTT
VTT
VTT PLANE
Cap
Cap
Cap
Cap
Cap
PGND
PGND
Cap
Cap
Cap
Cap
Cap
Cap
Cap
PGOOD
VDD
EN
NC
NC
PGND
NC
NC
NC
NC
Res
Cap
NC
NC
TPS7H3302-SEP
To GPIO or Host
Main Ground
Plane
From GPIO or Host
图9-11. Layout Example
9.4.3 Thermal Considerations
VTT current can flow in both source and sink directions. As the TPS7H3302 is a linear regulator, power is
dissipated internal to the device. When the device is sourcing current, the voltage difference between VLDOIN
and VTT times IO (IIO ) current becomes the power dissipation as shown in 方程式2.
P
=
V
(
- V
x I
O _SRC
)
DISS _SRC
VLDOIN
VO
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power
loss can be reduced. For the sink phase, VTT voltage is applied across the internal LDO regulator and the power
dissipation (PDISS_SNK) can be calculated by 方程式3.
P
= V ´ I
VO O _SNK
DISS _SNK
(3)
Because the device does not sink and source current at the same time and the IO current may vary rapidly with
time, the actual power dissipation should be the time average of the above dissipations over the thermal
relaxation duration of the system. Another source of power consumption is the current used for the internal
current control circuitry from the VDD supply and the VLDOIN supply. This can be estimated as 5 mW or less
during normal operating conditions. This power must be effectively dissipated from the package.
The thermal performance of an LDO depends on the printed circuit board (PCB) layout.
To further improve the thermal performance of this device, using a larger than recommended thermal land as
well as increasing the number of vias helps lower the thermal resistance from junction to heat slug.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGX6
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10 Device and Documentation Support
10.1 Device Support
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS7H3302-SEP Single-Event Effects Summary radiation report (SLVK132)
• Texas Instruments, TPS7H3302EVM-CVAL (HREL022) user's guide (SLVUCK2)
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 Support Resources
10.5 Trademarks
所有商标均为其各自所有者的财产。
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OUTLINE
TM
PowerPAD TSSOP - 1.2 mm max height
DAP0032F
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID AREA
30X 0.65
32
1
11.1
10.9
NOTE 3
2X
9.75
16
B
17
0.30
32X
0.19
6.2
6.0
0.1 C
0.1
C A B
SEATING PLANE
(0.15) TYP
C
SEE DETAIL A
4.11
3.29
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
4.06
3.16
1.2 MAX
0.75
0.50
0.15
0.05
2X (0.9)
NOTE 5
0 - 8
2X (0.15)
NOTE 5
DETAIL A
TYPICAL
4226056/A 07/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DAP0032F
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(4.11)
32X (1.5)
SYMM
SEE DETAILS
1
32
32X (0.45)
30X (0.65)
(11)
NOTE 9
SYMM
(4.06)
(1.2 TYP)
(R0.05) TYP
(
0.2) TYP
VIA
16
17
(0.65) TYP
(1.3) TYP
METAL COVERED
BY SOLDER MASK
(7.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4226056/A 07/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: TPS7H3302-SP TPS7H3302-SEP
English Data Sheet: SLVSGX6
TPS7H3302-SP, TPS7H3302-SEP
ZHCSRP2A –FEBRUARY 2023 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DAP0032F
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(4.11)
BASED ON
0.125 THICK
STENCIL
32X (1.5)
1
32
32X (0.45)
30X (0.65)
(4.06)
BASED ON
SYMM
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
16
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
4.60 X 4.54
4.11 X 4.06 (SHOWN)
3.75 X 3.71
0.125
0.15
0.175
3.47 X 3.43
4226056/A 07/2020
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS7H3302-SP TPS7H3302-SEP
English Data Sheet: SLVSGX6
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7H3302MDAPTSEP
V62/22615-01XE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
DAP
32
32
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
TPS7H3302
TPS7H3302
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
DAP 32
8.1 x 11, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225303/A
www.ti.com
PACKAGE OUTLINE
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID AREA
30X 0.65
32
1
11.1
10.9
NOTE 3
2X
9.75
16
B
17
0.30
32X
0.19
6.2
6.0
0.1 C
0.1
C A B
SEATING PLANE
(0.15) TYP
C
SEE DETAIL A
4.11
3.29
EXPOSED
THERMAL PAD
0.25
4.06
3.16
1.2 MAX
GAGE PLANE
0.75
0.50
0.15
0.05
2X (0.9)
NOTE 5
0 - 8
2X (0.15)
NOTE 5
DETAIL A
TYPICAL
4226056/A 07/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(4.11)
32X (1.5)
SYMM
SEE DETAILS
1
32
32X (0.45)
30X (0.65)
(11)
NOTE 9
SYMM
(4.06)
(1.2 TYP)
(R0.05) TYP
(
0.2) TYP
VIA
16
17
(0.65) TYP
(1.3) TYP
(7.5)
METAL COVERED
BY SOLDER MASK
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4226056/A 07/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAP0032F
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(4.11)
BASED ON
0.125 THICK
STENCIL
32X (1.5)
1
32
32X (0.45)
30X (0.65)
(4.06)
BASED ON
SYMM
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
16
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
4.60 X 4.54
4.11 X 4.06 (SHOWN)
3.75 X 3.71
0.125
0.15
0.175
3.47 X 3.43
4226056/A 07/2020
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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