TPS8804DCPR [TI]
商用烟雾探测器模拟前端 | DCP | 38 | -40 to 85;
| 型号： | TPS8804DCPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 商用烟雾探测器模拟前端 | DCP | 38 | -40 to 85 |
| 文件： | 总58页 (文件大小：2232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS8804
ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
TPS8804 烟雾探测器AFE
1 特性
2 应用
• 照相室AFE
• 烟雾和一氧化碳探测器
3 说明
– 双8 位可编程电流LED 驱动器
– LED 电流温度补偿
TPS8804 集成了双波光电烟雾探测和一氧化碳探测系
统所需的所有放大器和驱动器。它的高度灵活性非常适
合精度和功耗至关重要的烟雾探测系统。
– 用于光电二极管的超低失调电压运算放大器
– 可编程和可旁路增益级
• 一氧化碳传感器AFE
器件信息(1)
– 超低失调电压增益级
– 可编程增益和基准
• 电源管理
封装尺寸（标称值）
器件型号
封装
TSSOP (38)
9.7mm x 4.4mm
– 用于外部微控制器的可编程LDO
• SLC 接口发送器和接收器
• 超低功耗
• I2C 串行接口
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 宽输入电压范围
VLINE
TPS8804
Pre-Regulator
VSLC
COO
5V to 15V
VCC
CON
COP
PLDO
VINT
CO
Sensor
REF0P3
LEDLDO
PREF
VMCU
MCUSEL
Photo
Chamber
PDP
PDN
PDO
ADC
AMUX
Blue IR
VIN
LEDEN
GPIO
GPIO
DINA
DINB
CSA
CSB
MCU
SCL
I2C
VLINE
SDA
CSEL
SLC_TX1
SLC_RX
GPIO
MCU_TX1
MCU_RX
AGND PGND DGND
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSF29
TPS8804
www.ti.com.cn
ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
Table of Contents
7.5 Programming............................................................ 31
7.6 Register Maps...........................................................31
8 Application and Implementation..................................40
8.1 Application Information............................................. 40
8.2 Typical Application.................................................... 40
9 Power Supply Recommendations................................44
10 Layout...........................................................................45
10.1 Layout Guidelines................................................... 45
10.2 Layout Example...................................................... 45
11 Device and Documentation Support..........................48
11.1 接收文档更新通知................................................... 48
11.2 支持资源..................................................................48
11.3 Trademarks............................................................. 48
11.4 静电放电警告...........................................................48
11.5 术语表..................................................................... 48
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics..............................................16
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................30
Information.................................................................... 49
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (March 2021) to Revision C (August 2021)
Page
• Updated 图7-3 ................................................................................................................................................ 23
• Added Connect a capacitor with a value between 1 µF and 100 µF to the LEDLDO. to 节7.3.4.2 ................ 24
• Updated VCCLOW description in 节7.6.2 .......................................................................................................33
Changes from Revision A (March 2020) to Revision B (March 2021)
Page
• Changed typical IMCULDO,Q based on measurement data...................................................................................6
• Changed typical ICO,Q based on measurement data.......................................................................................... 6
Changes from Revision * (October 2019) to Revision A (March 2020)
Page
• 将文档状态从预告信息 更改为量产数据 ............................................................................................................ 1
• Added typical value to VPDIN,OFS ....................................................................................................................... 6
• Added typical value to VOFFS,CO ........................................................................................................................ 6
• Added typical value to VMUX,OFFS ...................................................................................................................... 6
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF29
2
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
5 Pin Configuration and Functions
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RESERVED
RESERVED
RESERVED
LEDLDO
AGND
REF0P3
PREF
COP
2
3
4
CON
5
COO
6
PDP
AMUX
DGND
LEDEN
MCU_TX1
CSEL
7
PDN
8
PDO
9
CSA
10
11
12
13
14
15
16
17
18
DINA
CSB
SDA
DINB
SCL
Thermal
Pad
MCUSEL
SLC_TX1
SLC_TX2
MCU_TX2
PGND
GPIO
MCU_RX
SLC_RX
VMCU
VINT
RESERVED
VSLC
PLDO
VCC
19
20
图5-1. DCP Package 38-Pin TSSOP Top View
Pin Functions
PIN
NAME
AGND
AMUX
CON
I/O
DESCRIPTION
Analog ground. Connect to ground plane.
NO.
5
I
O
I
33
35
34
36
9
Analog multiplexer output.
Negative terminal of CO operational amplifier. Connect to GND if unused.
Output of CO operational amplifier. Connect to GND if unused.
Positive terminal of CO operational amplifier. Connect to GND if unused.
LED driver A current sense.
COO
O
I
COP
CSA
I
CSB
11
I
LED driver B current sense. Connect to GND if unused.
Device address select pin for I2C serial interface. Pull to GND for I2C address 0x3F. Pull to
VMCU for I2C address 0x2A. Do not leave floating.
CSEL
29
I
DGND
32
10
12
26
31
4
I
I
Digital ground. Connect to AGND.
DINA
LED driver A current sink. Connect to cathode of LED.
LED driver B current sink. Connect to cathode of LED. Connect to GND if unused.
Multi-purpose digital input and output.
DINB
I
GPIO
I/O
I
LEDEN
LEDLDO
MCU_RX
MCU_TX1
MCU_TX2
LED driver enable. Do not leave floating while device is powered.
LDO output for charging LED supply capacitor. Connect to GND if unused.
SLC interface output for receiving data from VLINE.
O
O
I
25
30
16
Primary SLC interface input for transmitting data to VLINE.
Secondary SLC interface input for transmitting data to VLINE.
I
Default MCULDO voltage selection input. Leave floating for VMCU = 3.3 V. Tie to VINT for
VMCU = 2.5 V. Tie to GND for VMCU = 1.8 V. Connect to GND with 620-Ωresistor for
VMCU = 1.5 V.
MCUSEL
13
I
PDN
PDO
PDP
7
8
I
O
I
Photo input amplifier negative input. Connect to cathode of photodiode.
Photo input amplifier output pin.
6
Photo input amplifier positive Input. Connect to anode of photodiode.
Power ground connection . Connect to AGND.
PGND
17
I
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English Data Sheet: SLVSF29
TPS8804
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
PIN
I/O
DESCRIPTION
Capacitor connection to PLDO regulator.
NAME
NO.
21
PLDO
O
O
PREF
37
Photo reference voltage and output for testing CO sensor connectivity.
300mV reference. Connect to GND if unused.
Connect to GND.
REF0P3
RESERVED
SCL
38
O
1, 2, 3, 18
27
N/A
I
Clock input for I2C serial interface.
SDA
28
I/O
I
Data line for I2C serial interface.
SLC_RX
SLC_TX1
SLC_TX2
VCC
24
SLC interface input for receiving data from VLINE.
Primary SLC interface output for transmitting data to VLINE.
Secondary SLC interface output for transmitting data to VLINE.
Input supply pin.
14
O
15
O
20
I
VINT
22
O
Capacitor connection to internal supply LDO.
LDO supply for external microcontroller and internal IO buffers.
SLC transmitter supply.
VMCU
23
I/O
I
VSLC
19
Thermal Pad
39
N/A
Metal connection for thermal dissipation. Connect to ground plane.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF29
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
–0.3
–0.3
MAX
16.5
12
UNIT
V
Power IO
Analog IO
SLC_TX1, SLCTX_2, VCC, VSLC
DINA, DINB, LEDLDO
V
VINT + 0.3 or
3.6, whichever
is lower
Analog
connections
AMUX, CON, COO, COP, PREF, MCUSEL, PDO, REF0P3
V
V
V
–0.3
–0.3
–0.3
PLDO + 0.3 or
3.6, whichever
is lower
LDO outputs
VINT, VMCU
CSA
DINA + 0.3 or
3.6, whichever
is lower
LED current
sense
DINB + 0.3 or
3.6, whichever
is lower
LED current
sense
CSB
V
V
–0.3
–0.3
Photo amplifier
inputs
PDN, PDP
3.6
PLDO voltage
SLC receiver
PLDO
7.0
18
V
V
–0.3
–0.3
SLC_RX
VMCU + 0.3 or
3.6, whichever
is lower
Digital IO
CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1, MCU_TX2, SCL, SDA
V
–0.3
-40
Max operating
ambient
temperature
TA
TJ
125
125
°C
°C
Max operating
junction
-40
temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
Value
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 1
±3000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 2
±1500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
SLC transmitter
VSLC
4.5
15.6
V
supply
Power supply
LED driver
VCC
2.6
0
15.6
11.5
V
V
DINA, DINB
1
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
2
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English Data Sheet: SLVSF29
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
0
MAX
17
UNIT
V
SLC receiver
Digital IO
SLC_RX
CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1, MCU_TX2, SCL, SDA
0
VMCU
V
Digital IO
supply
VMCU
TA
1.425
–40
–40
3.6
85
85
V
Ambient
temperature
°C
°C
Junction
temperature
TJ
6.4 Thermal Information
TPS8804
THERMAL METRIC(1)
DCP
38 PINS
29.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
20.0
10.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
10.0
ΨJB
RθJC(bot)
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
INPUT VOLTAGE AND CURRENTS
Power up threshold. Note:
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPWRUP
Device enters active state
when MCU_PG=1.
VCC rising
1.2
1.55
2.0
V
VPWRDOWN
VPWR, HYS
Power down threshold
VCC falling
0.932
6.4
1.15
400
2.0
V
VCC power up to power down
hysteresis
580
mV
PLDO voltage rising
Deglitch time
2.35
110
2.54
141
2.42
141
2.7
172
2.6
V
µs
V
VCC low warning reset
threshold
VVCCLOW, RISE
PLDO voltage falling
Deglitch time
2.15
110
VCC low warning assert
threshold
VVCCLOW, FALL
172
µs
All blocks that can be
disabled are off, TJ=27C,
VCC=3V, VMCU=1.8V
3.8
7.7
4.4
9.1
µA
µA
ISTANDBY
Standby Supply Current
All blocks that can be
disabled are off, TJ=27C,
VCC=9V, VMCU=3.3V
POWER LDO
VCC = 2.0 V, IPLDO = 10 mA
VCC = 2.0 V, IPLDO = 30 mA
VCC = 3.3 V, IPLDO = 30 mA
VCC = 9 V, IPLDO = 30 mA
VCC = 11.5 V, IPLDO = 30 mA
1.93
1.8
3.1
4.1
4.1
1.96
1.89
3.22
4.9
1.99
1.95
3.3
V
V
V
V
V
VPLDO
Output Voltage
6.7
5
6.7
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF29
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLDO capacitor required for
stability
CPLDO
INTERNAL LDO
Output Voltage
0.7
1
1.3
µF
IVINT < 10 mA
2.25
2.25
2.3
2.3
2.35
2.40
V
V
IVINT < 10 uA, T>80C
No external/internal load,
VCC = 2.6 V - 11.5 V
DC Output Voltage Accuacy
Line Regulation
2
2
2
8
5
%
%
%
%
%
dB
–2
–2
–2
–8
–5
50
VCC = 2.6 V-11.5 V, IOUT =
10 mA
IVINT = 0 mA - 10 mA, VCC =
3 V
VINTLDO
Load Regulation
IVINT stepped from 0 mA to 10
mA in 1us
Transient regulation
PSRR
IVINT stepped from 10 mA to 0
mA in 1us
VIN = 3.0 V, IOUT = 10 mA, f =
60 Hz (200 mVpp)
IINTLDO, OUT
IINTLDO, SC
Output current range
0
10
mA
mA
Short Circuit Current Limit
30
280
52
1
500
From PLDO to VINT, IVINT
10 mA, PLDO = 2.2 V
=
VINTLDO, DO
Dropout Voltage
66
mV
Output Capacitor
0.7
1.3
µF
CINTLDO, OUT
Ceramic
ESR of Output Capacitor
100
mΩ
MCU LDO
IMCULDO < 30 mA, VCC > 2.2
V, VMCUSET = 00 (T < 80°C
for no load)
1.425
1.425
1.71
1.71
2.38
2.38
3.13
1.5
1.5
1.8
1.8
2.5
2.5
3.3
1.575
1.65
1.89
1.98
2.63
2.75
3.47
V
V
V
V
V
V
V
IMCULDO < 10 uA, VCC > 2.2 V,
VMCUSET = 00, T > 80°C
IMCULDO < 30 mA, VCC > 2.6
V, VMCUSET = 01 (T < 80°C
for no load)
IMCULDO < 10 uA, VCC > 2.6 V,
VMCUSET = 01, T > 80°C
IMCULDO < 30 mA, VCC > 3.65
V, VMCUSET = 10 (T < 80°C
for no load)
Output Voltage(1)
VMCULDO
IMCULDO < 10 uA, VCC > 3.65
V, VMCUSET = 10, T > 80°C
IMCULDO < 10 mA, VCC > 3.65
V, VMCUSET = 11 (T < 80°C
for no load)
IMCULDO < 10 uA, VCC > 4.5 V,
VMCUSET = 11, T > 80°C
3.13
3.13
3.3
3.3
3.60
3.47
V
V
IMCULDO < 50 mA, VCC > 5.5
V, VMCUSET = 11
DC Output Voltage Accuracy T < 80°C
5
95
85
%
%
%
–5
75
VMCU rising
VMCU falling
82
78
MCULDO power good
threshold
VMCULDO,PG
65
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English Data Sheet: SLVSF29
TPS8804
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC > 2.2 V, VMCUSET = 00
VCC > 2.6 V, VMCUSET = 01
MIN
0
TYP
MAX
30
UNIT
mA
0
30
mA
IMCULDO
Output Current Range
VCC > 3.65 V, VMCUSET =
10
0
0
30
50
7
mA
mA
%
VCC > 4.5 V, VMCUSET = 11
IMCULDO stepped from 0 mA
to 10 mA in 1us, T < 80°C
–7
IMCULDO stepped from 0 mA
to 10 mA in 1us, T > 80°C
8
5
%
%
–8
–5
MCULDO load transient
regulation
VMCULDO, TR
IMCULDO stepped from 10 mA
to 0 mA in 1us, T < 80°C
IMCULDO stepped from 10 mA
to 0 mA in 1us, T > 80°C
8
%
–8
IMCULDO, SC
Short Circuit current limit
72
162
600
253
mA
CMCULDO = 1µF, time from
VMCU=0V to 90% of target
voltage
tMCULDO, PWR Power Up Time
1100
158
µs
µs
MCULDO power good
deglitch time
TMCULDO, PG
92
125
10
MCULDO low voltage error
mask time. MCULDO_ERR is
masked for
T_MCULDO,MASK after
VMCUSET or MCU_DIS is
changed.
TMCULDO,
ms
MASK
IMCULDO, Q
CMCULDO
Quiescent Current
Output Capacitor
IMCULDO = 0µA
Ceramic
2.04
1
3
10
µA
µF
0.7
ESR of Output Capacitor
100
mΩ
Pull-down resistance to set
VMCUSET[1:0]=00 on
powerup
558
0
620
682
10
Ω
Ω
Ω
pF
Pull-down resistance to set
VMCUSET[1:0]=01 on
powerup
MCUSEL component
requirements. Not tested in
production
RMCUSEL
Pull-up resistance to VINT to
set VMCUSET[1:0]=10 on
powerup
0
10
Capacitance to set
VMCUSET[1:0]=11 on
powerup
300
1000
PHOTO CHAMBER INPUT STAGE AMPLIFIER
PAMP_EN=1, Feedback
network: 1.5M Ω, 10pF
VPDO
Output voltage range
0
0.5
V
fPDIN, BW
Unity Gain Bandwidth
Input Offset Voltage
1
5
MHz
µV
VPDIN, OFS
-530
-195
240
50mV applied to PDP with
1.5MΩ series resistor. 1.5MΩ
resistor connects PDN to
PDO. Voltage measured
between 50mV and PDO.
VPDO, OFS
Output Offset Voltage
Chop Frequency
-10
10
mV
fPDIN, CHOP
2
MHz
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF29
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Feedback network: 1.5M Ω,
10pF. 1 nA to 10 nA applied
from PDN to PDP. 0V
reference
0
30
40
µs
Input amplifier settling time.
Time between stepping the
current and measuring 90%
of the final value + 10% of the
initial value at PDO
TPDIN, SET
Feedback network: 1.5MΩ,
5pF. 1.5MΩ connected from
PDP to PREF. 1 nA to 10 nA
applied from PDN to PDP.
PREF_SEL=1
0
20
40
µs
Active current. Current does
not include bias block or 8
MHz oscillator.
IPDIN, ACT
175
210
µA
PHOTO CHAMBER GAIN STAGE AMPLIFIER
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
00
4.75
10.67
19.4
4.9
11
5.05
11.33
20.6
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
Closed Loop Gain
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
01
Slope (VAOUT_PH2
-
VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
COTEST to PDO and
measure AOUT_PH
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
10
20
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
11
33.95
4.61
35
36.05
4.89
GPGAIN
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
00
4.75
10.4
18.5
Closed Loop Gain
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
01
Slope (VAOUT_PH2
-
10.09
17.94
31.28
10.71
19.06
33.22
VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
PREF to PDO and measure
AOUT_PH
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
10
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
11
32.25
5
FPGAIN, BW
VPGAIN, OFS
Unity Gain Bandwidth
Input offset Voltage
1
8
5
MHz
mV
-6
Gain amplifier settling time.
Time between stepping the
PGAIN[1:0]=00. PDO
TPGAIN, SET
voltage and measuring 90% stepped from 3mV to 30mV.
of the final value + 10% of the PREF_SEL=0
initial value at AOUT_PH
1.8
40
2.522
70
µs
µA
V
1.0 V input voltage,
Active current. Current does
PGAIN[1:0] = 00, PGAIN_EN
not include bias block.
IPGAIN, ACT
= 1
LED LDO
LEDLDO output voltage
range
VLEDLDO
7.5
-5
10
5
VLEDLDO,ACC LDO output accuracy
I_LEDLDO = 0uA to 100uA
%
V
VLEDLDO, RES LED LDO output step size
0.5
3
ILEDLDO, OUT
ILEDLDO, Q
LDO output current limit
1
6
mA
Quiescent current. Current
does not include bias block.
31
60
µA
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLEDLDO, DROP LED LDO dropout voltage
LED DRIVER A
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSLC=7V, ILEDLDO=100uA
565
1000
mV
NPDACA, RES
Resolution
8
Bits
mV
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
274
567
252
546
164
458
54
299
323
619
301
597
213
510
104
403
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
593
277
572
188
484
79
mV
mV
mV
mV
mV
mV
mV
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
VCSA
CSA output voltage
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
350
376
DAC step size
VPDACA, STEP INL
DNL
Settling Time
1.18
mV
LSB
LSB
µs
-10
10
1.5
5
-1.5
tPDACA, SET
1
TEMPCOA[1:0] = 00,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
0.174
0.208
0.346
0.520
0.347
0.521
0.624
1.039
1.560
mV/°C
mV/°C
mV/°C
mV/°C
TEMPCOA[1:0] = 01,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
0.416
0.693
1.040
CSA temperature
compensation coefficient
KPDACA, COMP
TEMPCOA[1:0] = 10,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
TEMPCOA[1:0] = 11,
PDAC_A[7:0] = 0x00, RCSA=1
kOhms, VDINA=3V, TJ=0°C,
50°C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSF29
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=11,
PDAC_A[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
Dropout voltage. Voltage
required between DINA and
CSA for current regulation.
VDINA, DROP
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=01,
PDAC_A[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
550
mV
mA
IDINA
LED current
Resolution
0
LED DRIVER B
NPDACB, RES
8
Bits
mV
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
271
562
250
541
163
456
55
299
327
626
305
604
216
516
108
408
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
594
277
572
189
486
81
mV
mV
mV
mV
mV
mV
mV
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
VCSB
CSB output voltage
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
350
379
DAC step size
VPDACB, STEP INL
DNL
Settling time
1.18
mV
LSB
LSB
µs
-10
10
1.5
5
-1.5
tPDACB, SET
1
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPCOB[1:0] = 00,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.174
0.347
0.521
mV/°C
TEMPCOB[1:0] = 01,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.208
0.346
0.520
0.416
0.693
1.040
0.624
1.039
1.560
mV/°C
mV/°C
mV/°C
CSB temperature
compensation coefficient
KPDACB, COMP
TEMPCOB[1:0] = 10,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
TEMPCOB[1:0] = 11,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=11,
PDAC[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
Dropout voltage. Voltage
required between DINB and
CSB for current regulation.
VDINB, DROP
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=01,
PDAC[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
550
mV
mA
IDINB
LED current
0
CO TRANSIMPEDANCE AMPLIFIER
RI, CO
CO input resistance
COSWRI = 1
0.7
1
1.5
kΩ
kΩ
COGAIN[1:0] = 00,
COSWRG = 1
770
1100
1430
COGAIN[1:0] = 01,
COSWRG = 1
210
350
560
0
300
500
800
390
650
1040
0.6
kΩ
kΩ
kΩ
V
RF, CO
CO feedback resistance
COGAIN[1:0] = 10,
COSWRG = 1
COGAIN[1:0] = 11, COSWRG
= 1
CO amplifier input voltage
(COP pin)
VIN, COP
VIN, CON
VOFFS, CO
VOUT, COO
ICO, Q
CO amplifier input voltage
(CON pin)
0
0.6
V
CO amplifier input offset
voltage
-130
0.1
94
300
2
µV
V
CO amplifier output voltage
(COO pin)
CO amplifier quiescent
current
0.63
2.1
µA
CO amplifier unity gain
bandwidth
fCO, BW
fCO, CHOP
RCOO
5
3.8
70
12
4
20
4.2
kHz
kHz
kΩ
CO amplifier chop frequency
CO amplifier output
resistance
COSWRO = 1
95
130
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English Data Sheet: SLVSF29
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COSWREF=1, COREF[1:0] =
00, TJ = 27°C
0.89
1.14
1.47
COSWREF=1, COREF[1:0] =
00, TJ = -40°C to 85°C
0.86
1.75
1.7
1.14
2.23
2.23
3.23
3.23
4.43
4.43
0.76
0.37
1.66
2.7
COSWREF=1, COREF[1:0] =
01, TJ = 27°C
COSWREF=1, COREF[1:0] =
01, TJ = -40°C to 85°C
2.95
4
CO amplifier reference
voltage
VCOPREF
mV
COSWREF=1, COREF[1:0] =
10, TJ = 27°C
2.6
COSWREF=1, COREF[1:0] =
10, TJ = -40°C to 85°C
2.55
3.45
3.4
4.24
5.38
5.48
1.1
COSWREF=1, COREF[1:0] =
11, TJ = 27°C
COSWREF=1, COREF[1:0] =
11, TJ = -40°C to 85°C
COTEST pull up FET
resistance
RCOTEST, PU
RCOTEST, PD
0.36
0.25
kΩ
kΩ
COTEST pull-down FET
resistance
0.82
SLC INTERFACE
SLCRX_EN=1, SLCRX_DE
G[1:0]=00
0
0.090
0.9
0
0.125
1
0.065
0.160
1.1
SLCRX_EN=1, SLCRX_DE
G[1:0]=01
tSLCRX, DEG
SLC receiver deglitch time
ms
SLCRX_EN=1, SLCRX_DE
G[1:0]=10
SLCRX_EN=1, SLCRX_DE
G[1:0]=11
19.8
20
20.2
ISLCRX, Q
SLC receiver standby current SLCRX_EN = 1
0.25
2.0
2.0
0.8
1.8
1.2
0.2
107
41
0.5
2.7
2.7
1.1
2.7
1.7
0.3
165
56
uA
V
SLCRX_HYS=0
SLCRX_HYS=1
SLCRX_HYS=0
SLCRX_HYS=1
SLCRX_HYS=0
SLCRX_HYS=1
SLCRX_PD=1
SLCRX_PD=0
1.3
1.3
0.5
1.2
0.7
0.01
65
SLC receiver input high
threshold voltage
VSLCRX,IHI
V
V
SLC receiver input low
threshold voltage
VSLCRX,ILO
VSLCRX,HYS
RSLCRX,PD
V
V
SLC receiver input hysteresis
V
kΩ
MΩ
SLC receiver input pulldown
resistance
3.5
VSLC=11.5V,
ISLC_TXx=−16mA
SLC transmitter output high
voltage
VSLCTXx ,OH
VSLCTXx,OL
11.0
0
11.3
0.1
11.5
0.5
V
V
SLC transmitter output low
voltage
VSLC=11.5V, ISLC_TXx=16mA
ANALOG MULTIPLEXER
Multiplexer buffer input signal
voltage range
VMUX
AMUX_BYP=0
0.05
0.99
-8
2
1.01
8
V
GMUX, GAIN
VMUX, OFFS
Multiplexer bufffer output gain AMUX_BYP=0
1
V/V
mV
Multiplexer buffer offset
AMUX_BYP=0
voltage
-0.5
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UNIT
ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AMUX_BYP=0, AMUX_SEL
stepped from 000 to 011 with
PDO=2V, PAMP_EN=0. Time
until AMUX reaches 99% of
its final value
Multiplexer buffer enable
settling time
tMUX, EN
0
10
15
us
us
AMUX_BYP=0,
AMUX_SEL=011, PDO
stepped from 50mV to 2V,
PAMP_EN=0. Time until
AMUX reaches 99% of its
final value
Multiplexer buffer input step
settling time
tMUX, STEP
0
10
1
15
fMUX, BW
Multiplexer bandwidth
AMUX_BYP=0
AMUX_BYP=0
0.5
25
10
MHz
uA
IMUX, OUT
Multiplexer output current
–10
Multiplexer quiescent
current. Current does not
include bias block.
IMUX, Q
AMUX_BYP=0
AMUX_BYP=0
8.3
50
uA
pF
Multiplexer buffer output
capacitor required for stability
CMUX
150
1000
OSCILLATOR, REFERENCE SYSTEM
Oscillator frequency
fOSC8
8
MHz
%
Frequency accuracy
TA = -10°C to 70°C
TA = -10°C to 70°C
3
–3
Low-power Oscillator
32
kHz
frequency
fOSC32
Frequency accuracy
3
%
s
–3
TTIMEOUT
IREF0P3, Q
Error timeout time
0.9
1
1.1
VCC current difference
between REF0P3_EN=0 and
REF0P3=1. IREF0P3=0 µA
REF0P3 buffer quiescent
current
0.38
0.76
1.5
µA
nF
ms
REF0P3 output capacitor
required for stability
CREF0P3
0.7
1
1
From REF0P3 enabled to
99% of final output voltage.
CREF0P3=1nF, IREF0P3=0 µA
TREF0P3, SET
REF0P3 settling time
1.8
IREF0P3 = 10 µA
IREF0P3 = -25 µA
270
270
300
300
330
330
mV
mV
VREF0P3, OUT REF0P3 output voltage
VCC_LOW monitor quiescent
IVCCLOW,Q
current
0.9
2
uA
IO BUFFERS
LEDEN, CSEL, MCU_TX1,
MCU_TX2, GPIO
VIO, ILO
VIO, IHI
IO buffer input low threshold
IO buffer input high threshold
0.3×VMCU
0.3×VMCU
0.7× VMCU
0.7× VMCU
V
V
LEDEN, CSEL, MCU_TX1,
MCU_TX2, GPIO
LEDEN
MCU_TX1
CSEL
100
100
100
nA
nA
nA
IO buffer input leakage
current
IIO, LEAK
MCU_RX, GPIO. IIO = 3 mA,
VMCU = 1.8 V
0
0
0
0
0.19
0.20
0.30
0.37
0.6
0.6
0.6
0.6
V
V
V
V
VIO, OL
IO buffer output low-level
MCU_RX, GPIO. IIO = 1 mA,
VMCU = 1.5 V
MCU_RX, GPIO. IIO = -3 mA,
VMCU = 1.8 V
IO buffer output high-level.
Spec is the voltage drop from
VMCU (i.e. VMCU - VOH)
VIO, OH
MCU_RX, GPIO. IIO = -1 mA,
VMCU = 1.5 V
Copyright © 2023 Texas Instruments Incorporated
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2
MAX
10
UNIT
pF
CIN, IO
CIN, IO
CIN, IO
RIO,PD
Input capacitance
Input capacitance
Pin capacitance
IO pulldown resistor
LEDEN, CSEL
MCU_TX1, MCU_TX2
MCU_RX, GPIO
2
10
pF
2
10
pF
MCU_RX, GPIO
0.8
10
50
MΩ
THERMAL WARNING
TWARNING
Thermal trip point
110
C
C
THERMAL SHUTDOWN
Thermal trip point
125
15
TSHTDWN
Thermal hysteresis
5
20
Thermal error mask time.
OTS_ERR is masked for
tOTS,MASK after device fully
powers up or OTS_EN set to
1
tOTS,MASK
300
350
us
I2C IO
VI2C,IL
VI2C,IH
Low-level input voltage
High-level input voltage
-0.5
0.3 × VMCU
V
V
0.7 × VMCU
Hysteresis of Schmitt trigger
inputs
VI2C,HYS
0.05 × VMCU
V
V
V
3 mA sink current; VMCU
>2V
0
0
0.4
VI2C,OL
Low-level output voltage
2 mA sink current; VMCU
< 2V
0.2 × VMCU
VOL = 0.4 V
VOL = 0.6 V
2.5
4
mA
mA
µA
pF
II2C,OL
Low-level output current
II2C,IN
Input current to each I/O pin 0.1VMCU < VI < 0.9VMCUmax
Capacitance for each I/O pin
-10
10
10
CI2C,IN
From VIHmin to VILmax
Standard-Mode
,
250
250
ns
ns
tI2C,OF
Output fall time
From VIHmin to VILmax, Fast-
Mode
Pulse width of spikes that
must be suppressed by the
input filter
tI2C,SP
0
50
ns
I2C BUS LINES
SCL clock frequency,
Standard-Mode
0
0
100
400
kHz
kHz
µs
fSCL
SCL clock frequency Fast-
Mode
hold time (repeated) START After this period, the first
condition, Standard-Mode clock pulse is generated.
4
tHD;STA
tSCL ,LOW
tSCL,HIGH
hold time (repeated) START After this period, the first
0.6
4.7
1.3
4
µs
condition, Fast-Mode
clock pulse is generated.
LOW period of the SCL clock,
Standard-Mode
µs
LOW period of the SCL clock,
Fast-Mode
µs
HIGH period of the SCL
clock, Standard-Mode
µs
HIGH period of the SCL
clock, Fast-Mode
0.6
µs
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
set-up time for a repeated
START condition, Standard-
Mode
4.7
µs
tSU;STA
set-up time for a repeated
START condition, Fast-Mode
0.6
µs
tHD;DAT
tHD;DAT
tHD;DAT
tHD;DAT
CBUS compatible masters
I2C-bus devices
5
0
0
0
µs
µs
µs
µs
data hold time, Standard-
Mode
CBUS compatible masters
I2C-bus devices
data hold time, Fast-Mode
data set-up time, Standard-
Mode
250
100
ns
ns
ns
tSU;DAT
data set-up time, Fast-Mode
rise time of both SDA and
SCL signals, Standard-Mode
1000
300
300
300
tI2C,RISE
rise time of both SDA and
SCL signals, Fast-Mode
20
ns
ns
ns
µs
µs
fall time of both SDA and SCL
signals, Standard-Mode
tI2C,FALL
fall time of both SDA and SCL
signals, Fast-Mode
20 × (VMCU /
5.5 V)
set-up time for STOP
condition, Standard-Mode
4
tSU;STO
set-up time for STOP
condition, Fast-Mode
0.6
bus free time between a
STOP and START condition,
Standard-Mode
4.7
1.3
µs
µs
tBUF
bus free time between a
STOP and START condition,
Fast-Mode
data valid time, Standard-
Mode
3.45
0.9
µs
µs
µs
tVD;DAT
data valid time, Fast-Mode
data valid acknowledge time,
Standard-Mode
3.45
tVD;ACK
data valid acknowledge time,
Fast-Mode
0.9
400
250
µs
pF
pF
V
capacitive load for each bus
line, Standard-Mode
CBUS
capacitive load for each bus
line, Fast-Mode
noise margin at the LOW
level
for each connected device
(including hysteresis)
VNL
VNH
0.1 × VMCU
0.2 × VMCU
noise margin at the HIGH
level
for each connected device
(including hysteresis)
V
(1) MCU LDO output voltage on power-up is determined by the MCUSEL pin state.
6.6 Typical Characteristics
TA = 27°C, VCC = 3.65 V
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ZHCSL08C –OCTOBER 2019 –REVISED AUGUST 2021
40
35
30
25
20
15
10
5
32
35
30
25
20
15
10
5
26
22
16
16
13
10
7
5
5
1
1
1
1
1
1
0
0
Current (µA)
Current (µA)
µ = 63.44 µA
N = 99 Units
σ= 1.13 µA
µ = 175.41 µA
N = 99 Units
σ= 3.25 µA
图6-2. Bias Block Current
图6-1. 8 MHz Oscillator Current
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7 Detailed Description
7.1 Overview
The TPS8804 integrates an analog supply LDO, digital supply LDO, photoelectric chamber analog front end
(AFE), carbon monoxide sensor AFE, SLC interface driver, analog multiplexer, and digital core. The high
integration greatly reduces component count in smoke detectors and carbon monoxide detectors. The two LED
drivers have highly configurable temperature compensation to support IR and blue LEDs over a wide range of
currents. The wide bandwidth of the photo-amplifier saves power due to reduced LED on-time. The CO amplifier
has integrated gain resistors. The SLC interface driver connects to the two-wire power line, driving it low and
sensing when the line has been pulled low. Each block is highly configurable with the digital core I2C interface,
supporting on-the-fly adjustment of amplifier gains, regulator voltages, and driver currents. Configurable status
and interrupt signal registers alert the MCU of fault conditions such as under-voltage, over-temperature, and
SLC power alerts.
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7.2 Functional Block Diagram
VCC
VSLC
Power LDO
MCU_TX1
VCCLOW
Under-Voltage
Monitor
MCU_TX2
SLC
PLDO
SLCTX_EN
SLC_TX1
Transmitter
SLC_TX2
PGND
VINT
Internal LDO
2.3V
To Digital Core
LED Driver A
VMCU
DINA
MCU LDO
1.5V to 3.3V
Temperature
Compensated
DAC
MCUSEL
+
œ
CSA
SLC_RX
MCU_RX
PDAC_A
VINT
SLC Receiver
LED Driver B
DINB
SCL
Temperature
Compensated
DAC
+
SDA
CSEL
VMCU
I2C Interface
œ
CSB
PDAC_B
GPIO
COTEST_EN
PREF_SEL
VINT
PREF
Photo Reference
and CO Test
Digital Core
LEDEN
DGND
Photo Amplifier
AMUX_SEL
AMUX_BYP
AOUT_PH
PDO
AMUX
AMUX
œ
COO
PDO
+
PDN
PDP
œ
CO Amplifier
COO
+
CON
COP
œ
+
VSLC
REF0P3
REF0P3_EN
LEDLDO_EN
LEDLDO
300mV
Reference
LED LDO
AGND
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7.3 Feature Description
7.3.1 System Power-up
VCC<VPWRDOWN
Shutdown
Active
All blocks configurable
VCC>VPWRUP
INTLDO enabled
Wait 6 ms
Registers loaded
Wait 2ms
Set VMCUSET[0:1] based
on MCUSEL pin
Enable MCU LDO
MCU_PG=1
Wait for MCU_PG=1
Power Up
图7-1. Power-up State Diagram
The TPS8804 can power-up from a DC power supply above 3.6 V connected to the VCC pin. When the VCC
voltage exceeds the VPWRUP threshold, the TPS8804 initializes for 6 ms. After the initialization, the MCUSEL pin
is sensed for 2 ms to determine the MCULDO voltage and program the VMCUSET register. 表 7-1 indicates the
VMCU setting for each MCUSEL configuration. The MCULDO is enabled and the system waits for VMCU to
reach its power-good threshold (typically 85% of its target voltage). It is only after VMCU reaches its power-good
threshold that I2C communication is allowed with the TPS8804. This sequence of events is outlined in 图7-1.
表7-1. VMCU Power-up Voltage
MCUSEL Connection
620-Ωto GND
Short to GND
VMCU (V)
1.5
1.8
Short to VINT
2.5
330-pF to GND
3.3
7.3.2 LDO Regulators
7.3.2.1 Power LDO Regulator
The power LDO is a voltage clamp that supplies many of the internal blocks in the TPS8804, including the
internal LDO and MCU LDO. Because the power LDO is designed to clamp the VCC voltage, it is not precise
and varies with VCC voltage and load. The power LDO shorts VCC and PLDO when the VCC voltage is below
approximately 5 V, and regulates VCC when VCC is above approximately 5 V. The power LDO has a dropout
voltage of approximately 1 V when it is regulating VCC. When the power LDO transitions from shorting to
regulating, the PLDO voltage drops by approximately 1 V. Connect a 1-µF capacitor to PLDO to stabilize the
PLDO voltage.
The power LDO is designed for use by the device and can be used to supply external circuitry that has a voltage
limit of 7 V. The power LDO can also be used to supply the IR or blue LED anode through a diode.
7.3.2.2 Internal LDO Regulator
The internal LDO (INT LDO) regulator powers the TPS8804 amplifiers and digital core with a stable 2.3 V supply.
Connect a 1-µF capacitor to VINT to stabilize the output. The INT LDO is always enabled when the device is
powered. The INT LDO can be used to supply external circuitry. It is not recommended to power noisy or
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switching loads with INT LDO, as any noise on VINT couples to the internal amplifiers and can generate noise.
The INT LDO can be used in the CO connectivity test circuitry and the photo reference circuitry.
7.3.2.3 Microcontroller LDO Regulator
The microcontroller LDO (MCU LDO) powers the internal digital input and output buffers (IO buffers) and
external MCU that controls and programs the TPS8804. Connect a 1-µF capacitor to VMCU to stabilize the
output. The MCU LDO can be programmed to output 1.5 V, 1.8 V, 2.5 V, and 3.3 V. The default MCU LDO
setting is determined by the configuration on the MCUSEL pin (see 表 7-1). After the device is powered, the
MCU LDO voltage can be changed using the VMCUSET register. The MCU LDO can also be disabled using the
MCU_DIS register.
The MCU LDO output VMCU powers the IO buffers on SCL, SDA, CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1,
MCU_TX2. The IO buffers level shift signals from the digital core to a level suitable for the microcontroller and
signals from the microcontroller to a level suitable for the digital core. In general, connect VMCU to the
microcontroller supply voltage to guarantee logic level compatibility. If the MCU LDO is disabled, connect an
external supply to VMCU.
The MCU LDO has a power good signal MCU_PG that indicates whether the MCU LDO is above 85% the
regulation voltage. A 125-µs deglitch filter prevents noise from affecting the MCU_PG signal. If MCU_PG is low
after 10 ms of changing the MCU LDO voltage or enabling the MCU LDO, the MCU_ERR flag is set high. If the
MCU_ERR flag is high and MCUERR_DIS is low, the MCU LDO fault state is entered. See 节 7.4.1.1 section for
more information.
7.3.3 Photo Chamber AFE
PDO
To AMUX
10 pF
1.5 Mꢀ
PDN
PDP
VINT
VINT
œ
+
PAMP_EN
+
To AMUX
PGAIN_EN
Photodiode
œ
PGAIN[1:0]
1.5 Mꢀ
10 pF
Photo Reference
5mV
1
0
Connect if
PGAIN set to
01, 10, or 11
+
50mV
œ
PREF_SEL
VINT
470 kꢀ
PGAIN_EN
PAMP_EN
PREF
To CO Amp
Test
图7-2. Photo Amplifier Circuit
The TPS8804 photo amplifier connects to a photoelectric chamber photodiode and has two stages—an input
stage and gain stage. When the photoelectric chamber LED is enabled, light scatters off smoke particles in the
chamber into the photodiode, producing a signal proportional to the smoke concentration. The output of each
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photo amplifier stage is connected to the AMUX for ADC reading. This configuration provides high bandwidth
and dynamic range for the photodiode signal chain as the gain stage is on-the-fly adjustable.
7.3.3.1 Photo Input Amplifier
The input stage is a wide-bandwidth, low-offset op-amp designed for amplifying photodiode currents. In 图 7-2,
negative feedback causes the photodiode to conduct with zero voltage bias. The photo-current flows through
resistors connected from PDP to a reference (GND or PREF) and PDN to PDO. These two resistors determine
the gain of the input stage. The same value must be used for these two resistors because PDP and PDN
leakage is amplified by these resistors. Capacitors installed in parallel with the resistors compensate the op-amp
feedback loop for optimal response. The optimal compensation capacitance depends on the photodiode's
capacitance. The compensation capacitance should be adjusted to minimize settling time without having
overshoot on the output of the amplifier. Overshoot adds unnecessary noise in the output. The input stage
outputs through the PDO pin, which is internally connected to the integrated photo gain stage and AMUX.
The input stage has the option of being referenced to GND or PREF. PREF is a reference that is normally pulled
to VINT and is set to 50 mV when PREF_SEL = 1 and either PAMP_EN = 1 or PGAIN_EN = 1. The 50 mV
reference keeps the input amplifier in a linear operating region when no signal is applied, improving the speed
and zero-current sensitivity of the amplifier. It is generally recommended to set PREF_SEL=1 and connect the
external gain resistor and compensation capacitor to PREF. Connect a 100-pF filtering capacitor from PREF to
GND to reduce high frequency noise on PREF.
When measuring the photo amplifier output, it is recommended to take multiple ADC samples. Averaging ADC
samples approximately reduces the noise by the square root of the amount of samples. The power consumed in
a photoelectric smoke measurement is dominated by the LED power consumption, which is proportional to the
LED on-time multiplied by the LED current. To maximize the signal-to-noise ratio for a given power level, set the
LED pulse length to approximately twice the photo amplifier rise time and take multiple ADC samples while the
output is stabilized.
In systems where the compensation capacitor is selected for a slower rise time and lower noise, take multiple
ADC samples around the peak of the photo amplifier output.
7.3.3.2 Photo Gain Amplifier
The high-bandwidth, low noise photo gain amplifier connects to the output of the photo input stage to further
amplify the photodiode signal. The gain amplifier is adjustable on-the-fly using the I2C interface. The gain
amplifier has four settings:
• 5x (4.75x if PREF_SEL=1)
• 11x (10.4x if PREF_SEL=1)
• 20x (18.5x if PREF_SEL=1)
• 35x (32.3x if PREF_SEL=1)
The gain stage has the option of being referenced to GND or PREF with the PREF_SEL bit. When
PREF_SEL=1, a 5 mV reference offset counteracts the gain stage's input offset voltage to keep the gain stage
output above 50 mV. The 5 mV reference offset is amplified by the gain stage, causing the output to change
when the gain is changed, even when there is zero photo-current. It is recommended to connect a 470 kΩ
resistor from PREF to VINT if the gain is set to 11x, 20x, or 35x. This resistor changes the PREF voltage to 70
mV and prevents the output from dropping below 50 mV in worst-case conditions. Referencing the gain stage to
PREF causes the 50 mV reference to change with signal level due to the finite impedance of the reference.
Because the reference is changing with the signal level, the gain is slightly less with PREF_SEL=1.
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7.3.4 LED Driver
VSLC
LEDLDO
VCC<11.5V
VCC
VCC>11.5V
LEDLDO
LEDLDO_EN
LEDLDO[0:2]
LED LDO
1 k
DINA
CSA
PLDO
Blue/IR
LED
TEMPCOA[1:0]
PDAC_A[7:0]
LED
DAC
+
–
100
F
GPIO[0:2]
R
CSA
PGND
0.1
To MCU
To MCU
GPIO
GPIO
Logic
VCC<11.5V
VCC
VCC>11.5V
LEDLDO
LEDEN
LEDPIN_EN
LEDSEL=0
1 k
DINB
CSB
Blue/IR
LED
PLDO
TEMPCOB[1:0]
PDAC_B[7:0]
LED
DAC
+
–
100
F
R
CSB
PGND
0.1
图7-3. LED Driver Circuit
7.3.4.1 LED Current Sink
The two LED drivers are current regulated, temperature compensated, and adjustable with an 8-bit DAC. When
the LED driver is enabled, the CSA voltage is regulated, and the current through the CSA resistor also flows
through the LED and the DINA pin. A current sense resistor connects to the CSA pin. The LED driver is enabled
with the LEDEN pin and LEDPIN_EN bit. Both the pin and bit must be high for the LED driver to operate. The
LEDSEL bit switches which driver the LEDEN signal connects to. The GPIO pin can be configured to enable
either LED driver.
The LED driver is temperature compensated to account for reduced LED intensity with increasing temperature.
Four temperature compensation settings are available to support a variety of IR and blue LEDs. Temperature
compensation is implemented by varying the CSA regulated voltage with temperature, thus the temperature
compensation also depends on the CSA resistor. Each temperature compensation setting has a different DAC
output at room temperature. To achieve a specific temperature compensation and current, the PDAC, TEMPCO,
and CSA resistor must all be adjusted according to the 节8.2.2.2 procedure.
The two LED drivers are interchangeable and support both IR and blue LEDs. The only difference between the
two LED drivers is a code CSA_BIN available to improve the LED A driver current accuracy for IR LEDs.
CSA_BIN in register 0x00 categorizes CSA voltage for each unit as close to the minimum, below average, above
average, or close to the maximum (see 节 7.6). Use CSA_BIN to adjust the DAC and compensate for the
variation on the LED A driver's current. After adjusting the DAC, the effective variation is reduced by a factor of 4
for the TEMPCOA = 11, PDAC_A = 00 setting. IR LEDs typically require the TEMPCOA = 11 temperature
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compensation setting. Therefore, use the LED driver A for powering IR LEDs. If better accuracy is required,
calibrate the LED driver current by connecting the CSA or CSB pin to the microcontroller ADC port, measuring
the CSA or CSB voltage, and adjusting PDAC_A or PDAC_B until the required current is achieved.
Ensure that the LED current remains below 550 mA, the pulse width remains below 1 ms, and the duty cycle
remains below 1%. There is no protection to prevent operation outside these conditions. Ensure the PDAC and
TEMPCO registers are programmed before enabling the LED driver.
7.3.4.2 LED Voltage Supply
Enough voltage must be provided to the LED such that the DINA voltage is at least the dropout voltage
(VDINA,DROP) above the CSA voltage while the LED driver is enabled. Ensure the DINA voltage does not exceed
11.5 V. Because of the high LED drive currents, a large capacitor connected to the LED anode is required to
provide pulsed power to the LED. Any of the internal regulators ( PLDO, LEDLDO) or external supply ( VDC)
meeting the voltage requirements can be used to charge the LED capacitor. Connect the LED anode to LEDLDO
when VCC > 11.5 V.
The LED LDO clamps the VSLC voltage and blocks reverse current with an integrated diode. It is current limited
to prevent inrush current caused by charging the large capacitor. The regulation voltage is adjustable in the
LEDLDO register. The LED LDO may be operated with VSLC below the regulation voltage. In this case, the
LEDLDO voltage stabilizes to VSLC minus a diode voltage drop.
The LED driver current and rise time can vary by a few millivolts and microseconds across the LED anode
supply and VCC voltages. It is recommended to use a consistent LED anode voltage whenever the LED driver is
enabled.
Connect a capacitor with a value between 1 µF and 100 µF to the LEDLDO.
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7.3.5 Carbon Monoxide Sensor AFE
To AMUX
COSWRO=1
RO=100 kꢀ
COO
CON
CO Connectivity Test
0.22 …F
COGAIN[1:0]
VINT
COSWRI=1
COSWRG=1
100 kꢀ
VINT
RI=1 kꢀ
œ
COAMP_EN
+
Working
COP
10 kꢀœ
100 kꢀ
CO
Sensor
100 kꢀ
REF0P3
REF0P3_EN
To MCU GPIO
Counter
COSWREF=1
COREF[1:0]
+
+
300 mV
œ
œ
PREF
To Photo Amp Reference
To Photo
Amp
For CO Connectivity Test
Use in place of pull-up resistor and
pull-down FET if PREF_SEL=0
VINT
200 kꢀ
COTEST_EN
COTEST_DIR
图7-4. Carbon Monoxide Detection Circuit Referenced to GND
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To AMUX
COSWRO=1
RO=100 kꢀ
COO
CON
CO Connectivity Test
VINT
0.22 …F
COGAIN[1:0]
COSWRI=1
COSWRG=1
100 kꢀ
VINT
RI=1 kꢀ
œ
COAMP_EN
+
Working
COP
10 kꢀœ
100 kꢀ
CO
Sensor
100 kꢀ
REF0P3
REF0P3_EN
COSWREF=0
To MCU GPIO
Counter
+
+
COREF[1:0]
300 mV
1 nF
œ
œ
PREF
To Photo Amp Reference
To Photo
Amp
For CO Connectivity Test
Use in place of pull-up resistor and
pull-down FET if PREF_SEL=0
VINT
200 kꢀ
COTEST_EN
COTEST_DIR
图7-5. Carbon Monoxide Detection Circuit Referenced to 300mV
The TPS8804 CO AFE connects to an electrochemical CO sensor. The amplifier converts the microamps of
sensor current into a voltage readable by an ADC. This is achieved with a low-offset, low-power op-amp with
configurable input, gain, and output resistors.
7.3.5.1 CO Transimpedance Amplifier
The CO transimpedance amplifier is a low-offset, low-power op-amp with integrated input, gain, and output
resistors. Each of these resistors can be disconnected using the COSW register bits if using external resistors.
The input resistor limits amplifier current during a CO sensor connectivity test. The gain resistor amplifies the CO
sensor signal. Adjust the gain resistor by changing the COGAIN register bits. Use the output resistor with an
external capacitor to filter the CO amplifier output signal.
The CO amplifier has two integrated references. A programmable 1.25-mV to 5-mV reference COREF is
internally connected to the op-amp positive terminal. A 300-mV reference is connected to the REF0P3 pin. When
the millivolt reference is used, the CO sensor must be connected to GND. The millivolt reference is amplified to
offset the amplifier output above GND. When the 300 mV reference is used, the reference offsets the CO
amplifier output by 300 mV. In general, either reference can be used. The 300-mV reference offers better DC
accuracy at the cost of extra power consumption. The 300 mV reference is generated with a reference and op-
amp buffer for high precision. The REF0P3 pin must connect to a 1 nF capacitor for stability if it is enabled. The
buffer is designed to source and sink small currents as required by the CO amplifier. The 300 mV reference and
the 1.25 mV to 5mV reference cannot be enabled simultaneously.
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A resistor connected in parallel with the CO sensor prevents charge from accumulating across its terminals. The
output of the CO amplifier is connected to the COO pin for continuous monitoring and the AMUX for periodic
sampling.
7.3.5.2 CO Connectivity Test
The built-in CO connectivity test function connects to the PREF pin and is available when the photo amplifier is
not referenced to PREF. The COTEST_EN and COTEST_DIR register bits program a pull-up and pull-down
switch on PREF. A 200 kΩ pull-up resistor charges the 1 µF capacitor when the CO test is not in use. When
PREF is pulled low, charge is injected into the amplifier and the output pulse shape can be used to determine if
the sensor is connected. An external MOSFET and pull-up resistor achieves the same function as the internal
COTEST circuitry.
7.3.6 SLC Interface Transmitter and Receiver
VLINE
SLCRX_HYS
SLCRX_DEG
SLC_RX
+
SLCRX_EN
100pF
œ
+
SLCRX_PD
MCU_RX
To
MCU
œ
Interrupt
STATUS_MCURX
VLINE
VSLC
4.7 kꢀ
MCU_TX1
MCU_TX2
SLC_TX1
SLC_TX2
From
MCU
VLINE
SLCTX_EN
VSLC
From
MCU
470 ꢀ
External component selection depends on SLC
protocol. Example configuration is shown
External component selection depends on SLC protocol. Example configuration is shown
图7-6. SLC Interface Circuit
In smoke detection systems where the power line carries communication signals between smoke detectors and
central fire panels, the SLC interface connects to the power line to transmit and receive data from the MCU. The
interface isolates the high voltage power line from the microcontroller, mitigating risk of damage and reducing
external component count.
7.3.6.1 SLC Transmitter
Signals are transmitted to the power line by pulling the line low with a controlled current sink. When the driver is
enabled, the microcontroller controls the SLC_TX1 and SLC_TX2 outputs by driving MCU_TX1 and MCU_TX2
high. In 图 7-6, the SLC_TX2 output driver connects to an external transistor and current-limiting resistor. The
current drawn from the power line is shown in 方程式 1. The SLC_TX1 output driver is able to pull the line
completely low. This configuration allows for multi-level communication.
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VSLC F VBE
ISINK
=
RE
(1)
7.3.6.2 SLC Receiver
The SLC receiver transmits signals from the power line to the microcontroller. A reverse biased Zener diode level
shifts the power line. The Zener diode is selected to drop the voltage such that when VLINE is high, the SLCRX
pin is above 3 V and when VLINE is low, the SLCRX pin is below 0.5 V. The 100-pF capacitor filters voltage
spikes that may occur on VLINE. The hysteretic and deglitched comparator filters spurious noise on VLINE. The
comparator output is synchronized with the 32 kHz clock before being deglitched. The hysteresis voltage and
deglitch time are programmable with the SLCRX_HYS and SLCRX_DEG register bits. An internal pulldown
resistor biases the Zener diode to maintain the SLC_RX voltage below 17 V, the recommended maximum.
7.3.7 AMUX
AMUX_BYP
AMUX_SEL[1:0]≠0
Hi-Z
VINT
0
To MCU
ADC
COO
10 kꢀ
AMUX
1
AMUX
AOUT_PH
PDO
2
3
1 nF
AMUX_BYP AMUX_SEL[1:0]
图7-7. Analog Multiplexer Circuit
The AMUX switch and buffer are used to connect the various TPS8804 amplifier outputs to a single ADC. The
unity-gain amplifier improves the drive strength and fidelity of the analog signals when connected to an ADC. A
330 pF to 1 nF capacitor must be connected to the AMUX pin to stabilize its output. The 10-kΩ resistor filters
high-frequency noise in the analog signal. Using a 10-kΩresistor and 1-nF capacitor reduces noise levels in the
photo amplifier signal. The buffer has the option of being bypassed to remove the added offset introduced by the
unity-gain amplifier. Because the AMUX requires the bias block (see 节 7.3.8), bypassing the buffer does not
eliminate the AMUX current consumption.
7.3.8 Analog Bias Block and 8 MHz Oscillator
A central analog bias block connects to many of the amplifiers, drivers, and regulators. This block is enabled
when any of its connected blocks are enabled. Similarly, an internal 8-MHz oscillator is enabled when the photo
input amplifier is enabled. 表 7-2 lists the conditions when the bias block and 8-MHz oscillator are enabled. The
bias block and 8-MHz oscillator consume current in addition to the connecting blocks whenever they are
enabled. Because the specified current consumption of each block does not include the bias block or the 8-MHz
oscillator, add the bias block and 8-MHz oscillator currents when calculating system power consumption. Typical
values of the bias block and 8-MHz oscillator current are shown in 节6.6.
表7-2. Conditions for Enabling the Bias Block and 8 MHz Oscillator
BLOCK
Photo input amplifier
AMUX buffer
CONDITION
BIAS ENABLED?
8-MHZ OSC ENABLED?
PAMP_EN = 1
Yes
Yes
Yes
Yes
Yes
No
No
No
AMUX_SEL[0:2] ≠000
LEDLDO_EN = 1
PGAIN_EN = 1
LED LDO
Photo gain amplifier
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表7-2. Conditions for Enabling the Bias Block and 8 MHz Oscillator (continued)
BLOCK
CONDITION
BIAS ENABLED?
8-MHZ OSC ENABLED?
LED driver
LEDEN = VMCU and
LEDPIN_EN = 1
Yes
No
Temperature monitor
SLC transmitter
OTS_EN = 1
Yes
Yes
No
No
SLCTX_EN = 1
7.3.9 Interrupt Signal Alerts
VCCLOW
VCCLOWM
MCULDO_ERR
Interrupt
Signal
MCULDO_ERRM
To GPIO Logic
To SLC Receiver
OTS_ERR
OTS_ERRM
OTS_WRN
OTS_WRNM
图7-8. Interrupt Signal Alert Logic
Configurable interrupt signals notify the MCU when a system anomaly occurs. The interrupt signal indicates the
STATUS1 register, which has bits that latch high when reaching various condition limits such as temperature or
voltage. Each of the bits in the STATUS1 register can be independently configured to send an interrupt signal by
setting the MASK register bit corresponding to each STATUS1 bit. The GPIO bits must be set to 0x2 to output
interrupt signals through the GPIO pin, and the STATUS_MCURX bit must be set to 1 to output interrupt signals
through the MCU_RX pin. By connecting the GPIO or MCU_RX pin to the microcontroller, the MCU can be
immediately notified when a STATUS1 bit changes instead of having to repeatedly read the STATUS1 register.
After the device sends the interrupt signal, the signal remains high until the STATUS1 register is read, at which
point the fault clears if the error condition is removed.
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7.4 Device Functional Modes
7.4.1 Fault States
Active
MCU_PG=0 after 10 ms
of enabling MCU LDO or
changing VMCUSET
TJ>125°C after 300 µs
of enabling OTS_EN
Set MCULDO_ERR=1
Set OTS_ERR=1
MCUERR_DIS=0
Enable temperature monitor
Disable amplifiers, drivers, and
MCU LDO
Enable temperature monitor
Disable amplifiers and drivers
TJ>125°C
Start 1-second timer
Start 1-second timer
MCU_PG=0
Timeout
TJ>110°C
Timeout
Check TJ
Check MCU_PG
TJ<110°C
MCU_PG=1
Enable blocks if previously
enabled
Enable blocks if previously
enabled
No
Yes
Was OTS entered from MCU
LDO fault state?
Over-Temperature Shutdown
MCU LDO Fault
图7-9. Fault States Diagram
The TPS8804 device uses several monitors to alert the MCU when system irregularities occur. In addition to
alerting the MCU, two monitors cause the device to enter protective fault states:
• MCULDO under-voltage
• system over-temperature
The fault states reduce risk of damage and brown-outs to the system in the event of short circuits or other power
errors.
7.4.1.1 MCU LDO Fault
The MCU LDO has an undervoltage monitor to notify the MCU if the LDO falls out of regulation. This monitor is
enabled any time the MCU LDO is enabled and its status is in the MCU_PG register bit. A 125-μs deglitch time
rejects load and line transient spikes that may briefly drop the MCU LDO voltage below the under-voltage
threshold. If MCU_PG is low while the MCU LDO is enabled and it has been more than 10 ms since the LDO
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was enabled or changed voltage, the MCU_ERR register bit latches high. When the MCU_ERR bit is set high
and the MCUERR_DIS bit is low, the MCU LDO fault state is entered.
When the MCU LDO fault state is entered, all amplifiers and drivers are disabled. The MCU LDO remains
enabled to attempt to recover the system. The device enables the over-temperature monitor (OTS_EN) to
prevent a VMCU short circuit from overheating the TPS8804 device. If a VMCU short circuit causes the
temperature of the TPS8804 to rise, an over-temperature shutdown occurs and the MCU LDO shuts off.
There are two methods to exit the fault state. Every second in the fault state, the MCU_PG register bit is
automatically read. If high, the fault state is exited. The MCU_ERR bit remains high until the STATUS1 register is
read. Alternatively, if the STATUS1 register is read and MCU_PG is high, the fault state is exited. When the
device exits the MCU_ERR fault state, the device re-enables all blocks that were enabled before the fault state
occurred.
If an over-temperature fault occurs while in the MCU LDO fault state, the device enters the over-temperature
fault state. The over-temperature fault state disables the MCU LDO in addition to the blocks that are disabled by
the MCU LDO fault state. After the device exits the over-temperature fault state, it immediately re-enters the
MCU LDO fault state to confirm the MCU LDO status.
7.4.1.2 Over-Temperature Fault
An over-temperature shutdown (OTS) fault occurs if OTS_EN = 1 and the die temperature exceeds 125°C. The
fault is masked for 300 μs after setting OTS_EN = 1. OTS_EN must be enabled for at least 300 μs in order to
determine if the die has overheated. After the device detects an over-temperature condition, it disables all
drivers, amplifiers, and regulators and sets OTS_ERR to 1. This action prevents additional temperature stress
caused by a short circuit.
Similar to the MCU LDO fault, the device exits the OTS fault state with two methods:
• The device checks the die temperature once every second. If the temperature is below 110°C, the device
exits the fault state.
• Reading the STATUS1 register with the die temperature below 110°C exits the fault state.
When the device exits the OTS fault state, it re-enables all blocks that were enabled before the OTS fault
occurred.
7.5 Programming
The TPS8804 serial interface follows the I2C industry standard. The device supports both standard and fast
mode, and it supports auto-increment for fast reading and writing of sequential registers. A 33-kΩpullup resistor
connecting the SDA and SCL pins to VMCU is recommended for fast mode operation. The VMCU voltage
determines the logic level for I2C communication. The CSEL pin selects the device address. When CSEL is
pulled to GND, the device address is 0x3F. When CSEL is pulled to VMCU, the device address is 0x2A.
7.6 Register Maps
表 7-3 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表
7-3 should be considered as reserved locations and the register contents should not be modified.
表7-3. Device Registers
Offset
0h
Acronym
REVID
Register Name
Device Information
Status 1
Section
Go
1h
STATUS1
STATUS2
MASK
Go
2h
Status 2
Go
3h
Interrupt Mask
Config 1
Go
4h
CONFIG1
CONFIG2
Go
5h
Config 2
Go
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表7-3. Device Registers (continued)
Offset
6h
Acronym
ENABLE1
ENABLE2
CONTROL
GPIO_AMUX
COSW
Register Name
Section
Go
Enable 1
7h
Enable 2
Go
8h
Control
Go
Bh
GPIO and AMUX
CO Switch
Go
Ch
Go
Dh
CO
CO Amplifier
LED LDO
Go
Fh
LEDLDO
Go
10h
11h
12h
PH_CTRL
LED_DAC_A
LED_DAC_B
Photo Amplifier
LED DAC A
LED DAC B
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. 表 7-4 shows the codes that are used for
access types in this section.
表7-4. Device Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
RC
R
C
Read
to Clear
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1 REVID Register (Offset = 0h) [reset = 0h]
REVID is shown in 表7-5.
Return to Summary Table.
表7-5. REVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CSA_BIN
R
0h
CSA voltage bin for TEMPCOA=11, PDAC_A=00 setting
0h = CSA voltage between specified minimum and typical, closer to
minimum
1h = CSA voltage between specified minimum and typical, closer to
typical
2h = CSA voltage between specified maximum and typical, closer to
typical
3h = CSA voltage between specified maximum and typical, closer to
maximum
5-0
RESERVED
R
0h
Reserved
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7.6.2 STATUS1 Register (Offset = 1h) [reset = 0h]
STATUS1 is shown in 表7-6.
Return to Summary Table.
表7-6. STATUS1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
VCCLOW
R
0h
Reserved
6
RC
0h
VCC low warning
0h = no VCCLOW error has occurred
1h = VCC below V_VCCLOW,FALL threshold and VCCLOW_DIS=1
for VCCLOW deglitch time. VCCLOW is masked for 1 ms after
VCCLOW_DIS is set to 0
5
MCULDO_ERR
RC
0h
MCU LDO power good error
0h = no MCULDO error has occurred
1h = MCU_PG=0 and MCU_EN=1 for TMCULDO,PG.
MCULDO_ERR is masked for TMCULDO,MASK after VMCUSET or
MCU_DIS has changed
4
3
OTS_ERR
OTS_WRN
RC
RC
0h
0h
Thermal shutdown error
0h = no thermal shutdown error has occurred
1h = junction temperature has exceeded T_SHUTDOWN
Thermal warning flag
0h = no thermal warning has occurred
1h = junction temperature has exceeded T_WARNING
2-1
0
RESERVED
SLC_RX
R
0h
0h
Reserved
RC
SLC_RX status
0h = deglitched SLC_RX is low or SLCRX_EN=0
1h = deglitched SLC_RX is high and SLCRX_EN=1
7.6.3 STATUS2 Register (Offset = 2h) [reset = 0h]
STATUS2 is shown in 表7-7.
Return to Summary Table.
表7-7. STATUS2 Register Field Descriptions
Bit
7-2
1
Field
Type
Reset
Description
RESERVED
MCU_PG
R
0h
Reserved
R
0h
MCU LDO power good indicator
0h = MCU LDO is below power good threshold or MCU_DIS=1
1h = MCU LDO is above power good threshold and MCU_DIS=0
0
RESERVED
R
0h
Reserved
7.6.4 MASK Register (Offset = 3h) [reset = 0h]
MASK is shown in 表7-8.
Return to Summary Table.
表7-8. MASK Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
VCCLOWM
R
0h
Reserved
6
R/W
0h
VCC low warning interrupt mask
0h = interrupt on VCC low
1h = no interrupt on VCC low
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表7-8. MASK Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
MCULDO_ERRM
R/W
0h
MCU LDO power good error interrupt mask
0h = interrupt on MCULDO power good error
1h = no interrupt on MCULDO power good error
4
3
OTS_ERRM
OTS_WRNM
R/W
R/W
0h
0h
Thermal shutdown error interrupt mask
0h = interrupt on thermal shutdown error
1h = no interrupt on thermal shutdown error
Thermal warning flag interrupt mask
0h = interrupt on thermal warning
1h = no interrupt on thermal warning
2-1
0
RESERVED
R
0h
0h
Reserved
STATUS_MCURX
R/W
Status interrupt on the MCU_RX pin
0h = disable
1h = MCU_RX outputs high if any unmasked STATUS1 flags
7.6.5 CONFIG1 Register (Offset = 4h) [reset = 20h]
CONFIG1 is shown in 表7-9.
Return to Summary Table.
表7-9. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SLCRX_DEG
R/W
0h
SLC_RX deglitch control
0h = none
1h = 125us
2h = 1ms
3h = 20ms
5
SLCRX_PD
VMCUSET
R/W
R/W
1h
0h
SLC_RX pulldown resistor enable
0h = >1MOhm pulldown resistor on SLC_RX
1h = 100k pulldown resistor on SLC_RX
4-3
MCU LDO voltage. Default value is set by MCUSEL on power-up.
0h = 1.5V
1h = 1.8V
2h = 2.5V
3h = 3.3V
2-0
RESERVED
R
0h
Reserved
7.6.6 CONFIG2 Register (Offset = 5h) [reset = 0h]
CONFIG2 is shown in 表7-10.
Return to Summary Table.
表7-10. CONFIG2 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
SLCRX_HYS
R
0h
Reserved
R/W
0h
SLC receiver comparator hysteresis
0h = 1.2V hysteresis
1h = 0.1V hysteresis
4-0
RESERVED
R
0h
Reserved
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7.6.7 ENABLE1 Register (Offset = 6h) [reset = 0h]
ENABLE1 is shown in 表7-11.
Return to Summary Table.
表7-11. ENABLE1 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
SLCRX_EN
R
0h
Reserved
R/W
0h
Control of SLC receiver
0h = disable
1h = enable
4
3
RESERVED
PAMP_EN
R
0h
0h
Reserved
R/W
Photo input amplifier control
0h = amplifier disabled
1h = amplifier enabled
2
PGAIN_EN
R/W
0h
Photo Gain amplifier control
0h = amplifier disabled
1h = amplifier enabled
1
0
RESERVED
LEDLDO_EN
R
0h
0h
Reserved
R/W
LED LDO control
0h = disabled
1h = enabled
7.6.8 ENABLE2 Register (Offset = 7h) [reset = 0h]
ENABLE2 is shown in 表7-12.
Return to Summary Table.
表7-12. ENABLE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LEDSEL
R/W
0h
LED input select
0h = LEDENA
1h = LEDENB
6-3
2
RESERVED
LEDPIN_EN
R
0h
0h
Reserved
R/W
LEDEN pin enable
0h = LEDEN pin does not enable LED block
1h = LEDEN pin enables LED block
1
0
SLCTX_EN
RESERVED
R/W
R
0h
0h
SLC transmitter enable
0h = SLC transmitter disabled
1h = SLC transmitter enabled
Reserved
7.6.9 CONTROL Register (Offset = 8h) [reset = 0h]
CONTROL is shown in 表7-13.
Return to Summary Table.
表7-13. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
Reserved
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表7-13. CONTROL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
MCU_DIS
R/W
0h
MCU LDO disable
0h = MCU LDO enabled
1h = MCU LDO disabled
4
3
2
VCCLOW_DIS
MCUERR_DIS
OTS_EN
R/W
R/W
R/W
0h
0h
0h
VCCLOW brown-out monitor disable
0h = VCCLOW monitor is enabled
1h = VCCLOW monitor is disabled
MCULDO error mode disable
0h = in case of MCULDO error, FAULT mode is entered
1h = disable entering FAULT mode in case of MCULDO error
Over-temperature shutdown mode disable
0h = disable entering over-temperature FAULT mode.
1h = in case of over-temperature, FAULT mode is entered and
OTS_ERR flag is raised.
1
0
SOFTRESET
RESERVED
R/W
R
0h
0h
Set registers to the default value
0h = do not reset registers
1h = reset all registers. SOFTRESET is reset. VMCUSET bits and
STATUS1 register is unchanged.
Reserved
7.6.10 GPIO_AMUX Register (Offset = Bh) [reset = 0h]
GPIO_AMUX is shown in 表7-14.
Return to Summary Table.
表7-14. GPIO_AMUX Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AMUX_BYP
R/W
0h
Analog multiplexer bypass
0h = analog multiplexer buffer is enabled when AMUX_SEL[1:0] !=
0h
1h = analog multiplexer buffer is bypassed with a low-resistance
switch
6
RESERVED
AMUX_SEL
R
0h
0h
Reserved
5-4
R/W
Analog multiplexer input select
0h = AMUX off
1h = COO
2h = AOUT_PH
3h = PDO
3
RESERVED
GPIO_2:0
R
0h
0h
Reserved
2-0
R/W
Multi-purpose digital input and output
0h = Hi-Z
1h = TI Reserved
2h = output low if no status errors, high if any unmasked errors
3h = TI Reserved
4h = GPIO or LEDENA enables LED A
5h = GPIO or LEDENB enables LED B
6h = TI Reserved
7h = TI Reserved
7.6.11 COSW Register (Offset = Ch) [reset = 0h]
COSW is shown in 表7-15.
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Return to Summary Table.
表7-15. COSW Register Field Descriptions
Bit
Field
Type
Reset
Description
7
COSWRO
R/W
0h
CO amplifier output resistor (output of amplifier to COO pin) enable
0h = 0 Ohms
1h = 100 kOhms
6
COSWRG
R/W
0h
CO gain resistor (output of amplifier to inverting input of amplifier)
enable
0h = Hi-Z
1h = Resistance set by COGAIN register
5
4
COSWRI
R/W
R/W
R
0h
0h
0h
CO input resistor (inverting input of amplifier to CON pin) enable
0h = 0 Ohms
1h = 1 kOhms
COSWREF
RESERVED
CO reference switch enable
0h = positive input of amplifier connected to COP
1h = positive input of amplifier connected to 1mV to 5mV COREF
3-0
Reserved
7.6.12 CO Register (Offset = Dh) [reset = 0h]
CO is shown in 表7-16.
Return to Summary Table.
表7-16. CO Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REF0P3_EN
R/W
0h
300mV reference enable
0h = Buffer disabled
1h = Buffer enabled
6-5
4-3
COREF
R/W
R/W
0h
0h
Reference voltage for CO amplifier
0h = 1.25mV
1h = 2.5mV
2h = 3.75mV
3h = 5mV
COGAIN
CO amplifier feedback resistance
0h = 1100 kOhm
1h = 300 kOhm
2h = 500 kOhm
3h = 800 kOhm
2
1
0
COTEST_DIR
COTEST_EN
COAMP_EN
R/W
R/W
R/W
0h
0h
0h
CO test output direction
0h = pull-down
1h = pull-up
Enable COTEST output on PREF
0h = disabled
1h = enabled
CO amplifier control
0h = disabled
1h = enabled
7.6.13 LEDLDO Register (Offset = Fh) [reset = 0h]
LEDLDO is shown in 表7-17.
Return to Summary Table.
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表7-17. LEDLDO Register Field Descriptions
Bit
7-4
3-1
Field
Type
Reset
Description
RESERVED
LEDLDO
R
0h
Reserved
R/W
0h
LED LDO settings
0h = 7.5V
1h = 8.0V
2h = 8.5V
3h = 9.0V
4h = 9.5V
5h = 10V
6h = Reserved
7h = Reserved
0
RESERVED
R
0h
Reserved
7.6.14 PH_CTRL Register (Offset = 10h) [reset = 0h]
PH_CTRL is shown in 表7-18.
Return to Summary Table.
表7-18. PH_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
TEMPCOB
R
0h
Reserved
6-5
R/W
0h
LED B Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
4-3
TEMPCOA
R/W
0h
LED A Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
2
PREF_SEL
PGAIN
R/W
R/W
0h
0h
Photo Reference setting
0h = Photo gain amplifier referenced to 0mV
1h = Photo gain amplifier and PREF pin connected to 50mV internal
reference
1-0
Photo Gain setting
0h = 5
1h = 11
2h = 20
3h = 35
7.6.15 LED_DAC_A Register (Offset = 11h) [reset = 0h]
LED_DAC_A is shown in 表7-19.
Return to Summary Table.
表7-19. LED_DAC_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_A
R/W
0h
LED DAC A setting
00h to FFh = 0mV to 300mV
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7.6.16 LED_DAC_B Register (Offset = 12h) [reset = 0h]
LED_DAC_B is shown in 表7-20.
Return to Summary Table.
表7-20. LED_DAC_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_B
R/W
0h
LED DAC B setting
00h to FFh = 0mV to 300mV
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS8804 supports a variety of smoke alarm platforms, including single-wave or dual-wave photoelectric
smoke and CO detection.
8.2 Typical Application
VSLC
PGND
Pre-Regulator
5V to 15V
VCC
0.1 …F
VLINE
GND
4.7 …F
PLDO
VINT
1 …F
VLINE
1 …F
SLC_RX
100pF
VLINE
VLINE
To MCU
VMCU
1 …F
SLC_TX1
SLC_TX2
MCUSEL
MCU_RX
MCU_TX1
MCU_TX2
To MCU GPIO
To MCU GPIO
To MCU GPIO
470 ꢀ
470 ꢀ
DINA
CSA
VMCU
IR LED
47 …F
0.92 ꢀ
SCL
To MCU I²C
To MCU I²C
SDA
CSEL
DINB
CSB
Blue LED
To MCU GPIO
GPIO
47 …F
6.8 ꢀ
To MCU GPIO
To MCU
LEDEN
DGND
LEDLDO
PDO
10 kꢀ
AMUX
To MCU ADC Port
1 nF
10 pF
VINT
PDN
COO
100 kꢀ
CON
COP
PDP
Photodiode
VINT
To MCU
GPIO
CO
Sensor
10 pF
REF0P3
470 kꢀ
PREF
Thermal Pad
AGND
RESERVED
图8-1. Dual-Wave Photoelectric Smoke and CO Detector
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8.2.1 Design Requirements
In this example, a smoke alarm requires the following:
• 100 MΩphotoamplifier transconductance with sub-nanoamp detection
• 100 mA IR LED current with 1-mA/°C temperature compensation
• 50mA blue LED current with 0.1mA/°C temperature compensation
8.2.2 Detailed Design Procedure
8.2.2.1 Photo Amplifier Component Selection
To meet the 100-MΩ photoamplifier transconductance requirement, set the gain stage to 35x with PGAIN = 11.
Because the application requires sub-nanoamp current detection, reference the photo amplifier to PREF and set
PREF_SEL = 1. This reference offsets the input stage output by 50 mV and offsets the gain stage output by 225
mV. Because the application uses PREF, the gain stage amplification reduces to 32.25x. Divide 100 MΩ by
32.25x to get 3.1 MΩ. The gain is distributed across two resistors, therefore use a resistor with a value of
approximately 1.55 MΩ. A 1.5-MΩ resistor is selected. The achieved transconductance is 96.8 MΩ. Use 10-pF
of compensation capacitance in parallel with the 1.5-MΩ resistors. Use an oscilloscope with averaging to verify
the photo amplifier is quickly settling but not overshooting. If the photo amplifier has overshoot, increase the
compensation capacitance. If the photo amplifier is settling slowly, decrease the compensation capacitance.
8.2.2.2 LED Driver Component Selection
The LED current depends on the TEMPCO bits, PDAC register and CSA and CSB resistors. Changing any of
these values affects the LED current and temperature compensation. The following method selects the
TEMPCO, PDAC, and CSA resistor value based on the required LED current and temperature compensation.
The 100-mA LED current and 1 mA/°C temperature compensation is used as an example for LED A. Repeat the
process for LED B.
1. Determine the room temperature current and temperature compensation required by the application.
• 100mA and 1mA/°C is required by the design.
2. Calculate the compensation in percentage per degree by dividing the compensation coefficient by the
current and multiplying by 100.
• 1 mA/°C divided by 100 mA is 1%/°C.
3. Use 表8-1 or 表8-2 to select a TEMPCO setting which contains the required compensation. If the required
compensation is in two ranges, use the range with a higher TEMPCO setting. If the required temperature
coefficient is not in any of the ranges, choose the TEMPCO and PDAC setting closest to the required
temperature coefficient, then go to step 5.
• 1%/°C is between the mimumum and maximum for TEMPCO = 11.
4. Calculate the target CSA voltage. Divide the driver temperature coefficient [mV/°C] by the desired
temperature coefficient [%/°C] and multiply by 100.
• 1.040 mV/°C divided by 1 %/°C is 104 mV.
5. Calculate the CSA resistor by dividing the target CSA voltage by the required current and subtracting 0.1 Ω
for internal resistance.
• 104 mV divided by 100 mA is 1.04 Ω. Subtract 0.1 Ωto get 0.94 Ω.
6. Select the closest available resistor and calculate the final CSA voltage by multiplying the required current by
the total resistance (external and internal).
• Use a 0.92 Ωresistor. Multiply 100 mA and 1.02 Ωto get 102mV CSA voltage.
7. Calculate the PDAC value by subtracting the final CSA voltage by the specified CSA voltage at PDAC =
0x00 and dividing the result by 1.176 mV (the DAC LSB, equal to 300 mV divided by 255).
• 102 mV minus 79 mV is 23 mV, divided by 1.176 mV is 20. Write 0x14 to the PDAC register.
8. Calibrate the PDAC value. If using the LED A driver, read the CSA_BIN register bits and add 0x11 if
CSA_BIN=00b, add 0x06 if CSA_BIN=01b, subtract 0x06 if CSA_BIN=10b, or subtract 0x11 if
CSA_BIN=11b. The CSA_BIN value varies from unit to unit and must be read on each unit calibrated using
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this method. Alternatively, measure the CSA or CSB voltage using the MCU ADC and adjust PDAC
accordingly.
• The microcontroller reads that a unit has CSA_BIN=01b. 0x20 is written to PDAC_A.
表8-1. Temperature Coefficients for Each TEMPCOA and DAC_A Setting
CSA Voltage [mV],
T = 27°C
Temperature Coefficient Temperature Coefficient
Register Setting
Coefficient Information
Max for TEMPCO = 11b
Min for TEMPCO = 11b
Max for TEMPCO = 10b
Min for TEMPCO = 10b
Max for TEMPCO = 01b
Min for TEMPCO = 01b
Max for TEMPCO = 00b
Min for TEMPCO = 00b
[mV/°C]
[%/°C]
TEMPCOA[1:0] = 11,
PDAC_A = 0x00
79
1.040
1.316%
TEMPCOA[1:0] = 11,
PDAC_A = 0xFF
376
188
484
277
572
299
593
1.040
0.693
0.693
0.416
0.416
0.347
0.347
0.277%
0.369%
0.143%
0.150%
0.073%
0.116%
0.059%
TEMPCOA[1:0] = 10,
PDAC_A = 0x00
TEMPCOA[1:0] = 10,
PDAC_A = 0xFF
TEMPCOA[1:0] = 01,
PDAC_A = 0x00
TEMPCOA[1:0] = 01,
PDAC_A = 0xFF
TEMPCOA[1:0] = 00,
PDAC_A = 0x00
TEMPCOA[1:0] = 00,
PDAC_A = 0xFF
表8-2. Temperature Coefficients for Each TEMPCOB and DAC_B Setting
CSB Voltage [mV], T =
27°C
Temperature Coefficient Temperature Coefficient
[mV/°C] [%/°C]
Register Setting
Coefficient Information
TEMPCOB[1:0] = 11,
PDAC_B = 0x00
81
1.040
1.040
0.693
0.693
0.416
0.416
0.347
0.347
1.284%
0.272%
0.369%
0.143%
0.150%
0.073%
0.116%
0.059%
Max for TEMPCO = 11b
TEMPCOB[1:0] = 11,
PDAC_B = 0xFF
379
189
486
277
572
299
594
Min for TEMPCO = 11b
Max for TEMPCO = 10b
Min for TEMPCO = 10b
Max for TEMPCO = 01b
Min for TEMPCO = 01b
Max for TEMPCO = 00b
Min for TEMPCO = 00b
TEMPCOB[1:0] = 10,
PDAC_B = 0x00
TEMPCOB[1:0] = 10,
PDAC_B = 0xFF
TEMPCOB[1:0] = 01,
PDAC_B = 0x00
TEMPCOB[1:0] = 01,
PDAC_B = 0xFF
TEMPCOB[1:0] = 00,
PDAC_B = 0x00
TEMPCOB[1:0] = 00,
PDAC_B = 0xFF
Use the same procedure for the blue LED, requiring 50 mA and 0.1 mA/°C, to calculate TEMPCOB = 10, RCSB
= 6.8 Ω, VCSB = 345 mV, PDAC_B = 0x85 (before calibration).
The two drivers are identical, except for the CSA_BIN code to improve the accuracy of the LED_A driver for IR
LEDs. Connect the IR LED to the LED A driver and the blue LED to the LED B driver in multi-wave systems.
8.2.2.3 LED Voltage Supply Selection
Each of the LED anodes must have enough voltage to forward bias the LED, regulate the CSA and CSB voltage,
and exceed the driver dropout voltage requirement from DINA to CSA and DINB to CSB. A typical IR LED at 100
mA has 1.5-V forward voltage. The LED driver dropout voltage at 100 mA is 300 mV. With the CSA voltage set
to 100 mV, the dropout voltage of 300 mV, and forward voltage of 1.5 V, at least 1.9 V must be applied to the IR
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LED anode for current regulation. Connect the IR LED anode to LEDLDO and set LEDLDO_EN = 1 to charge
the IR LED anode capacitor.
A typical blue LED at 50 mA has 4 V forward voltage. For the blue LED, the CSB voltage is 340 mV, the dropout
voltage is 300 mV, and the forward voltage is 4 V. Supply over 4.64 V to the anode for the duration of the LED
pulse. With a 47 µF capacitor derated to 30 µF, 100 µs LED pulse, the anode voltage drops by 170 mV. Thus,
the capacitor must be charged to 4.81 V. If the VCC voltage is between 5 V and 6 V, connect the blue LED
anode to VCC through a 1-kΩ resistor. If VCC is between 6 V and 15 V, connect the blue LED anode to
LEDLDO and set LEDLDO_EN = 1 to charge the blue LED anode capacitor. The LED LDO has a diode voltage
drop between the VSLC voltage and LEDLDO voltage. The LEDLDO prevents the DINA pin from exceeding its
recommended operating limit of 11.5 V.
8.2.2.4 Regulator Component Selection
To stabilize the output voltage on each regulator, install 1-µF capacitors on VINT, VMCU, and PLDO. Connect
the MCUSEL pin to GND to set the MCU LDO voltage to 1.8V. The MCU LDO can be set to other voltages by
changing the MCUSEL pin connection. Connect the MCUSEL pin to GND through a 1 nF capacitor to set the
MCU LDO voltage to 3.3 V. Connect MCUSEL to VINT to set the MCU LDO to 2.5 V. Connect MCUSEL to GND
with a 620-Ωresistor to set the MCU LDO to 1.5 V.
8.2.3 Application Curves
All curves use the schematics shown in 图 8-1. The photo amplifier curves do not have the 470 kΩ PREF
resistor installed.
图8-2. LED Driver and Photo Amplifier Waveforms 图8-3. LED Driver and Photo Amplifier Waveforms
with 128 Averages
图8-4. Carbon Monoxide Amplifier Waveforms with Calibration Gas
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9 Power Supply Recommendations
A 4.5-V to 15-V power supply is recommended on VCC and VSLC. If a blue LED is used with the LED driver,
higher voltage may be required. Ensure the power supply can tolerate transient currents caused by the LED
driver. A supply capable of 5 mA average current is generally sufficient. Ensure the power supply's rise time is
less than 100 ms.
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10 Layout
10.1 Layout Guidelines
These blocks require careful layout placement:
• Photo amplifier
• CO amplifier
• Ground plane and traces
10.1.1 Photo Amplifier Layout
The photo amplifier is a very sensitive analog block in the TPS8804 device. Minimal trace lengths must be used
to connect the photodiode and relevant external components to PDP, PDN, PDO, PREF and AGND. It is
recommended to shield the PDP, PDN, PDO, and PREF traces with the AGND plane.
10.1.2 CO Amplifier Layout
Similar to the photo amplifier, the CO amplifier is very sensitive to noise. Connect the CO electrochemical sensor
close to the TPS8804 device and shield the COP, CON, and COO traces with the AGND plane.
10.1.3 Ground Plane Layout
Connect AGND and DGND to the ground plane. Ensure there is a short path from AGND to DGND. Route
PGND and its associated blocks (LED driver, SLC transmitter) separately from the ground plane. Connect PGND
to AGND at a single point near the IC.
10.2 Layout Example
图10-1. Photo Amplifier Layout
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图10-2. CO Amplifier Layout
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AGND
DGND
AGND Plane
PGND
PGND
PGND
PGND
PGND
PGND Pla ne
图10-3. Ground Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS8804DCPR
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS8804DCP
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS8804DCPR
TPS8804DCPR
HTSSOP DCP
HTSSOP DCP
38
38
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS8804DCPR
TPS8804DCPR
HTSSOP
HTSSOP
DCP
DCP
38
38
2000
2000
367.0
356.0
367.0
356.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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