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TPS92692, TPS92692-Q1

SLVSDD9 –MARCH 2017

TPS92692, TPS92692-Q1 High Accuracy LED Controller With

Spread Spectrum Frequency Modulation

1 Features

3 Description

The TPS92692 and TPS92692-Q1 are high accuracy

peak current mode based controllers designed to

support step-up/down LED driver topologies. The

device incorporates a rail-to-rail current amplifier to

measure LED current and spread spectrum frequency

modulation technique for improved EMI performance.

1

•

Wide Input Voltage: 4.5 V to 65 V

Better than ± 4% LED Current Accuracy over

–40°C to 150°C Junction Temperature Range

•

Spread Spectrum Frequency Modulation for

Improved EMI

Comprehensive Fault Protection Circuitry with

Current Monitor output and Open Drain Fault Flag

Indicator

This high performance LED controller can

independently modulate LED current using either

analog or PWM dimming techniques. Linear analog

dimming response with over 15:1 range is obtained

by varying the voltage across the high impedance

analog adjust (IADJ) input. PWM dimming of LED

current is achieved by directly modulating the

DIM/PWM input pin with the desired duty cycle or by

enabling the internal PWM generator circuit. The

PWM generator translates the DC voltage at

DIM/PWM pin to corresponding duty cycle by

comparing it to the internal triangle wave generator.

The optional PDRV gate driver output can be used to

drive an external P-Channel series MOSFET.

•

Internal Analog Voltage to PWM Duty Cycle

Generator for stand-alone Dimming Operation

Compatible with Direct PWM Input with over

1000:1 Dimming Range

Analog LED Current Adjust Input (IADJ) with over

15:1 Contrast Ratio

Integrated P-Channel Driver to enable Series FET

Dimming and LED Protection

TPS92692-Q1: Automotive Q100 Grade 1

Qualified

The TPS92692 and TPS92692-Q1 devices support

continuous LED status check through the current

monitor (IMON) output. The devices also include an

open drain fault indicator output to indicate LED

2 Applications

•

TPS92692-Q1: Automotive Exterior Lighting

Applications

overcurrent,

output

overvoltage

and

output

undervoltage conditions.

•

Driver Monitoring Systems (DMS)

LED General Lighting Applications

Exit Signs and Emergency Lighting

Device Information⁽¹⁾

PART NUMBER

TPS92692-Q1

TPS92692

PACKAGE

BODY SIZE (NOM)

HTSSOP (20)

5.10 mm × 6.60 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Typical Boost LED Driver

D

R_CS

L

Q_DIM

VIN

LED +

C_IN

TPS92692-Q1

1

2

3

4

5

6

7

8

20

C_VCC

R_OV2

C_VREF

VIN

VCC

VREF

FLT

C_OUT

19

18

Q_M

GATE

IS

SS

C_SS

R_OV1

DM

C_DM

R_IS

RT

17

16

GND

LED Þ

R_T

COMP

IMON

R_SLP

SLOPE

C_COMP

15

14

13

12

11

OV

CSP

C_IMON

R_ADJ2

R_DIM2

D_DIM

CSN

R_ADJ1

9

IADJ

PDRV

RAMP

PAD

C_RAMP

R_DIM1

V_/Çw[

10

DIM/PWM

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS92692, TPS92692-Q1

SLVSDD9 –MARCH 2017

www.ti.com

Table of Contents

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Applications ................................................ 34

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Typical Boost LED Driver...................................... 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 9

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 14

9

10 Power Supply Recommendations ..................... 46

11 Layout................................................................... 47

11.1 Layout Guidelines ................................................. 47

11.2 Layout Example .................................................... 48

12 Device and Documentation Support ................. 49

12.1 Related Links ........................................................ 49

12.2 Community Resources.......................................... 49

12.3 Trademarks........................................................... 49

12.4 Electrostatic Discharge Caution............................ 49

12.5 Glossary................................................................ 49

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 49

5 Revision History

DATE

REVISION

NOTES

March 2017

*

Initial release.

2

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6 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP with PowerPAD™

Top View

VIN

VREF

FLT

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VCC

GATE

IS

SS

GND

SLOPE

OV

DM

Thermal

Pad

RT

COMP

IMON

IADJ

CSP

CSN

PDRV

RAMP

DIM/PWM

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Transconductance error amplifier output. Connect compensation network to achieve desired closed-

loop response.

COMP

7

I/O

Current sense amplifier negative input (–). Connect directly to the negative node of LED current

CSN

CSP

13

14

I

sense resistor, R_CS

Current sense amplifier positive input (+). Connect directly to the positive node of LED current

sense resistor, R_CS

.

External analog to PWM dimming command or direct PWM dimming input. The external analog

dimming command between 1 V and 3 V is compared to the internal PWM generator triangle

waveform to set LED current duty cycle between 0% and 100%. With PWM generator disabled, a

direct PWM dimming command can be applied to control the LED current duty cycle and frequency.

The analog or PWM command is used to generate an internal PWM signal that controls the GATE

and PDRV outputs. Setting the internal PWM signal to logic level low, turns off switching, idles the

oscillator, disconnects the COMP pin, and sets PDRV to V_CSP. Connect to VREF when not used for

PWM dimming.

DIM/PWM

10

I

Triangle wave spread spectrum modulation frequency, f_m, programming pin. Connect a capacitor to

GND to set the spread spectrum modulating frequency. Connect directly to GND to disable spread

spectrum modulation of switching frequency.

DM

5

3

I/O

O

Open-drain fault indicator. Connect to VREF with a resistor to create active low fault signal output.

Internal LED short circuit protection and auto-restart timer can enabled by directly connecting the

pin to SS input.

FLT

N-channel MOSFET gate driver output. Connect to gate of external main switching N-channel

MOSFET.

GATE

GND

19

17

O

—

Analog and Power ground connection pin. Connect to circuit ground to complete return path.

LED current reference input. Connect this pin to VCC with a 100-kΩ series resistor to set the

internal reference voltage to 2.42 V and the current sense threshold, V_(CSP-CSN)to 170.7 mV. The

pin can be modulated by an external voltage source from 140 mV to 2.25 V to implement analog

dimming.

IADJ

9

I

LED current report pin. The LED current sensed by CSP/CSN input is reported as V_IMON= 14 × I_LED

× R_CS. Bypass with a 1-nF ceramic capacitor connected to GND.

IMON

IS

8

O

I

Switch current sense input. Connect to the switch sense resistor, R_ISto set the switch current limit

threshold based on the internal 250 mV reference.

18

15

12

Output voltage input. Connect a resistor divider from output voltage to GND to set output

overvoltage and under-voltage protection thresholds.

OV

I

Series dimming P-channel FET gate driver output. Connect to gate of external P-channel MOSFET

to implement series FET PWM dimming and fault disconnect.

PDRV

O

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Programming input for internal PWM generator. Connect a capacitor to GND to set the triangle

wave frequency for PWM generator circuit. Connect a 249-kΩ resistor to GND to disable the PWM

generator and to set a fixed reference for direct external PWM dimming input. Do not allow this pin

to float.

RAMP

11

I/O

Oscillator frequency programming pin. Connect a resistor to GND to set the switching frequency.

The internal oscillator can be synchronized by coupling an external clock pulse through a series

capacitor with a value of 100 nF.

RT

6

I/O

Slope compensation input. Connect a resistor to GND to set the desired slope compensation ramp

based on inductor value, input and output voltages.

SLOPE

SS

16

4

I/O

—

Soft-start programming pin. Connect a capacitor to GND to extend the start-up time. Switching can

be disabled by shorting this pin to GND.

VCC (7.5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value

between 2.2-µF and 4.7-µF). Locate close to the controller.

VCC

20

1

Input supply for the internal regulators. Bypass with a low-pass filter using a series 10-Ω resistor

and 10- nF capacitor connected to GND. Locate the capacitor close to the controller.

VIN

—

VREF (5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value

between 2.2-µF and 4.7-µF) located close to the controller.

VREF

Thermal Pad

2

—

The GND pin must be connected to the exposed thermal pad for proper operation. This PowerPAD

must be connected to PCB ground plane using multiple vias for good thermal performance.

—

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

V_CSP– 8.8

–0.3

—

MAX

65

UNIT

V

VIN, CSP, CSN

DIM/PWM

14

V

Input voltage

IS, RT, FLT

8.8

5.5

0.3

8.8

V_CSP

5.0

100

500

50

V

OV, SS, RAMP, DM, SLOPE, VREF, IADJ

CSP to CSN⁽³⁾

V

VCC, GATE

V

Output voltage⁽⁴⁾

PDRV

V

COMP

V

IMON

µA

mA

°C

Source current

Sink current

GATE (pulsed < 20 ns)

PDRV (pulsed < 10 µs)

GATE (pulsed < 20 ns)

PDRV (pulsed < 10 µs)

—

500

50

—

Operating junction temperature, T_J

Storage temperature, T_stg

–40

150

165

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted

(3) Continuous sustaining voltage

(4) All output pins are not specified to have an external voltage applied.

4

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7.2 ESD Ratings

VALUE

UNIT

TPS92692-Q1 IN PWP (HTSSOP) PACKAGE

Human-body model (HBM), per AEC Q100-002, all pins⁽¹⁾

±2000

±500

±750

Electrostatic

discharge

V_(ESD)

All pins except 1, 10, 11, and 20

Pins 1, 10, 11, and 20

V

Charged-device model (CDM), per AEC Q100-011

TPS92692 IN PWP (HTSSOP) PACKAGE

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾

±2000

±500

Electrostatic

discharge

V_(ESD)

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

6.5

NOM

MAX

UNIT

V

VIN

Supply input voltage

14

65

VIN, crank

V_CSP, V_CSN

ƒ_SW

Supply input, battery crank voltage

Current sense common mode

Switching frequency

4.5

V

6.5

60

800

V

80

kHz

Hz

V

ƒ_m

Spread spectrum modulation frequency

Internal PWM ramp generator frequency

Current reference voltage

0.1

12

f_RAMP

V_IADJ

100

0.14

–40

2000

V_IADJ(CLAMP)

125

T_A

Operating ambient temperature

°C

7.4 Thermal Information

TPS92692

TPS92692-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP) PWP (HTSSOP)

UNIT

20 PINS

40.8

26.1

22.2

0.8

20 PINS

40.8

26.1

22.2

0.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

22.0

2.3

22.0

2.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

–40°C ≤ T_J≤ 150°C, V_IN= 14 V, V_IADJ= 2.1 V, V_RAMP= 500 mV, V_DIM/PWM= 3 V, V_OV= 500 mV, C_VCC= 1 µF, C_VREF= 1 µF,

C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)⁽¹⁾

PARAMETER

INPUT VOLTAGE (VIN)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_IN(STBY)

I_IN(SW)

Input stand-by current

Input switching current

V_PWM= 0 V

1.8

5.1

2.5

6.6

mA

V_CC= 7.5 V, C_GATE= 1 nF

BIAS SUPPLY (VCC)

V_CC(REG)

Regulation voltage

No load

7.0

3.7

30

7.5

4.5

4.1

400

36

8.0

4.9

V

VCC rising threshold, V_IN= 8 V

VCC falling threshold, V_IN= 8 V

Hysteresis

V_CC(UVLO)

Supply undervoltage protection

V

mV

mA

mV

I_CC(LIMIT)

V_DO

Supply current limit

LDO dropout voltage

V_CC= 0 V

46

I_CC= 20 mA, V_IN= 5 V

300

REFERENCE VOLTAGE (VREF)

VREF

Reference voltage

Current limit

No load

4.77

30

4.96

36

5.15

46

V

I_REF(LIMIT)

V_REF= 0 V

mA

OSCILLATOR (RT)

R_T= 40 kΩ

R_T= 20 kΩ

175

341

200

390

1

225

439

kHz

V

ƒ_SW

Switching frequency

V_RT

RT output voltage

SYNC rising threshold

SYNC falling threshold

Minimum SYNC clock pulse width

V_RTrising

V_RTfalling

2.5

2

3.1

V

V_SYNC

t_SYNC(MIN)

1.8

V

100

ns

SPREAD SPECTRUM FREQUENCY MODULATION (DM)

Triangle wave generator sink current

10

µA

I_DM

Triangle wave generator source

current

Triangle wave voltage peak (High)

Triangle wave voltage valley (Low)

1.15

850

V

V_DM(TR)

V_DM(EN)

mV

Spread spectrum modulation enable

threshold

700

mV

V

V_DM(CLAMP)Internal clamp voltage

V_PWM= 0 V, R_RAMP= 200 kΩ

1.25

GATE DRIVER (GATE)

R_GH

R_GL

Gate driver high side resistance

Gate driver low side resistance

I_GATE= –10 mA

I_GATE= 10 mA

5.4

4.3

11.2

10.5

Ω

CURRENT SENSE (IS)

V_DIM/PWM= 5 V, R_RAMP= 249 kΩ

V_DIM/PWM= 0 V, R_RAMP= 249 kΩ

230.6

665

88

250

700

118

35

270

735

158

mV

ns

V_IS(LIMIT)

Current limit threshold

t_IS(BLANK)

t_IS(FAULT)

t_ILMT(DLY)

Leading edge blanking time

Current limit fault time

µs

IS to GATE propagation delay

V_ISpulsed from 0 V to 1 V

78

ns

(1) All voltages are with respect to GND unless otherwise noted

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Electrical Characteristics (continued)

–40°C ≤ T_J≤ 150°C, V_IN= 14 V, V_IADJ= 2.1 V, V_RAMP= 500 mV, V_DIM/PWM= 3 V, V_OV= 500 mV, C_VCC= 1 µF, C_VREF= 1 µF,

C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM COMPARATOR AND SLOPE COMPENSATION (SLOPE)

D_MAX

Maximum duty cycle

90

%

V_SLOPE

Adaptive slope compensation

V_CSP= 24 V

V_CSP= 0 V

410

mV

Minimum slope compensation output

voltage

V_SLOPE(MIN)

72

mV

V_LV

I_LV

IS to COMP level shift voltage

IS level shift bias current

No slope compensation added

1.42

1.60

17

1.82

V

µA

CURRENT SENSE AMPLIFIER (CSP, CSN)

V_CSP= 14 V, V_IADJ= 3 V

V_CSP= 14 V, V_IADJ= 1.4 V

163.4

95.83

170.7

100.5

500

177.6

mV

kHz

V_(CSP-CSN)

Current sense thresholds

103.85

CS_(BW)

G_CS

Current sense unity gain bandwidth

Current sense amplifier gain

G = V_IADJ/V_(CSP-CSN)

14

Ratio of over-current detection

threshold to analog adjust voltage

K_(OCP)

K _(OCP)= V_(OCP-THR)/V_IADJ

1.46

1.5

1.61

I_CSP(BIAS)

I_CSN(BIAS)

CSP bias current

CSN bias current

V_CSN= 14.1 V, V_CSP= 14 V

107

110

µA

FAULT INDICATOR (FLT)

R_(FLT)

Open-drain pull down resistance

241

36

Ω

t_{(FAULT_TMR)}Fault timer

CURRENT MONITOR (IMON)

24

48

ms

V_(CSP-CSN)= 150 mV,

V_IMON= 0 V

I_IMON(SRC)

IMON source current

144

µA

V_IMON(CLP)

V_IMON(OS)

IMON output voltage clamp

IMON buffer offset voltage

3.2

3.7

0

4.2

8.5

V

–7.2

mV

ANALOG ADJUST (IADJ)

V_IADJ(CLP)

I_IADJ(BIAS)

R_IADJ(LMT)

IADJ internal clamp voltage

I_IADJ= 1 µA

V_IADJ< 2.2 V

V_IADJ> 2.6 V

2.29

2.40

10.5

12

2.55

V

IADJ input bias current

nA

kΩ

IADJ current limiting series resistor

ERROR AMPLIFIER (COMP)

g_M

Transconductance

121

130

5

µA/V

µA

I_COMP(SRC)

I_COMP(SINK)

EA_(BW)

COMP current source capacity

COMP current sink capacity

Error amplifier bandwidth

V_IADJ= 1.4 V, V_(CSP-CSN)= 0 V

V_IADJ= 0 V, V_(CSP-CSN)= 0.1 V

Gain = –3 dB

µA

MHz

mV

Ω

V_COMP(RST)COMP pin reset voltage

R_COMP(DCH)COMP discharge FET resistance

SOFT-START (SS)

100

246

I_SS

Soft-start source current

7

10

12.8

µA

V

Soft-start voltage threshold to enable

output under-voltage protection

V_{SS(UVP_EN)}

2.4

V_SS(RST)

R_SS(DCH)

Soft-start pin reset voltage

50

mV

SS discharge FET resistance

240

Ω

OUTPUT VOLTAGE INPUT (OV)

V_OVP(THR)Overvoltage protection threshold

V_UVP(THR)

1.195

81.7

1.228

100

1.262

115.1

V

Undervoltage protection threshold

mV

Undervoltage protection blanking

period

t_(UVP-BLANK)

I_OVP(HYS)

4

µs

OVP hysteresis current

12

20

27.5

µA

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Electrical Characteristics (continued)

–40°C ≤ T_J≤ 150°C, V_IN= 14 V, V_IADJ= 2.1 V, V_RAMP= 500 mV, V_DIM/PWM= 3 V, V_OV= 500 mV, C_VCC= 1 µF, C_VREF= 1 µF,

C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, no load on GATE and PDRV (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL PWM RAMP GENERATOR (RAMP)

Ramp generator source current

I_RAMP

7.75

8.24

10

3

12.73

12.41

µA

V

Ramp generator sink current

Ramp signal peak (high)

V_RAMP

Ramp signal valley (low)

1

V

PWM INPUT (DIM/PWM)

Schmitt trigger logic level (high

V_PWM(HIGH)

threshold)

V_RAMP= 2.0 V

2.0

2.2

V

Schmitt trigger logic level (low

V_PWM(LOW)

threshold)

V_RAMP= 2.0 V

1.8

R_PWM(PD)

t_DLY(RISE)

t_DLY(FALL)

PWM pull-down resistance

PWM rising to PDRV delay

PWM falling to PDRV delay

10

294

326

MΩ

ns

C_PDRV= 1 nF

ns

SERIES P-CHANNEL PWM FET GATE DRIVE OUTPUT (PDRV)

V_PDRV(OFF)

V_PDRV(ON)

I_PDRV(SRC)

R_PDRV(L)

P-channel gate driver off-state voltage V_CSP= 14 V

P-channel gate driver on-state voltage V_CSP= 14 V

14

7.4

50

V

PDRV sink current

Pulsed

mA

Ω

PDRV driver pull up resistance

82

THERMAL SHUTDOWN

T_SD

Thermal shutdown temperature

Thermal shutdown hysteresis

175

25

°C

T_SD(HYS)

8

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7.6 Typical Characteristics

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and PDRV (unless otherwise noted)

7.54

7.53

7.52

7.51

7.5

4.975

4.97

4.965

4.96

4.955

4.95

7.49

7.48

7.47

7.46

4.945

4.94

4.935

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D001

D020

Figure 1. VCC Regulation Voltage vs Junction Temperature

Figure 2. VREF Reference Voltage vs Junction Temperature

600

44

42

40

38

36

34

32

30

500

400

300

200

100

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D002

D003

V_IN= 5 V,

I_VCC= 20 mA

Figure 4. VCC Current Limit vs Junction Temperature

Figure 3. VCC Dropout Voltage vs Junction Temperature

100

4.85

Rising

Falling

80

70

60

4.75

4.65

4.55

4.45

4.35

4.25

4.15

4.05

3.95

3.85

50

40

30

20

10

-40 -20

0

20

40

60

80 100 120 140 160

50

150

250

350

450

550

650

750800

Junction Temperature (^oC)

Frequency (kHz)

D004

D005

Figure 5. VCC UVLO Threshold vs Junction Temperature

Figure 6. Timing Resistance (RT) vs Switching Frequency

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Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and PDRV (unless otherwise noted)

398

396

394

392

390

388

386

384

382

90.3

90.2

90.1

90

89.9

89.8

89.7

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D006

D007

R_T= 20 kΩ

Figure 8. Maximum Duty Cycle vs Junction Temperature

Figure 7. Switching Frequency vs Junction Temperature

135

130

125

120

115

110

105

251

250.5

250

249.5

249

248.5

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D008

D009

Figure 9. Current Limit Threshold vs Junction Temperature

Figure 10. Leading Edge Blanking Period vs Junction

Temperature

174

171.2

171

173

172

171

170

169

168

170.8

170.6

170.4

170.2

170

169.8

0

5

10 15 20 25 30 35 40 45 50 55 60 65

V_CSP(V)

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D010

D011

V_IADJ> 2.6 V

Figure 11. V_(CSP-CSN)Threshold vs V_CSPVoltage

Figure 12. V_(CSP-CSN)Threshold vs Junction Temperature

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Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and PDRV (unless otherwise noted)

101

100.75

100.5

100.25

100

125

120

115

110

105

100

95

CSP

CSN

99.75

99.5

99.25

99

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D0012

D013

V_IADJ= 1.4 V

V_CSP= V_CSN= 14 V

Figure 13. V_(CSP-CSN)Threshold vs Junction Temperature

Figure 14. CSP/CSN Input Bias Current vs Junction

Temperature

4

3.5

3

3.76

3.74

3.72

3.7

2.5

2

1.5

1

3.68

3.66

3.64

0.5

0

30

60

90 120 150 180 210 240 270 300

V_(CSP-CSN)(mV)

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperaure (^oC)

D014

D015

Figure 15. V_IMONvs V_(CSP-CSN)

Figure 16. V_IMON(CLP)vs Junction Temperature

200

180

160

140

120

100

80

2.403

2.402

2.401

2.4

2.399

2.398

2.397

2.396

2.395

60

40

20

0

0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 2.52 2.8

V_IADJ(V)

3

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D016

D017

Figure 17. V(_CSP-CSN)Threshold vs V_IADJ

Figure 18. V_IADJVoltage Clamp vs Junction Temperature

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Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and PDRV (unless otherwise noted)

1.232

1.231

1.23

21

20.8

20.6

20.4

20.2

20

1.229

1.228

1.227

1.226

1.225

1.224

1.223

1.222

19.8

19.6

19.4

19.2

19

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (^oC)

D018

D019

Figure 19. OVP Detection Threshold vs Junction

Temperature

Figure 20. OVP Hysteresis Current vs Junction Temperature

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8 Detailed Description

8.1 Overview

The TPS92692 and TPS92692-Q1 devices feature all of the functions necessary to implement a compact LED

driver based on step-up or step-down power converter topologies. The devices implement a fixed-frequency,

peak current mode control technique to achieve constant output current and fast transient response. The

integrated low offset, rail-to-rail current sense amplifier provides the flexibility required to power a single string

consisting of 1 to 20 series connected LEDs while maintaining better than 4% current accuracy over the

operating temperature range. The LED current regulation threshold is set by the analog adjust input, IADJ and

can be externally programmed to implement analog dimming with over 15:1 linear dimming range. The high

impedance IADJ input simplifies LED current binning and thermal protection.

The TPS92692 and TPS92692-Q1 devices incorporate an internal PWM generator that can be programmed to

implement pulse width modulation (PWM) dimming of LED current. The PWM duty cycle can be varied from 0%

to 100% by modulating the analog voltage on DIM/PWM input from 1 V to 3 V. The PWM dimming frequency is

externally programmable and is set by the capacitor connected to RAMP input. As an alternative, the TPS92692

and TPS92692-Q1 devices can also be configured to implement direct PWM dimming based on the duty cycle of

external PWM signal by connecting a 249-kΩ resistor across RAMP pin and GND. The internal PWM signal

controls the GATE and PDRV outputs which control the external n-channel switching FET and p-channel

dimming FET connected in series with LED string, respectively.

The current monitor output, IMON, reports the instantaneous status of LED current measured by the rail-to-rail

current sense amplifier. This feature indicates instantaneous current as a result of LED short circuit and cable

harness failure, independent of LED driver topology. An open-drain fault indicator is also provided to report faults

including cycle-by-cycle current limit, output overvoltage, and output undervoltage conditions. LED driver

protection with auto-restart (hiccup) mode is enabled by connecting the fault pin (FLT) to the SS pin. Other

protection features include VCC undervoltage protection and thermal shutdown. A remote signal can force the

device in to shutdown by pulling down on the SS pin.

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8.2 Functional Block Diagram

5 V LDO

Regulator

VREF

VCC

7.5 V LDO

Regulator

VIN

Internal

References

Thermal

Limit

UVLO

(4.1 V)

Standby

LEB

Clock

RT

S

R

Q

GATE

Oscillator

Max Duty

Spread

DM

Spectrum

Modulator

GND

OV

20 ꢀ!

10 ꢀ!

2.4 V

SS_DONE

+

SS

Overvoltage

Fault

+

PWM

Comp

1.23 V

Undervoltage

Fault

COMP

+

100 mV

CSP

PWM

100 mV

SS_DONE

Reset

Logic

50 mV

Fault

SS

PDRV

Fault

7 V

DIM/

PWM

10 ꢀ!

+

100 ꢀ!

Triangle

Wave

Generator

3 V

1 V

RAMP

CSP

VIN CSP

1.4 V

Gain = 14

+

Slope

Generator

SLOPE

8 kꢁ

Current Sense

Amplifier

CSN

IS

+

35 …s

Çimer

+

IMON

700 mV

S0

Standby

LEB

3.7 V

S1

250 mV

PWM

Overcurrent

Detector

12 kꢁ

IADJ

36 ms

Çimer

FLT

+

Undervoltage

Fault

2.4 V

Fault

14

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8.3 Feature Description

8.3.1 Internal Regulator and Undervoltage Lockout (UVLO)

The device incorporates a 65-V input voltage rated linear regulators to generate the 7.5 V (typ) V_CCbias supply,

the 5 V (typ) V_REFreference supply and other internal reference voltages. The device monitors the V_CCoutput to

implement UVLO protection. Operation is enabled when V_CCexceeds the 4.5-V (typ) threshold and is disabled

when V_CCdrops below the 4.1-V (typ) threshold. The UVLO comparator provides 400 mV of hysteresis to avoid

chatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. An internal current

limit circuit is implemented to protect the device during VCC pin short-circuit conditions. The V_CCsupply powers

the internal circuitry and the N-channel gate driver output, GATE. Place a bypass capacitor in the range of 2.2 µF

to 4.7 µF across the V_CCoutput and GND to ensure proper operation. The regulator operates in dropout when

input voltage V_INfalls below 7.5 V forcing V_CCto be lower than V_INby 300 mV for a 20-mA supply current. The

V_CCis a regulated output of the internal regulator and is not recommended to be driven from an external power

supply.

The V_REFsupply is internally used to generate voltage thresholds for the RAMP generator circuit and to power

some digital circuits. This supply can be used in conjunction with a resistor divider to set voltage levels for the

IADJ pin and DIM/PWM pin to set LED current and PWM dimming duty cycle. It can also be used to bias

external circuitry requiring a reference supply. The supply current is internally limited to protect the device from

output overload and short-circuit conditions. Place a bypass capacitor in the range of 2.2 µF to 4.7 µF across the

VREF output to GND to ensure proper operation.

The TPS92692 and TPS92692-Q1 devices incorporate features that simplify compliance with the CISPR and

automotive EMI requirements. The devices have optional spread spectrum frequency modulation circuit that can

be externally configured to reduce peak and average conducted and radiated EMI. The internal programmable

oscillator has a range of 80 kHz to 800 kHz and can be tuned based on the EMI requirements. The devices are

available in HTSSOP-20 package with an exposed pad to aid in thermal dissipation.

8.3.2 Oscillator

The switching frequency is programmable by a single external resistor connected between the RT pin and GND.

To set a desired frequency, ƒ_SW(Hz), the resistor value can be calculated from Equation 1.

1.432ì10¹⁰

R_T

=

W

(

)

1.047

f

(

)

SW

(1)

Figure 6 shows a graph of switching frequency versus resistance, R_T. TI recommends a switching frequency

setting between 80 kHz and 700 kHz for optimal performance over input and output voltage operating range and

for best efficiency. Operation at higher switching frequencies requires careful selection of N-channel MOSFET

characteristics as well as detailed analysis of switching losses.

Clock

f_SYNC

RT

R_T

Oscillator

C_SYNC

Figure 21. Oscillator Synchronization Through AC Coupling

The internal oscillator can be synchronized by AC coupling an external clock pulse to RT pin as shown in

Figure 21. The positive going synchronization clock at the RT pin must exceed the RT sync threshold and the

negative going synchronization clock at the RT pin must exceed the RT sync falling threshold to trip the internal

synchronization pulse detector. TI recommends that the frequency of the external synchronization pulse is within

±20% of the internal oscillator frequency programmed by the R_Tresistor. TI recommends a minimum coupling

capacitor of 100 nF and a typical pulse width of 100 ns for proper synchronization. In the case where external

synchronization clock is lost the internal oscillator takes control of the switching rate based on the R_Tresistor to

maintain output current regulation. The R_Tresistor is always required whether the oscillator is free running or

externally synchronized.

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Feature Description (continued)

8.3.3 Spread Spectrum Frequency Modulation

The TPS92692 and TPS92692-Q1 devices provide a frequency dithering option that is enabled by connecting a

capacitor from the DM pin to GND. A triangle waveform centered at 1 V is generated across the C_DMcapacitor.

The triangle waveform modulates the oscillator frequency by ± 15% of the nominal frequency set by an external

timing resistor, R_T. The C_DMcapacitance value sets the rate of the low frequency modulation. To achieve

maximum attenuation in average EMI scan set modulation frequency ranging from 100 Hz to 1.2 kHz. The low

modulating frequency has little impact on the quasi-peak EMI scan. Set the modulation frequency to 10 KHz or

higher to achieve attenuation for quasi-peak EMI measurements. The modulation frequency higher than the

receiver resolution bandwidth (RBW) of 9 kHz only impacts the quasi-peak EMI scan and has little impact on the

average measurement. The device simplifies EMI compliance by providing the means to tune the modulation

frequency based on measured EMI signature. Equation 2 calculates the C_DMcapacitance required to set the

modulation frequency, f_MOD(Hz).

10 mA

2ì f_MODì0.3 V

C_DM

=

(F)

(2)

1.15 V

+

1 V

0.85 V

10 ꢀA

S

R

Q

DM

10 ꢀA

+

C_DM

0.85 V

Figure 22. Frequency Dither Operation

Connect the DM pin to GND to disable frequency dither circuit operation. Internal frequency dithering is not

supported when the devices are synchronized based on an external clock signal.

8.3.4 Gate Driver

The TPS92692 and TPS92692-Q1 devices contain a N-channel gate driver that switches the output V_GATE

between V_CCand GND. A peak source and sink current of 500 mA allows controlled slew-rate of the MOSFET

gate and drain node voltages, limiting the conducted and radiated EMI generated by switching.

VCC

C_VCC

GATE_IN

GATE

GND

Figure 23. Push-Pull N-Channel Gate Driver Circuit

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Feature Description (continued)

The gate driver supply current I_CC(GATE)depends on the total gate drive charge (Q_G) of the MOSFET and the

I_CC(GATE)= Q_Gì f

operating frequency of the converter, ƒ_SW

,

^SW. Choose a MOSFET with a low gate charge

specification to limit the junction temperature rise and switch transition losses.

It is important to consider the MOSFET threshold voltage when operating in the dropout region when the input

voltage, V_IN, is below the V_CCregulation level. TI recommends a logic level device with a threshold voltage below

5 V when the device is required to operate at an input voltage less than 7 V.

8.3.5 Rail-to-Rail Current Sense Amplifier

The internal rail-to-rail current sense amplifier measures the average LED current based on the differential

voltage drop between the CSP and CSN inputs over a common mode range of 0 V to 65 V. The differential

voltage, V_(CSP-CSN), is amplified by a voltage-gain factor of 14 and is connected to the negative input of the

transconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative input

offset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and

the transconductance error amplifier offset voltage) to less than 5 mV over the recommended common-mode

voltage, and temperature range.

Differential Mode

R_FS

Filter Capacitor

CSP

+

R_CS

C_FDM

CSN

R_FS

Common Mode

Filter Capacitors

C_FCMC_FCM

Figure 24. Current Sense Amplifier Input Filter Options

An optional common-mode or differential mode low-pass filter implementation, as shown in Figure 24, can be

used to smooth out the effects of large output current ripple and switching current spikes caused by diode

reverse recovery. TI recommends a filter resistance in the range of 10 Ω to 100 Ω to limit the additional offset

caused by amplifier bias current mismatch to achieve the best accuracy and line regulation.

8.3.6 Transconductance Error Amplifier

The internal transconductance amplifier generates an error signal proportional to the difference between the LED

current sense feedback voltage and the external IADJ input voltage. The output of the error amplifier is

connected to an external compensation network to achieve closed-loop LED current regulation. In most LED

driver applications a simple integral compensation circuit consisting of a capacitor connected from COMP output

to GND provides a stable response over wide range of operating conditions. TI recommends a capacitor value

between 10 nF and 100 nF as a good starting point. To achieve higher closed-loop bandwidth a proportional-

integral compensator, consisting of a series resistor and a capacitor network connected across the COMP output

and GND, is required. Based on the converter topology, tune the compensation network to achieve a minimum of

60° of phase margin and 10 dB of gain margin. The Application and Implementation section includes a

summarized detailed design procedure.

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Feature Description (continued)

8.3.7 Switch Current Sense

The IS input pin monitors the main MOSFET current to implement peak current mode control. The GATE output

duty cycle is derived by comparing the peak switch current, measured by the R_ISresistor, to the internal COMP

voltage threshold. An internal slope signal, V_SL, generated by slope compensation circuit is added to the

measured sense voltage, V_IS, to prevent subharmonic oscillations for duty cycles greater than 50%. An internal

blanking circuit prevents MOSFET switching current spike propagation and premature termination of duty cycle

by internally shunting the IS input for 150 ns after the beginning of the new switching period. For additional noise

suppression connect an external low-pass RC filter with resistor values ranging from 100 Ω to 500 Ω and a 1000

pF capacitor. The external RC filter ensures proper operation when operating in the dropout region (V_INless than

7 V).

ILIM

Comparator

150 ns

IS

+

ILIM

35 …s

ÇLa9w

LEB

700 mV

S0

S1

250 mV

PWM

Figure 25. Switch Current Limit Circuit

Cycle-by-cycle current limit is accomplished by a redundant internal comparator. The current limit threshold is set

based on the status of internal PWM signal. The current limit threshold is set to 250 mV (typ) when PWM signal

is high and to 700 mV (typ) when PWM signal is low. The transition between the two thresholds work in

conjunction with slope compensation and the error amplifier circuit to allow for higher inductor current

immediately after the PWM transition and to improve LED current transient response during PWM dimming.

Refer to the DIM/PWM Input section for details on PWM Dimming operation.

The device immediately terminates the GATE and PDRV output when the IS input voltage, V_IS, exceeds the

threshold value. Upon a current limit event, the SS and COMP pin are internally grounded to reset the state of

the controller. The GATE output is enabled after the expiration of the 35-µs internal fault timer and a new start-up

sequence is initiated through the SS pin. Equation 3 calculates the peak inductor current in the current limit.

250mV

I_L(PK)

=

(A)

R_IS

(3)

8.3.8 Slope Compensation

Peak current mode based regulators are subject to sub-harmonic oscillations for duty cycle greater than 50%. To

avoid this instability problem, the control scheme is modified by the addition of an artificial ramp to the sensed

switch current waveform. The slope of the artificial ramp required is dependent on the input voltage, V_IN, output

voltage, V_O, inductor, L, and switch current sense resistor, R_IS. The devices incorporate an adaptive slope

compensation technique that modifies the slope of the artificial ramp generated based on the input voltage, V_IN

and output voltage measured at CSP pin, V_CSP, thus greatly simplifying the design for common LED driver

topologies, such as boost, buck-boost, and boost-to-battery. The magnitude of the internal ramp signal can be

calculated as follows:

0.494ì V

- V_O+1

(

)

(

)

CSP

V_SL= 278ì10⁶ìDì

f_SWìR_SLP

where

•

D is the converter duty cycle

(4)

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Feature Description (continued)

The resistor, R_SLOPEprovides the flexibility to set the slope of the internal artificial ramp based on the inductance

value, L and the LED driver topology. The Application and Implementation section includes detailed calculations

for the resistor, R_SLOPE, based on the LED driver topology. The SLOPE pin cannot be left floating.

8.3.9 Analog Adjust Input

The voltage across the LED current sense resistor, V_(CSP–CSN), is regulated to the analog adjust input voltage,

V_IADJ, scaled by the current sense amplifier voltage gain of 14. The LED current can be linearly adjusted by

varying the voltage on IADJ pin from 140 mV to 2.25 V using either a resistor divider from V_REFor a voltage

source. The IADJ pin can be connected to V_REFthrough an external resistor to set LED current based on the 2.4-

V internal reference voltage. This device offers different methods to set the IADJ voltage. Figure 27 shows how

the IADJ input can be used in conjunction with a NTC resistor to implement thermal foldback protection. A PWM

signal in conjunction with first- or second-order low-pass filter can be used to program the IADJ voltage as shown

in Figure 28).

VREF

R_ADJ

R_ADJ2

IADJ

C_ADJ

PWM

Signal

Åt°

R_ADJ1

R_NTC

Figure 26. Static Reference

Setting Resistor Divider From

VCC

Figure 27. Thermal Fold-back

Circuit Using External NTC

Resistor

Figure 28. Analog Dimming

Achieved By Low-pass Filtering

External PWM Signal

8.3.10 DIM/PWM Input

The TPS92692 and TPS92692-Q1 devices incorporate a PWM generator circuit to facilitate analog voltage to

PWM duty cycle translation. The dimming frequency is set by connecting a capacitor from RAMP pin to GND.

The dimming frequency, f_DIM, can be calculated as follows:

10 mA

2ì 2 V ìC_DIM

f_DIM

=

(Hz)

(5)

The internal PWM signal can be varied from 0% to 100% by setting the DIM/PWM pin voltage between 1 V and 3

V. Equation 6 describes the relationship between DIM/PWM pin voltage, V_DIMand internal PWM duty cycle,

D_PWM(INT)

.

V_DIM-1

D_PWM(INT)

=

2

(6)

For improved dimming accuracy, use the VREF pin and a resistor divider to set the DIM/PWM pin voltage, V_DIM

,

and the corresponding duty cycle. The device can be configured to step the duty cycle between 100% and the

programmed value by diode connecting the external control signal, V_CTRL, to the DIM/PWM pin, as shown in

Figure 29. The external control signal, of amplitude 3-V, is usually generated by the command module and is

based on the light output required by the application.

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Feature Description (continued)

5V LDO

VREF

Regulator

C_VREF

3 V

1 V

Triangle

Wave

Generator

3 V

1 V

RAMP

C_RAMP

R_DIM2

PWM

+

DIM/PWM

D_DIM

V_/Çw[

R_DIM1

Figure 29. PWM Dimming Using Internal PWM Generator

The devices can be configured to be compatible with external PWM signal, V_PWM(EXT), where the LED current is

modulated based on the duty cycle, D_PWM(EXT). To enable direct PWM, it is required to disable the internal

triangle wave generator by connecting a 249-kΩ resistor from RAMP pin to GND. In this case, the internal

comparator threshold is set to 2.49-V and the internal PWM duty cycle, D_PWM(INT), is controlled by the external

PWM command. The RAMP pin cannot be left floating.

5V LDO

VREF

Regulator

C_VREF

3 V

1 V

Triangle

Wave

Generator

RAMP

R_RAMP

PWM

+

V_PWM(EXT)

DIM/PWM

Figure 30. Direct PWM Dimming

The internal PWM signal, V_PWMcontrols the GATE and PDRV outputs. Forcing V_PWMin a logic low state turns off

switching, parks the oscillator, disconnects the COMP pin, and sets the PDRV output to V_CSPin order to maintain

the charge on the compensation network and output capacitors. On the rising edge of the PWM voltage (V_PWM

set to logic level high), the GATE and PDRV outputs are enabled to ramp the inductor current to the previous

steady-state value. The COMP pin is connected and the error amplifier and oscillator are enabled only when the

switch current sense voltage V_ISexceeds the COMP voltage, V_COMP, thus immediately forcing the converter into

steady-state operation with minimum LED current overshoot. When dimming is not required, connect the

DIM/PWM pin to the V_CCpin. An internal pull-down resistor sets the input to logic-low and disables the device

when the pin is disconnected or left floating.

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Feature Description (continued)

8.3.11 Series P-Channel FET Dimming Gate Driver Output

The PDRV output is a function of the internal PWM signal and is capable of sinking and sourcing up to 50 mA of

peak current to control a high-side series connected P-channel dimming FET. The PDRV switches between V_CSP

and (V_CSP– 7 V) based on the status of PWM signal to completely turn-off and turn-on the external P-channel

dimming FET. The series dimming FET is required to achieve high contrast ratio as it ensures fast rise and fall

times of the LED current in response to the PWM input. Without any dimming FET, the rise and fall times are

limited by the inductor slew rate and the closed-loop bandwidth of the system. Leave the PDRV pin unconnected

if not used.

8.3.12 Soft-Start

The soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startup

stresses and surges. The devices clamp the COMP pin to the SS pin, separated by a diode, until LED current

nears the regulation threshold. The internal 10-µA soft-start current source gradually increases the voltage on an

external soft-start capacitor C_SSconnected to the SS pin. This results in a gradual rise of the COMP voltage from

GND.

The internal 10-µA current source turns on when VCC exceeds the UVLO threshold. At the beginning of the soft-

start sequence, the SS pull-down switch is active and is released when the voltage V_SSdrops below 50 mV. The

SS pin can also be pulled down by an external switch to stop switching. When the SS pin is externally driven to

enable switching, the slew-rate on the COMP pin is controlled by the compensation capacitor. In this case, the

startup duration and LED current transient is controlled by tunning the compensation network. It is essential to

ensure that the softstart duration is longer than the time required to charge the output capacitor when selecting

the soft-start capacitor, C_SSand the compensation capacitor, C_COMP

.

8.3.13 Current Monitor Output

The IMON pin voltage represents the LED current measured by the rail-to-rail current sense amplifier across the

external current shunt resistor. The linear relationship between the IMON voltage and LED current includes the

amplifier gain-factor of 14 (see Feature Description section). The IMON output can be connected to an external

microcontroller or comparator to facilitate LED open, short, or cable harness fault detection and mitigation. The

IMON voltage is internally clamped to 3.7 V.

8.3.14 Output Overvoltage Protection

The TPS92692 and TPS92692-Q1 devices include a dedicated OV pin which can be used for either input or

output overvoltage protection. This pin features a precision 1.228 V (typ) threshold with 20-µA (typ) of hysteresis

current. The overvoltage threshold limit is set by a resistor divider network from the input or output terminal to

GND. When the OV pin voltage exceeds the reference threshold, the GATE pin is immediately pulled low, the

PDRV output is disabled, and the SS and COMP capacitors are discharged. The GATE and PDRV outputs are

enabled and a new startup sequence is initiated after the voltage drops below the hysteresis threshold set by the

20-µA source current and the external resistor divider.

8.3.15 Output Short-circuit Protection

The device monitors the output of the current sense amplifier and the output voltage via OV pin to determine

LED Short-circuit fault. The device signals an output overcurrent fault when the voltage across the current sense

amplifier, (V_(CSP-CSN)), exceeds the regulation set point based on the IADJ pin voltage, V_IADJ. The overcurrent fault

threshold is calculated as follows:

V

IADJ

V _{(CSP-CSN),OCP}= 1.5ì

(

)

14

(7)

The device also indicates a short-circuit condition when the voltage across the OV pin and GND falls below 100

mV. In this case, the output voltage, V_O, is below the undervoltage fault threshold determined based on the

resistor divider connected to the OV pin.

R_OV1+ R_OV2

V_O(UV)= 0.1ì

R_OV1

(8)

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Feature Description (continued)

The devices indicate a fault by forcing the open-drain fault indicator FLT pin to GND and initiating a 36-ms timer.

The devices do not internally initiate any protection action and continue to operate until externally disabled by

pulling SS pin to GND. This provides maximum design flexibility to enable user defined fault protection by using

either the fault indicator output, FLT, or the analog IMON output based on the LED driver topology and end

application.

The undervoltage fault detection circuit is internally disable based on the SS pin voltage and internal PWM

status. The fault blanking circuit is designed to prevent false undervoltage detection during the startup sequence

and PWM dimming operation.

8.3.16 Thermal Protection

Internal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 175°C, the controller is forced into a shutdown mode,

disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.

8.3.17 Fault Indicator (FLT)

The devices include an open-drain output to indicate fault conditions. The FLT pin goes low under the following

conditions:

•

Overvoltage across the LED string (V_OV> 1.24 V)

Under voltage across the LED string (V_OV< 100 mV)

Overcurrent across the LED string (14 × V_(CSP-CSN)> 1.5 × V_IADJ

Cycle-by-cycle switch current limit condition (V_IS> 250 mV)

)

The FLT pin goes high when the fault conditions ends or when the internal 36-ms timer expires. The status of the

FLT under different fault conditions is summarized in the Device Functional Modes section.

8.4 Device Functional Modes

The following table summarizes the device behavior under fault condition.

Table 1. Fault Descriptions

FAULT

DETECTION

ACTION

V_CC(RISE)< 4.5 V

The device enters the standby state when the VCC voltage falls below the UVLO

threshold. In standby state, GATE and PDRV outputs are disabled and the SS and

COMP capacitors are discharged. FLT pin remains in high-impedance state.

Input undervoltage

(UVLO)

V_CC(FALL)< 4.1 V

V_IS> 250 mV

Cycle-by-cycle current limit is activated when the IS pin voltage exceeds 250 mV. The

GATE and PDRV outputs are disabled, the SS and COMP pin capacitors are discharged

and FLT pin is forced to ground. An internal 35-μs timer is activated. Soft-start sequence

is initiated after expiration of the 35 μs timer period.

Switch current limit

Thermal protection

Internal thermal shutdown circuitry is activated when the junction temperature exceeds

175 °C. The controller is forced into a shutdown mode, disabling the internal regulators.

A startup sequence is initiated when the junction temperature falls below 155˚C. The

FLT pin remains in a high-impedance state.

T_J> 175°C

When the OV pin voltage exceeds 1.228 V, GATE and PDRV outputs are disabled, SS

and COMP capacitors are discharged, and the FLT pin is forced to GND. A soft-start

sequence is initiated once the output voltage drops below the hysteresis threshold set by

the 20 μA current source.

Programmable output

overvoltage protection

V_OV> 1.228 V

The FLT pin is forced to ground for 36-ms when the LED current exceeds 1.5 times the

Fixed LED Overcurrent

protection

V_(CSP-CSN)> V_((CSP-regulation set point. The FLT pin is released after timer expires. Under sustained short-

circuit condition, the FLT pin transitions between a high-impedance state and ground

CSN),OCP)

until the fault is cleared. Device continues to operate while in this condition.

The FLT pin is forced to ground for 36-ms when OV pin voltage drops below 100 mV.

Output undervoltage

protection

The FLT pin is released after timer expires. Under sustained short-circuit condition, the

FLT pin transitions between the high-impedance state and ground until fault is cleared.

V_OV< 100 mV

Device continues to operate while in this condition.

Current monitor output (IMON) can be used to externally program current limit. The

IMON output can be connected to an external microcontroller or comparator to facilitate

LED open, short, or cable harness fault detection.

Programmable LED

overcurrent protection

V_IMON> V_IADJ

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Device Functional Modes (continued)

Table 1. Fault Descriptions (continued)

FAULT

DETECTION

ACTION

COMP pin short to

ground

Switching is disabled when COMP voltage falls below 1.6 V. The FLT pin remains a in

high-impedance state.

V_COMP< 1.6 V

The device enters standby when the VCC voltage falls below the UVLO threshold. In the

standby state, GATE and PDRV outputs are disabled and the SS and COMP capacitors

are discharged. The FLT pin will remain in a high-impedance state.

VREF pin short to

ground

V_REF< 2.0 V

8.4.1 Hiccup Mode Short-circuit Protection

Connecting the FLT pin to the SS pin enables hiccup mode operation under output short-circuit conditions.

SS

FLT

C_SS

Figure 31. Hiccup Mode Short-Circuit Protection

On detection of output short-circuit fault, the FLT pin forces the SS pin to GND (V_SS< 50 mV) and disables

GATE and PDRV outputs for 36-ms. Upon timer expiration, the FLT pin is released and a new soft start

sequence is initiated. Under sustained fault conditions the device operates in hiccup mode, attempting to recover

after every 36-ms period.

Overcurrent

Detected

Fault

Cleared

Undervoltage

Detected

Fault

Cleared

V_CSP

I_LED

SS/FLT

2.4 V

V_{SS(UVP_EN)}

I_SS= 10ꢀA

2.4 V

V_{SS(UVP_EN)}

GATE

PDRV

GATE

PDRV

T_{(FAULT_TMR)}

Figure 32. Output Overcurrent Fault Protection

Figure 33. Output Undervoltage Fault Protection

8.4.2 Fault Indication Mode

The FLT pin output can be setup to indicate fault status to a microcontroller and aid in fault diagnostics and

protection. In case of a fault, the FLT pin is forced low when biased through an external resistor connected either

to reference voltage output, VREF, or an external bias supply. When connected to VREF, the FLT pin is driven

low when the device enters standby mode during UVLO, thermal shutdown, or VREF short-circuit conditions. The

Fault Indicator (FLT) section lists fault diagnostics and system level faults.

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Microcontroller

BIAS

TPS92692

VREF

Microcontroller

GPIO1

R_FLT

GPIO1

FLT

SS

FLT

SS

C_SS

GPIO2

Figure 34. FLT Pin Interface With Microcontroller

Figure 35. FLT Pin Interface With Microcontroller

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS92692 and TPS92692-Q1 controllers are suitable for implementing step-up or step-down LED driver

topologies including boost, buck-boost, SEPIC, and flyback. Use the following design procedure to select

component values for the TPS92692-Q1 device. This section presents a simplified discussion of the design

process for the boost and buck-boost converter. The expressions derived for the buck-boost topology can be

altered to select components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be easily

adapted for flyback and similar converter topologies.

D

R_CS

L

Q_DIM

VIN

LED +

C_IN

TPS92692-Q1

1

2

3

4

5

6

7

8

20

C_VCC

R_OV2

C_VREF

VIN

VCC

VREF

FLT

C_OUT

19

18

Q_M

GATE

IS

SS

C_SS

R_OV1

DM

C_DM

R_IS

RT

17

16

GND

LED Þ

R_T

COMP

IMON

R_SLP

SLOPE

C_COMP

15

14

13

12

11

OV

CSP

C_IMON

R_ADJ2

R_DIM2

D_DIM

CSN

R_ADJ1

9

IADJ

PDRV

RAMP

PAD

C_RAMP

R_DIM1

V_/Çw[

10

DIM/PWM

Figure 36. Boost LED Driver

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Application Information (continued)

LED Þ

C_OUT

R_CS

L

D

Q_DIM

VIN

LED +

C_IN

TPS92692-Q1

R_OV2

1

20

C_VCC

C_VREF

VIN

VCC

2

3

4

5

6

7

8

VREF

FLT

19

18

Q_M

GATE

IS

SS

C_SS

DM

R_OV1

R_IS

C_DM

17

16

RT

GND

R_T

COMP

IMON

R_SLP

SLOPE

C_COMP

15

14

13

12

11

OV

CSP

C_IMON

R_ADJ2

R_DIM2

D_DIM

CSN

R_ADJ1

9

PDRV

RAMP

PAD

IADJ

C_RAMP

R_DIM1

V_/Çw[

10

DIM/PWM

Figure 37. Buck-Boost LED Driver

L₁

C_C

R_DC

D

R_CS

Q_DIM

VIN

LED +

C_DC

C_IN

TPS92692-Q1

R_OV2

1

2

3

4

5

6

7

8

20

19

18

C_VREF

VIN

VCC

GATE

IS

C_OUT

VREF

FLT

C_VCC

L₂

Q_M

SS

C_SS

R_OV1

DM

C_DM

RT

R_IS

17

16

R_T

COMP

IMON

GND

LED Þ

R_SLP

C_COMP

SLOPE

15

14

13

12

11

C_IMON

OV

CSP

R_ADJ2

R_DIM2

D_DIM

R_ADJ1

9

CSN

IADJ

PDRV

RAMP

PAD

C_RAMP

R_DIM1

V_/Çw[

10

DIM/PWM

Figure 38. SEPIC LED Driver

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Application Information (continued)

9.1.1 Duty Cycle Considerations

The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In

steady state, the duty cycle is derived using expression:

Boost:

V_O- V

IN

D =

V_O

(9)

Buck-Boost:

V_O

D =

V

_IN+ V_O

(10)

The minimum duty cycle, D_MIN, and maximum duty cycle, D_MAX, are calculated by substituting maximum input

voltage, V_IN(MAX), and the minimum input voltage, V_IN(MIN), respectively in the previous expressions. The minimum

duty cycle achievable by the device is determined by the leading edge blanking period and the switching

frequency. The maximum duty cycle is limited by the internal oscillator to 90% (typ) to allow for minimum off-time.

It is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loop

LED current regulation over the specified input and output voltage range.

9.1.2 Inductor Selection

The choice of inductor sets the continuous conduction mode (CCM) and discontinuous conduction mode (DCM)

boundary condition. Therefore, one approach of selecting the inductor value is by deriving the relationship

between the output power corresponding to CCM-DCM boundary condition, P_O(BDRY)and inductance, L. This

approach ensures CCM operation in battery-powered LED driver applications that are required to support

different LED string configurations with a wide range of programmable LED current set points. The CCM-DCM

boundary condition can be estimated either based on the lowest LED current and the lowest output voltage

requirements for a given application or as a fraction of maximum output power, P_O(MAX)

.

P_O(BDRY)Ç I_LED(MIN)ì V_O(MIN)

(11)

(12)

P_O(MAX)

Ç P_O(BDRY)

Ç

4

2

Boost:

L =

V²

V

IN(MAX)

≈

’

IN(MAX)

ì ∆1-

÷

◊

∆

2ìP_O(BDRY)ì f_SW

V_O(MAX)

«

(13)

Buck-Boost:

1

L =

2

≈

’

1

2ìP_O(BDRY)ì f_SW

ì

+

∆

«

÷

◊

V_O(MAX)

V

IN(MAX)

(14)

Select inductor with saturation current rating greater than the peak inductor current, I_L(PK), at the maximum

operating temperature.

Boost:

≈

’

P_O(MAX)

V

IN(MIN)

i_L(PK)

=

+

ì∆1-

÷

◊

∆

V

2ìLì f_SWì V_O(MAX)

V_O(MAX)

IN(MIN)

«

(15)

Buck-Boost:

≈

’

V_O(MIN)ì V

1

IN(MIN)

I_L(PK)= P_O(MAX)ì∆

+

÷ +

∆

÷

V_O(MIN)

V

IN(MIN)

2ìL ì f_SWì V

+ V

(

)

O(MIN)

IN(MIN)

«

◊

(16)

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Application Information (continued)

9.1.3 Output Capacitor Selection

The output capacitors are required to attenuate the discontinuous or large ripple current generated by switching

and achieve the desired peak-to-peak LED current ripple, Δi_LED(PP). The capacitor value depends on the total

series resistance of the LED string, r_Dand the switching frequency, ƒ_SW.The capacitance required for the target

LED ripple current can be calculated based on following equations.

Boost:

≈

’

P_O(MAX)

V

IN(MIN)

C_OUT

Buck-Boost:

C_OUT

=

ì∆1-

÷

◊

∆

Di_LED(PP)ìr_D(MIN)ì f_SWì V_O(MAX)

V_O(MAX)

«

(17)

P_O(MAX)

=

Di_LED(PP)ìf_SWìr_D(MIN)ì V_O(MIN)+ V

(

)

IN(MIN)

(18)

When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they

directly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple

current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is

important to consider the derating factors associated with higher temperature and DC bias operating conditions.

TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An aluminum

electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. The

aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged operating

lifetime. The minimum allowable RMS output capacitor current rating, I_COUT(RMS), can be approximated:

Boost and Buck-Boost:

D_MAX

I_COUT(RMS)= I_LED

ì

1- D_MAX

(19)

9.1.4 Input Capacitor Selection

The input capacitors, C_IN, smooth the input voltage ripple and store energy to supply input current during input

voltage or PWM dimming transients. The series inductor in the Boost and SEPIC topologies provides continuous

input current and requires a smaller input capacitor to achieve desired input ripple voltage, Δv_IN(PP). The Buck-

Boost and Flyback topologies have discontinuous input current and require a larger capacitor to achieve the

same input voltage ripple. Based on the switching frequency, ƒ_SW, and the maximum duty cycle, D_MAX, the input

capacitor value can be calculated as follows:

Boost:

≈

’

V

IN(MIN)

C_IN

=

ì ∆1-

÷

◊

8ìL ì f_S²_Wì Dv_IN(PP)

∆

V_O(MAX)

«

(20)

Buck-Boost:

P_O(MAX)

C_IN

=

f_SWì Dv_IN(PP)ì V

+ V

IN(MIN)

(

)

O(MIN)

(21)

X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, and

good temperature performance. For applications using PWM dimming, TI recommends an aluminum electrolytic

capacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transients

generated in conjunction with the rising and falling edges of the LED current.

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Application Information (continued)

R_VIN

VIN

C_VIN

Figure 39. VIN Filter

Decouple VIN pin with a 0.1-µF ceramic capacitor, placed as close as possible to the device and a series 10-Ω

resistor to create a 150-kHz low-pass filter.

9.1.5 Main Power MOSFET Selection

The power MOSFET is required to sustain the maximum switch node voltage, V_SW, and switch RMS current

derived based on the converter topology. TI recommends a drain voltage V_DSrating of at least 10% greater than

the maximum switch node voltage to ensure safe operation. The MOSFET drain-to-source breakdown voltage,

V_DS, is calculated using the following expressions.

Boost:

V_DS= 1.1ì V_O(OV)

(22)

Buck-Boost:

V_DS= 1.1ì V_O(OV)+ V

(

)

IN(MAX)

(23)

The voltage, V_O(OV), is the overvoltage protection threshold and the worst-case output voltage under fault

conditions. The worst case MOSFET RMS current for Boost and Buck-Boost topology is dependent on maximum

output power, P_O(MAX), and is calculated as follows:

≈

’

P_O(MAX)

V

IN(MIN)

I_Q(RMS)

=

ì ∆1+

÷

◊

∆

V

V_O(MIN)

IN(MIN)

«

(24)

Select a MOSFET with low total gate charge, Q_g, to minimize gate drive and switching losses. The MOSFET R_DS

resistance is usually a less critical parameter because the switch conduction losses are not a significant part of

the total converter losses at high operating frequencies. The switching and conduction losses are calculated as

follows:

P_COND= R_DSìI_Q²_(RMS)

(25)

I_Lì V_S²_WìC_RSSì f_SW

P_SW

=

I_GATE

(26)

C_RSSis the MOSFET reverse transfer capacitance. I_Lis the average inductor current. I_GATEis gate drive output

current, typically 500 mA. The MOSFET power rating and package is selected based on the total calculated loss,

the ambient operating temperature, and maximum allowable temperature rise.

9.1.6 Rectifier Diode Selection

A Schottky diode (when used as a rectifier) provides the best efficiency due to its low forward voltage drop and

near-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, V_D(BR), greater than

or equal to MOSFET drain-to-source voltage, V_DS, for reliable performance. It is important to understand the

leakage current characteristics of the Schottky diode, especially at high operating temperatures because it

impacts the overall converter operation and efficiency.

Use Equation 27 to calculate the current through the diode, I_D.

I_D= I_LED(MAX)

(27)

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Application Information (continued)

The diode power rating and package is selected based on the calculated current, the ambient temperature and

the maximum allowable temperature rise.

9.1.7 LED Current Programming

The LED current is set by the external current sense resistor, R_CS, and the analog adjust voltage, V_IADJ. The

current sense resistor is placed in series with the LED load. The CSP and CSN inputs of the internal rail-to-rail

current sense amplifier are connected to the R_CSresistor to enable closed-loop regulation. When V_IADJ> 2.5 V,

the internal 2.4-V reference sets the V_(CSP-CSN)threshold to 170.7 mV and the LED current is regulated to:

170.7 mV

I_LED

=

R_CS

(28)

The LED current can be programmed by varying V_IADJbetween 140 mV to 2.25 V. The LED current can be

calculated using:

V

IADJ

I_LED

=

14ìR_CS

(29)

TI recommends a low-pass common-mode filter consisting of 10-Ω resistors in series with CSP and CSN inputs

and 0.01-µF capacitors to ground to minimize the impact of voltage ripple and noise on LED current accuracy

(see Figure 24 section). A 0.1-µF capacitor across CSP and CSN is included to filter high-frequency differential

noise.

9.1.8 Switch Current Sense Resistor

The switch current sense resistor, R_IS, is used to implement peak current mode control and to set the peak

switch current limit. The value of R_ISis selected to protect the main switching MOSFET under fault conditions.

The R_IScan be calculated based on peak inductor current, i_L(PK), and switch current limit threshold, V_IS(LIMIT)

.

V

IS(LIMIT)

R_IS

=

I_L(PK)

(30)

VCC

GATE

IS

100 ꢀ

R_IS

1 nF

GND

Figure 40. IS Input Filter

The use of a 1-nF and 100-Ω low-pass filter is optional. If used, the recommended resistor value is less than 500

Ω in order to limit its influence on the internal slope compensation signal.

9.1.9 Slope Compensation

The magnitude of internal artificial ramp, V_SL, is set by slope resistor R_SLP. The device compensates for the

changes in input voltage, V_INand output voltage sensed by CSP pin, V_CSPto achieve stable inner current loop

operation over wide range of operating conditions. The value of R_SLPis determined by the inductor, L and the

switch current sense resistor, R_ISand is independent of input and output voltage for Boost, Boost-to-Battery and

Buck-Boost topologies.

L

R_SL= 274.4ì10⁶ì

(W)

R_IS

(31)

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Application Information (continued)

9.1.10 Feedback Compensation

The open-loop response is the product of the modulator transfer function (shown in Equation 32) and the

feedback transfer function. Using a first-order approximation, the modulator transfer function can be modeled as

a single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zero

created by the inductor, where both have a dependence on the LED string dynamic resistance, r_D. The ESR of

the output capacitor is neglected in the analysis. The small-signal modulator model also includes a DC gain

factor that is dependent on the duty cycle, output voltage, and LED current.

≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

1-

1+

Ù

w_Z

i

LED

= G₀ì

Ù

v_COMP

s

w_P

(32)

The Table 2 summarizes the expression for the small-signal model parameters.

Table 2. Small-Signal Model Parameters

DC GAIN (G₀)

POLE FREQUENCY (ω_P)

ZERO FREQUENCY (ω_Z)

(1- D)ì V_O

V + r ìI

LED

(

)

V_Oì(1-D)²

L ìI_LED

O

D

Boost

R_ISì V + r ìI

(

)

(

)

V_Oìr_Dì C_OUT

O

D

LED

(1-D)ì V_O

V + Dìr ìI

(

)

V_Oì(1-D)²

DìL ìI_LED

O

D

LED

Buck-Boost

R_ISì V + Dìr ìI

(

)

(

)

V_Oìr_DìC_OUT

O

D

LED

The feedback transfer function includes the current sense resistor and the loop compensation of the

transconductance amplifier. A compensation network at the output of the error amplifier is used to configure loop

gain and phase characteristics. A simple capacitor, C_COMP, from COMP to GND (as shown in Figure 41) provides

integral compensation and creates a pole at the origin. Alternatively, a network of R_COMP, C_COMP, and C_HF, shown

in Figure 42, can be used to implement proportional and integral (PI) compensation to create a pole at the origin,

a low-frequency zero, and a high-frequency pole.

The feedback transfer function is defined as follows.

Feedback transfer function with integral compensation:

Ù

v_COMP14ì g_MìR_CS

-

=

Ù

sì C_COMP

i

LED

(33)

Feedback transfer function with proportional integral compensation:

Ù

1+ sìR_COMPìC_COMP

v_COMP

14ì g_MìR_CS

sì C + C_HF

(

)

-

=

Ù

≈

’

(

)

i

≈

∆

«

’

÷

◊

C_COMPìC_HF

C_COMP+ C_HF

COMP

LED

1+ sìR

ì

∆

÷

COMP

«

◊

(34)

The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator

by placing the low-frequency zero an order of magnitude less than the crossover frequency. Use the following

expressions to calculate the compensation network.

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COMP

R_COMP

C_HF

C_COMP

GAIN = 14

+

GAIN = 14

+

CSP

CSN

CSP

R_CS

CURRENT SENSE

AMPLIFIER

CSN

CURRENT SENSE

AMPLIFIER

I_LED

VCC

IADJ

VCC

IADJ

+

2.42V

Figure 41. Integral Compensator

Figure 42. Proportional Integral Compensator

Boost and Buck-Boost with integral compensator:

8.75ì10^-3ìR_CS

C_COMP

=

w_P

(35)

Boost and Buck-Boost with proportional integral compensator:

≈

∆

«

’

÷

◊

R_CSìG₀

C_COMP= 8.75ì10^-3ì

w_Z

(36)

(37)

C_COMP

C_HF

=

100

1

R_COMP

=

w_PìC_COMP

(38)

The loop response is verified by applying step input voltage transients. The goal is to minimize LED current

overshoot and undershoot with a damped response. Additional tuning of the compensation network may be

necessary to optimize PWM dimming performance.

9.1.11 Soft-Start

The soft-start time (t_SS) is the time required for the LED current to reach the target set point. The required soft-

start time is programmed using a capacitor, C_SS, from SS pin to GND, and is based on the LED current, output

capacitor, and output voltage.

C_SS= 12.5ì10^-6ì t_SS

(39)

9.1.12 Overvoltage and Undervoltage Protection

The overvoltage threshold is programmed using a resistor divider, R_OV2and R_OV1, from the output voltage, V_O, to

GND for Boost and SEPIC topologies, as shown in Figure 36 and Figure 38. If the LEDs are referenced to a

potential other than GND, as in the Buck-Boost, the output voltage is sensed and translated to ground by using a

PNP transistor and level-shift resistors, as shown in Figure 37. The overvoltage turn-off threshold, V_O(OV), is:

Boost:

≈

∆

«

’

÷

◊

R_OV1+ R_OV2

V_O(OV)= V_OVP(THR)

ì

R_OV1

(40)

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Buck and Buck-Boost:

R_OV2

R_OV1

V_O(OV)= V_OVP(THR)

ì

+ 0.7

(41)

(42)

The overvoltage hysteresis, V_OV(HYS)is:

V_OV(HYS)= I_OVP(HYS)ìR_OV2

The corresponding undervoltage fault threshold, V_O(UV)is:

R_OV1+ R_OV2

V_O(UV)= 0.1ì

R_OV1

(43)

9.1.13 Analog to PWM Dimming Considerations

The analog to PWM duty cycle translation is based on the internal PWM generator, configured by connecting a

capacitor across RAMP pin and GND, as shown in Figure 29. The minimum PWM duty cycle is programmed by

setting the voltage on DIM/PWM pin, V_DIMusing a resistor divider from VREF pin to GND.

V_DIM= 1+ 2ìD_DIM(MIN)

(44)

≈

∆

«

’

÷

◊

V_REF- V_DIM

R_DIM2

=

ìR

DIM1

V_DIM

(45)

The device is designed to support a minimum PWM duty cycle of 4% with better than 5% accuracy from

DIM/PWM input to PDRV output in this operating mode. To avoid excess loading of the VREF LDO output, TI

recommends a resistor network with sum of resistors R_DIM1and R_DIM2greater than 10 kΩ. A bypass capacitor of

0.1-µF prevents noise coupling and improves performs for low dimming values.

9.1.14 Direct PWM Dimming Considerations

The device can be configured to implement dimming function based on external PWM command by disabling the

internal ramp generator, as explained in DIM/PWM Input section. The internal comparator reference is set to 2.49

V by connecting a 249-kΩ resistor, R_RAMP, from the RAMP pin to GND. The internal PWM duty cycle is controlled

by an external 5-V or 3.3-V signal, generated by a command module or a microcontroller.

9.1.15 Series P-Channel MOSFET Selection

When PWM dimming, the device requires another P-channel MOSFET placed in series with the LED load. Select

a P-channel MOSFET with gate-to-source voltage rating of 10-V or higher and with a drain-to-source breakdown

voltage rating greater than the output voltage. Ensure that the drain current rating of the P-channel MOSFET

exceeds the programmed LED current by at least 10%.

It is important to consider the FET input capacitance and on-resistance as it impacts the accuracy and efficiency

of the LED driver. TI recommends a FET with lower input capacitance and gate charge to minimize the errors

caused by rise and fall times when PWM dimming at low duty cycles.

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9.2.1.1 Design Requirements

Table 3 shows the design parameters for the boost LED driver application.

Table 3. Design Parameters

PARAMETER

INPUT CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input voltage range

Input UVLO setting

7

14

18

V

4.5

OUTPUT CHARACTERISTICS

LED forward voltage

2.8

3.2

14

3.6

V

Number of LEDs in series

V_O

Output voltage

LED+ to LED–

39.2

44.8

350

4%

3

50.4

500

V

I_LED

RR

Output current

mA

LED current ripple ratio

LED string resistance

Maximum output power

PWM dimming frequency

r_D

Ω

W

Hz

%

P_O(MAX)

f_PWM

D_PWM

25

240

8

Analog to PWM duty cycle set point (low

brightness mode)

SYSTEMS CHARACTERISTICS

P_O(BDRY)

Output power at CCM-DCM boundary

6

W

condition

Δv_IN(PP)

V_O(OV)

V_OV(HYS)

t_ss

Input voltage ripple

20

62

3

mV

V

Output overvoltage protection threshold

Output overvoltage protection hysteresis

Soft-start period

V

8

ms

Hz

kHz

f_DM

Dither Modulation Frequency

Switching frequency

600

390

f_SW

9.2.1.2 Detailed Design Procedure

This procedure is for the boost LED driver application.

9.2.1.2.1 Calculating Duty Cycle

Solve for D, D_MAX, and D_MIN

:

V_O(TYP)- V

44.8 -14

44.8

IN(TYP)

D_MAX

D_MIN

=

= 0.688

= 0.861

= 0.541

V_O(TYP)

V_O(MAX)- V

(46)

50.4 - 7

50.4

IN(MIN)

=

V_O(MAX)

V_O(MIN)- V

(47)

(48)

39.2 -18

IN(MAX)

=

V_O(MIN)

39.2

9.2.1.2.2 Setting Switching Frequency

Solve for R_T:

1.432ì10¹⁰

R_T

=

= 20.05ì10³

1.047

)

1.047

390ì10³

f

(

SW

(

)

(49)

35

The closest standard resistor of 20 kΩ is selected.

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9.2.1.2.3 Setting Dither Modulation Frequency

Solve for C_DM

:

10ì10^-6

2ì f_MODì0.3 2ì 600 ì0.3

10 ì10^-6

C_DM

=

= 27.7ì10^-9

(50)

The closest standard capacitor is 27 nF.

9.2.1.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, P_O(BDRY). In most applications,

P_O(BDRY)is set to be 1/3 of the maximum output power, P_O(MAX). The inductor value is calculated for typical input

voltage, V_IN(TYP), and output voltage, V_O(TYP)

:

2

V²

V

IN(TYP)

≈

’

14

(

)

14

≈

’

IN(MAX)

L =

ì∆1-

÷ =

÷

ì 1-

= 21.59ì10^-6

∆

÷

◊

2ì8ì390ì10³

«

∆

2ìP_O(BDRY)ì f_SW

V_O(TYP)

44.8

«

◊

(51)

The closest standard inductor is 22 µH.

For best results, ensure that the inductor saturation current rating is greater than the peak inductor current, I_L(PK)

.

= 3.58

(52)

≈

’

P_O(MAX)

V

IN(MIN)

25

7

≈

’

IN(MIN)

i_L(PK)

=

+

ì∆1-

÷ =

÷

+

ì 1-

∆

÷

◊

2ì22ì10^-6ì390ì10³ì50.4

«

∆

V

2ìLì f_SWì V_O(MAX)

V_O(MAX)

50.4

IN(MIN)

«

◊

9.2.1.2.5 Output Capacitor Selection

The specified peak-to-peak LED current ripple, Δi_LED(PP), is:

Di_LED(PP)= RRìI_LED(MAX)= 0.03ì500ì10^-3= 15 ì10^-3

(53)

The output capacitance required to achieve the target LED current ripple is:

≈

’

P_O(MAX)

V

IN(MIN)

25

7

≈

’

C_OUT

=

ì∆1-

÷ =

÷

ì 1-

= 17.38ì10^-6

∆

÷

◊

15ì10^-3ì 4.2ì390ì10³ì50.4

«

∆

Di_LED(PP)ìr_D(MIN)ì f_SWì V_O(MAX)

V_O(MAX)

50.4

«

◊

(54)

Four 4.7-µF, 100-V rated X7R ceramic capacitors are used in parallel to achieve a combined output capacitance

of 18.8 µF.

9.2.1.2.6 Input Capacitor Selection

The input capacitor is required to reduce switching noise conducted through the input wires and reduced the

input impedance of the LED driver. The capacitor required to limit peak-to-peak input ripple voltage ripple,

Δv_IN(PP), to 20 mV is given by:

≈

’

V

IN(MIN)

7

≈

’

IN(MIN)

C

=

ì∆1-

÷ =

÷

ì 1-

= 11.26ì10^-6

IN

∆

÷

◊

8ìLìf_S²_Wì Dv_IN(PP)

8ì22ì10^-6ì390ì10³ì20ì10^-3

«

∆

V_O(MAX)

50.4

«

◊

(55)

Two 4.7-µF, 50-V X7R ceramic capacitors are used in parallel to achieve a combined input capacitance of 9.4-

µF.

9.2.1.2.7 Main N-Channel MOSFET Selection

Ensure that the MOSFET ratings exceed the maximum output voltage and RMS switch current.

V_DS= V_O(OV)ì1.1= 62ì1.1= 68.2

(56)

≈

’

P_O(MAX)

V

25

7

≈

’

I_Q(RMS)

=

ì ∆1+ ^IN(MIN)÷ =

ì

1+

= 3.88

∆

«

÷

◊

∆

÷

V

V_O(MIN)

39.2

IN(MIN)

«

◊

(57)

A N-channel MOSFET with a voltage rating of 100-V and a current rating of 4 A is required for this design.

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9.2.1.2.8 Rectifying Diode Selection

Select a diode should be selected based on the following voltage and current ratings:

V_D(BR)= V_O(OV)ì1.2 = 62ì1.1= 68.2

(58)

(59)

I_D= I_LED(MAX)= 0.5

A 100-V Schottky diode with low reverse leakage current is suitable for this design. The package must be able to

handle the power dissipation resulting from continuous forward current, I_D, of 0.5 A.

9.2.1.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, R_ADJ1and

R_ADJ2, from V_REFto GND for a given sense resistor, R_CS, as shown in Figure 43. To maximize the accuracy, the

IADJ pin voltage is set to 2.1 V for the specified maximum LED current of 500-mA. The current sense resistor,

R_CS, is then calculated as:

V

2.1

IADJ(MAX)

R_CS

=

= 0.3

14ìI_LED(MAX)14 ì0.5

(60)

A standard resistor of 0.3 Ω is selected. Table 4 summarizes the IADJ pin voltage and the choice of the R_ADJ1

and R_ADJ2resistors for different current settings.

Table 4. Design Requirements

LED CURRENT

100 mA

IADJ VOLTAGE (V_IADJ

)

R_ADJ1

R_ADJ2

420 mV

1.47 V

2.1 V

6.34 kΩ

29.4 kΩ

49.9 kΩ

68.1 kΩ

350 mA

500 mA

9.2.1.2.10 Setting Switch Current Limit

Solve for current sense resistor, R_IS:

V

0.25

3.58

IS(LIMIT)

R_IS

=

= 0.07

I_L(PK)

(61)

(62)

A standard value of 0.06 Ω is selected.

9.2.1.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, R_SL.

L

22ì10^-6

R_SL= 274.4ì10⁶ì

= 274.4ì10⁶ì

= 100.6ì10³

R_IS

0.06

A standard resistor of 100 kΩ is selected.

9.2.1.2.12 Deriving Compensator Parameters

The modulator transfer function for the Boost converter is derived for nominal V_INvoltage and corresponding duty

cycle, D, and is given by the following equation. (See Feedback Compensation section for more information.)

≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

≈

s

’

1-

1+

1-

∆

÷

311.8ì10³

Ù

w_Z

i

«

◊

LED

= G₀ì

= 2.184ì

Ù

v_COMP

≈

s

’

s

1+

∆

÷

13.4ì10³

w_P

«

◊

(63)

The proportional-integral compensator components C_COMPand R_COMPare obtained by solving the following

expressions:

≈

∆

«

’

÷

◊

R_CSìG₀

≈ 0.3ì 2.184 ’

C_COMP= 8.75ì10^-3ì

= 8.75ì10^-3ì

= 0.018ì10^-6

÷

∆

311.8ì10³

w_Z

«

◊

(64)

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1

R_COMP

=

= 4.12ì10³

13.4ì10³ì18ì10^-9

w_PìC_COMP

(65)

The closet standard capacitor of 18-nF and resistor of 4.12-kΩ is selected. The high frequency pole location is

set by a 1-nF C_HFcapacitor.

9.2.1.2.13 Setting Start-up Duration

The soft-start capacitor required to achieve start-up in 8 ms is given by:

C_SS= 12.5ì10^-6ì t_SS= 12.5ì10^-6ì8ì10^-3= 100ì10^-9

(66)

The closet standard capacitor of 100 nF is selected.

9.2.1.2.14 Setting Overvoltage Protection Threshold

The overvoltage protection threshold of 62 V and hysteresis of 3 V is set by the R_OV1and R_OV2resistor divider.

V_OV(HYS)

20ì10^-620ì10^-6

3

R_OV2

=

= 150ì10³

(67)

(68)

≈

’

1.228

62 -1.228

≈

’

R_OV1= ∆

÷ìR_OV2

=

ì150ì10³= 3.03ì10³

∆

«

÷

◊

∆

÷

V_O(OV)-1.228

«

◊

The standard resistor values of 150 kΩ and 3.01 kΩ are chosen.

9.2.1.2.15 Analog-to-PWM Dimming Considerations

The PWM dimming frequency is set by the C_RAMPcapacitor.

10ì10^-6

2ì 2ì f_DIM2ì 2ì240

10ì10^-6

C_DIM

=

= 10.4ì10^-9

(69)

The closet standard capacitor of 10 nF is selected.

The PWM duty cycle of 8% programmed by setting the DIM/PWM voltage using resistor divider, R_DIM1and

connected from VREF pin to GND.

RDIM2

V_DIM= 2ìD_PWM+1= 2ì0.08 +1= 1.16

(70)

The value of resistor, R_DIM1is set as of 10-kΩ. The resistor R_DIM2is calculated using the following equation:

V_REF- V_DIM

4.96 -1.16

R_DIM2

=

ìR_DIM1

=

ì10ì10³= 32.76ì10³

V_DIM

4.96

(71)

A standard resistor of 33 kΩ is selected.

A P-channel MOSFET with a voltage rating of 100-V and a current rating of 1 A is required to enable series FET

dimming for this design.

9.2.1.3 Application Curves

These curves are for the boost LED driver.

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Ch1: Switch node voltage;

Ch1: Dither modulation voltage;

Ch2: Switch current sense voltage;

Ch4: LED current; Time: 1 µs/div

Ch4: LED current; Time: 400 µs/div

Figure 45. Spread Spectrum Frequency Modulation

Figure 44. Normal Operation

Ch1: Input voltage; Ch2: Soft-start (SS) voltage;

Ch3: Input current;

Ch1: Dim/PWM voltage;

Ch2: RAMP pin voltage;

Ch4: LED current; Time: 4 ms/div

Figure 46. Startup Transient

Ch4: LED current; Time: 2 ms/div

Figure 47. Analog-to-PWM Dimming Transient

Ch1: External PWM input signal;

Ch2: PDRV voltage;

Ch4: LED current; Time: 2 ms/div

Figure 48. Direct PWM Dimming Transient

Ch1: External PWM input voltage;

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 4 µs/div

Figure 49. PWM Dimming Transient (Zoomed)

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Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 50. LED Open-Circuit Fault

Figure 51. LED Short-Circuit Fault

Figure 53. Conducted EMI Scan (SSFM Enabled)

Figure 52. Conducted EMI Scan (SSFM Disabled)

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9.2.2.1 Design Requirements

Buck-Boost LED drivers provide the flexibility needed in applications that support multiple LED load

configurations. For such applications, it is necessary to modify the design procedure presented in to account for

the wider range of output voltage and LED current specifications. This design is based on the maximum output

power P_O(MAX), set by the lumen output specified for the lighting application. The design procedure for a battery

connected application with 3 to 9 LEDs in series and maximum 15 W output power is outlined in this section.

Table 5. Design Parameters

PARAMETER

INPUT CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input voltage range

Input UVLO setting

7

14

18

V

4.5

OUTPUT CHARACTERISTICS

LED forward voltage

2.8

3

3.2

7

3.6

11

V

Number of LEDs in series

V_O

Output voltage

LED+ to LED–

8.4

100

22.4

500

5%

2.1

39.6

1500

V

I_LED

Output current

mA

Δi_LED(PP)

r_D

P_O(MAX)

D_PWM

LED current ripple

LED string resistance

Maximum output power

Direct PWM dimming range

0.9

4%

3.3

12.6

Ω

W

f_PWM= 240 Hz

100%

SYSTEMS CHARACTERISTICS

P_O(BDRY)

Output power at CCM-DCM boundary

3

W

condition

Δv_IN(PP)

V_O(OV)

V_OV(HYS)

t_SS

Input voltage ripple

70

45

3

mV

V

Output overvoltage protection threshold

Output overvoltage protection hysteresis

Soft-start period

V

8

ms

kHz

f_SW

Switching frequency

390

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Calculating Duty Cycle

Solving for D, D_MAX, and D_MIN

:

V_O(TYP)

22.4

D =

=

= 0.615

V_O(TYP)+ V

22.4 +14

IN(TYP)

(72)

V_O(MAX)

39.6

D_MAX

=

= 0.850

= 0.318

V_O(MAX)+ V

39.6 + 7

IN(MIN)

(73)

(74)

V_O(MIN)

8.4

D_MIN

=

V_O(MIN)+ V

8.4 +18

IN(MAX)

9.2.2.2.2 Setting Switching Frequency

Solving for R_Tresistor:

1.432ì10¹⁰

R_T

=

= 20.05ì10³

1.047

390ì10³

f

(

)

SW

(

)

(75)

9.2.2.2.3 Setting Dither Modulation Frequency

Solve for C_DM

:

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10ì10^-6

2ì f_MODì0.3 2ì 600 ì0.3

10 ì10^-6

C_DM

=

= 27.7ì10^-9

(76)

The closest standard capacitor is 27 nF.

9.2.2.2.4 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, P_O(BDRY). Typically, the boundary

condition is set to enable CCM operation at the lowest possible operating power based on minimum LED forward

voltage drop and LED current. In most applications, P_O(BDRY)is set to be 1/3 of the maximum output power,

P_O(MAX). The inductor value is calculated for maximum input voltage, V_IN(MAX), and output voltage, V_O(MAX)

:

1

L =

=

= 31.72ì10^-6

2

1

≈

’

≈

’

2ì3ì390ì10³ì

+

1

2ìP_O(BDRY)ì f_SW

ì

+

∆

«

÷

◊

∆

«

÷

◊

22.4 14

V_O(TYP)

V

IN(TYP)

(77)

(78)

The closest standard value of 33 µH is selected. The inductor ripple current is given by:

V_IN(MIN)ìD_MAX

7ì0.85

Di_L(PP)

=

= 0.4623

33ì10^-6ì390ì10³

L ì f_SW

Ensure that the inductor saturation rating exceeds the calculated peak current which is based on the maximum

output power using Equation 79.

≈

’

V_O(MIN)ì V

1

IN(MIN)

I_L(PK)= P_O(MAX)ì∆

+

÷ +

÷

∆

V_O(MIN)

V

IN(MIN)

2ìL ì f_SWì V

+ V

(

)

O(MIN)

IN(MIN)

«

◊

(79)

1

7

8.4ì7

≈

’

I_L(PK)= 12.6ì

+

= 3.45

∆

«

÷

◊

2ì33ì10^-6ì390ì10³ì 8.4 + 7

8.4

(

)

9.2.2.2.5 Output Capacitor Selection

Select the output capacitance to achieve the 5% peak-to-peak LED current ripple specification. Based on the

maximum power, the capacitor is calculated in Equation 80.

P_O(MAX)

C_OUT

=

f_SWìr_D(MIN)ì Di_LED(PP)ì V_O(MIN)+ V

(

)

IN(MIN)

(80)

12.6

C_OUT

=

= 31.08ì10^-6

390ì10³ì0.9ì0.075ì 8.4 + 7

(

)

This design requires a minimum of three, 10-µF, 50-V and one 4.7-µF, 100-V, X7R ceramic capacitors in parallel

to meet the LED current ripple specification over the entire range of output power. Additional capacitance may be

required based on the derating factor under DC bias operation.

9.2.2.2.6 Input Capacitor Selection

The input capacitor is calculated based on the peak-to-peak input ripple specifications, Δv_IN(PP). The capacitor

required to limit the ripple to 70 mV over range of operation is calculated using:

P_O(MAX)

12.6

C_IN

=

= 29.97ì10^-6

f_SWì Dv_IN(PP)ì V_O(MIN)+ V

390ì10³ì0.07ì 8.4 + 7

(

)

(

)

IN(MIN)

(81)

A parallel combination of four 10-µF, 50-V X7R ceramic capacitors are used for a combined capacitance of 40

µF. Additional capacitance may be required based on the derating factor under DC bias operation.

9.2.2.2.7 Main N-Channel MOSFET Selection

Calculating the minimum transistor voltage and current rating:

V_DS= 1.1ì V

+ V

= 1.1ì(45 +18) = 69.3

(

)

O(OV)

IN(MAX)

(82)

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≈

’

P_O(MAX)

V

IN(MIN)

12.6

7

≈

’

I_Q(RMS)

=

ì ∆1+

÷ =

÷

ì

1+

= 2.44

∆

«

÷

◊

∆

V

V_O(MIN)

8.4

IN(MIN)

«

◊

(83)

This application requires a 100-V N-channel MOSFET with a current rating exceeding 3 A.

9.2.2.2.8 Rectifier Diode Selection

Calculating the minimum Schottky diode voltage and current rating:

V_D(BR)= 1.1ì V_O(OV)+ V

= 1.1ì(45 +18) = 69.3

(

)

IN(MAX)

(84)

(85)

I_D= I_LED(MAX)= 1.5

This application requires a 100-V Schottky diode with a current rating exceeding 1.5 A. TI recommends a single

high-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation over

temperature.

9.2.2.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, R_ADJ1and

R_ADJ2, from V_REFto GND for a given sense resistor, R_CS, as shown in Figure 54. To maximize the accuracy, the

IADJ pin voltage is set to 2.1 V for the specified LED current of 1.5 A. The current sense resistor, R_CS, is then

calculated as:

V

2.1

14ìI_LED(MAX)14ì1.5

IADJ

R_CS

=

= 0.1

(86)

A standard resistor of 0.1 Ω is selected. Table 5 summarizes the IADJ pin voltage and the choice of the R_ADJ1

and R_ADJ2resistors for different current settings.

Table 6. Design Requirements

LED CURRENT

100 mA

IADJ VOLTAGE (V_IADJ

)

R_ADJ1

2.0 kΩ

11.2 kΩ

50 kΩ

R_ADJ2

140 mV

68.1 kΩ

500 mA

700 mV

1.5 A

2.1 V

9.2.2.2.10 Setting Switch Current Limit and Slope Compensation

Solving for R_IS:

V

0.25

3.45

IS(LIMIT)

R_IS

=

= 0.072

I_L(PK)

(87)

(88)

A standard resistor of 0.06 Ω is selected.

9.2.2.2.11 Programming Slope Compensation

The artificial slope is programmed by resistor, R_SL.

L

33ì10^-6

R_SL= 274.4ì10⁶ì

= 274.4ì10⁶ì

= 150.7ì10³

R_IS

0.06

A standard resistor of 150 kΩ is selected.

9.2.2.2.12 Deriving Compensator Parameters

A simple integral compensator provides a good starting point to achieve stable operation across the wide

operating range. The modulator transfer function with the lowest frequency pole location is calculated based on

maximum output voltage, V_O(MAX), duty cycle, D_MAX, LED dynamic resistance, r_D(MAX), and minimum LED string

current, I_LED(MIN). (See Table 2 for more information.)

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≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

≈

s

’

1-

1+

1-

∆

«

÷

◊

145.7ì10³

Ù

w_Z

i

LED

= G₀ì

= 2.48ì

Ù

v_COMP

≈

s

’

s

1+

∆

÷

8.9ì10³

w_P

«

◊

(89)

(90)

The compensation capacitor needed to achieve stable response is:

8.75ì10^-3ìR_CS

8.75ì10^-3ì0.1

8.9ì10³

C_COMP

=

= 98.3ì10^-9

w_P

A 100 nF capacitor is selected.

A proportional integral compensator can be used to achieve higher bandwidth and improved transient

performance. However, it is necessary to experimentally tune the compensator parameters over the entire

operating range to ensure stable operation.

9.2.2.2.13 Setting Startup Duration

Solving for soft-start capacitor, C_SS, based on 8-ms startup duration:

C_SS= 12.5ì10^-6ì t_SS= 12.5ì10^-6ì8ì10^-3= 100ì10^-9

(91)

A 100-nF soft-start capacitor is selected.

9.2.2.2.14 Setting Overvoltage Protection Threshold

Solving for resistors, R_OV1and R_OV2

:

V_OV(HYS)

20ì10^-620ì10^-6

3

R_OV2

=

= 150ì10³

(92)

(93)

1.228ì150ì10³

45 - 0.7

1.228ìR_OV2

V_O(OV)- 0.7

R_OV1

=

= 4.16ì10³

The closest standard values of 150 kΩ and 4.12 kΩ along with a 60-V PNP transistor are used to set the OVP

threshold to 45 V with 3 V of hysteresis.

9.2.2.2.15 Direct PWM Dimming Consideration

A 60-V, 2-A P-channel FET is used to achieve series FET PWM dimming.

9.2.2.3 Application Curves

These curves are for the buck-boost LED driver.

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1600

1400

1200

1000

800

600

400

200

0

100

90

80

70

60

50

40

3 LEDs

5 LEDs

7 LEDs

9 LEDs

3 LEDs

2.2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

100

200

300 400 500 700 1000

LED Current (mA)

2000

V_IADJ(V)

D021

D022

V_IN= 14 V

Figure 55. LED Current vs IADJ Voltage

Figure 56. Efficiency

Ch1: FLT output;

Ch2: CSP pin voltage;

Ch4: LED current; Time: 100 ms/div

Figure 58. LED Short-Circuit Fault

Figure 57. LED Open-Circuit Fault

10 Power Supply Recommendations

This device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input could

be a car battery or another preregulated power supply. If the input supply is located more than a few inches from

the TPS92692 or TPS92692-Q1 device, additional bulk capacitance or an input filter may be required in addition

to the ceramic bypass capacitors to address noise and EMI concerns.

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11 Layout

11.1 Layout Guidelines

•

The performance of the switching regulator depends as much on the layout of the PCB as the component

selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI

within the circuit.

•

Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths.

The main path for discontinuous current in the devices using a buck regulator topology contains the input

capacitor, C_IN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, R_IS. In the

TPS92692 and TPS92692-Q1 devices using a boost regulator topology, the discontinuous current flows

through the output capacitor C_OUT, diode, D, N-channel MOSFET, Q1, and the current sense resistor, R_IS. In

devices using a buck-boost regulator topolog. Be careful when laying out both discontinuous loops. Ensure

that these loops are as small as possible. In order to minimize parasitic inductance, ensure that the

connection between all the components are short and thick. In particular, make the switch node (where L, D,

and Q1 connect) just large enough to connect the components. To minimize excessive heating, large copper

pours can be placed adjacent to the short current path of the switch node.

•

Route the CSP and CSN together with Kelvin connections to the current sense resistor with traces as short

as possible. If needed, use common mode and differential mode noise filters to attenuate switching and diode

reverse recovery noise from affecting the internal current sense amplifier.

•

Because the COMP, IS, OV, DIM/PWM, and IADJ pins are all high-impedance inputs that couple external

noise easily, ensure that the loops containing these nodes are minimized whenever possible.

In some applications, the LED or LED array can be far away from the TPS92692 and TPS92692-Q1 devices,

or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is

large or separated from the rest of the regulator, place the output capacitor close to the LEDs to reduce the

effects of parasitic inductance on the AC impedance of the capacitor.

•

The TPS92692 and TPS92692-Q1 devices have an exposed thermal pad to aid power dissipation. Adding

several vias under the exposed pad helps conduct heat away from the device. The junction-to-ambient

thermal resistance varies with application. The most significant variables are the area of copper in the PCB

and the number of vias under the exposed pad. The integrity of the solder connection from the device

exposed pad to the PCB is critical. Excessive voids greatly decrease the thermal dissipation capacity.

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11.2 Layout Example

VIA TO BOTTOM GROUND PLANE

VIN

LED+

GND

VCC

GATE

IS

VIN

VREF

FLT

GND

SLOPE

OVP

SS

DM

RT

CSP

COMP

IMON

IADJ

DIM

CSN

PDRV

RAMP

Figure 59. Layout Recommendation

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12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 7. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TPS92692

Click here

TPS92692-Q1

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS92692QPWPTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有扩频频率调制功能和内部 PWM 发生器的高精度 LED 控制器 \| PWP \| 20 \| -40 to 125 驱动控制器光电二极管接口集成电路
文件：	总57页 (文件大小：1986K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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