TPSM41615 [TI]

4V 至 16V、15A 可堆叠电源模块;


型号：	TPSM41615
厂家：	TEXAS INSTRUMENTS
描述：	4V 至 16V、15A 可堆叠电源模块电源电路
文件：	总34页 (文件大小：2462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM41615

ZHCSLX4A – OCTOBER 2020 – REVISED DECEMBER 2020

TPSM41615

www.ti.com.cn

具有均流功能的 TPSM41615 4V 至 16V 输入、15A 直流/直流电源模块

1 特性

3 说明

•

集成电感器电源解决方案

TPSM41615 电源模块是一款易于使用的集成式电源，

它在紧凑的 QFN 封装内整合了一个带有功率

MOSFET 的直流/直流转换器、一个屏蔽式电感器和多

个无源器件。该电源解决方案需要的外部组件很少，同

时仍能够调整关键参数以满足特定的设计要求。需要更

大电流的应用可通过并联两个 TPSM41615 器件而受

益。

• 11mm × 16mm × 4.2mm QFN 封装

– 所有引脚均分布在封装外围

•

输入电压范围：4V 至 16V

宽输出电压范围：0.6V 至 7.1V

可选内部基准（精度为 ±0.5%）

最多可堆叠两个器件

具有出色封装布局的 11mm × 16mm × 4.2mm、69 引

脚 QFN 封装具有优异的功率耗散能力，可提高热性

能。该封装的所有信号引脚均分布在外围，器件底部具

有大散热垫。TPSM41615 通过电源正常状态信号、时

钟同步、可编程 UVLO、软启动时序选择、预偏置启动

以及过流和过热保护等众多功能提供灵活性，从而成为

向各种器件和系统供电的出色产品。

– 并行输出，可获得更高的电流

– 相位交错，可降低纹波

效率高达 97%

•

可调节固定开关频率

（300kHz 至 1MHz）

支持与外部时钟同步

高级电流模式可提供

超快负载阶跃响应

•

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPSM41615

•

电源正常状态输出

QFN (69)

11mm × 16mm

符合 EN55011 辐射 EMI 限值

工作环境温度范围：-40°C 至 +105°C

• IC 工作结温范围：–40°C 至 +125°C

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

•

与以下器件引脚兼容：25A TPSM41625

使用 TPSM41615 并借助 WEBENCH^®Power

Designer 创建定制设计方案

空白

•

2 应用

•

电信和无线基础设施

工业自动化测试设备

企业交换和存储应用

高密度分布式电源系统

100

V_OUT, f_SW

5V_IN, 3.3V_OUT

5V_IN, 1.8V_OUT

5V_IN, 1.2V_OUT

12V_IN, 5V_OUT

12V_IN, 3.3V_OUT

12V_IN, 1.8V_OUT

6 9

Output Current (A)

典型效率

简化原理图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

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www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

Product Folder Links: TPSM41615

English Data Sheet: SLVSEX5

TPSM41615

ZHCSLX4A – OCTOBER 2020 – REVISED DECEMBER 2020

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Table of Contents

7.4 Device Functional Modes..........................................20

8 Application and Implementation..................................21

8.1 Application Information............................................. 21

8.2 Typical Application.................................................... 21

9 Power Supply Recommendations................................23

10 Layout...........................................................................24

10.1 Layout Guidelines................................................... 24

10.2 Layout Examples.................................................... 24

11 Device and Documentation Support..........................26

11.1 Device Support........................................................26

11.2 Receiving Notification of Documentation Updates..26

11.3 Support Resources................................................. 26

11.4 Trademarks............................................................. 26

11.5 Electrostatic Discharge Caution..............................26

11.6 Glossary..................................................................26

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics ............................................7

6.6 Typical Characteristics (PV_IN= 12 V)..........................9

6.7 Typical Characteristics (PV_IN= 5 V)..........................10

7 Detailed Description......................................................11

7.1 Overview................................................................... 11

7.2 Functional Block Diagram......................................... 11

7.3 Feature Description...................................................12

Information.................................................................... 27

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (October 2020) to Revision A (December 2020)

Page

•

将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

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5 Pin Configuration and Functions

PGND

VOUT

66 65 64 63 62 61 60 59

58 57 56

VOUT

PGND

PVIN

PGND

VOUT

PVIN

PGND

VIN

DNC

PGND

AGND

ILIM

DNC

PGND

RS-

BP5

RS+

23 24 25 26 27 28 29 30

31 32 33

BP5

PGND

图 5-1. 69-Pin QFN MOV Package (Top View)

表 5-1. Pin Functions

TYPE

DESCRIPTION

(1)

NAME

NO.

Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to

PGND; the connection is made internal to the device.

AGND

Output of an internal 5-V regulator used for the controller driver stage within the module. This output

can be used to connect a pullup resistor to the PGOOD pin. Leave these pins open if not used as a

pullup for PGOOD.

BP5

21, 22

38, 40

Do Not Connect. Do not connect these pins to AGND, PGND, another DNC pin, or any other

voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

DNC

–

Enable pin. This pin turns the converter on when floated or opened. This pin is internally pulled up to

the BP5 voltage when left open. The converter can be turned off by either driving it directly with a

logic input or an open drain/collector device to connect this pin to AGND. An external voltage divider

can be placed between this pin, AGND, and PVIN/VIN to create an external UVLO.

Current limit setting pin. This pin sets the current limit threshold of the converter. Leave this pin open

for the full current limit threshold. The current limit threshold can be lowered by connecting an

appropriate resistor from this pin to AGND.

ILIM

Current sharing pin. This pin is interconnected between modules for multi-phase configurations.

Leave this pin open for single-phase configurations.

ISHARE

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表 5-1. Pin Functions (continued)

TYPE

DESCRIPTION

(1)

NAME

NO.

Mode select pin. This pin is used to configure the module for single-phase or multi-phase operation.

For single-phase operation, this pin is used to select the API and Body Brake functions. For multi-

phase operation, this pin selects the primary/secondary and SYNC configurations.

MODE

Not connected. These pins are not connected to any circuitry within the module. It is recommended

that these pins be connected to the PGND plane on the application board to enhance shielding and

thermal performance.

39, 41,

45-52

–

8-11, 17,

18, 34, 37,

53-58, 68

This is the return path for the power stage of the device. Connect these pins to the input supply

return, load return, and bypass capacitors associated with the PVIN and VOUT pins.

PGND

Power Good pin. Open-drain output that asserts low if the remote sense feedback voltage is not

within the specified PGOOD thresholds. When using this signal as an output, a pullup resistor is

required. If unused, leave this pin open. The BP5 output can be used as the pullup voltage source.

PGOOD

PVIN

Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins

to the input supply. Connect bypass capacitors between these pins and PGND, close to the module.

12-15, 67

Internal ramp selection. This pin is used to select an internal ramp amplitude. See 表 7-3 for

recommended settings. An internal 78.7-kΩ resistor is connected between RAMP and RAMP_SEL

within the module. To select the internal resistor, it is recommended to leave this pin open and to

connect the RAMP_SEL pin to AGND.

RAMP

Internal default ramp selection. This pin is used to select the internal default ramp selection for the

control loop. An internal 78.7-kΩ resistor is connected between RAMP and RAMP_SEL pins.

Connect the RAMP_SEL pin to AGND and leave the RAMP pin open to select the internal resistor.

RAMP_SEL

Positive input to the internal differential remote sense amplifier. This pin is used for the feedback

connection to VOUT. Connect this pin to the output voltage at the load. This connection can be

made using a direct connection or an external upper feedback resistor, depending on the magnitude

of VOUT and the VSEL selection. A 1-kΩ lower feedback resistor is connected across RS+ and

RS– internal to the module. The RS+ connection is not needed for secondary devices in multi-

phase configurations, and should be left open.

RS+

Negative input to the internal differential remote sense amplifier. This pin is used for the feedback

connection to VOUT return. Connect this pin to the output voltage return at the load. A 1-kΩ lower

feedback resistor is connected across RS+ and RS– internal to the module. The RS- connection is

not needed for secondary devices in multi-phase configurations, and should be left open.

RS–

Switching frequency setting pin. This analog pin is used to set the switching frequency of the

converter by placing an external resistor from this pin to AGND. This pin also selects the phase

interleaving of the module when used in multi-phase configurations.

Soft-start selection pin. This pin is used to select the soft-start time. Ten possible selections are

available by connecting an appropriate resistor from this pin to AGND. The selections range from 0.5

ms to 32 ms.

Switch node. These pins are connected to the internal output inductor and switching MOSFETs.

Connect these pins together using a small copper island beneath the device. Keep this copper

island to a minimum to prevent issues with noise and EMI.

42-44

Frequency synchronization pin. MODE can be used to configure this pin as a sync input or a sync

output for external clock and multi-phase primary/secondary configurations.

SYNC

Input bias voltage. Supplies the control circuitry of the power converter. Connect a 1-µF bypass

capacitor from this pin to PGND (pins 17 and 18) in close proximity to the module. For split rail

applications, connect this pin to an input bias supply. For strapped rail applications, connect this pin

to PVIN through a 0 Ω to 10 Ω resistor.

VIN

Output voltage. These pins are connected to the internal output inductor. Connect these pins to the

output load and connect external bypass capacitors between these pins and PGND in close

proximity to the module.

1-7, 59-66,

VOUT

Internal reference voltage selection. This pin is used to select the desired internal reference voltage.

Ten possible selections are available by connecting an appropriate resistor from this pin to AGND.

The selections range from 0.6 V to 1.1 V.

VSEL

Voltage sharing pin. This pin is interconnected between modules for multi-phase configurations.

Leave this pin open for single-phase configurations.

VSHARE

(1) G = Ground, I = Input, O = Output, – = Not Connected

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

–5

MAX UNIT

PVIN

PVIN to SW

<10 ns

VIN

–0.3

–5.0

–0.3

VSEL, SS, MODE, RT, SYNC, EN, ISHARE, ILIM

Input voltage

RS+

3.6

0.3

RS-

AGND, PGND

<10 ns

VOUT

Output voltage

BP5, PGOOD, RAMP

VSHARE

3.6

500

Mechanical shock

Mil-STD-883H, Method 2002.5, 1 msec, 1/2 sine, mounted

°C

Mechanical vibration

Mil-STD-883H, Method 2007.3, 20 to 2000 Hz

(2)

Operating IC junction temperature, T_J

125

105

150

–40

(2)

Operating ambient temperature, T_A

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating

area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the

module is never exceeded.

6.2 ESD Ratings

VALUE

500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾

1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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MAX UNIT

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

PV_IN, V_IN

5.5

1.7

0.1

7.1

5.5

3.3

VSEL, SS, MODE, RT, SYNC, EN, ISHARE, ILIM

–0.1

0.6

RS+

Input voltage

RS-

AGND, PGND

V_OUT

BP5, PGOOD, RAMP

VSHARE

Output voltage

Output current

–0.3

I_OUT

Operating IC junction temperature, T_J

Operating ambient temperature, T_A

125

105

°C

–40

6.4 Thermal Information

TPSM41625

THERMAL METRIC ⁽¹⁾

MOV (QFN)

69 PINS

13.8

UNIT

R_θJA

ψ_JT

Junction-to-ambient thermal resistance ⁽²⁾

Junction-to-top characterization parameter ⁽³⁾

Junction-to-board characterization parameter ⁽⁴⁾

Thermal Shutdown Temperature

°C/W

°C

4.4

9.8

ψ_JB

165

T_SHDN

Thermal Shutdown Hysteresis

°C

(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The junction-to-ambient thermal resistance, R_θJA, applies to devices soldered directly to a 90 mm × 90 mm, 6-layer PCB with 2 oz.

copper and natural convection cooling. Additional airflow reduces R_θJA

(3) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT× Pdis + T_T; where Pdis is the power dissipated in the device and T_Tis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB× Pdis + T_B; where Pdis is the power dissipated in the device and T_B

is the temperature of the board 1mm from the device.

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6.5 Electrical Characteristics

Limits apply over T_A= –40°C to +105°C, PV_IN= 12 V, V_IN= 12 V, V_OUT= 1.8 V, V_REF= 1.0 V, F_SW= 500 kHz, IOUT = 25 A,

(unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values

represent the most likely parametric norm and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY

PV_IN

V_IN

Input switching voltage

Input bias voltage

PV_INincreasing, I_OUT= 0 A

3.2

3.0

3.8

3.6

PV_INundervoltage lockout

V_INundervoltage lockout

PV_INdecreasing, I_OUT= 2.5 A

V_INincreasing, I_OUT= 0 A

V_INdecreasing, I_OUT= 2.5 A

UVLO

V_RS+= 1.2 V, I_OUT= 0 A, EN = OPEN, T_A=

25°C

I_VIN

V_INbias current⁽¹⁾

4.3

I_VIN-STBY

V_INstandby current

I_OUT= 0 A, EN = 0 V, T_A= 25°C

OUTPUT VOLTAGE

RS+ connected directly to V_OUT

0.6

1.1

Output voltage adjust

RS+ connected to V_OUTfeedback divider

7.1^{(1) (2)}

0.6V ≤ V_REF≤ 1.1V, V_RS+= V_OUT,I_OUT

0A, -40°C ≤ T_J= T_A≤ 125°C⁽¹⁾

V_OUTaccuracy

-1.0

1.0

15⁽²⁾

5.5

V_OUT

Over PV_INrange, PV_IN= V_IN, I_OUT= 0 A,

T_A= 25°C

Line regulation

Load regulation

0.01

0.03

Over I_OUTrange, T_A= 25°C

OUTPUT CURRENT

Output current

Natural convection, T_A= 25°C

I_OUT

Overcurrent threshold

±3

_OUT≤ 20 A/phase

_OUT≥ 20 A/phase

Current sharing for multi-phase

operation⁽¹⁾

I_SHARE

±15%

BP5 REGULATOR

V_BP5BP5 regulator output voltage

4.5

V_BP5-DROPOUTBP5 regulator dropout voltage⁽¹⁾V_IN= 4.5 V, f_SW= 750 kHz, T_A= 25°C

365 mV

PERFORMANCE

Efficiency

I_OUT= 10 A

RS+

Lower feedback resistor

from RS+ to RS-

R_RS+-RS-

0.995

1.005

kΩ

ENABLE

V_EN-H

EN rising threshold

I_OUT= 0 A

1.45

1.6

1.3

1.75

V_EN-L

EN falling threshold

EN input leakage current

I_OUT= 2.5 A

I_{EN_LKG}

SOFT START

t_SS

V_IN= 4.5 V, I_OUT= 0 A

µA

–1

Soft-start time⁽¹⁾

Soft-start range⁽¹⁾

SS = OPEN

t_SS-Range

Programmable using SS pin

0.5

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Limits apply over T_A= –40°C to +105°C, PV_IN= 12 V, V_IN= 12 V, V_OUT= 1.8 V, V_REF= 1.0 V, F_SW= 500 kHz, IOUT = 25 A,

(unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values

represent the most likely parametric norm and are provided for reference only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PGOOD

V_RS+rising (fault)

112%

105%

95%

V_RS+falling (good)

V_RS+rising (good)

V_RS+falling (fault)

V_PGOOD

PGOOD thresholds⁽¹⁾

88%

PGOOD low voltage with no

supply voltage

V_PGOOD-LOW

0.8

PV_IN= V_IN= 0 V, I_PGOOD= 80 μA

I_PGOOD-LKG

PGOOD leakage current

V_IN= 4.5 V, V_PGOOD= 5 V, I_OUT= 0 A

µA

OVP / UVP

Overvoltage protection

threshold⁽¹⁾

V_OVP

V_UVP

V_RS+rising

V_RS+falling

117%

83%

Under-voltage protection

threshold⁽¹⁾

FREQUENCY and SYNC

Switching frequency

450

300

500

550 kHz

VSEL = OPEN, RT = 44.2 kΩ, I_OUT= 2.5 A

f_SW

Switching frequency range⁽¹⁾

Minimum on-time of SW⁽¹⁾

Minimum off-time of SW⁽¹⁾

Logic-high for SYNC⁽¹⁾

I_OUT= 2.5 A

1000 kHz

ton_min

toff_min

V_CLK-H

340

V_CLK-L

Logic-low for SYNC⁽¹⁾

0.8

T_CLK-MIN

Minimum pulse width for SYNC⁽¹⁾SYNC F_SW= 500 kHz

100

(1) Ensured by design, not production tested.

(2) To determine IOUT range for a given set of conditions, see the Safe Operating Area graphs in "Typical Characteristics" section of the

datasheet for more information.

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6.6 Typical Characteristics (PV_IN= 12 V)

T_A= 25°C, unless otherwise noted.

100

V_OUT, f_SW

7.0V, 700kHz

5.0V, 700kHz

3.3V, 600kHz

1.8V, 500kHz

1.2V, 400kHz

0.6V, 400kHz

V_OUT, f_SW

7.0V, 700kHz

5.0V, 700kHz

3.3V, 600kHz

1.8V, 500kHz

1.2V, 400kHz

0.6V, 400kHz

6 9

Output Current (A)

6 9

Output Current (A)

图 6-2. Power Dissipation vs Output Current

图 6-1. Efficiency vs Output Current

115

105

V_OUT, f_SW

3.3V, 500kHz

1.8V, 500kHz

1.2V, 500kHz

1.0V, 500kHz

0.8V, 400kHz

0.6V, 400kHz

Airflow

400LFM

200LFM

100LFM

Nat conv

6 9

Output Current (A)

6 9

Output Current (A)

C_OUT= C_OUTmin

V_OUT= 1.8 V

f_SW= 500 kHz

图 6-3. Output Voltage Ripple

图 6-4. Safe Operating Area

115

105

115

105

Airflow

400LFM

200LFM

100LFM

Nat conv

400LFM

200LFM

100LFM

Nat conv

Output Current (A)

V_OUT= 3.3 V

f_SW= 600 kHz

V_OUT= 5 V

f_SW= 700 kHz

图 6-5. Safe Operating Area

图 6-6. Safe Operating Area

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6.7 Typical Characteristics (PV_IN= 5 V)

T_A= 25°C, unless otherwise noted.

100

V_OUT, f_SW

3.3V, 500kHz

1.8V, 500kHz

1.2V, 500kHz

1.0V, 500kHz

0.8V, 400kHz

0.6V, 400kHz

V_OUT, f_SW

3.3V, 500kHz

1.8V, 500kHz

1.2V, 500kHz

1.0V, 500kHz

0.8V, 400kHz

0.6V, 400kHz

6 9

Output Current (A)

6 9

Output Current (A)

图 6-8. Power Dissipation vs Output Current

图 6-7. Efficiency vs Output Current

115

105

V_OUT, f_SW

3.3V, 500kHz

1.8V, 500kHz

1.2V, 500kHz

1.0V, 500kHz

0.8V, 400kHz

0.6V, 400kHz

Airflow

100LFM

Nat conv

6 9

Output Current (A)

6 9

Output Current (A)

C_OUT= C_OUTmin

V_OUT= 1 V

f_SW= 500 kHz

图 6-9. Output Voltage Ripple

图 6-10. Safe Operating Area

115

105

115

105

Airflow

100LFM

Nat conv

200LFM

100LFM

Nat conv

Output Current (A)

V_OUT= 1.8 V

f_SW= 500 kHz

V_OUT= 3.3 V

f_SW= 500 kHz

图 6-11. Safe Operating Area

图 6-12. Safe Operating Area

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7 Detailed Description

7.1 Overview

The TPSM41615 is a full-featured, 4-V to 16-V input, 15-A, synchronous step-down converter with PWM,

MOSFETs, inductor, and control circuitry integrated into a QFN package. The device integration enables small

designs, while still leaving the ability to adjust key parameters to meet specific design requirements. The

TPSM41615 provides an output voltage range of 0.6 V to 7.1 V, with a selectable internal reference form 0.6 V to

1.1 V, for greater accuracy. An external resistor is used to adjust the output voltage to the desired output. The

switching frequency is also adjustable by using an external resistor or a synchronization clock to accommodate

various input and output voltage conditions and to optimize efficiency. Applications requiring increased current

can benefit from the stackability (parallel outputs and phase-interleaving) of the TPSM41615 device.

The TPSM41615 has been designed for safe start-up into pre-biased loads. The EN pin has an internal pullup

current source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external

resistors. In addition, the internal pullup current of the EN pin allows the device to operate with the EN pin

floating. The EN pin can also be pulled low to put the device in standby mode to reduce input quiescent current.

The device provides a power-good (PGOOD) signal to indicate when the output voltage is within regulation.

Thermal shutdown and current limit features protect the device during an overload condition. A 69-pin QFN

package that includes exposed bottom pads provides a thermally-enhanced solution for space-constrained

applications.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Setting the Output Voltage

The output voltage adjustment range of the TPSM41615 is 0.6 V to 7.1 V. Setting the output voltage requires first

setting the internal reference voltage (V_REF). The internal reference voltage can be set from 0.6 V to 1.1 V using

a resistor (R_VSEL) connected from VSEL (pin 28) to AGND (pin 19). 表 7-1 lists reference voltage selections and

their corresponding setting resistors. If the required output voltage is the same as the reference voltage, connect

the RS+ pin (pin 35) directly to VOUT to set the output voltage as shown in 图 7-1. Output voltages greater than

the reference voltage require an external voltage setting resistor (R_ADJ) between the RS+ pin and VOUT to set

the output voltage as shown in 图 7-2. The value for R_ADJcan be calculated using 方程式 1 or simply selected

from the recommended values given in 表 7-2. Additionally, 表 7-3 includes the recommended switching

frequency (F_SW), the recommended Ramp resistor (R_RAMP), and the minimum output capacitance for several

output voltage ranges.

V_OUT

( _V)

(kꢀ)

R_ADJ

ref

(1)

When setting the output voltage, selecting the highest reference voltage will result in the most accurate output

voltage set point. The output voltage will be regulated at the connection point of RS+ or R_ADJto VOUT. Making

the connection near the load improves regulation at the load.

表 7-1. Setting the Reference Voltage

V_REF(V)

0.6

0.7

0.75

0.8

0.85

0.9

0.95

78.7

1.0

1.05

121

1.1

R_VSELValue (kΩ)⁽¹⁾

8.66

15.4

23.7

34.8

51.1

open

187

(1) Resistors with ≤ 1% tolerance are recommended.

表 7-2. Setting the Output Voltage

V_OUT(V)

V_REF(V) ⁽¹⁾

0.6 - 1.1

short

1.2

1.5

1.8

2.5

3.3

5.0

6.0

1.1

7.0

1.1

R_ADJValue (Ω)⁽¹⁾

90.9

365

634

1270

2000

3570

4420

5360

(1) Selecting the highest reference voltage will result in the most accurate output voltage set point.

VOUT

R_ADJ

RS+

VSEL

R_VSEL

187 kꢀ

R_VSEL

AGND

图 7-1. Setting the Output Voltage

图 7-2. Setting the Output Voltage

(V_OUT> V_REF

(V_OUT= V_REF

)

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表 7-3. Recommended F_SW, RAMP, and Required C_OUT

PV_IN= 5 V

V_OUTRANGE (V)

MINIMUM REQUIRED C_OUT(µF)⁽⁴⁾

RECOMMENDED

F_SW(kHz)⁽¹⁾

ALLOWABLE F_SW

RANGE (KHZ)

MINIMUM

ADDITIONAL

REQUIRED

R_RAMP(kΩ)

CERAMIC⁽³⁾

MIN

MAX

CAPACITANCE⁽⁵⁾

400

500

600

700

400

500

900

500

300 - < 450

450 - < 550

550 - < 700

700 - 1000

300 - < 450

450 - < 850

850 - 1000

400 - 1000

PV_IN= 12 V

78.7

187

78.7

187

78.7

610

490

300

280

600

420

240

190

100

0.6

< 0.8

294⁽²⁾

0.8

< 1.0

289⁽²⁾

1.0

1.2

1.5

1.8

2.5

< 1.2

< 1.5

< 1.8

< 2.5

3.3

284⁽²⁾

277⁽²⁾

266⁽²⁾

254⁽²⁾

224⁽²⁾

V_OUTRANGE (V)

MINIMUM REQUIRED C_OUT(µF) ⁽⁴⁾

RECOMMENDED

F_SW(kHz) ⁽¹⁾

ALLOWABLE F_SW

RANGE (kHz)

MINIMUM

ADDITIONAL

REQUIRED

R_RAMP(kΩ)

CERAMIC ⁽³⁾

MIN

MAX

CAPACITANCE ⁽⁵⁾

400

500

600

400

550

600

400

500

600

400

500

600

700

500

700

1000

600

700

350 - < 450

450 - < 550

550 - 750

78.7

121

78.7

187

78.7

187

121

187

760

430

250

760

430

250

760

185

100

600

430

250

0.6

< 1.0

294⁽²⁾

284⁽²⁾

277⁽²⁾

350 - < 500

500 - < 600

600 - 1000

350 - < 500

500 - < 600

600 - 1000

350 - < 500

500 - < 600

600 - < 850

850 - 1000

450 - < 650

650 - < 950

950 - 1000

550 - 1000

600 - 1000

1.0

1.2

< 1.2

< 1.8

1.8

2.5

< 2.5

254⁽²⁾

450

< 3.3

224⁽²⁾

3.3

5.0

< 5.0

7.1

191⁽²⁾

134⁽²⁾

(1) The recommended F_SWis shown in bold text. Increasing the frequency can reduce the required output capacitance as well as reduce

ripple, however it may also reduce efficiency.

(2) This value of minimum ceramic is the effective amount of 6x 47µF after taking into account DC bias and temperature derating.

(3) The minimum required ceramic output capacitance must account for DC bias and temperature derating.

(4) The Minimum Required output capacitance ensures start-up and stability. Additional output capacitance may be needed to meet

transient response requirements.

(5) The Additional Required Capacitance can be either ceramic or low-ESR polymer type. The total required output capacitance must

include at least the amount of ceramic type listed in the Minimum Ceramic column.

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7.3.2 RS+/RS- Remote Sense Function

RS+ and RS- pins are the remote sensing inputs to the internal differential remote sense amplifier. An 1-kΩ

lower feedback resistor is connected across RS+ and RS– internal to the module. The RS+ pin is used for the

feedback connection to VOUT. Connect this pin to the output voltage at the load. This connection can be made

using a direct connection or an external upper feedback resistor, depending on the magnitude of VOUT and the

VSEL selection. The RS- pin is used for the feedback connection to VOUT return. Connect this pin to the output

voltage return at the load. The RS- connection is not needed for secondary devices in multi-phase

configurations, and should be left open.

7.3.3 Ramp Select (RAMP and RAMP_SEL)

The RAMP and RAMP_SEL pins set the ramp amplitude for the internal control loop. Internal to the device, a

78.7-kΩ resistor is connected between RAMP and RAMP_SEL. Applications requiring 78.7-kΩ ramp setting

should connect the RAMP_SEL pin to AGND and leave the RAMP pin open. Applications requiring a larger ramp

setting resistor should connect it between the RAMP pin to AGND and leave the RAMP_SEL pin open. The

recommended ramp setting resistor can be found in 表 7-3.

7.3.4 Switching Frequency (RT)

The switching frequency range of the TPSM41615 is 300 kHz to 1 MHz. The switching frequency can easily be

set by connecting a resistor (R_RT) between the RT pin (pin 30) and AGND. Select R_RTfrom 表 7-4 based on

input voltage and desired switching frequency.

The switching frequency must be selected based on the input voltage and output voltage of the application. See

表 7-3 for the allowable switching frequency range for each output voltage.

表 7-4. R_RTFrequency Setting Resistor (kΩ)

SWITCHING FREQUENCY

INPUT

VOLTAGE

300

kHz

350

kHz

400

kHz

450

kHz

500

kHz

550

kHz

600

kHz

650

kHz

700

kHz

750

kHz

800

kHz

850

kHz

900

kHz

950

kHz

1 MHz

5 V

8 V

69.8

73.2

59.0

61.9

63.4

52.3

53.6

54.9

45.3

47.5

48.7

40.2

42.2

43.2

36.5

38.3

39.2

33.2

34.8

35.7

30.1

32.4

33.2

28.0

29.4

30.1

26.1

27.4

28.0

23.7

25.5

26.1

22.1

23.7

24.3

21.0

22.1

23.2

19.6

21.0

21.5

18.2

19.6

20.5

10 V - 16 V 75.0

7.3.5 Synchronization (SYNC)

The TPSM41615 device can be synchronized to an external clock. When synchronizing, the external clock signal

must be applied to the SYNC pin before the device reaches its VIN UVLO threshold. In a stand-alone

configuration, the external clock frequency must be within ±20% of the frequency set by the R_RTresistor.

In stackable configuration: (see 节 7.3.6.1.1 for information on configuring the SYNC pins.)

1. When there is no external system clock applied, the SYNC pin of the primary device should be configured as

Sync-Out and the SYNC pin of the secondary device should be configured as Sync-In. Connecting the SYNC

pins of the primary and any secondary devices will synchronize all devices to the frequency of the primary.

2. When an external system clock is applied, the SYNC pin of the primary and secondary device should be

configured as Sync-In and both devices will synchronize to the external system clock.

7.3.5.1 Loss of Synchronization

This device does not support the dynamic application or removal of an external SYNC signal. If the external

SYNC signal is removed, the device treats this as a clock fault and stops power conversion.

7.3.6 Stand-alone/Stackable Operation

The TPSM41615 can be operated as a single stand-alone device or two devices can be combined to operate

together in a stackable configuration for increased current. These operation modes are selected using a resistor

connected from MODE pin to AGND. In stand-alone mode, the resistor value connected to the MODE pin also

selects whether the transient response feature is ON or OFF (see 表 7-8). In stackable mode, the transient

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response feature is not available. In stackable mode, the MODE resistor sets the device as primary or

secondary, as well as SYNC pin function (sync in or sync out) of the primary device (see 表 7-5).

表 7-5. MODE Pin Selections

OPERATION MODE

TRANSIENT FEATURE

SYNC MODE

MODE RESISTOR VALUE (kΩ)

78.7

187

Stand-alone

Sync in

OFF

open

23.7

34.8

51.1

Primary sync out

Primary sync in

Stackable

OFF

Secondary sync in

7.3.6.1 Stackable Synchronization

7.3.6.1.1 Sync Configuration

In stackable mode, a resistor between the MODE pin and AGND sets the device as primary or secondary, as

well as SYNC pin function (sync in or sync out) of the primary device. See 表 7-6 for Mode resistor values.

表 7-6. MODE Setting for SYNC Function

SYNC FUNCTION

NOTE

MODE RESISTOR VALUE (kΩ)

•

Sync pin to send out clock

RT pin to set frequency

Primary sync out

23.7

•

Sync pin to receive clock

RT pin to set sync point

Primary sync in

34.8

51.1

•

Sync pin to receive clock

RT pin to set sync point

Secondary sync in

7.3.6.1.2 Clock Sync Point Selection

The TPSM41615 device implements a unique clock synchronization scheme for phase interleaving between

devices. This is only used when stacking multiple devices. The device will receive a clock signal through the

SYNC pin and generate sync points to achieve phase interleaving. Sync point options can be selected with a

resistor from the RT pin to AGND. 图 7-3 shows the clock signals for a primary and a secondary device with a

180° phase shift. See 表 7-7 for clock sync options and the corresponding RT resistor value.

图 7-3. 2-Phase Stackable with 180° Clock Phase Shift

表 7-7. Sync Point Selection

CLOCK SYNC OPTIONS

RT RESISTOR VALUE (kΩ)

0 (0° Interleaving)

SHORT

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表 7-7. Sync Point Selection (continued)

CLOCK SYNC OPTIONS

RT RESISTOR VALUE (kΩ)

1/2 (180° Interleaving)

OPEN

7.3.6.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary

• Direct SYNC, VSHARE, and ISHARE connections between primary and secondary

• Switching frequency is set by RT pin of primary, and pass to secondary through SYNC pin. SYNC pin of

primary will be configured as sync out by its MODE pin.

• Secondary receives clock from SYNC pin. Its RT pin determines the sync point for clock phase shift.

图 7-4. 2-Phase Stackable, 180° Phase Shift: Primary Sync-Out Clock to Secondary

7.3.6.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock

• Direct connection between external clock and SYNC pin of primary and secondary.

• Direct VSHARE and ISHARE connections between primary and secondary.

• SYNC pin of primary is configured as sync in by its MODE pin.

• Primary and secondary receive external system clock from SYNC pin. Their RT pin determine the sync point

for clock phase shift.

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图 7-5. 2-Phase Stackable, 180° Phase Shift: Primary and Secondary Sync to External System Clock

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7.3.7 Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)

The TPSM41615 is a fixed frequency converter. The major limitation for any fixed frequency converter is that

during transient load step up, the output voltage drops until the next clock cycle of the converter before it can

respond to the load change. The TPSM41615 implements a special circuitry to improve transient performance.

During a load step up, the converter can issue an additional PWM pulse before the next available clock cycle to

stop output voltage from further dropping, thus reducing the undershoot voltage. The additional pulse during a

transient means that the device is not fixed frequency during the transient.

During load step-down, the TPSM41615 implements a body-brake function that turns off both high-side and low-

side FET, and allows power to dissipate through the low-side body diode, reducing overshoot. This approach is

very effective while having some impact on efficiency during transient.

In stand-alone mode, choose whether the transient response feature is enabled by placing either a 78.7-kΩ or

187-kΩ resistor between the MODE pin and AGND. A 78.7-kΩ MODE resistor is recommended when the

output voltage is 0.6 V to 1.8 V or in applications that are more susceptible to noise. Leave the MODE pin open

to operate in fixed frequency during a load step, (see 表 7-8).

表 7-8. Stand-Alone Operation Feature Selections

STAND-ALONE OPERATION

MODE RESISTOR VALUE (kΩ)

78.7

187

Transient Feature

Fixed Frequency

open

7.3.8 Output On/Off Enable (EN)

The EN pin provides electrical ON/OFF control of the device. Once the EN pin voltage exceeds the threshold

voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator

stops switching and enters low operating current state. The EN pin has an internal pullup to BP5, allowing the

user to float the EN pin for enabling the device.

If an application requires controlling the EN pin, either drive it directly with a logic input or use an open drain/

collector device to interface with the pin. Applying a low voltage to the enable control (EN) pin disables the

output of the supply. When the EN pin voltage exceeds the threshold voltage, the supply executes a soft-start

power-up sequence.

7.3.9 Power Good (PGOOD)

The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the

output voltage is between 92% and 108% of the set-point voltage, the PGOOD pin pulldown is released and the

pin floats. A pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source of 5.5 V or less is

recommended. The PGOOD pin is pulled low when the output voltage is lower than 88% or greater than 112% of

the set-point voltage.

7.3.10 Soft-Start Operation

For the TPSM41615 device, the soft-start time controls the inrush current required to charge the output

capacitors during start-up. When the device is enabled, the output voltage ramps from 0 V to the set-point

voltage in the time selected by the SS pin. The device offers 10 selectable soft start options ranging from 0.5 ms

to 32 ms. See 表 7-9 for details.

表 7-9. SS Pin Configuration

SS TIME

0.5 ms

1 ms

2 ms

4 ms

5 ms

8 ms

12 ms

16 ms

24 ms

32 ms

RESISTOR VALUE

8.66

15.4

OPEN

23.7

34.8

51.1

78.7

121

187

(kΩ)

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7.3.11 Input Capacitor Selection

The TPSM41615 requires a minimum input capacitance of 88 µF of ceramic type. Use only high-quality ceramic

type X5R or X7R capacitors with sufficient voltage rating. An additional 100 µF of non-ceramic, bulk capacitance

is recommended for applications with transient load requirements. The voltage rating of input capacitors must be

greater than the maximum input voltage. 表 7-10 includes a preferred list of capacitors by vendor.

表 7-10. Recommended Input Capacitors

CAPACITOR CHARACTERISTICS

VENDOR⁽¹⁾

TDK

SERIES

PART NUMBER

ESR (mΩ) ⁽²⁾

WORKING VOLTAGE (V)

CAPACITANCE (µF) ⁽³⁾

X7R

C3225X7R1E226M250AB

GRM32ER71E226KE15L

EEHZA1H101P

Murata

Panasonic

100

(1) Capacitor Supplier Verification , RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material

composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table.

(2) Maximum ESR at 100 kHz, 25°C

(3) Specified capacitance values

7.3.12 Output Capacitor Selection

The minimum required output capacitance of the TPSM41615 is a function of the output voltage and is shown in

表 7-3. The required capacitance can be comprised of all ceramic capacitors or a combination of ceramic and

low-ESR polymer type capacitors. When adding additional capacitors, low-ESR capacitors like the ones

recommended in 表 7-11 are required. The required capacitance above the minimum is determined by actual

transient deviation requirements.

表 7-11. Recommended Output Capacitors

CAPACITOR CHARACTERISTICS

VENDOR⁽¹⁾

Murata

SERIES

PART NUMBER

ESR (mΩ) ⁽²⁾

WORKING VOLTAGE (V)

CAPACITANCE (µF) ⁽³⁾

X7R

GCM32ER70J476K

LMK325B7476MM-PR

GRM32ER71A476K

C3225X5R0J107M

GRM32ER60J107M

GRM32ER61A107M

GRM32EC80G227ME05L

4TPE220MF

6.3

Taiyo Yuden

Murata

X7R

TDK

X5R

6.3

100

220

330

Murata

X5R

Murata

X5R

Murata

X6S

4.0

6.3

Panasonic

Kemet

POSCAP

T520

POSCAP

T520

T520D227M006ATE015

6TPE330MAA

Panasonic

Kemet

T520D337M006ATE010

T520X337M010ATE010

Kemet

(1) Capacitor Supplier Verification , RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material

composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table.

(2) Maximum ESR at 100 kHz, 25°C

(3) Specified capacitance values

7.3.13 Current Limit (ILIM)

The current limit of the TPSM41615 is internally set to 23 A (typ.) by leaving the ILIM pin open. Connecting a

resistor between the ILIM pin and AGND adjusts the current limit threshold lower. Refer to 表 7-12 for current

limit adjustment values.

表 7-12. Current Limit Adjust

CURRENT LIMIT REDUCTION

10 %

20 %

30 %

40 %

50 %

191

118

78.7

54.9

37.4

R_ILIM(kΩ)

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7.3.14 Safe Start-up into Pre-Biased Outputs

The TPSM41615 device has been designed to prevent the low-side MOSFET from discharging a pre-biased

output. During pre-biased start-up, the low-side MOSFET is not allowed to sink current until the SS/TR pin

voltage is higher than the FB pin voltage and the high-side MOSFET begins to switch.

7.3.15 Overcurrent Protection

For protection against load faults, the TPSM41615 is protected from overcurrent conditions by cycle-by-cycle

current limiting. In an extended overcurrent condition, the device enters hiccup mode to reduce power

dissipation. In hiccup mode, the module continues in a cycle of successive shutdown and power up until the load

fault is removed. During this period, the average current flowing into the fault is significantly reduced, which

reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal

operation.

7.3.16 Output Overvoltage and Undervoltage Protection

The device includes both output overvoltage protection and output undervoltage protection capability. The

devices compare the RS+ pin voltage to internal selectable pre-set voltages. If the RS+ voltage with respect to

RS- voltage rises above the output overvoltage protection threshold, the device terminates normal switching and

turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output

voltage. Then, the device enters continuous restart hiccup.

If the RS+ pin voltage falls below the undervoltage protection level, after soft start has completed, the device

terminates normal switching and forces both the high-side and low-side MOSFETs off, then enters hiccup time-

out delay prior to restart.

7.3.17 Overtemperature Protection

An internal temperature sensor protects the device from thermal runaway. The internal thermal shutdown

circuitry forces the device to stop switching if the junction temperature exceeds 165°C typically. The device

reinitiates the power-up sequence when the junction temperature drops below 135°C typically.

7.4 Device Functional Modes

7.4.1 Active Mode

The TPSM41615 is in active mode when VIN is above the UVLO threshold and the EN pin voltage is above the

EN high threshold. The EN pin has an internal current source to enable the output when the EN pin is left

floating. If the EN pin is pulled low the device is put into a low quiescent current state.

7.4.2 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPSM41615. When the EN pin voltage is below the

EN low threshold, the device is in shutdown mode. In shutdown mode, the device is put into a low quiescent

current state. The TPSM41615 also employs undervoltage lockout protection. If V_INis below the UVLO level, the

output of the regulator turns off.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPSM41615 is a synchronous step-down DC-DC power module. It is used to convert a higher DC voltage to

a lower DC voltage with a maximum output current of 15 A. The following design procedure can be used to

select components for the TPSM41615. Alternately, the WEBENCH^®software may be used to generate

complete designs. When generating a design, the WEBENCH software utilizes an iterative design procedure and

accesses comprehensive databases of components. See www.ti.com/webench for more details.

8.2 Typical Application

The TPSM41615 requires only a few external components to convert from a wide input voltage supply range to a

wide range of output voltages. 图 8-1 shows a typical TPSM41615 schematic with only the minimum required

components.

PGOOD

BP5

100kꢀ

12 V

PVIN

VIN

TPSM41615

RS+

47µF

0.95 V

1µF

VOUT

PGND

ILIM

100µF 100µF 100µF 100µF 330µF

PGND

RS-

SYNC

VSEL

MODE

RAMP

78.7kꢀ

43.2kꢀ

78.7kꢀ

RAMP_SEL

AGND

图 8-1. TPSM41615 Typical Application

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 8-1. Follow the design procedures in 节 8.2.2.

表 8-1. Design Example Parameters

DESIGN PARAMETER

Input voltage V_IN

VALUE

12 V typical

0.95 V

Output voltage V_OUT

Output current rating

Key care-abouts

15 A

Small solution size

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM41615 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM41615 is externally adjustable by first setting the reference voltage, V_REF, using

the VSEL pin and then, if needed, setting the output voltage adjust resistor R_ADJ. For this application, V_REFis the

same as the output voltage, so R_ADJis not needed and RS+ should be connected to the output rail, near the

load.

To set the output voltage to 0.95 V, select V_REFof 0.95 V by connecting a 78.7-kΩ resistor between VSEL pin

and AGND and connect RS+ pin to the output voltage rail. VSEL resistor values for setting VREF can be found

in 表 7-1.

8.2.2.3 Setting the Switching Frequency

To set the switching frequency of the TPSM41615, a resistor (R_RT) between the RT pin and AGND is required.

Select the value of R_RTfrom 表 7-4. Before selecting the switching frequency, reference 表 7-3 for the allowable

switching frequency range, required output capacitance, and RAMP setting for the desired output voltage.

For this application, after referencing 表 7-3, 500 kHz was selected and a 43.2-kΩ RT resistor is required for a

12-V input according to 表 7-4.

8.2.2.4 RAMP Setting

The value of the RAMP resistor, R_RAMP, must be selected based on the switching frequency and output

capacitance of the application, as shown in 表 7-3. For this application, the required R_RAMPis 78.7 kΩ. There is

a 78.7-kΩ resistor internal to the device connected between RAMP and RAMP_SEL. To select the internal 78.7-

kΩ resistor, leave the RAMP pin open and connect RAMP_SEL to AGND.

8.2.2.5 Input Capacitors

The TPSM41615 requires a minimum of 88 μF of ceramic input capacitance. Applications with load transient

requirements can benefit from adding addition bulk input capacitance.

For this design, two 47-μF ceramic capacitors rated for 25 V are used for the input decoupling capacitors.

Additionally, a 1-μF bypass capacitor is required on the VIN pin, close to the device pins.

8.2.2.6 Output Capacitors

The minimum required output capacitance for a 12-V input and 0.95-V output at 500 kHz switching frequency is

294 μF of ceramic capacitance, as well as an additional 430 μF of either ceramic or low-ESR polymer, as

shown in 表 7-3.

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For this design, four 100-μF ceramic capacitors plus a 330-μF polymer capacitor where used to meet the

requirements.

8.2.3 Application Curves

图 8-2. Output Ripple Waveform

图 8-3. Start-Up Waveforms

图 8-4. 5-A Transient Load Step

图 8-5. 10-A Transient Load Step

9 Power Supply Recommendations

The TPSM41615 is designed to operate from an input voltage supply range between 4 V and 16 V. The input

supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the TPSM41615 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the TPSM41615 additional bulk capacitance can be

required in addition to the ceramic bypass capacitors. Typically, a 47-µF or 100-μF electrolytic capacitor will

suffice.

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10 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. The following guidelines will help users design a PCB with the best power conversion performance,

thermal performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 10-1 through 图

10-4 shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

• Locate additional output capacitors between the ceramic capacitor and the load.

• Keep AGND and PGND separate from one another. The connection is made internal to the device.

• Place R_VSEL, R_ADJ, R_RT, R_MODE, and C_SSas close as possible to their respective pins.

• Use multiple vias to connect the power planes (PVIN, VOUT, and PGND) to internal layers.

10.2 Layout Examples

图 10-2. Bottom-Layer Components (Top View)

图 10-1. Top-Layer Components (Top View)

图 10-3. Top-Layer Layout (Top View)

图 10-4. Bottom-Layer Layout (Top View)

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10.2.1 Package Specifications

TPSM41615

VALUE

UNIT

Weight

1.32

grams

Flammability

Meets UL 94 V-O

MTBF Calculated Reliability

Per Bellcore TR-332, 50% stress, T_A= 40°C, ground benign

39.7

MHrs

10.2.2 EMI

The TPSM41615 is compliant with EN55011 Class B radiated emissions. 图 10-5 and 图 10-6 show typical

examples of radiated emissions plots for the TPSM41615. The graphs include the plots of the antenna in the

horizontal and vertical positions.

10.2.2.1 EMI Plots

EMI plots were measured using the standard TPSM41615EVM with an input filter in series with the input wires.

图 10-5. Radiated Emissions 5-V Input, 1.8-V Output, 15-A Load (EN55011 Class B)

图 10-6. Radiated Emissions 12-V Input, 7.1-V Output, 15-A Load (EN55011 Class B)

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM41615 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

5-Feb-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSM41615MOVR

ACTIVE

QFM

MOV

500

RoHS Exempt

& Green

NIAU

Level-3-260C-168 HR

-40 to 125

TPSM41615

MOV

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

28-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPSM41615MOVR

QFM

MOV

500

330.2

32.4

11.4

16.4

4.69

16.0

32.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

28-May-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFM MOV 69

SPQ

Length (mm) Width (mm) Height (mm)

381.0 381.0 101.6

TPSM41615MOVR

500

Pack Materials-Page 2

PACKAGE OUTLINE

MOV0069A

QFM - 4.4 mm max height

QUAD FLAT MODULE

11.15

10.85

PIN 1 ID

AREA

16.15

15.85

4.4

4.0

1.1 MAX

SEATING PLANE

0.1 C

1.4

1.2

1.1

0.9

62X

7.4

2X 7.25

(0.25) TYP

4X (0.6)

3.15

1.9 0.05

0.000 PKG

1.15

4X (1)

1.4 0.05

2X 12.35

0.05

0.4

62X

0.3

0.1

0.05

C A B

2X 7.25

7.4

58X 0.65

(0.1) TYP

2X 2 0.05

1.8

1.6

2X 6.5

4225958/A 06/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

MOV0069A

QFM - 4.4 mm max height

QUAD FLAT MODULE

27X (1.2)

(0.05) MIN

SOLDER MASK

DEFINED PADS

METAL UNDER

SOLDER MASK

TYP

(7.5)

SOLDER MASK

OPENING

TYP

2X (7.35)

9X (7)

(6.2)

6X (5.8)

27X (0.35)

(5.1)

3X (5.2)

4X (4.6)

3X (4)

58X (0.65)

3X (3.4)

3X (2.8)

(1.8)

4X (2.2)

(1.45)

(1.1)

(

0.2) TYP

VIA

3X (1)

2X (2)

(1.4)

(0.25)

0.000 PKG

4X (0.4)

3X (0.95)

2X (1.15)

(1.9)

2X (1.9)

(2.75)

5X (1.95)

5X (3.15)

(3.3)

(0.05) MAX

NON-SOLDER MASK

DEFINED PADS

2X (5)

(R0.05) TYP

5X (4.35)

35X (0.35)

3X (5.35)

(5.8)

(5.05)

(5.85)

(6.4)

2X (7.35)

35X (1.2)

4X (1.5)

(7.5)

COPPER KEEP-OUT

AREA

COPPER KEEP-OUT

AREA

4X (1.9)

LAND PATTERN EXAMPLE

SCALE: 8X

4225958/A 06/2020

NOTES: (continued)

4. This package is designed to be soldered to the thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

MOV0069A

QFM - 4.4 mm max height

QUAD FLAT MODULE

(7.5)

EXPOSED METAL

TYP

2X (7.35)

METAL UNDER

SOLDER MASK

TYP

2X (5.8)

2X (4.6)

2X (3.4)

2X (2.2)

SOLDER MASK

OPENING

TYP

(R0.05) TYP

16X (1)

16X

(0.8)

4X (0.55)

0.000 PKG

2X (0.65)

2X (1.35)

2X (2.55)

2X (3.75)

2X (4.95)

4X (0.8)

2X (1.65)

58X (0.65)

62X (0.35)

2X (7.35)

(7.5)

4X (1.35)

62X (1.2)

4X (1.75)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 8X

66% SOLDER COVERAGE BY PRINTED AREA ON PAD 67

64% SOLDER COVERAGE BY PRINTED AREA ON PADS 68 & 69

4225958/A 06/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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