TRF3765_15 [TI]
Integer-N/Fractional-N PLL With Integrated VCO;
| 型号： | TRF3765_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Integer-N/Fractional-N PLL With Integrated VCO |
| 文件： | 总51页 (文件大小：1415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF3765
www.ti.com
SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
Integer-N/Fractional-N PLL with Integrated VCO
Check for Samples: TRF3765
1
FEATURES
DESCRIPTION
The TRF3765 is a wideband Integer-N/Fractional-N
frequency synthesizer with an integrated, wideband
voltage-controlled oscillator (VCO). Programmable
output dividers enable continuous frequency
coverage from 300 MHz to 4.8 GHz. Four separate
differential, open-collector RF outputs allow multiple
devices to be driven in parallel without the need of
external splitters.
2
•
Output Frequencies: 300 MHz to 4.8 GHz
•
Low-Noise VCO: –133 dBc/Hz
(1-MHz Offset, fOUT = 2.65 GHz)
•
•
•
•
13-/16-Bit Reference/Feedback Divider
25-Bit Fractional-N and Integer-N PLL
Low RMS Jitter: 0.35 ps
Input Reference Frequency Range:
0.5 MHz to 350 MHz
The TRF3765 also accepts external VCO input
signals and allows on/off control through
a
•
•
•
Programmable Output Divide-by-1/-2/-4/-8
Four Differential LO Outputs
programmable control output. For maximum flexibility
and wide reference frequency range, wide-range
divide ratio settings are programmable and an
off-chip loop filter can be used.
External VCO Input with Programmable VCO
On/Off Control
The TRF3765 is available in an RHB-32 QFN
package.
APPLICATIONS
•
•
•
•
Wireless Infrastructure
Wireless Local Loop
Point-to-Point Wireless Access
Wireless MAN Wideband Transceivers
STROBED ATA CLOCK
LD
VCCs
EXTVCO_IN
Lock
Detect
Serial
Interface
GNDs
REF_IN
R Div
CP_OUT
Charge
Pump
PFD
VTUNE_IN
Prescaler
div p/p_+1
RF
Divider
N-Divider
From
4WI
SD
Control
From
4WI
From
4WI
Divide-by
1/2/4/8
RF4OUT
RF3OUT
RF2OUT
RF1OUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TRF3765
SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
TRANSPORT MEDIA,
QUANTITY
PRODUCT
ORDERING NUMBER
TRF3765IRHBT
Tape and Reel, 250
Tape and Reel, 3000
TRF3765
RHB-32
RHB
–40°C to +85°C
TRF3765IRHB
TRF3765IRHBR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
–0.3 to +3.6
–0.3 to +5.5
–0.3 to VI + 0.5
–40 to +150
–40 to +85
–40 to +150
1000
UNIT
V
All VCC pins except VCC_TK
VCC_TK
Supply voltage range(2)
Digital I/O voltage range
V
V
Operating virtual junction temperature range, TJ
Operating ambient temperature range, TA
Storage temperature range, Tstg
°C
°C
°C
V
Human body model, HBM
Charged device model, CDM
ESD ratings
1500
V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN NOM
MAX
3.6
UNIT
V
VCC
Power-supply voltage
3.0
3.0
3.3
3.3
VCC_TK 3.3-V to 5.5-V power-supply voltage
5.5
V
TA
TJ
Operating ambient temperature range
–40
–40
+85
+150
°C
°C
Operating virtual junction temperature range
THERMAL INFORMATION
TRF3765
RHB
32 PINS
31.6
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
21.6
5.6
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
5.5
θJCbot
1.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS
At TA = +25°C and power supply = 3.3 V, unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PARAMETERS
Internal VCO, 1 output buffer on, divide-by-1
Internal VCO, 4 output buffers on, divide-by-1
Internal VCO, 1 output buffer on, divide-by-8
Internal VCO, 4 output buffers on, divide-by-8
External VCO mode, 1 output buffer on, divide-by-1
115
190
120
182
89
mA
mA
mA
mA
mA
ICC
Total supply current
DIGITAL INTERFACE
VIH
VIL
High-level input voltage
2
0
3.3
V
V
V
V
Low-level input voltage
High-level output voltage
Low-level output voltage
0.8
VOH
VOL
Referenced to VCC_DIG
Referenced to VCC_DIG
0.8 × VCC
0.2 × VCC
REFERENCE OSCILLATOR PARAMETERS
fREF
Reference frequency
0.5(1)
0.2
350(1)
3.3
MHz
VPP
pF
Reference input sensitivity
Parallel capacitance, 10 MHz
Parallel resistance, 10 MHz
2
Reference input impedance
2500
Ω
PLL
fPFD
PFD frequency
0.5
65(2)
MHz
mA
ICP_OUT Charge pump current
In-band normalized phase noise floor
INTERNAL VCO
4WI programmable; ICP[4..0] = 00000(3)
Integer mode
1.94
–221
dBc/Hz
fVCO
KV
VCO frequency range
Divide-by-1
VCP = 1 V
At 10 kHz
At 100 kHz
At 1 MHz
2400
4800
MHz
VCO gain
–65
–82
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–110
–130
–149
–155
–89
VCC_TK = 3.3 V
At 10 MHz
At 40 MHz
At 10 kHz
At 100 kHz
At 1 MHz
VCO free-running
phase noise,
fVCO = 2650 MHz
–113
–133
–151
–156
VCC_TK = 5 V
At 10 MHz
At 40 MHz
CLOSED-LOOP PLL/VCO
Integrated RMS jitter(4)
RF OUTPUT/INPUT
Fractional mode, fOUT = 2.6 GHz, fPFD = 30.72 MHz(5)
Integer mode, fOUT = 2.6 GHz, fPFD = 1.6 MHz
0.36
0.52
ps
ps
Divide-by-1
Divide-by-2
Divide-by-4
Divide-by-8
2400
1200
600
4800
2400
1200
600
MHz
MHz
MHz
MHz
fOUT
Output frequency range
300
Differential, divide-by-1, one output buffer on, maximum
BUFOUT_BIAS
PLO
Output power(6)
6.5
dBm
External VCO input maximum frequency
External VCO input minimum frequency
External VCO input level
20-dB gain loss, VCO pass-through, no PLL
9000
15
MHz
MHz
dBm
20-dB gain loss, VCO pass-through, no PLL, divide-by-1
0
(1) See Application Information section for discussion of VCO calibration clock limitations on reference clock frequency.
(2) See Application Information section for discussion on PFD frequency selection and calibration logic frequency limitations.
(3) See the 4WI Register Descriptions section for all possible programmable charge pump currents.
(4) Integrated from 1 kHz to 10 MHz.
(5) See Application Information section for information on loop filter characteristics.
(6) See Application Information section for external output buffers details.
Copyright © 2011–2012, Texas Instruments Incorporated
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DEVICE INFORMATION
RHB PACKAGE
QFN-32
(TOP VIEW)
GND_DIG
VCC_DIG
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VTUNE_REF
VTUNE_IN
GND_OSC
VCC_OSC
DATA
CLOCK
VCC_TK
STROBE
EXTVCO_CTRL
EXTVCO_IN
GND_BUFF2
READBACK
VCC_DIV
GND_BUFF1
PIN FUNCTIONS
PIN
NAME
CLOCK
CP_OUT
CP_REF
DATA
NO.
4
I/O
I
DESCRIPTION
Serial programming interface, clock input
26
25
3
O
Charge pump output
Charge pump reference ground
Serial programming interface, data input
Digital control to enable/disable external VCO
External VCO input
I
O
I
EXTVCO_CTRL
EXTVCO_IN
GND
19
18
29
31
8
Ground
GND
Ground
GND_BUFF1
GND_BUFF2
GND_DIG
GND_OSC
LD
Output buffer ground
17
1
Output buffer ground
Digital ground
22
32
10
9
VCO core ground
O
O
O
O
O
O
O
O
O
Lock detector output
LO1_OUTM
LO1_OUTP
LO2_OUTM
LO2_OUTP
LO3_OUTM
LO3_OUTP
LO4_OUTM
LO4_OUTP
LO1 output: negative terminal
LO1 output: positive terminal
LO2 output: negative terminal
LO2 output: positive terminal
LO3 output: negative terminal
LO3 output: positive terminal
LO4 output: negative terminal
LO4 output: positive terminal
11
12
14
13
15
16
4
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
PIN FUNCTIONS (continued)
PIN
NAME
READBACK
REF_IN
NO.
6
I/O
DESCRIPTION
Serial programming interface, readback
O
I
30
5
Reference signal input
Serial programming interface, latch enable
Charge pump power supply
Digital power supply
STROBE
I
VCC_CP
27
2
VCC_DIG
VCC_DIV
VCC_OSC
VCC_PLL
VCC_TK
7
Divider power supply
21
28
20
23
24
VCO core power supply
PLL power supply
VCO LC tank power supply
VCO control voltage
VTUNE_IN
VTUNE_REF
VTUNE reference ground
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
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TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
Table of Graphs
Open-Loop Phase Noise
Open-Loop Phase Noise
Open-Loop Phase Noise
Open-Loop Phase Noise
vs Temperature(1)
vs Voltage(1)
Figure 1, Figure 2, Figure 3, Figure 4
Figure 5, Figure 6, Figure 7, Figure 8
Figure 9, Figure 10, Figure 11, Figure 12
Figure 13, Figure 14, Figure 15, Figure 16
vs Temperature(1)(2)
vs Voltage(1)(2)
Figure 17, Figure 18, Figure 19, Figure 20,
Figure 21, Figure 22, Figure 23
Closed-Loop Phase Noise
Closed-Loop Phase Noise
vs Temperature(3)
Figure 24, Figure 25, Figure 26, Figure 27,
Figure 28, Figure 29, Figure 30
vs Temperature(2)(3)
Closed-Loop Phase Noise
Closed-Loop Phase Noise
vs Divide Ratio(3)
vs Divide Ratio(2)(3)
Figure 31
Figure 32
Figure 33, Figure 34, Figure 35, Figure 36,
Figure 37, Figure 38, Figure 39
Closed-Loop Phase Noise
Closed-Loop Phase Noise
vs Temperature(4)
Figure 40, Figure 41, Figure 42, Figure 43,
Figure 44, Figure 45, Figure 46
vs Temperature(2)(4)
Closed-Loop Phase Noise
Closed-Loop Phase Noise
PFD Spurs
vs Divide Ratio(4)
vs Divide Ratio(2)(4)
vs Temperature(4)
Figure 47
Figure 48
Figure 49
Multiples of PFD Spurs(4)
Multiples of PFD Spurs(4)(5)
Fractional Spurs
Figure 50, Figure 51, Figure 52
Figure 53
vs LO Divider(3)
Figure 54
Fractional Spurs
vs RF Divider and Prescaler(3)
vs Temperature(3)
Figure 55
Fractional Spurs
Figure 56
Multiples of PFD Spurs(3)
LO Harmonics(4)
Figure 57
Figure 58
Output Power with Multiple Buffers(4)
Figure 59, Figure 60
Figure 61
Output Power
Output Power
VCO Gain (Kv)
vs Output Port(4)
vs Buffer Bias(4)
Figure 62
vs Frequency
Figure 63
(1) VCO_TRIM = 32, VTUNE_IN = 1.1 V, CP_TRISTATE = 3 (3-state), and CAL_BYPASS = On.
(2) VCO_BIAS = 600 µA.
(3) Reference frequency = 61.44 MHz; PFD frequency = 30.72 MHz.
(4) Reference frequency = 40 MHz; PFD frequency = 1.6 MHz.
(5) Performance change at frequencies above 1500 MHz results from PLL_DIV_SEL changing from divide-by-1 to divide-by-2.
6
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 0 and VCC_TK = 3.3 V)
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 1 and VCC_TK = 3.3 V)
−10
−20
−10
−20
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
−30
−30
−40
−40
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
−50
VCC_TK = 3.3 V
VCC_TK = 3.3 V
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 25°C
1kHz = −49.8
10kHz = −83
100kHz = −109.6
1MHz = −130.1
10MHz = −149
*See Note 1
Note: At 25°C
1kHz = −45.1
10kHz = −81.6
100kHz = −107.9
1MHz = −128.1
10MHz = −147.3
*See Note 1
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G001
G002
Figure 1.
Figure 2.
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 2 and VCC_TK = 3.3 V)
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 3 and VCC_TK = 3.3 V)
−10
−20
−10
−20
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
−30
−30
−40
−40
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
−50
VCC_TK = 3.3 V
VCC_TK = 3.3 V
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 25°C
Note: At 25°C
1kHz = −38.3
10kHz = −70.6
100kHz = −104.2
1MHz = −125.5
10MHz = −145.2
*See Note 1
1kHz = −50.7
10kHz = −83.31
100kHz = −107.9
1MHz = −128.0
10MHz = −146.9
*See Note 1
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G003
G004
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 0)
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 1)
−10
−20
−10
−20
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−30
−30
−40
−40
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 3.3 V
Note: At 3.3 V
1kHz = −45.1
10kHz = −81.6
100kHz = −107.7
1MHz = −128.1
10MHz = −147.3
*See Note 1
1kHz = −49.8
10kHz = −83.0
100kHz = −109.6
1MHz = −130.1
10MHz = −149.0
*See Note 1
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G005
G006
Figure 5.
Figure 6.
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 2)
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 3)
−10
−20
−10
−20
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−30
−30
−40
−40
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 3.3 V
Note: At 3.3 V
1kHz = −50.7
10kHz = −83.3
100kHz = −107.9
1MHz = −128.0
10MHz = −147.4
*See Note 1
1kHz = −37.3
10kHz = −71.0
100kHz = −104.0
1MHz = −125.5
10MHz = −145.2
*See Note 1
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G007
G008
Figure 7.
Figure 8.
8
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 0 and VCC_TK = 5 V)
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 1 and VCC_TK = 5 V)
−10
−20
−10
−20
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
−30
−30
−40
−40
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
−50
VCC_TK = 5.0 V
VCC_TK = 5.0 V
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 25°C
Note: At 25°C
1kHz = −58.0
10kHz = −89.0
100kHz = −112.6
1MHz = −133.1
10MHz = −151.2
*See Notes 1and 2
1kHz = −48.8
10kHz = −80.4
100kHz = −110.5
1MHz = −130.9
10MHz = −149.7
*See Notes 1and 2
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G009
G010
Figure 9.
Figure 10.
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 2 and VCC_TK = 5 V)
OPEN-LOOP PHASE NOISE vs TEMPERATURE
(VCO_SEL = 3 and VCC_TK = 5 V)
−10
−20
−10
−20
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
−30
−30
−40
−40
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
−50
VCC_TK = 5.0 V
VCC_TK = 5.0 V
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 25°C
Note: At 25°C
1kHz = −54.3
10kHz = −86.2
100kHz = −97.2
1MHz = −130.8
10MHz = −149.0
*See Notes 1and 2
1kHz = −40.3
10kHz = −73.1
100kHz = −106.8
1MHz = −128.4
10MHz = −147.5
*See Notes 1and 2
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G011
G012
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 0)
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 1)
−10
−20
−10
−20
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−30
−30
−40
−40
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 3.3 V
Note: At 3.3 V
1kHz = −58.0
10kHz = −88.4
100kHz = −112.8
1MHz = −133.1
10MHz = −151.2
*See Notes 1and 2
1kHz = −48.8
10kHz = −81.5
100kHz = −110.5
1MHz = −130.9
10MHz = −149.8
*See Notes 1and 2
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G013
G014
Figure 13.
Figure 14.
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 2)
OPEN-LOOP PHASE NOISE vs VOLTAGE
(VCO_SEL = 3)
−10
−20
−10
−20
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−30
−30
−40
−40
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−100
−110
−120
−130
−140
−150
−160
Note: At 3.3 V
Note: At 3.3 V
1kHz = −54.3
10kHz = −86.2
100kHz = −110.5
1MHz = −131.2
10MHz = −149.0
*See Notes 1and 2
1kHz = −40.3
10kHz = −73.1
100kHz = −106.7
1MHz = −128.4
10MHz = −147.5
*See Notes 1and 2
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G015
G016
Figure 15.
Figure 16.
10
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(725 MHz, VCC_TK = 3.3 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(942.5 MHz, VCC_TK = 3.3 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 725 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 942.5 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 3
*See Note 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G023
G022
Figure 17.
Figure 18.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(1880 MHz, VCC_TK = 3.3 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2120 MHz, VCC_TK = 3.3 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 1880 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 2120 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 3
*See Note 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G021
G020
Figure 19.
Figure 20.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2650 MHz, VCC_TK = 3.3 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(3500 MHz, VCC_TK = 3.3 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 2650 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 3500 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 3
*See Note 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G017
G018
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(4750 MHz, VCC_TK = 3.3 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(725 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 4750 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 725 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 3
*See Notes 2 and 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G019
G030
Figure 23.
Figure 24.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(942.5 MHz, VCC_TK = 5 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(1880 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 942.5 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 1880 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 3
*See Notes 2 and 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G029
G028
Figure 25.
Figure 26.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2120 MHz, VCC_TK = 5 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2650 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 2120 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 2650 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 3
*See Notes 2 and 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G027
G024
Figure 27.
Figure 28.
12
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(3500 MHz, VCC_TK = 5 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(4750 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 3500 MHz
Fractional Mode (EN_FRAC = 1)
LO_Out = 4750 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 3
*See Notes 2 and 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G025
G026
Figure 29.
Figure 30.
CLOSED-LOOP PHASE NOISE vs DIVIDE RATIO
(VCC_TK = 3.3 V, Fractional Mode)
CLOSED-LOOP PHASE NOISE vs DIVIDE RATIO
(VCC_TK = 5 V, Fractional Mode)
−60
−70
−60
−70
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 3600 MHz
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 3600 MHz
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 3
*See Notes 2 and 3
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G031
G032
Figure 31.
Figure 32.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(728 MHz, VCC_TK = 3.3 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(942.5 MHz, VCC_TK = 3.3 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 728 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 942.5 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 4
*See Note 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G039
G038
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(1842.5 MHz, VCC_TK = 3.3 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2140 MHz, VCC_TK = 3.3 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 1842.5 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 2140 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 4
*See Note 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G037
G036
Figure 35.
Figure 36.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2600 MHz, VCC_TK = 3.3 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(3500 MHz, VCC_TK = 3.3 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 2600 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 3500 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 4
*See Note 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G033
G034
Figure 37.
Figure 38.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(4800 MHz, VCC_TK = 3.3 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(728 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 4800 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 728 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 4
*See Notes 2 and 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G035
G046
Figure 39.
Figure 40.
14
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(942.5 MHz, VCC_TK = 5 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(1842.5 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 942.5 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 1842.5 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 4
*See Notes 2 and 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G045
G044
Figure 41.
Figure 42.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2140 MHz, VCC_TK = 5 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(2600 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 2140 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 2600 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 4
*See Notes 2 and 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G043
G040
Figure 43.
Figure 44.
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(3500 MHz, VCC_TK = 5 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs TEMPERATURE
(4800 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 3500 MHz
Integer Mode (EN_FRAC = 0)
LO_Out = 4800 MHz
−70
−80
−70
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Notes 2 and 4
*See Notes 2 and 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G041
G042
Figure 45.
Figure 46.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
CLOSED-LOOP PHASE NOISE vs DIVIDE RATIO
(VCC_TK = 3.3 V, Integer Mode)
CLOSED-LOOP PHASE NOISE vs DIVIDE RATIO
(VCC_TK = 5 V, Integer Mode)
−60
−70
−60
−70
Integer Mode (EN_FRAC = 0)
VCO Frequency = 3600 MHz
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
Integer Mode (EN_FRAC = 0)
LO_Out = 3600 MHz
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−160
−170
−100
−110
−120
−130
−140
−150
−160
−170
*See Note 4
*See Notes 2 and 4
1k
10k
100k
1M
10M
40M
1k
10k
100k
1M
10M
40M
Frequency (Hz)
Frequency (Hz)
G047
G048
Figure 47.
Figure 48.
16
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
PFD SPURS vs TEMPERATURE
(Integer Mode)
MULTIPLES OF PFD SPURS
(Integer Mode)
−60
−65
−60
−65
TA = −40°C
TA = 25°C
TA = 85°C
PFD Spur 1x = 1.6 MHz
PFD Spur 2x = 3.2 MHz
PFD Spur 3x = 4.8 MHz
PFD Spur 4x = 6.4 MHz
−70
−70
−75
−75
−80
−80
−85
−85
−90
−90
−95
−95
−100
−105
−110
−115
−120
−125
−130
−100
−105
−110
−115
−120
−125
−130
Integer Mode (EN_FRAC = 0)
PFD Spur = 1.6 MHz
*See Note 4
*See Note 4
Integer Mode (EN_FRAC = 0)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (MHz)
Frequency (MHz)
G049
G050
Figure 49.
Figure 50.
MULTIPLES OF PFD SPURS
(LO_DIV = 8, Integer Mode)
MULTIPLES OF PFD SPURS
(LO_DIV = 4, Integer Mode)
−60
−65
−60
−65
PFD Spur /8 = 0.2 MHz
PFD Spur /4 = 0.4 MHz
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
PFD Spur /4 = 0.4 MHz
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
−70
−70
−75
−75
−80
−80
−85
−85
−90
−90
−95
−95
−100
−105
−110
−115
−120
−125
−130
−100
−105
−110
−115
−120
−125
−130
Integer Mode (EN_FRAC = 0)
LO_DIV = 8
Integer Mode (EN_FRAC = 0)
LO_DIV = 4
*See Note 4
350
*See Note 4
700
300
400 450 500
Frequency (MHz)
550
600
600
800 900 1000
Frequency (MHz)
1100
1200
G051
G052
Figure 51.
Figure 52.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
MULTIPLES OF PFD SPURS
(LO_DIV = 2, Integer Mode)
FRACTIONAL SPURS vs LO DIVIDER
−60
−65
−45
−50
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−55
−70
−60
−75
−65
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
−80
−70
−75
−85
−80
−90
−85
−95
−90
−100
−105
−110
−115
−120
−125
−130
−95
−100
−105
−110
−115
−120
−125
−130
Integer Mode (EN_FRAC = 0)
LO_DIV = 2
*See Notes 4 and 5
1200 1400 1600
*See Note 3
5M
1800
2000
2200
2400
0
10M
15M
20M
25M
30M
35M
Frequency (MHz)
Fractional PLL N Divider Value (NFRAC)
G053
G054
Figure 53.
Figure 54.
FRACTIONAL SPURS vs RF DIVIDER AND PRESCALER
FRACTIONAL SPURS vs TEMPERATURE
−60
−55
−60
TA = −40°C
PLL_DIV_SEL = 0 (Div1), PRSC_SEL = 1 (8/9)
PLL_DIV_SEL = 1 (Div2), PRSC_SEL = 1 (8/9)
−65
TA = 25°C
TA = 85°C
PLL_DIV_SEL = 2 (Div4), PRSC_SEL = 0 (4/5)
−70
−75
−65
Integer Mode (EN_FRAC = 0)
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
VCO Frequency = 2703.36 at Div1,8/9
VCO Frequency = 4730.88 at Div2,8/9
VCO Frequency = 3686.40 at Div4,4/5
−70
−80
−85
−75
−90
−80
−95
−85
−100
−105
−110
−115
−120
−125
−130
−90
−95
−100
−105
−110
*See Note 3
5M
*See Note 3
5M
0
10M
15M
20M
25M
30M
35M
0
10M
15M
20M
25M
30M
35M
Fractional PLL N Divider Value (NFRAC)
Fractional PLL N Divider Value (NFRAC)
G055
G056
Figure 55.
Figure 56.
18
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
MULTIPLES OF PFD SPURS
(Fractional Mode)
LO HARMONICS
−80
−82.5
−85
0
−5
1xPFD Spur = 30.72 MHz
2nd Harmonic
3rd Harmonic
4th Harmonic
2xPFD Spur = 61.44 MHz
3xPFD Spur = 92.16 MHz
4xPFD Spur = 122.88 MHz
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
−87.5
−90
−92.5
−95
−97.5
−100
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
*See Note 3
5M
*See Note 4
Integer Mode (EN_FRAC = 0)
0
10M
15M
20M
25M
30M
35M
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Fractional PLL N Divider Value (NFRAC)
LO_OUT Frequency (MHz)
G057
G058
Figure 57.
Figure 58.
OUTPUT POWER ON LO1_OUTP
WITH MULTIPLE BUFFERS
OUTPUT POWER
WITH MULTIPLE BUFFERS
7
6
7
6
TA = −40°C
TA = 25°C
TA = 85°C
PWD_BUFF1 = ON
PWD_BUFF1,2 = ON
PWD_BUFF1,2,3 = ON
PWD_BUFF1,2,3,4 = ON
5
5
4
4
3
3
2
2
1
1
0
0
−1
−2
−3
−1
−2
−3
*See Note 4
Integer Mode (EN_FRAC = 0)
*See Note 4
Integer Mode (EN_FRAC = 0)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
LO_OUT Frequency (MHz)
G059
G060
Figure 59.
Figure 60.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO_Out_1 (single ended), buffer 2, 3, 4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions section, and standard operating condition, unless otherwise noted.
OUTPUT POWER vs OUTPUT PORT
OUTPUT POWER vs BUFFER BIAS
7
6
8
7
BUFOUT_BIAS = 600µA
LO1_OUT
BUFOUT_BIAS = 500µA
BUFOUT_BIAS = 400µA
BUFOUT_BIAS = 300µA
LO2_OUT
LO3_OUT
LO4_OUT
6
5
5
4
4
3
2
3
1
2
0
−1
−2
−3
−4
−5
−6
−7
−8
1
0
−1
−2
−3
*See Note 4
Integer Mode (EN_FRAC = 0)
*See Note 4
Integer Mode (EN_FRAC = 0)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
LO_OUT Frequency (MHz)
G061
G062
Figure 61.
Figure 62.
VCO GAIN (Kv) vs FREQUENCY
−30
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
VCO_SEL = 0
VCO_SEL = 1
VCO_SEL = 2
VCO_SEL = 3
VTUNE_IN = 1V
CP_TRISTATE = 3
2000 2400 2800 3200 3600 4000 4400 4800 5200
VCO Frequency (MHz)
G063
Figure 63.
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SLWS230C –SEPTEMBER 2011–REVISED JANUARY 2012
SERIAL PROGRAMMING INTERFACE REGISTER DEFINITIONS
OVERVIEW
The TRF3765 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift
register. There are a total of three signals that must be applied: the clock (CLOCK, pin 4); the serial data (DATA,
pin 3); and the latch enable (STROBE, pin 5).
The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of CLOCK.
STROBE is asynchronous to the CLOCK signal; at its rising edge, the data in the shift register are loaded into
the selected internal register. Figure 64 shows the timing for the 4WI. Table 1 lists the 4WI timing for the write
operation.
t(CL)
tsu1
t(CLK)
th
t(CH)
1st
32nd
Write
Clock
Pulse
CLOCK
Write
Clock
Pulse
DB0 (LSB)
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB31 (MSB)
DB29
DB30
DATA
tsu3
tsu2
End of Write Cycle
Pulse
LATCH ENABLE
tw
Figure 64. 4WI Timing Diagram
Table 1. 4WI Timing: Write Operation
PARAMETER
MIN
MAX
UNITS
ns
th
Hold time, data to clock
Setup time, data to clock
Clock low duration
Clock high duration
Setup time, clock to enable
Clock period
20
20
20
20
20
50
50
70
tsu1
t(CH)
t(CL)
tsu2
t(CLK)
tw
ns
ns
ns
ns
ns
Enable time
ns
tsu3
Setup time, latch to data
ns
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PLL 4WI REGISTERS
Register 1
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Table 2. PLL 4WI Register 1
REGISTER ADDRESS
REFERENCE CLOCK DIVIDER
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
VCO
NEG
CP
DOUBLE
VCO CAL CLK
DIV/MULT
REF CLOCK DIV
Bit16 Bit17
RSV
REF INV
CHARGE PUMP CURRENT
Bit22 Bit23 Bit24
RSV
Bit18
Bit19
Bit20
Bit21
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
RDIV_0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
Bit1
Bit2
Register address bits
Bit3
Bit4
Bit5
Bit6
RDIV_1
Bit7
RDIV_2
Bit8
RDIV_3
Bit9
RDIV_4
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
RDIV_5
RDIV_6
13-bit Reference Divider value
RDIV_7
RDIV_8
RDIV_9
RDIV_10
RDIV_11
RDIV_12
RSV
Reserved
Invert Reference Clock polarity; 1 = use falling edge
REF_INV
NEG_VCO
ICP_0
VCO polarity control; 1= negative slope (negative KV)
ICP_1
Program Charge Pump dc current, ICP
1.94 mA, B[25..21] = [00 000]
0.65 mA, B[25..21] = [11 111]
ICP_2
0.97 mA, default value, B[25..21] = [01 010]
ICP_3
ICP_4
ICPDOUBLE
CAL_CLK_SEL_0
CAL_CLK _SEL_1
CAL_CLK _SEL_2
CAL_CLK _SEL_3
RSV
1 = Set ICP to double the current
Multiplication or division factor to create VCO calibration
clock from PFD frequency
Fastest clock, B[25..21] = [00 000]
Slowest clock, B[25..21] = [11 111]
Reserved
22
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CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the phase
detector frequency. Table 3 shows the calibration clock scale factors.
Table 3. Calibration Clock Scale Factors
CAL_CLK_SEL
1111
SCALING FACTOR
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1
1110
1101
1100
1011
1010
1001
1000
0110
2
0101
4
0100
8
0011
16
0010
32
0001
64
0000
128
ICP[4..0]: Set the charge pump current. Table 4 lists the charge pump current settings.
Table 4. Charge Pump Current Settings
ICP[4..0]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
CURRENT (mA)
1.94
1.76
1.62
1.49
1.38
1.29
1.21
1.14
1.08
1.02
0.97
0.92
0.88
0.84
0.81
0.78
0.75
0.72
0.69
0.67
0.65
0.63
0.61
0.59
0.57
0.55
0.54
0.52
0.51
0.5
0.48
0.47
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Register 2
Table 5. PLL 4WI Register 2
REGISTER ADDRESS
N-DIVIDER VALUE
Bit10 Bit11
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit12
Bit13
Bit14
Bit15
PRE-
SCALER
SELECT
VCO
SEL
MODE
PLL DIVIDER
SETTING
N-DIVIDER VALUE
RSV
RSV
VCO SELECT
Bit26 Bit27
CAL ACCURACY
EN CAL
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit28
Bit29
Bit30
Bit31
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
NINT_0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
Bit1
Bit2
Register address bits
Bit3
Bit4
Bit5
Bit6
NINT_1
Bit7
NINT_2
Bit8
NINT_3
Bit9
NINT_4
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
NINT_5
NINT_6
NINT_7
PLL N-divider division setting
NINT_8
NINT_9
NINT_10
NINT_11
NINT_12
NINT_13
NINT_14
NINT_15
PLL_DIV_SEL0
PLL_DIV_SEL1
PRSC_SEL
RSV
Select division ratio of divider in front of prescaler
Set prescaler modulus (0 → 4/5; 1 → 8/9)
Reserved
Reserved
RSV
VCO_SEL_0
VCO_SEL_1
VCOSEL_MODE
CAL_ACC_0
CAL_ACC_1
Selects between the four integrated VCOs
00 = lowest frequency VCO; 11= highest frequency VCO
Single VCO auto-calibration mode (1 = active)
Error count during the cap array calibration
Recommended programming [00].
Execute a VCO frequency auto-calibration. Set to '1' to
initiate a calibration. Resets automatically.
Bit31
EN_CAL
0
24
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PLL_DIV <1.0>: Select division ratio of divider in front of prescaler, according to Table 6.
Table 6. PLL_DIV Selection
PLL_DIV
FREQUENCY DIVIDER
00
01
10
1
2
4
VCOSEL_MODE: When VCOSEL_MODE is set to '1', the cap array calibration is executed on the VCO selected
through bits VCO_SEL[1:0].
Register 3
Table 7. PLL 4WI Register 3
REGISTER ADDRESS
FRACTIONAL N-DIVIDER VALUE
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit28
Bit13
Bit29
Bit14
Bit15
FRACTIONAL N-DIVIDER VALUE
Bit21 Bit22 Bit23 Bit24
RSV
RSV
Bit16
Bit17
Bit18
Bit19
Bit20
Bit25
Bit26
Bit27
Bit30
Bit31
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR_0
ADDR_1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit1
Bit2
ADDR_2
Register address bits
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
NFRAC<0>
NFRAC<1>
NFRAC<2>
NFRAC<3>
NFRAC<4>
NFRAC<5>
NFRAC<6>
NFRAC<7>
NFRAC<8>
NFRAC<9>
NFRAC<10>
NFRAC<11>
NFRAC<12>
NFRAC<13>
NFRAC<14>
NFRAC<15>
NFRAC<16>
NFRAC<17>
NFRAC<18>
NFRAC<19>
NFRAC<20>
NFRAC<21>
NFRAC<22>
NFRAC<23>
NFRAC<24>
RSV
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Fractional PLL N divider value
0 to 0.99999
Reserved
Reserved
RSV
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Register 4
Table 8. PLL 4WI Register 4
REGISTER ADDRESS
PD PLL
POWER-DOWN PLL BLOCKS
POWER-DOWN OUTPUT BUFFERS
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit27
Bit12
Bit13
Bit14
Bit15
EN
FRACT
MODE
EXT VCO
Bit16 Bit17
PLL TESTS CONTROL
Bit20 Bit21 Bit22
ΔΣ MOD ORDER
ΔΣ MOD CONTROLS
Bit28 Bit29 Bit30
Bit18
Bit19
Bit23
Bit24
Bit25
Bit26
Bit31
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR_0
ADDR_1
0
0
1
1
0
0
0
0
0
Bit1
Bit2
ADDR_2
Register address bits
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
PWD_PLL
PWD_CP
Power-down all PLL blocks (1 = off)
When 1, charge pump is off
Bit6
Bit7
PWD_VCO
PWD_VCOMUX
When 1, VCO is off
Bit8
Power-down the four VCO mux blocks (1 = off)
Power-down programmable RF divider in PLL feedback
path (1 = off)
Bit9
PWD_DIV124
0
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
PWD_PRESC
PWD_LO_DIV
PWD_BUFF_1
PWD_BUFF_2
PWD_BUFF_3
PWD_BUFF_4
EN_EXTVCO
0
1
1
1
1
1
0
Power-down programmable prescaler (1 = off)
Power-down LO divider block (1 = off)
Power-down LO output buffer 1 (1 = off)
Power-down LO output buffer 2 (1 = off)
Power-down LO output buffer 3 (1 = off)
Power-down LO output buffer 4 (1 = off)
Enable external VCO input buffer (1 = enabled)
Can be used to enable/disable an external VCO through
pin EXTVCO_CTRL (1 = high).
Bit17
Bit18
EXT_VCO_CTRL
EN_ISOURCE
0
0
Enable offset current at Charge Pump output (to be used
in Fractional mode only; 1 = on).
Bit19
Bit20
Bit21
LD_ANA_PREC_0
LD_ANA_PREC_1
CP_TRISTATE_0
0
0
0
Control precision of analog lock detector
1 = low; 0 = high
Set the charge pump output into 3-state mode.
Normal, B[22..21] = [00]
Down, B[22..21] = [01]
Up, B[22..21] = [10]
Bit22
CP_TRISTATE_1
0
3-state, B[22..21] = [11]
Speed up PLL block by bypassing bias stabilizer
capacitors.
Bit23
Bit24
SPEEDUP
0
0
Lock detector precision
(increases sampling time if set to 1)
LD_DIG_PREC
Bit25
Bit26
EN_DITH
1
0
Enable ΔΣ modulator dither (1 = on)
MOD_ORD_0
ΔΣ modulator order (1 through 4). Not used in Integer
mode.
First order, B[27..26] = [00]
Second order, B[27..26] = [01]
Third order, B[27..26] = [10]
Fourth order, B[27..26] = [11]
Bit27
MOD_ORD_1
1
Select dither mode for ΔΣ modulator
(0 = pseudo-random; 1 = constant)
Bit28
DITH_SEL
0
Bit29
Bit30
Bit31
DEL_SD_CLK_0
DEL_SD_CLK_1
EN_FRAC
0
1
0
ΔΣ modulator clock delay. Not used in Integer mode.
Min delay = 00; Max delay = 11
Enable Fractional mode (1 = fractional enabled)
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Register 5
Table 9. PLL 4WI Register 5
REGISTER ADDRESS
VCO_R_TRIM
PLL_R_TRIM
VCO CURRENT
Bit11 Bit12
VCOBUF BIAS
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit13
Bit14
Bit15
BIAS
SEL
VCO BIAS
VOLTAGE
EN_LD
ISRC
VCOMUX BIAS
OUTBUF BIAS
RSV
RSV
VCO CAL REF
VCOMUX AMPL
Bit26 Bit27
RSV
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit28 Bit29
Bit30
Bit31
BIT NUMBER
Bit0
BIT NAME
ADDR_0
RESET VALUE
DESCRIPTION
1
0
1
1
0
0
0
1
0
1
0
0
0
Bit1
ADDR_1
Bit2
ADDR_2
Register address bits
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
VCOBIAS_RTRIM_0
VCOBIAS_RTRIM_1
VCOBIAS_RTRIM_2
PLLBIAS_RTRIM_0
PLLBIAS_RTRIM_1
VCO_BIAS_0
VCO_BIAS_1
VCO_BIAS_2
VCO bias resistor trimming.
Recommended programming [100].
Bit6
Bit7
Bit8
PLL bias resistor trimming.
Recommended programming [10].
Bit9
Bit10
Bit11
Bit12
VCO bias reference current.
300 μA, B[13..10] = [00 00]
600 μA, B[13..10] = [11 11]
Bias current varies directly with reference current
Recommended programming:
400 μA, B[13..10] = [0101] with VCC_TK = 3.3 V
600 μA, B[13..10] = [1111] with VCC_TK = 5.0V
Bit13
Bit14
VCO_BIAS_3
1
0
VCOBUF_BIAS_0
VCO buffer bias reference current.
300 μA, B[15..14] = [00]
600 μA, B[15..14] = [11]
Bias current varies directly with reference current
Recommended programming [10]
Bit15
Bit16
Bit17
VCOBUF _BIAS_1
VCOMUX_BIAS_0
VCOMUX _BIAS_1
1
0
1
VCO muxing buffer bias reference current.
300 μA, B[17..16] = [00]
600 μA, B[17..16] = [11]
Bias current varies directly with reference current
Recommended programming [10]
Bit18
Bit19
BUFOUT_BIAS_0
BUFOUT_BIAS_1
1
0
PLL output buffer bias reference current.
300 μA, B[19..18] = [00]
600 μA, B[19..18] = [11]
Bias current varies directly with reference current
Bit20
Bit21
RSV
RSV
0
1
Reserved
Reserved
Select bias current type for VCO calibration circuitry
0 = PTAT; 1 = constant over temperature.
Recommended programming [0].
Bit22
VCO_CAL_IB
0
Bit23
Bit24
Bit25
VCO_CAL_REF_0
VCO_CAL_REF_1
VCO_CAL_REF_2
0
0
1
VCO calibration reference voltage trimming.
0.9 V, B[25..23] = [000]
1.4 V, B[25..23] = [111]
Recommended programming 1.11 V, B[25..23] = [011]
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BIT NUMBER
BIT NAME
RESET VALUE
DESCRIPTION
Bit26
VCO_AMPL_CTRL_0
0
Adjust the signal amplitude at the VCO mux input.
[00] = maximum voltage swing
[11] = minimum voltage swing
Recommended programming [11]
Bit27
Bit28
VCO_AMPL_CTRL_1
VCO_VB_CTRL_0
1
0
VCO core bias voltage control
1.2 V, B[29..28] = [00]
1.35 V, B[29..28] = [01]
1.5 V, B[29..28] = [10]
1.65 V, B[29..28] = [11]
Recommended programming [01]
Bit29
Bit30
VCO_VB_CTRL _1
RSV
1
0
Reserved
Enable monitoring of LD to turn on ISOURCE when in
frac-n mode (EN_FRAC=1).
Bit31
EN_LD_ISOURCE
1
0 = ISOURCE set by EN_ISOURCE
1 = ISOURCE set by LD
Recommended programming [0]
Register 6
Table 10. PLL 4WI Register 6
VCO
LD
TEST
CAL
REGISTER ADDRESS
RSV
RSV
VCO CAP ARRAY CONTROL
MODE
MODE
BYPASS
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
VCO
BIAS
SEL
ISRC
SINK
MUX CONTROL
Bit17
OFFSET CURRENT ADJUST
Bit20 Bit21 Bit22
LO DIV
LO DIV BIAS
VCO MUX BIAS
Bit27 Bit28
DC OFF REF
Bit16
Bit18
Bit19
Bit23
Bit24
Bit25
Bit26
Bit29
Bit30
Bit31
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR_0
ADDR_1
0
1
1
1
0
0
0
0
0
0
0
0
1
Bit1
Bit2
ADDR_2
Register address bits
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
RSV
Reserved
Reserved
Bit6
RSV
Bit7
VCO_TRIM_0
VCO_TRIM_1
VCO_TRIM_2
VCO_TRIM_3
VCO_TRIM_4
VCO_TRIM_5
Bit8
Bit9
VCO capacitor array control bits; used in manual cal mode
Bit10
Bit11
Bit12
Initiate automatic calibration if LD indicates loss of lock.
(1 = Initiate calibration if LD is low)
Bit13
Bit14
EN_LOCKDET
0
0
Counter mode: measure maximum/minimum frequency of each
VCO
VCO_TEST_MODE
Bypass of VCO auto-calibration. When '1', VCO_TRIM and
VCO_SEL bits are used to select the VCO and the capacitor array
setting
Bit15
CAL_BYPASS
0
Bit16
Bit17
MUX_CTRL_0
MUX_CTRL_1
1
0
Select signal for test output (pin 5, LD).
[000] = Ground
[001] = Lock detector
[010] = NDIV counter output
[011] = Ground
[100] = RDIV counter output
[101] = Ground
[110] = A_counter output
[111] = Logic high
Bit18
Bit19
MUX_CTRL_2
0
0
Charge pump offset current polarity. 0 = source
ISOURCE current enabled by EN_ISOURCE.
Recommended programming [0].
ISOURCE_SINK
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BIT NUMBER
Bit20
BIT NAME
RESET VALUE
DESCRIPTION
ISOURCE_TRIM_0
ISOURCE_TRIM_1
ISOURCE_TRIM_2
LO_DIV_SEL_0
0
0
1
0
Adjust ISOURCE bias current.
Minimum value, ISOURCE_TRIM = 0, B[22..20] = [000]
Maximum value, ISOURCE_TRIM = 7, B[22..20] = [111]
ISOURCE current enabled by EN_ISOURCE.
Bit21
Bit22
Bit23
Adjust LO path divider
Divide-by-1, [B24..23] = [00]
Divide-by-2, [B24..23] = [01]
Divide-by-4, [B24..23] = [10]
Divide-by-8, [B24..23] = [11]
Bit24
Bit25
Bit26
Bit27
LO_DIV_SEL_1
LO_DIV_IB_0
0
0
0
0
Adjust LO divider bias current. [B26..25] =
[00] = 25 μA
[01] = 50 μA
[10] = 75 μA
[11] = 100 μA
LO_DIV_IB_1
DIV_MUX_REF<0>
Sets reference bias current of DIV_MUX buffer when bit 31=1;
[00] = 200 μA
[01] = 300 μA
[10] = 400 μA
[11] = 500 μA
Recommended programming [10]
Bit28
Bit29
Bit30
DIV_MUX_REF<1>
DIV_MUX_OUT<0>
DIV_MUX_OUT<1>
1
0
1
Set multiply factor for DIV_MUX_REF current.
x16, B[30..29] = 00
x24, B[30..29] = 01
x32, B[30..29] = 10
x40, B[30..29] = 11
Recommended programming [10]
Overrides DIV_MUX auto-bias current control.
When set to '1', DIV_MUX bias current is set by [B30..27].
Bit31
DIV_MUX_BIAS_OVRT
0
READBACK MODE
Register 0 functions as a readback register. The TRF3765 implements the capability to read back the content of
any serial programming interface register by initializing Register 0.
Each read-back operation consists of two phases: a write followed by the actual reading of the internal data. This
sequence is described in the timing diagram (see Figure 65). During the write phase, a command is sent to
TRF3765 Register 0 to set it to readback mode and to specify which register is to be read. In the proper reading
phase, at each rising clock edge, the internal data are transferred to the READBACK pin where it can be read at
the following falling edge (LSB first). The first clock after the latch enable STROBE, pin 5, goes high (that is, the
end of the write cycle) is idle and the following 32 clock pulses transfer the internal register contents to the
READBACK pin (pin 6).
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tsu1
t(CLK)
t(CL)
th
t(CH)
1st Write
Clock
Pulse
31st
Write
Clock
Pulse
CLOCK
DATA
DB0 (LSB)
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB31 (MSB)
DB29
DB30
LATCH ENABLE
CLOCK
tsu3
32nd
1st Read
Clock
Pulse
2nd Read
Clock
Pulse
32nd
Read
Clock
Pulse
33rd
Read
Clock
Pulse
Write
Clock
Pulse
End of Write Cycle
Pulse
td
LATCH ENABLE
tsu2
tw
Readback
Data Bit0
Readback
Data Bit30
Readback
Data Bit31
Read
back
Read
back
READBACK DATA
Data
Bit1
Data
Bit29
Figure 65. 4WI Readback Timing Diagram
Table 11 lists the readback timing parameters.
Table 11. Readback 4WI Timing
PARAMETER
MIN
MAX
UNITS
COMMENTS
Hold time, data to clock
Setup time, data to clock
Clock low duration
th
tsu1
t(CH)
t(CL)
tsu2
tsu3
td
20
20
20
20
20
20
10
50
50
ns
ns
ns
ns
ns
Clock high duration
Setup time, clock to enable
Setup time, enable to Readback clock
Delay time, clock to Readback data output
Enable time
ns
ns
ns
tw
Equals Clock period
Clock period
t(CLK)
READBACK FROM THE INTERNAL REGISTER BANKS
The TRF3765 integrates eight registers: Register 0 (000) to Register 7 (111). Registers 1 through 6 are used to
set up and control the TRF3765 functions, Register 7 is used for factory functions, and Register 0 is used for the
readback function.
Register 0 must be programmed with a specific command that sets the TRF3765 into readback mode and
specifies the register to be read, according to the following parameters:
•
•
•
Set B[31] to '1' to put TRF3765 into readback mode.
Set B[30,28] equal to the address of the register to be read ('000' to '111').
Set B27 to control the VCO frequency counter in VCO test mode.
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REGISTER 0
Table 12. Register 0 Write
REGISTER ADDRESS
N/C
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit28
Bit13
Bit14
Bit15
COUNT_
MODE_
MUX_SEL
RB_
ENABLE
N/C
Bit21
RB_REG
Bit16
Bit17
Bit18
Bit19
Bit20
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit29
Bit30
Bit31
Register 0 Write
TYPE
BIT NUMBER
Bit0
BIT NAME
RESET VALUE
DESCRIPTION
ADDR<0>
ADDR<1>
ADDR<2>
ADDR<3>
ADDR<4>
N/C
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit1
Register 0 to be programmed to set the TRF3765 into
readback mode.
Address
Bit2
Bit3
Bit4
Bit5
Bit6
N/C
Bit7
N/C
Bit8
N/C
Bit9
N/C
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Data
Field
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Select Readback for VCO maximum frequency or
minimum frequency.
0 = Maximum
COUNT_MODE
_MUX_SEL
Bit27
0
1 = Minimum
Bit28
Bit29
Bit30
Bit31
RB_REG<0>
RB_REG<1>
RB_REG<2>
RB_ENABLE
X
X
X
1
Three LSBs of the address for the register that is
being read
Register 1, B[30..28] = [000]
Register 7, B[30..28] = [111]
1 → Put the device into readback mode
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Register 0 Read
Table 13. Register 0 Read
R_SAT_
ERR
REGISTER ADDRESS
CHIP_ID
NOT USED
COUNT0-7/VCO_TRIM
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
COUNT8
COUNT
MODE
MUX_SEL
/
COUNT9-
10/VCO_SEL
COUNT0-7/VCO_TRIM
NU
COUNT11-17
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22 Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
RESET
VALUE
BIT NUMBER
BIT NAME
DESCRIPTION
Bit0
Bit1
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
CHIP_ID
NU
0
0
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit2
Register address bits
Bit3
Bit4
Bit5
Bit6
Bit7
NU
Bit8
NU
Bit9
NU
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
NU
NU
R_SAT_ERR
count_0/NU
count_1/NU
Error flag for calibration speed
count_2/VCO_TRIM_0
count_3/VCO_TRIM_1
count_4/VCO_TRIM_2
count_5/VCO_TRIM_3
count_6/VCO_TRIM_4
count_7/VCO_TRIM_5
count_8/NU
B[30..13] = VCO frequency counter high when
COUNT_MODE_MUX_SEL = 0 and
VCO_TEST_MODE = 1
B[30..13] = VCO frequency counter low when
COUNT_MODE_MUX_SEL = 1 and
VCO_TEST_MODE = 1
B[20..15] = Autocal results for VCO_TRIM
B[23..22] = Autocal results for VCO_SEL when
VCO_TEST_MODE = 0
count_9/VCO_sel_0
count_10/VCO_sel_1
count<11>
count<12>
count<13>
count<14>
count<15>
count<16>
count<17>
0 = Minimum frequency
1 = Maximum frequency
Bit31
COUNT_MODE_MUX_SEL
x
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APPLICATION INFORMATION
INTEGER AND FRACTIONAL MODE SELECTION
The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO)
frequency is an integer multiple of the phase frequency detector (PFD) frequency, fPFD, then Integer mode can be
selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer
mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the
register bits corresponding to the fractional control are don’t care.
In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional
resolution, RF stepsize fPFD/225 is less than 1 Hz with a fPFD up to 33 MHz. The appropriate fractional control bits
in the serial register must be programmed.
PLL ARCHITECTURE
Figure 66 shows a block diagram of the PLL loop.
EXT_VCO
LO1
VCO0
LO2
fREF
fPFD
Divide by
R
Phase Frequency
Detector and
Charge Pump
REFIN
Loop Filter
Z(f)
Divide-by
1/2/4/8
VCO1
VCO2
VCO3
CP_OUT
VTUNE
LO3
LO4
fVCO
fCOMP
RF
Divider
Dig Divider
fN
Prescaler
4/5 or 8/9
Divide-by
1/2/4
Divide-by
NF
NINT and NFRAC Dividers
Figure 66. PLL Loop
The output frequency is given by Equation 1:
fREF
NFRAC
225
fVCO
=
(PLL_DIV_SEL) NINT +
RDIV
(1)
The rate at which phase comparison occurs is fREF/RDIV. In Integer mode, the fractional setting is ignored and
Equation 2 is applied.
fVCO
= NINT ´ PLL_DIV_SEL
fPFD
(2)
The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The
prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an
M counter.
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Selecting PLL Divider Values
Operation of the PLL requires the LO_DIV_SEL, RDIV, PLL_DIV_SEL, NINT, and NFRAC bits to be calculated.
The LO or mixer frequency is related to fVCO according to divide-by-1/-2/-4/-8 blocks and the operating range of
fVCO
.
a. LO_DIV_SEL
1
2
3
4
2400 MHz £ fRF £ 4800 MHz
1200 MHz £ fRF £ 2400 MHz
600 MHz £ fRF £ 1200 MHz
300 MHz £ fRF £ 600 MHz
LO_DIV_SEL =
Therefore:
fVCO = LO_DIV_SEL ´ fRF
b. PLL_DIV_SEL
Given fVCO, select the minimum value for PLL_DIV_SEL so that the programmable RF divider limits the input
frequency into the prescaler block, fPM, to a maximum of 3000 MHz.
PLL _ DIV _ SEL = min(1, 2, 4) such that fPM ≤ 3000 MHz
This calculation can be restated as Equation 3.
LO_DIV_SEL ´ fRF
PLL_DIV_SEL = Ceiling
3000 MHz
(3)
Higher values of fPFD correspond to better phase noise performance in Integer mode or Fractional mode.
fPFD, along with PLL_DIV_SEL, determines the fVCO stepsize in Integer mode. Therefore, in Integer mode,
select the maximum fPFD that allows for the required RF stepsize, as shown by Equation 4.
fVCO, Stepsize
f
RF, Stepsize ´ LO_DIV_SEL
=
fPFD
=
PLL_DIV_SEL
PLL_DIV_SEL
(4)
In Fractional mode, a small RF stepsize is accomplished through the Fractional mode divider. A large fPFD
should be used to minimize the effects of fractional controller noise in the output spectrum. In this case, fPFD
may vary according to the reference clock and fractional spur requirements; for example, fPFD = 20 MHz.
c. RDIV, NINT, NFRAC, PRSC_SEL
fREF
RDIV =
fPFD
fVCORDIV
NINT = floor
fREFPLL_DIV_SEL
fVCORDIV
NFRAC = floor
- NINT 225
(
fREFPLL_DIV_SEL
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The P/(P+1) programmable prescaler is set to 8/9 or 4/5 through the PRSC_SEL bit. To allow proper
fractional control, set PRSC_SEL according to Equation 5.
8
9
NINT ³ 75 in Fractional Mode or NINT ³ 72 in Integer mode
PRSC_SEL =
4
23 £ NINT < 75 in Fractional mode or 20 £ NINT < 72 in Integer mode
5
(5)
The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode,
the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of
PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum frequency to be
input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown
by Equation 6.
fVCO
fN,Max
=
PLL_DIV_SEL ´ P
(6)
Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz,
choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.
Setup Example for Integer Mode
Suppose the following operating characteristics are desired for Integer mode operation:
•
•
•
fREF = 40 MHz (reference input frequency)
Step at RF = 2 MHz (RF channel spacing)
fRF = 1600 MHz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
•
•
LO_DIV_SEL = 2
fVCO = LO_DIV_SEL × 1600 MHz = 3200 MHz
In order to keep the frequency of the prescaler below 3000 MHz:
PLL_DIV_SEL = 2
The desired stepsize at RF is 2 MHz, so:
•
•
•
fPFD = 2 MHz
fVCO, stepsize = PLL_DIV_SEL × fPFD = 4 MHz
Using the reference frequency along with the required fPFD gives:
•
•
RDIV = 20
NINT = 800
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
This example shows that Integer mode operation gives sufficient resolution for the required stepsize.
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Setup Example for Fractional Mode
Suppose the following operating characteristics are desired for Fractional mode operation:
•
•
•
fREF = 40 MHz (reference input frequency)
Step at RF = 5 MHz (RF channel spacing)
fRF = 1,600,000,045 Hz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
•
•
LO_DIV_SEL = 2
fVCO = LO_DIV_SEL × 1,600,000,045 Hz = 3,200,000,090 Hz
In order to keep the frequency of the prescaler below 3000 MHz:
PLL_DIV_SEL = 2
Using a typical fPFD of 20 MHz:
•
•
•
•
RDIV = 20
NINT = 80
NFRAC = 75
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
The actual frequency at RF is:
•
fRF = 1600000044.9419 Hz
For a frequency error of –0.058 Hz.
Fractional Mode Setup
Optimal operation of the PLL in Fractional mode requires several additional register settings. Recommended
values are listed in Table 14. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and
ISOURCE_TRIM values according to the chosen frequency band.
Table 14. Fractional Mode Register Settings
REGISTER BIT
EN_ISOURCE
REGISTER ADDRESSING
Reg4B18
RECOMMENDED VALUE
1
EN_DITH
Reg4B25
1
MOD_ORD
Reg4B[27..26]
Reg4B28
B[27..26] = [10]
DITH_SEL
0
DEL_SD_CLK
EN_FRAC
Reg4B[30..29]
Reg4B31
B[30..29] = [10]
1
0
0
EN_LD_ISOURCE
ISOURCE_SINK
Reg5B31
Reg6B19
B[22..20] = [100] or [111]; see
Typical Characteristics
ISOURCE_TRIM
ICPDOUBLE
Reg6B[22..20]
Reg1B26
0
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SELECTING THE VCO AND VCO FREQUENCY CONTROL
To achieve a broad frequency tuning range, the TRF3765 includes four VCOs. Each VCO is connected to a bank
of coarse tuning capacitors that determine the valid operating frequency of each VCO. For any given frequency
setting, the appropriate VCO and capacitor array must be selected.
The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to
initiate the calibration algorithm. During the calibration process, the device selects a VCO and a tuning capacitor
state such that VTUNE matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the resulting tuning
word is increased through bits CAL_ACC_n at the expense of increased calibration time. A calibration begins
immediately when EN_CAL is set; as a result, all registers must contain valid values before a calibration is
initiated.
The calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled
according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequencies enable faster calibrations, but the logic
is limited to clock frequencies up to 600 kHz. The flag R_SAT_ERR is evaluated during the calibration process to
indicate calibration counter overflow errors, which occur if CAL_CLK runs too quickly. If R_SAT_ERR is set
during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK.
CAL_CLK frequencies should not be set below 0.05 MHz. Reference clock frequency is usually limited by the
calibration logic. fREF × CAL_CLK_SEL scaling factor > 0.01 MHz and fREF/(CAL_CLK_SEL scaling factor × fPFD
)
< 8000 are required. For example, with fREF = 61.44 MHz, fPFD = 30.72 MHz and CAL_CLK_SEL at 1/128,
61.44/128 = 0.5 > 0.01 and 61.44/(30.72 × 1/128) = 256 < 8000.
When VCOSEL_MODE is '0', the device automatically selects both the VCO and capacitor bank within 46
CAL_CLK cycles. When VCOSEL_MODE is '1', the device uses the VCO selected in VCO_SEL_0 and
VCO_SEL_1 and automatically selects the capacitor array within 34 CAL_CLK cycles. The VCO and capacitor
array settings that result from a calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in
Registers 2 and 7. These settings can only be read from Register 0.
Automatic calibration can be disabled by setting CAL_BYPASS to '1'. In this manual calibration mode, the VCO is
selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits
VCO_TRIM_n. Calibration modes are summarized in Table 15. After calibration is complete, the PLL is released
from calibration mode and reaches phase lock.
Table 15. VCO Calibration Modes
MAX CYCLES
CAL_CLK
CAPACITOR
ARRAY
CAL_BYPASS
VCOSEL_MODE
VCO
0
0
1
0
1
46
34
Automatic
VCO_SEL_n
VCO_SEL_n
Automatic
don't care
N/A
VCO_TRIM_n
During the calibration process, the TRF3765 scans through many frequencies. RF and LO outputs should be
disabled until calibration is complete. At power-up, the RF and LO output are disabled by default. Once a
calibration has been performed at a given frequency setting, the calibration remains valid over all operating
temperature conditions.
EXTERNAL VCO
An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered
external signal instead of an internal VCO. Dividers, phase-frequency detector, and charge pump remain enabled
and may be used to control VTUNE or an external VCO. NEG_VCO must correspond to the sign of the external
VCO tuning characteristic. EXT_VCO_CTRL = '1' asserts a logic 1 output level at the corresponding output pin.
This configuration can be used to enable or disable the external VCO circuit or module.
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VCO_TEST_MODE
Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by
disconnecting the charge pump input from the phase detector and loop filter, and forcing its output high or low.
The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.
VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in Register
0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur
during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL. Table 16 summarizes the
settings for VCO_TEST_MODE.
Table 16. VCO_TEST_MODE Settings
VCO_TEST_MODE
COUNT_MODE_MUX_SEL
VCO OPERATION
REGISTER 0 B[30..13]
B[30..24] = undefined
B[23..22] = VCO_SEL selected during autocal
B21 = undefined
0
Don't care
Normal
B[20..15] = VCO_TRIM selected during autocal
B[14..13] = undefined
1
1
0
1
Max frequency
Min frequency
B[30..13] = Max frequency counter
B[30..13] = Min frequency counter
LOOP FILTER
Loop filter design is critical for achieving low closed-loop phase noise. Some typical loop filter component values
are given in Table 17, referenced to designators in Figure 67. These loop filters are designed using a charge
pump current of 1.94 mA to minimize noise.
Table 17. Typical Loop Filter Components
fPFD (MHz)
1.6
C1 (pF)
47
C2 (pF)
560
R2 (kΩ)
10
C3 (pF)
4.7
R3 (kΩ)
5
C4 (pF)
open
R4 (kΩ)
0
30.72
2200
22000
0.47
220
0.47
220
0.47
R3
R4
CP_OUT
VTUNE_IN
C1
C2
C3
C4
R2
CP_REF
VTUNE_REF
Figure 67. Loop Filter Component Reference Designators
LOCK DETECT
The lock detect signal is generated in the phase frequency detector by comparing the VCO target phase against
the VCO actual phase. When the two compared phase signals remain aligned for several clock cycles, an
internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This
internal signal is then averaged and compared against a reference voltage to generate the LD signal. The
number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked,
LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.
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By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL_n can
be used to control a multiplexer to output other diagnostic signals on the LD output. The LD control signals are
shown in Table 18. Table 19 shows the LD Control Signal Mode settings.
Table 18. LD Control Signals
ADJUSTMENT
Lock detect precision
Unlock detect precision
LD averaging count
Diagnostic output
REGISTER BITS
LD_ANA_PREC_0
LD_ANA_PREC_1
LD_DIG_PREC
MUX_CTRL_n
BIT ADDRESSING
Reg4B19
Reg4B20
Reg4B24
Reg6B[18..16]
Table 19. LD Control Signal Mode Settings
CONDITION
RECOMMENDED SETTINGS
LD_ANA_PREC_0 = 0
LD_ANA_PREC_1 = 0
LD_DIG_PREC = 0
Integer mode
LD_ANA_PREC_0 = 1
LD_ANA_PREC_1 = 1
LD_DIG_PREC = 0
Fractional mode
LO DIVIDER
The LO divider is shown in Figure 68. It frequency divides the VCO output. Only one of the dividers operates at a
time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SEL_n. The
output is buffered and provided on output pins LOn_OUT_P and LOn_OUT_N. Outputs are phase-locked but not
phase-matched. The output level is controlled through BUFOUT_BIAS.
BUFOUT_BIAS
LO_OUT1
DIV8
DIV4
DIV2
DIV1
PWD1
PWD2
PWD3
PWD_LO_DIV
LO_OUT2
VCO, P/N
Buffer
Div2
LO_OUT3
LO_OUT4
Div4
Div8
Speedup
Bias
LO_DIV_IB
PWD4
Figure 68. LO Divider
LO_DIV_IB determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a
stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should
be disabled during normal operation.
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POWER-SUPPLY DISTRIBUTION
Power-supply distribution for the TRF3765 is shown in Table 20. Proper isolation and filtering of the supplies are
critical for low phase noise operation of the device. Each supply pin should be supplied with local decoupling
capacitance and isolated with a ferrite bead.
Table 20. Power-Supply Distribution
PIN
SUPPLY
BLOCKS
Fractional divider
N-Divider
2
VCC_DIG
LO_OUT buffers
7
VCC_DIV
LO 1/2/4/8 divider
VCO tank
VCO bias
Charge pump
4WI
20
21
27
VCC_TK
VCC_OSC
VCC_CP
LD
Prescaler
REF_IN buffer
ISource
28
VCC_PLL
RF-Divider
R-Divider
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APPLICATION SCHEMATIC
Figure 69 illustrates a typical application schematic for the TRF3765. Table 21 lists the pin termination
requirements and interfacing for the circuit.
+3.3 V
+3.3 V
FB
1 kW
FB
1 kW
Loop
Filter
R3
C3
R4
C4
4.7 pF
1 mF
1 mF
4.7 pF
C1
C2
R2
22 pF
REF_IN
LD
+3.3 V/
5.0 V
+3.3 V
FB
1 kW
FB
1 kW
1 mF
10 nF
27 pF
GND_DIG
VCC_DIG
VTUNE_REF
VTUNE_IN
GND_OSC
VCC_OSC
VCC_TK
4.7 pF
10 nF
1 mF
DATA
CLOCK
DATA
+3.3 V
CLOCK
STROBE
FB
1 kW
+3.3 V
STROBE
READBACK
VCC_DIV
FB
1 kW
EXTVCO_CTRL
EXTVCO_IN
READBACK
EXTVCO_CTRL
EXTVCO_IN
4.7 pF
10 nF
1 mF
GND_BUFF1
GND_BUFF2
4.7 pF
1 mF
10 nF
4.7 pF
+3.3 V
+3.3 V
FB
1 kW
FB
1 kW
1 mF
10 nF
27 pF
27 pF
10 nF
1 mF
100 W
100 W
100 W
100 W
47 pF
47 pF
LO1_OUTP
LO1_OUTM
LO4_OUTP
LO4_OUTM
+3.3 V
+3.3 V
FB
1 kW
FB
1 kW
47 pF
47 pF
1 mF
10 nF
27 pF
27 pF
10 nF
1 mF
100 W
100 W
100 W
100 W
47 pF
47 pF
LO2_OUTP
LO2_OUTM
LO3_OUTP
LO3_OUTM
47 pF
47 pF
Figure 69. TRF3765 Application Schematic
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Table 21. Pin Termination Requirements and Interfacing
PIN
3
NAME
DATA
DESCRIPTION
4WI data input: digital input, high impedance
4WI clock input: digital input, high impedance
4WI latch enable: digital input, high impedance
4
CLOCK
STROBE
5
Readback output; digital output pins can source or sink up to 8 mA
of current
6
READBACK
Local oscillator output: open-collector output. A pull-up resistor is
required, normally ac-coupled. Any unused output differential pairs
may be left open.
9 through 16
LO_OUT
18
19
30
32
EXTVCO_IN
EXTVCO_CTRL
REF_IN
External local oscillator input: high impedance, normally ac-coupled
Power-down control pin for optional external VCO; digital output pins
can source or sink up to 8 mA of current
Reference clock input: high impedance, normally ac-coupled
Lock detector digital output, as configured by MUX_CTRL; digital
output pins can source or sink up to 8 mA of current
LD
APPLICATION LAYOUT
Layout of the application board significantly impacts the analog performance of the TRF3765 device. Noise and
high-speed signals should be prevented from leaking onto power-supply pins or analog signals. Follow these
recommendations:
1. Place supply decoupling capacitors physically close to the device, on the same side of the board. Each
supply pin should be isolated with a ferrite bead.
2. Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
3. The pad on the bottom of the device must be electrically grounded. Connect GND pins directly to the pad on
the surface layer. Connect the GND pins and pad directly to surface ground where possible.
4. Power planes should not overlap each other or high-speed signal lines.
5. Isolate REF_IN routing from loop filter lines, control lines, and other high-speed lines.
See Figure 70 for an example of critical component layout (for the top PCB layer).
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Figure 70. Layout of Critical TRF3765 Components
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2011) to Revision C
Page
•
Changed Reference Oscillator Parameters, Reference input impedance parameter rows in Electrical Characteristics
table ...................................................................................................................................................................................... 3
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TRF3765IRHBR
TRF3765IRHBT
ACTIVE
ACTIVE
QFN
QFN
RHB
RHB
32
32
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TRF3765IRHBR
TRF3765IRHBT
QFN
QFN
RHB
RHB
32
32
3000
250
330.0
330.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TRF3765IRHBR
TRF3765IRHBT
QFN
QFN
RHB
RHB
32
32
3000
250
338.1
338.1
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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