TS3L110RGYR [TI]
QUAD SPDT HIGH BANDWIDTH 10/100 BASE T LAN SWITCH DIFFERENTIAL 8 CHANNEL TO 4 CHANNEL MULTIPLEXER; QUAD SPDT高带宽10/100 BASE T LAN SWITCH差分8通道与4通道多路复用器
| 型号： | TS3L110RGYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD SPDT HIGH BANDWIDTH 10/100 BASE T LAN SWITCH DIFFERENTIAL 8 CHANNEL TO 4 CHANNEL MULTIPLEXER |
| 文件： | 总18页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒꢄ ꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢉꢌ ꢕ ꢕꢓ ꢖꢓ ꢐꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋꢈ ꢐꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀꢌ ꢊ ꢃꢓ ꢛꢓ ꢖ
SCDS176 − SEPTEMBER 2004
D
D
D
D
D
D
D
Wide Bandwidth (BW = 500 MHz Typ)
Low Crosstalk (X = −30 dB Typ)
D
D
D
Data and Control Inputs Have Undershoot
Clamp Diodes
TALK
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low and Flat ON-State Resistance
(r = 4 W Typ, r
= 1 W)
on
on(flat)
Switching on Data I/O Ports (0 to 5 V)
− 1000-V Charged-Device Model (C101)
V
Operating Range From 3 V to 3.6 V
CC
D
Suitable for Both 10 Base-T/100 Base-T
Signaling
I
Supports Partial-Power-Down Mode
off
Operation
RGY PACKAGE
(TOP VIEW)
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
ID
ID
YD
IC
S
CC
1
16
IA
0
IA
IA
15
14
13
12
11
10
2
3
4
5
6
7
E
ID
ID
YD
IC
0
1
1
0
YA
IA
1
0
1
IB
YA
0
IB
1
YB
IB
0
0
IC
1
YC
IB
1
YB
0
GND
IC
1
8
9
description/ordering information
The TI TS3L110 LAN switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (E) input.
When E is low, the switch is enabled, and the I port is connected to the Y port. When E is high, the switch is
disabled, and the high-impedance state exists between the I and Y ports. The select (S) input controls the data
path of the multiplexer/demultiplexer.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Tape and reel
Tube
TS3L110RGYR
TK110
TS3L110D
TS3L110
TK110
Tape and reel
TS3L110DR
TS3L110DBQR
TS3L110PW
TS3L110PWR
TS3L110DGVR
SSOP (QSOP) − DBQ Tape and reel
Tube
−40°C to 85°C
TSSOP − PW
TK110
TK110
Tape and reel
TVSOP − DGV
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ
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ꢉ ꢌꢕ ꢕ ꢓꢖ ꢓꢐ ꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐ ꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋ ꢈꢐ ꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖ
SCDS176 − SEPTEMBER 2004
description/ordering information (continued)
This device can be used to replace mechanical relays in LAN applications. This device has low and flat r , wide
on
bandwidth, and low crosstalk, making it suitable for 10 Base-T, 100 Base-T, and various other LAN applications.
The device can be used to route signals from a 10/100 Base-T ethernet transceiver to the RJ-45 LAN connectors
in laptops or in docking stations. The device is designed for low channel-to-channel skew and low crosstalk.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, E should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
INPUTS
INPUT/OUTPUT
YX
FUNCTION
E
S
L
L
L
IX
IX
YX = IX
YX = IX
0
0
H
X
1
1
H
Z
Disconnect
PIN DESCRIPTIONS
PIN NAME
IAn−IDn
S
DESCRIPTION
Data I/Os
Select input
Enable input
Data I/Os
E
YA−YD
2
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ꢀꢁ ꢂꢃ ꢄꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒꢄ ꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢉꢌ ꢕ ꢕꢓ ꢖꢓ ꢐꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋꢈ ꢐꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀꢌ ꢊ ꢃꢓ ꢛꢓ ꢖ
SCDS176 − SEPTEMBER 2004
logic diagram (positive logic)
4
7
9
2
IA
IA
YA
0
3
1
5
6
YB
YC
YD
IB
IB
0
1
11
10
IC
IC
0
1
12
14
13
ID
ID
0
1
1
S
E
Control
Logic
15
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ ꢌꢕ ꢕ ꢓꢖ ꢓꢐ ꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐ ꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋ ꢈꢐ ꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖ
SCDS176 − SEPTEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
3
MAX
3.6
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage (E, S)
Low-level control input voltage (E, S)
Input/output voltage
2
V
IH
0
V
IL
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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ꢉꢌ ꢕ ꢕꢓ ꢖꢓ ꢐꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋꢈ ꢐꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀꢌ ꢊ ꢃꢓ ꢛꢓ ꢖ
SCDS176 − SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature range,
= 3.3 V + 0.3 V (unless otherwise noted)
V
CC
†
PARAMETER
E, S
TEST CONDITIONS
= −18 mA
MIN TYP
MAX
−1.8
1
UNIT
V
V
IK
V
V
V
V
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 0,
I
IN
CC
CC
CC
CC
CC
I
I
I
I
E, S
V
V
V
= 5.5 V
= GND
= 0 to 5.5 V ,
= 0,
µA
µA
µA
mA
pF
IH
IN
IN
E, S
1
IL
V = 0
I
1
off
CC
O
= 3.6 V,
I
Switch ON or OFF
0.7
2.5
1.5
3.5
I/O
C
E, S
f = 1 MHz,
V
= 0
in
IN
f = 1 MHz,
Outputs open,
I port
V = 0,
Switch OFF
Switch OFF
Switch ON
3.5
5.5
5
7
I
C
pF
io(OFF)
io(ON)
f = 1 MHz,
Outputs open,
Y port
V = 0,
I
f = 1 MHz,
Outputs open,
C
I or Y port
V = 0,
I
10.5
13
8
pF
V
CC
V
CC
V
CC
= 3 V
1.25 V ≤ V ≤ V
,
I = −10 mA to −30 mA
I
4
1
Ω
Ω
Ω
r
r
I
CC
on
on(flat)
‡
= 3 V
= 3 V,
V = 1.25 V and V
I
,
I = −10 mA to −30 mA
I
CC
§
1.25 V ≤ V ≤ V
,
I = −10 mA to −30 mA
I
0.9
2
∆r
I
CC
on
V , V , I , and I refer to I/O pins. V refers to the control inputs.
I
O
I
O
IN
= 3.3 V (unless otherwise noted), T = 25°C.
on
†
‡
§
All typical values are at V
CC
A
r
is the difference of r in a given channel at specified voltages.
on(flat)
∆r is the difference of r in a given device.
on on
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V, R = 200 Ω, C = 10 pF (unless otherwise noted) (see Figures 5 and 6)
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
¶
t
Y or I
I or Y
I or Y
Y or I
0.25
ns
ns
ns
ns
I or Y
E or S
E or S
I or Y
pd
t
t
t
, t
0.5
0.5
7
5
PZH PZL
, t
PHZ PLZ
#
0.1
0.2
sk(p)
†
¶
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
Skew between opposite transitions of the same output |t |. This parameter is not production tested.
#
− t
PHL PLH
dynamic characteristics over recommended operating free-air temperature range,
= 3.3 V + 0.3 V (unless otherwise noted)
V
CC
†
PARAMETER
TEST CONDITIONS
f = 250 MHz, see Figure 7
f = 250 MHz, see Figure 8
MIN TYP
MAX
UNIT
dB
X
R
R
R
= 100 Ω,
−26
−28
500
TALK
L
L
L
O
= 100 Ω,
dB
IRR
BW
= 100 Ω, see Figure 6
MHz
†
All typical values are at V
CC
= 3.3 V (unless otherwise noted), T = 25°C.
A
5
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ꢉ ꢌꢕ ꢕ ꢓꢖ ꢓꢐ ꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐ ꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋ ꢈꢐ ꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖ
SCDS176 − SEPTEMBER 2004
OPERATING CHARACTERISTICS
0
−1
−2
−3
−4
−5
−6
−7
0
Phase
−10
−20
−30
Gain
J
Y
−40
−50
−60
−70
1
10
100
700
Frequency (MHz)
J
Phase at 627 MHz, −36 Degrees
Gain −3 dB at 627 MHz
Y
Figure 1. Gain/Phase vs Frequency
20
0
120
100
80
60
40
20
0
Phase
J
Y
−20
−40
−60
−80
−100
Gain
1
10
100
700
Frequency (MHz)
J
Y
Phase at 250 MHz, 88.2 Degrees
Gain −28.5 dB at 250 MHz
Figure 2. OFF Isolation vs Frequency
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉꢌ
ꢕ
ꢕꢓ
ꢖꢓ
ꢐ
ꢀ
ꢌ
ꢈꢃ
ꢗ
ꢎꢔ
ꢋ
ꢈꢐ
ꢐꢓ
ꢃ
ꢀ ꢘ
ꢙ
ꢎꢔ
ꢋꢈ
ꢐꢐ
ꢓꢃ
ꢚ
ꢇ
ꢃ
ꢀ
ꢌ
ꢊ
ꢃ
ꢓ
ꢛ
ꢓ
ꢖ
ꢒ
ꢉ
ꢓ
ꢚ
ꢇ
ꢃ
ꢀ
ꢌ
ꢊ
ꢃ
ꢓ
ꢛ
ꢓ
ꢖ
SCDS176 − SEPTEMBER 2004
OPERATING CHARACTERISTICS
0
180
160
140
−10
−20
−30
−40
−50
−60
−70
−80
−90
J
Y
120
100
80
Phase
Gain
60
40
20
0
1
10
100
700
Frequency (MHz)
J
Phase at 250 MHz, 137.92 Degrees
Gain −26 dB at 250 MHz
Y
Figure 3. Crosstalk vs Frequency
5
4
3
2
1
0
20
16
12
8
V
O
r
ON
4
0
0
1
2
3
4
5
Input Voltage (V)
Figure 4. Output Voltage/ON-State Resistance vs Input Voltage
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒ ꢄꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢉ
ꢌ
ꢕ
ꢕ
ꢓ
ꢖ
ꢓ
ꢐ
ꢀ
ꢌ
ꢈ
ꢃ
ꢗ
ꢎꢔ
ꢋ
ꢈꢐ
ꢐ
ꢓ
ꢃ
ꢀ ꢘ
ꢙ
ꢎꢔ
ꢋ
ꢈꢐ
ꢐꢓ
ꢃ
ꢚ
ꢇꢃꢀ
ꢌꢊ
ꢃ
ꢓ
ꢛꢓ
ꢖꢒ
ꢉꢓ
ꢚ
ꢇꢃꢀ
ꢌ
ꢊ
ꢃ
ꢓ
ꢛ
ꢓ
ꢖ
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
FOR ENABLE AND DISABLE TIMES
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
C
R
V
TEST
/t
∆
L
L
CC
t
3.3 V 0.3 V
3.3 V 0.3 V
2 × V
200 Ω
200 Ω
GND
10 pF
10 pF
0.3 V
0.3 V
PLZ PZL
CC
t
/t
GND
V
PHZ PZH
CC
Output Control
2.5 V
(V
IN
)
1.25 V
1.25 V
Output
0 V
Waveform 1
t
t
PLZ
PZL
S1 at 2 y V
CC
V
OH
(see Note B)
V
/2
CC
V
V
+0.3 V
OL
V
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
−0.3 V
OH
V
CC
/2
V
OL
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHZ
PZH
are the same as t
.
en
Figure 5. Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒꢄ ꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢉꢌ ꢕ ꢕꢓ ꢖꢓ ꢐꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋꢈ ꢐꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀꢌ ꢊ ꢃꢓ ꢛꢓ ꢖ
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
FOR SKEW
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
50 Ω
V
G2
C
R
L
L
(see Note A)
V
IN
(see Note B)
S1
GND
C
R
V
CC
TEST
L
L
t
3.3 V 0.3 V
200 Ω
V
CC
or GND
10 pF
sk(p)
3.5 V
2.5 V
1.5 V
Data Input
t
t
PHL
PLH
V
OH
0.5 V (V
Data Output
− V
)
OH
OL
V
OL
tsk(p) = |t
− t
PHL PLH
|
VOLTAGE WAVEFORMS
PULSE SKEW (t
)
sk(p)
NOTES: A.
C includes probe and jig capacitance.
L
B. Switch is ON during the measurement of t
, i.e., voltage at E = 0 and S = V
CC
or GND
sk(p)
Figure 6. Test Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒ ꢄꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢉ ꢌꢕ ꢕ ꢓꢖ ꢓꢐ ꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐ ꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋ ꢈꢐ ꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖ
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
BIAS
V
(HP8753ES)
P1
P2
V
CC
YA
S
IA
0
C
= 10 pF
R = 100 Ω
L
L
(see Note A)
DUT
V
V
S
E
E
NOTE A: C includes probe and jig capacitance.
L
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when V = 0, V = 0, and YA is the
S
E
input, the output is measured at IA . All unused analog I/O ports are left open.
0
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBm
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢄꢅ
ꢆ ꢇꢈꢉ ꢁꢊ ꢉꢀ ꢋꢌ ꢍꢋ ꢎꢏꢈꢐꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒꢄ ꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁ ꢑꢌ ꢀꢔ ꢋ
ꢌ ꢕ ꢕꢓ ꢖꢓ ꢐꢀ ꢌ ꢈꢃ ꢗ ꢎꢔꢋ ꢈꢐꢐꢓ ꢃ ꢀ ꢘ ꢙ ꢎꢔꢋꢈ ꢐꢐꢓꢃ ꢚ ꢇꢃꢀ ꢌꢊ ꢃꢓ ꢛꢓꢖꢒ ꢉꢓꢚ ꢇꢃꢀꢌ ꢊ ꢃꢓ ꢛꢓ ꢖ
ꢉ
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
YA
S
IA
0
R
= 100 Ω
C
= 10 pF
L
50 Ω
(see Note B)
L
(see Note A)
V
V
S
DUT
E
E
YB
IB
0
R
= 100 Ω
C = 10 pF
L
(see Note A)
L
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 8. Test Circuit for Crosstalk (X
)
TALK
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V = 0,
S
V = 0, and YA is the input, the output is measured at IB . All unused analog input (Y) ports are connected to GND,
E
0
and output (I) ports are connected to GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBm
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ
ꢆꢇ ꢈ ꢉ ꢁꢊ ꢉꢀ ꢋ ꢌ ꢍꢋ ꢎꢏꢈꢐ ꢉꢑ ꢌ ꢉꢀ ꢋ ꢄ ꢅ ꢒ ꢄꢅ ꢅ ꢏꢈꢁ ꢓꢎꢀ ꢃ ꢈꢐ ꢁꢑ ꢌ ꢀꢔ ꢋ
ꢉ
ꢌ
ꢕ
ꢕ
ꢓ
ꢖ
ꢓ
ꢐ
ꢀ
ꢌ
ꢈ
ꢃ
ꢗ
ꢎꢔ
ꢋ
ꢈꢐ
ꢐ
ꢓ
ꢃ
ꢀ ꢘ
ꢙ
ꢎꢔ
ꢋ
ꢈꢐ
ꢐꢓ
ꢃ
ꢚ
ꢇꢃꢀ
ꢌꢊ
ꢃꢓ
ꢛꢓ
ꢖꢒ
ꢉꢓ
ꢚ
ꢇꢃꢀ
ꢌ
ꢊ
ꢃꢓ
ꢛꢓ
ꢖ
SCDS176 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
CC
YA
S
IA
0
R
R
= 100 Ω
= 100 Ω
C = 10 pF
L
L
(see Note A)
DUT
V
V
S
IA
1
E
C
= 10 pF
50 Ω
(see Note B)
L
L
(see Note A)
E
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 9. Test Circuit for OFF Isolation (O
)
IRR
OFF isolation is measured at the output of the OFF channel. For example, when V = V , V = 0, and YA is the input,
S
CC
E
the output is measured at IA . All unused analog input (Y) ports are left open, and output (I) ports are connected to
0
GND through 50-Ω pulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBm
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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