TS3L301DGGG4 [TI]
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE; 16位到8位SPDT千兆网卡低收入和FLAT开关导通电阻
| 型号： | TS3L301DGGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE |
| 文件： | 总17页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
FEATURES
DGG OR DGV PACKAGE
(TOP VIEW)
•
•
•
•
Wide Bandwidth (BW = 900 MHz Typ)
Low Crosstalk (XTALK = –41 dB Typ)
Low Bit-to-Bit Skew [tsk(o) = 0.2 ns Max]
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
0B
1B
DD
1
1
2
A
0
Low and Flat ON-State Resistance
3
GND
GND
0B
1B
GND
2B
3B
GND
2B
3B
GND
(ron = 4 Ω Typ, ron(flat) = 0.7 Ω Typ)
4
A
1
2
•
•
Low Input/Output Capacitance
(CON = 10 pF Typ)
5
GND
2
6
V
DD
Rail-to-Rail Switching on Data I/O Ports
(0 to 5 V)
7
GND
1
8
A
2
1
•
•
VDD Operating Range From 3 V to 3.6 V
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
3
Ioff Supports Partial Power-Down-Mode
Operation
2
GND
2
V
DD
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND
NC
V
DD
4B
5B
GND
4B
5B
1
ESD Performance Tested Per JESD 22
A
4
1
– 2000-V Human-Body Model
(A114-B, Class II)
GND
A
5
2
2
– 1000-V Charged-Device Model (C101)
GND
•
Suitable for 10-/100-/1000-Mbit Ethernet
Signaling
V
DD
GND
6B
7B
GND
6B
GND
1
A
6
1
APPLICATIONS
GND
•
•
•
•
•
10/100/1000 Base-T Signal Switching
Differential (LVDS, LVPECL) Signal Switching
Digital Video Signal Routing
Notebook Docking Signal Routing
Hub and Router Signal Switching
A
7
2
SEL
7B
2
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The TS3L301 is a 16-bit to 8-bit multiplexer/demultiplexer local area network (LAN) switch with a single select
(SEL) input. The SEL input controls the data path of the multiplexer/demultiplexer.
The device provides a low and flat ON-state resistance (ron) and an excellent ON-state resistance match. Low
input/output capacitance, high-bandwidth, low skew, and low crosstalk among channels make this device
suitable for various LAN applications, such as 10/100/1000 Base-T.
ORDERING INFORMATION
TA
PACKAGE(1)
Tape and reel
Tape and reel
ORDERABLE PART NUMBER
TS3L301DGGR
TOP-SIDE MARKING
TS3L301
TK301
TSSOP – DGG
TVSOP – DGV
–40°C to 85°C
TS3L301DGVR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
FUNCTION TABLE
INPUT
SEL
INPUT/OUTPUT
An
FUNCTION
L
nB1
nB2
An = nB1
An = nB2
H
PIN DESCRIPTION
NAME
An
DESCRIPTION
Data I/Os
Data I/Os
nBm
SEL
Select input
LOGIC DIAGRAM (POSITIVE LOGIC)
48
2
0B
1B
0B
1B
A
1
1
2
2
0
1
47
45
44
4
A
8
42
41
39
38
2B
3B
2B
3B
A
A
1
1
2
2
2
10
3
15
17
35
34
32
31
4B
1
5B
1
4B
2
5B
2
A
A
4
5
21
23
29
28
26
25
6B
1
7B
1
6B
2
7B
2
A
A
6
7
24
SEL
2
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VDD
VIN
VI/O
IIK
Supply voltage range
4.6
7
V
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
V
7
V
VIN < 0
VI/O < 0
–50
–50
±128
±100
70
mA
mA
mA
mA
II/OK
II/O
ON-state switch current(5)
Continuous current through VDD or GND
DGG package
DGV package
θJA
Package thermal impedance(6)
Storage temperature range
°C/W
°C
58
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
3
MAX UNIT
VDD
VIH
VIL
Supply voltage
3.6
5.5
0.8
5.5
85
V
V
High-level control input voltage (SEL)
Low-level control input voltage (SEL)
Input/output voltage
2
0
V
VI/O
TA
0
V
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
Electrical Characteristics
for 1000 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V
(unless otherwise noted)
PARAMETER
SEL
TEST CONDITIONS(1)
IIN = –18 mA
MIN TYP(2) MAX UNIT
VIK
IIH
VDD = 3.6 V,
VDD = 3.6 V,
VDD = 3.6 V,
VDD = 0,
–0.7 –1.2
V
SEL
VIN = VDD
±1
µA
µA
µA
µA
pF
pF
pF
Ω
IIL
SEL
VIN = GND
VO = 0 to 3.6 V,
II/O = 0,
±1
1
Ioff
IDD
CIN
VI = 0
VDD = 3.6 V,
f = 1 MHz,
VI = 0,
Switch ON or OFF
250 600
SEL
VIN = 0
2.5
3.5
3
4
COFF
CON
ron
B port
f = 1 MHz,
f = 1 MHz,
1.5 V ≤ VI ≤ VDD
Outputs open,
Outputs open,
IO = –40 mA
IO = –40 mA
IO = –40 mA
Switch OFF
Switch ON
VI = 0,
10 10.9
VDD = 3 V,
VDD = 3 V,
VDD = 3 V,
,
4
0.7
0.2
8
(3)
ron(flat)
VI = 1.5 V and VDD
,
Ω
(4)
∆ron
1.5 V ≤ VI ≤ VDD
,
1.2
Ω
(1) VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
(3) ron(flat) is the difference of ron in a given channel at specified voltages.
(4) ∆ron is the difference of ron from center (A4, A5) ports to any other port.
Electrical Characteristics
for 10/100 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN TYP(2)
MAX UNIT
VIK
SEL
SEL
SEL
VDD = 3.6 V,
VDD = 3.6 V,
VDD = 3.6 V,
VDD = 0,
IIN = –18 mA
VIN = VDD
–0.7
–1.2
±1
±1
1
V
IIH
µA
µA
µA
µA
pF
pF
pF
Ω
IIL
VIN = GND
Ioff
VO = 0 to 3.6 V,
II/O = 0,
VI = 0
IDD
VDD = 3.6 V,
f = 1 MHz,
VI = 0,
Switch ON or OFF
250
2.5
3.5
10
600
3
CIN
COFF
CON
ron
SEL
VIN = 0
B port
f = 1 MHz,
f = 1 MHz,
1.25 V ≤ VI ≤ VDD
Outputs open,
Switch OFF
Switch ON
4
VI = 0,
Outputs open,
10.9
8
VDD = 3 V,
VDD = 3 V,
VDD = 3 V,
,
IO = –10 mA to –30 mA
IO = –10 mA to –30 mA
IO = –10 mA to –30 mA
4
(3)
ron(flat)
VI = 1.25 V and VDD
,
0.7
0.2
Ω
(4)
∆ron
1.25 V ≤ VI ≤ VDD
,
1.2
Ω
(1) VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
(3) ron(flat) is the difference of ron in a given channel at specified voltages.
(4) ∆ron is the difference of ron from center (A4, A5) ports to any other port.
4
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
Switching Characteristics
over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF
(unless otherwise noted) (see Figures 4 and 5)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP(1)
MAX
UNIT
(2)
tpd
A or B
SEL
B or A
A or B
A or B
B or A
0.25
ns
ns
ns
ns
ns
tPZH, tPZL
1.5
1
11.5
8.5
0.2
0.2
tPHZ, tPLZ
SEL
(3)
tsk(o)
A or B
0.1
0.1
(4)
tsk(p)
(1) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
(3) Output skew between center port (A4 to A5) to any other port
(4) Skew between opposite transitions of the same output in a given device |tPHL – tPLH
|
Dynamic Characteristics
over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
XTALK
TEST CONDITIONS
f = 250 MHz,
TYP(1) UNIT
RL = 100 Ω,
RL = 100 Ω,
RL = 100 Ω,
See Figure 7
See Figure 8
–41
–39
900
dB
dB
OIRR
f = 250 MHz,
See Figure 6
BW
MHz
(1) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.
5
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
OPERATING CHARACTERISTICS
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
1
10
100
1,000
10,000
Frequency − MHz
Gain at 900 MHz, −3 dB
Figure 1. Gain vs Frequency
0
−20
−40
−60
−80
−100
−120
1
10
100
1,000
10,000
Frequency − MHz
OFF Isolation at 250 MHz, −39 dB
Figure 2. OFF Isolation vs Frequency
6
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
OPERATING CHARACTERISTICS (continued)
0
−20
−40
−60
−80
−100
−120
1
10
100
1,000
10,000
Frequency − MHz
Crosstalk at 250 MHz, −41 dB
Figure 3. Crosstalk vs Frequency
7
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
V
DD
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
DD
Input Generator
S1
Open
R
L
V
I
V
O
GND
50 Ω
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
2 × V
V
I
C
V
∆
R
V
TEST
L
L
DD
t
/t
3.3 V ± 0.3 V
3.3 V ± 0.3 V
200 Ω
200 Ω
GND
10 pF
10 pF
0.3 V
0.3 V
PLZ PZL
DD
t
/t
GND
V
DD
PHZ PZH
Output Control
2.5 V
0 V
(V )
IN
1.25 V
1.25 V
Output
Waveform 1
t
t
PLZ
PZL
S1 at 2 y V
DD
V
V
OH
(see Note B)
V
/2
/2
DD
V
V
+0.3 V
OL
OL
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
−0.3 V
OH
V
DD
OL
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHZ
PZH
are the same as t
en
Figure 4. Test Circuit and Voltage Waveforms
8
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
(Skew)
V
DD
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
DD
Input Generator
S1
Open
GND
R
L
V
I
V
O
50 Ω
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
V
I
C
L
R
L
V
DD
TEST
t
3.3 V ± 0.3 V
3.3 V ± 0.3 V
Open
Open
200 Ω
V
V
or GND
or GND
10 pF
10 pF
sk(o)
DD
t
200 Ω
sk(p)
DD
3.5 V
2.5 V
1.5 V
Data In at
Ax or Ay
t
t
PHLx
PLHx
3.5 V
2.5 V
1.5 V
V
OH
Data Out at
XB or XB
(V + V )/2
Input
OH
OL
V
OL
1
2
t
t
t
t
PHL
sk(o)
sk(o)
PLH
V
OH
V
OH
Data Out at
YB or YB
Output
(V + V )/2
(V + V )/2
OH
OL
OH
OL
V
OL
V
OL
1
2
t
t
t
= |t
− t
|
PLHy
PHLy
sk(p)
PLH
PLH
t
= |t
− t
PLHx
| or |t
− t
PHLx
|
sk(o)
PLHy
PHLy
VOLTAGE WAVEFORMS
OUTPUT SKEW [t
VOLTAGE WAVEFORMS
PULSE SKEW [t
]
]
sk(p)
sk(o)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Test Circuit and Voltage Waveforms
9
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
DD
A
0
0B
1
C
L
= 10 pF
(see Note A)
DUT
SEL
V
SEL
A. CL includes probe and jig capacitance.
Figure 6. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the
input, the output is measured at 0B1. All unused analog I/O ports are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
10
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
DD
A
A
0B
0
1
R
L
= 100 Ω
1B
0B
1
1
2
1B
2B
2
1
DUT
A
A
2
R
L
= 100 Ω
3B
1
3
2B
3B
2
2
SEL
V
SEL
A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 7. Test Circuit for Crosstalk (XTALK
)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is the
input, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B)
ports are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
11
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TS3L301
16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ON-STATE RESISTANCE
www.ti.com
SCDS178C–NOVEMBER 2004–REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
DD
A
A
0B
1B
0
1
R
L
= 100 Ω
1
1
DUT
0B
2
1B
2
SEL
V
SEL
A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 8. Test Circuit for Off Isolation (OIRR
)
OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1 is the
input, the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B)
ports are left open.
HP8753ES Setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
TS3L301DGG
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
48
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3L301DGGE4
TS3L301DGGG4
TS3L301DGGR
TS3L301DGGRE4
TS3L301DGGRG4
TS3L301DGVR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TVSOP
TVSOP
TVSOP
DGG
DGG
DGG
DGG
DGG
DGV
DGV
DGV
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TS3L301DGVRE4
TS3L301DGVRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3L301DGGR
TS3L301DGVR
TSSOP
TVSOP
DGG
DGV
48
48
2000
2000
330.0
330.0
24.4
16.4
8.6
7.1
15.8
10.2
1.8
1.6
12.0
12.0
24.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS3L301DGGR
TS3L301DGVR
TSSOP
TVSOP
DGG
DGV
48
48
2000
2000
346.0
346.0
346.0
346.0
41.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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