TS3L301DGGR [TI]
16 BIT TO 8 BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON STATE RESISTANCE; 16位到8位SPDT千兆网卡低收入和开关平通电阻
| 型号： | TS3L301DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 BIT TO 8 BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON STATE RESISTANCE |
| 文件： | 总16页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢅ ꢆ ꢇꢈꢉ ꢀ ꢀ ꢊ ꢋ ꢇꢈꢉ ꢀ ꢁꢌ ꢍꢀ ꢎ ꢉꢎ ꢏꢈꢉ ꢀ ꢃ ꢏꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
DGG OR DGV PACKAGE
(TOP VIEW)
D
D
D
D
D
D
Wide Bandwidth (BW = 900 MHz Typ)
Low Crosstalk (X = −41 dB Typ)
TALK
Low Bit-to-Bit Skew [t
= 0.2 ns Max]
sk(o)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
0B
1B
GND
DD
1
Low and Flat ON-State Resistance
(r = 4 ꢀ Typ, r = 0.7 ꢀ Typ)
2
A
0
1
3
GND
on
on(flat)
4
A
0B
Low Input/Output Capacitance
(C = 10 pF Typ)
1
2
5
GND
V
GND
1B
2
GND
ON
6
DD
Rail-to-Rail Switching on Data I/O Ports
(0 to 5 V)
7
2B
3B
1
8
A
2
1
D
V Operating Range From 3 V to 3.6 V
DD
9
GND
GND
D
I
Supports Partial-Power-Down Mode
off
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
2B
3B
3
2
Operation
GND
V
GND
NC
2
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND
DD
V
DD
4B
5B
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
1
A
4
1
GND
GND
− 1000-V Charged-Device Model (C101)
A
4B
5B
5
2
GND
V
GND
D
D
Suitable for 10/100/1000-Mbit Ethernet
Signaling
2
GND
DD
6B
7B
1
Applications
A
6
1
− 10/100/1000 Base-T Signal Switching
− Differential (LVDS, LVPECL) Signal
Switching
− Digital Video Signal Routing
− Notebook Docking Signal Routing
− Hub and Router Signal Switching
GND
GND
A
6B
7B
7
2
2
SEL
NC − No internal connection
description/ordering information
The TS3L301 is a 16-bit to 8-bit multiplexer/demultiplexer LAN switch with a single select (SEL) input. The SEL
input controls the data path of the multiplexer/demultiplexer.
The device provides a low and flat on-state resistance (r ) and an excellent on-resistance match. Low
on
input/output capacitance, high-bandwidth, low skew, and low crosstalk among channels make this device
suitable for various LAN applications, such as 10/100/1000 Base-T.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
TSSOP − DGG
TVSOP − DGV
Tape and reel
Tape and reel
TS3L301DGGR
TS3L301DGVR
TS3L301
TK301
−40°C to 85°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢂ ꢄꢅ
ꢅꢆ ꢇꢈꢉ ꢀ ꢀꢊ ꢋ ꢇꢈ ꢉ ꢀ ꢁ ꢌꢍ ꢀ ꢎ ꢉꢎ ꢏꢈ ꢉ ꢀ ꢃꢏ ꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑꢉ ꢀ ꢓ ꢃ ꢊꢑ ꢏ ꢐꢍ ꢔꢃ ꢏꢀ ꢊ ꢐꢇꢁ ꢀꢏꢀ ꢕ ꢖꢕ ꢁ ꢉ ꢁ ꢀꢏꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
FUNCTION TABLE
INPUT
INPUT/OUTPUT
An
FUNCTION
SEL
L
nB
nB
A
A
= nB
= nB
1
n
1
H
2
n
2
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
Data I/Os
A
n
nB
m
Data I/Os
SEL
Select input
logic diagram (positive logic)
2
4
48
47
45
44
0B
1B
0B
1B
A
A
1
1
2
2
0
1
8
42
41
39
38
2B
3B
2B
3B
A
A
1
1
2
2
2
3
10
15
17
35
34
32
31
4B
5B
4B
5B
A
A
1
1
2
2
4
5
21
23
29
28
26
25
6B
7B
6B
7B
A
A
1
1
2
2
6
7
24
SEL
2
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ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
DD
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
DD
Package thermal impedance, θ (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
3
MAX
3.6
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
DD
High-level control input voltage (SEL)
Low-level control input voltage (SEL)
Input/output voltage
2
V
IH
0
V
IL
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
DD
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢂ ꢄꢅ
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ꢑꢉ ꢀ ꢓ ꢃ ꢊꢑ ꢏ ꢐꢍ ꢔꢃ ꢏꢀ ꢊ ꢐꢇꢁ ꢀꢏꢀ ꢕ ꢖꢕ ꢁ ꢉ ꢁ ꢀꢏꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
electrical characteristics for 1000 Base-T ethernet switching over recommended operating free-air
temperature range, V
= 3.3 V + 0.3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
1
UNIT
V
V
SEL
SEL
SEL
V
V
V
V
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 0,
I = −18 mA
IN
−0.7
IK
DD
DD
DD
DD
DD
I
I
I
I
V
V
V
= V
DD
µA
µA
µA
µA
pF
IH
IN
IN
= GND
= 0 to 3.6 V ,
= 0,
1
IL
V = 0
I
1
off
CC
O
= 3.6 V,
I
Switch ON or OFF
250
2.5
600
3
I/O
C
SEL
f = 1 MHz,
V
IN
= 0
IN
f = 1 MHz,
Outputs open,
C
B port
V = 0,
Switch OFF
Switch ON
3.5
10
4
pF
pF
OFF
I
f = 1 MHz,
Outputs open,
C
r
V = 0,
I
10.9
8
ON
V
DD
V
DD
V
DD
= 3 V
1.5 V ≤ V ≤ V
,
I
O
I
O
I
O
= −40 mA
= −40 mA
= −40 mA
4
0.7
0.2
Ω
Ω
Ω
I
DD
on
‡
= 3 V
= 3 V,
V = 1.5 V and V
I
,
r
DD
on(flat)
§
1.5 V ≤ V ≤ V
,
1.2
∆r
I
DD
on
V , V , I , and I refer to I/O pins. V refers to the control inputs.
I
O
I
O
IN
= 3.3 V (unless otherwise noted), T = 25°C.
on
†
‡
§
All typical values are at V
DD
A
r
is the difference of r in a given channel at specified voltages.
on(flat)
∆r is the difference of r from center (A , A ) ports to any other port.
on on
4
5
electrical characteristics for 10/100 Base-T ethernet switching over recommended operating
free-air temperature range, V
= 3.3 V + 0.3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
1
UNIT
V
V
SEL
SEL
SEL
V
V
V
V
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 0,
I = −18 mA
IN
−0.7
IK
DD
DD
DD
DD
DD
I
I
I
I
V
V
V
= V
DD
µA
µA
µA
µA
pF
IH
IN
IN
= GND
= 0 to 3.6 V,
= 0,
1
IL
V = 0
I
1
off
CC
O
= 3.6 V,
I
Switch ON or OFF
250
2.5
600
3
I/O
C
SEL
f = 1 MHz,
V
IN
= 0
IN
f = 1 MHz,
Outputs open,
C
B port
V = 0,
Switch OFF
Switch ON
3.5
10
4
pF
pF
OFF
I
f = 1 MHz,
Outputs open,
C
r
V = 0,
I
10.9
8
ON
V
DD
V
DD
V
DD
= 3 V
1.25 V ≤ V ≤ V
,
I
O
I
O
I
O
= −10 mA to −30 mA
= −10 mA to −30 mA
= −10 mA to −30 mA
4
0.7
0.2
Ω
Ω
Ω
I
DD
on
‡
= 3 V
= 3 V,
V = 1.25 V and V
I
,
r
DD
on(flat)
§
1.25 V ≤ V ≤ V
,
1.2
∆r
I
DD
on
V , V , I , and I refer to I/O pins. V refers to the control inputs.
I
O
I
O
IN
= 3.3 V (unless otherwise noted), T = 25°C.
on
†
‡
§
All typical values are at V
DD
A
r
is the difference of r in a given channel at specified voltages.
on(flat)
on
∆r is the difference of r from center (A , A ) ports to any other port.
on
4
5
4
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ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V, R = 200 Ω, C = 10 pF (unless otherwise noted) (see Figures 4 and 5)
DD
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
‡
t
t
t
t
t
B or A
A or B
A or B
B or A
0.25
ns
ns
ns
ns
ns
A or B
SEL
pd
, t
1.5
1
11.5
8.5
0.2
0.2
PZH PZL
, t
SEL
PHZ PLZ
§
0.1
0.1
A or B
sk(o)
¶
sk(p)
†
‡
All typical values are at V
DD
= 3.3 V (unless otherwise noted), T = 25°C.
A
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
§
¶
Output skew between center port (A to A ) to any other port
Skew between opposite transitions of the same output in a given device |t |
4
5
− t
PHL PLH
dynamic characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
f = 250 MHz,
TYP
UNIT
dB
X
R
R
R
= 100 Ω,
= 100 Ω,
= 100 Ω,
See Figure 7
See Figure 8
−41
−39
900
TALK
L
L
L
O
f = 250 MHz,
dB
IRR
BW
See Figure 6
MHz
†
All typical values are at V
DD
= 3.3 V (unless otherwise noted), T = 25°C.
A
5
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SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
OPERATING CHARACTERISTICS
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
1
10
100
1,000
10,000
Frequency − MHz
Gain at 900 MHz, −3 dB
Figure 1. Gain vs Frequency
0
−20
−40
−60
−80
−100
−120
1
10
100
1,000
10,000
Frequency − MHz
Off-Isolation at 250 MHz, −39 dB
Figure 2. Off-Isolation vs Frequency
6
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ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
OPERATING CHARACTERISTICS (continued)
0
−20
−40
−60
−80
−100
−120
1
10
100
1,000
10,000
Frequency − MHz
Crosstalk at 250 MHz, −41 dB
Figure 3. Crosstalk vs Frequency
7
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ꢑꢉ ꢀ ꢓ ꢃ ꢊꢑ ꢏ ꢐꢍ ꢔꢃ ꢏꢀ ꢊ ꢐꢇꢁ ꢀꢏꢀ ꢕ ꢖꢕ ꢁ ꢉ ꢁ ꢀꢏꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
FOR ENABLE AND DISABLE TIMES
V
DD
Input Generator
V
IN
50 Ω
50 Ω
V
V
G1
TEST CIRCUIT
DUT
2 × V
DD
Open
Input Generator
S1
R
V
V
O
L
I
GND
50 Ω
50 Ω
C
R
L
G2
L
(see Note A)
S1
V
I
V
C
R
V
TEST
/t
∆
L
L
DD
t
3.3 V 0.3 V
3.3 V 0.3 V
2 × V
200 Ω
200 Ω
GND
10 pF
10 pF
0.3 V
0.3 V
PLZ PZL
DD
t
/t
GND
V
PHZ PZH
DD
Output Control
2.5 V
0 V
(V
IN
)
1.25 V
1.25 V
Output
Waveform 1
t
t
PLZ
PZL
S1 at 2 y V
DD
V
OH
(see Note B)
V
/2
DD
V
V
+0.3 V
OL
V
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
−0.3 V
OH
V
DD
/2
V
OL
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHZ
PZH
are the same as t
.
en
Figure 4. Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂꢄ ꢅ
ꢅ ꢆ ꢇꢈꢉ ꢀ ꢀ ꢊ ꢋ ꢇꢈꢉ ꢀ ꢁꢌ ꢍꢀ ꢎ ꢉꢎ ꢏꢈꢉ ꢀ ꢃ ꢏꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
FOR SKEW
V
DD
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
DD
Open
Input Generator
S1
R
V
I
V
O
L
GND
50 Ω
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
DD
TEST
L
L
t
3.3 V 0.3 V
3.3 V 0.3 V
Open
Open
200 Ω
200 Ω
V
V
or GND
10 pF
10 pF
sk(o)
DD
t
or GND
sk(p)
DD
3.5 V
2.5 V
1.5 V
Data In at
Ax or Ay
t
t
PHLx
PLHx
3.5 V
2.5 V
1.5 V
V
OH
Data Out at
XB or XB
0.5 V (V
− V
)
Input
OH
OL
V
OL
1
2
t
t
t
t
PHL
sk(o)
sk(o)
PLH
V
OH
V
OH
Data Out at
YB or YB
Output
0.5 V (V
− V
)
0.5 V (V
− V )
OL
OH
OL
OH
V
OL
V
OL
1
2
t
t
tsk(p) = ꢁtPLH − tPLHꢁ
PLHy
PHLy
tsk(o) = ꢁtPLHy − tPLHxꢁ or ꢁtPHLy − TPHLxꢁ
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PULSE SKEW (t
OUTPUT SKEW (t
)
)
sk(p)
sk(o)
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Test Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢂ ꢄꢅ
ꢅꢆ ꢇꢈꢉ ꢀ ꢀꢊ ꢋ ꢇꢈ ꢉ ꢀ ꢁ ꢌꢍ ꢀ ꢎ ꢉꢎ ꢏꢈ ꢉ ꢀ ꢃꢏ ꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑꢉ ꢀ ꢓ ꢃ ꢊꢑ ꢏ ꢐꢍ ꢔꢃ ꢏꢀ ꢊ ꢐꢇꢁ ꢀꢏꢀ ꢕ ꢖꢕ ꢁ ꢉ ꢁ ꢀꢏꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
V
BIAS
(HP8753ES)
P1
P2
V
DD
A
0B
1
0
C
= 10 pF
L
(see Note A)
DUT
SEL
V
SEL
NOTE A: C includes probe and jig capacitance.
L
Figure 6. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when V
= 0 and A is the input,
0
SEL
the output is measured at 0B . All unused analog I/O ports are left open.
1
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢂꢄ ꢅ
ꢅ ꢆ ꢇꢈꢉ ꢀ ꢀ ꢊ ꢋ ꢇꢈꢉ ꢀ ꢁꢌ ꢍꢀ ꢎ ꢉꢎ ꢏꢈꢉ ꢀ ꢃ ꢏꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑ ꢉꢀ ꢓ ꢃ ꢊꢑ ꢏꢐꢍ ꢔ ꢃꢏꢀ ꢊ ꢐꢇꢁꢀꢏꢀ ꢕ ꢖꢕꢁ ꢉ ꢁꢀꢏ ꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
BIAS
V
(HP8753ES)
P1
P2
V
DD
A
A
0B
0
1
1
R
= 100 Ω
L
1B
0B
1
2
1B
2B
2
DUT
A
A
2
3
1
R
= 100 Ω
L
3B
1
2B
3B
2
2
SEL
V
SEL
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 7. Test Circuit for Crosstalk (X
)
TALK
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when V
= 0
SEL
and A is the input, the output is measured at A . All unused analog input (A) ports are connected to GND, and output
1
3
(B) ports are left open.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢂ ꢄꢅ
ꢅꢆ ꢇꢈꢉ ꢀ ꢀꢊ ꢋ ꢇꢈ ꢉ ꢀ ꢁ ꢌꢍ ꢀ ꢎ ꢉꢎ ꢏꢈ ꢉ ꢀ ꢃꢏ ꢐ ꢁ ꢑꢉ ꢀꢒ ꢓ
ꢑꢉ ꢀ ꢓ ꢃ ꢊꢑ ꢏ ꢐꢍ ꢔꢃ ꢏꢀ ꢊ ꢐꢇꢁ ꢀꢏꢀ ꢕ ꢖꢕ ꢁ ꢉ ꢁ ꢀꢏꢐꢒ ꢕ
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
V
BIAS
P1
P2
V
DD
A
A
0B
1B
0
1
1
R
= 100 Ω
L
1
DUT
0B
1B
2
2
SEL
V
SEL
NOTES: A.
C includes probe and jig capacitance.
L
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
Figure 8. Test Circuit for Off Isolation (O
)
IRR
OFF isolation is measured at the output of the OFF channel. For example, when V
= GND and A is the input,
1
SEL
the output is measured at 1B . All unused analog input (A) ports are connected to ground, and output (B) ports are
2
left open.
HP8753ES setup
Average = 4
RBW = 3 kHz
V
= 0.35 V
BIAS
ST = 2 s
P1 = 0 dBM
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2005
PACKAGING INFORMATION
Orderable Device
TS3L301DGGR
TS3L301DGVR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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