TS5A26542 [TI]
0.75-W DUAL SPDT ANALOG SWITCH WITH INPUT LOGIC TRANSLATION; 0.75 -W双路SPDT模拟开关输入逻辑转换
| 型号： | TS5A26542 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.75-W DUAL SPDT ANALOG SWITCH WITH INPUT LOGIC TRANSLATION |
| 文件： | 总21页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
FEATURES
APPLICATIONS
•
•
•
Cell Phones
PDAs
Portable Instrumentation
•
•
•
•
•
•
•
•
•
Specified Break-Before-Make Switching
Low ON-State Resistance (0.75 Ω Max)
Control Inputs Reference to VIO
Low Charge Injection
(1)
YZT PACKAGE
Excellent ON-State Resistance Matching
Low Total Harmonic Distortion (THD)
2.25-V to 5.5-V Power Supply (V+)
1.65-V to 1.95-V Logic Supply (VIO)
(BOTTOM VIEW)
A B C D
3
4
9
10
1
2
1
5
6
8
7
11
12
2
3
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
(1)
The GND balls are internally connected.
•
ESD Performance Tested Per JESD 22
A
B
C
D
–
2000-V Human-Body Model
(A114-B, Class II)
IN1
NO1 COM1 NC1
GND V+
NO2 COM2 NC2
1
VIO GND
IN2
2
3
–
–
1000-V Charged-Device Model (C101)
300-V Machine Model (A115-A)
•
COM Inputs
–
8000-V Human-Body Model
(A114-B, Class II)
–
±15-kV Contact Discharge (IEC 61000-4-2)
DESCRIPTION
The TS5A26542 is a dual single-pole double-throw (SPDT) analog switch that is designed to operate from
2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state
resistance matching, and the break-before-make feature to prevent signal distortion during the transferring of a
signal from one path to the another. The device has excellent total harmonic distortion (THD) performance and
consumes very low power. These features make this device suitable for portable audio applications.
The TS5A26542 has a separate logic supply pin (VIO) that operates from 1.65 V to 1.95 V. VIO powers the
control circuitry, which allows the TS5A26542 to be controlled by 1.8-V signals.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
–40°C to 85°C 0.23-mm Large Bump – YZT
Reel of 3000
TS5A26542YZTR
_ _ _ JN7_
(Pb-free) 0.625-mm max height
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
(2) YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
SUMMARY OF CHARACTERISTICS(1)
2:1 Multiplexer/Demultiplexer
Configuration
(2 × SPDT)
Number of channels
2
ON-state resistance (ron
)
0.75 Ω max
0.1 Ω max
0.1 Ω max
25 ns/20 ns
15 pC
ON-state resistance match (∆ron
)
ON-state resistance flatness (ron(flat)
)
Turn-on/turn-off time (tON/tOFF
Charge injection (QC)
Bandwidth (BW)
)
43 MHz
OFF isolation (OISO
Crosstalk (XTALK
)
–63 dB at 1 MHz
–63 dB at 1 MHz
0.004%
)
Total harmonic distortion (THD)
Leakage current (INO(OFF)/INC(OFF)
Package option
)
20 nA
12-pin WCSP
(1) V+ = 5 V, TA = 25°C
FUNCTION TABLE
NC TO COM, NO TO COM,
COM TO NC COM TO NO
IN
L
ON
OFF
ON
H
OFF
Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V+
VIO
Supply voltage range(3)
–0.5
6.5
V
VNC
VNO
Analog voltage range(3)(4)(5)
–0.5
V+ + 0.5
V
VCOM
II/OK
Analog port diode current(6)
ON-state switch current
VNO, VNC, VCOM < 0 or VNO, VNC, VCOM > V+
VNO, VNC, VCOM = 0 to V+
–50
50
mA
mA
INC
INO
ICOM
–200
200
ON-state peak switch current(7)
–400
400
6.5
VI
Digital input voltage range(3)(4)
Digital input clamp current
–0.5
–50
V
IIK
VI < 0
mA
I+
IGND
Continuous current through V+ or GND
–100
100
mA
θJA
Package thermal impedance(8)
Storage temperature range
102
150
°C/W
°C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(5) This value is limited to 5.5 V maximum.
(6) Requires clamp diodes on analog port to V+
(7) Pulse at 1-ms duration <10% duty cycle
(8) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 5-V Supply(1)
V+ = 4.5 V to 5.5 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP
MAX UNIT
VCOM
VNO
,
Analog signal range
ON-state resistance
0
V+
V
25°C
Full
0.5
0.75
0.8
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
ron
4.5 V
4.5 V
Ω
ON-state resistance
match between
channels
25°C
0.05
0.1
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
∆ron
Ω
Ω
Full
0.1
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
25°C
0.1
0.1
ON-state resistance
flatness
ron(flat)
4.5 V
5.5 V
VNO or VNC = 1 V, 1.5 V,
2.5 V,
ICOM = –100 mA,
25°C
Full
0.25
0.25
20
Switch ON,
See Figure 14
VNO = 1 V, 4.5 V,
VCOM = 4.5 V, 1 V,
VNC = Open,
25°C
–20
2
NO, NC
OFF leakage
current
INO(OFF)
INC(OFF)
,
Switch OFF,
See Figure 15
or
nA
Full
–100
100
VNC = 1 V, 4.5 V,
VCOM = 4.5 V, 1 V,
VNO = Open,
VNO = 1 V, 4.5 V,
VNC and VCOM = Open,
or
VNC = 1V, 4.5 V,
VNO and VCOM = Open,
25°C
Full
–20
–200
–20
2
2
20
200
20
NC, NO
ON leakage current
Switch ON,
See Figure 16
INO(ON)
5.5 V
5.5 V
nA
nA
VCOM = 1 V,
VNO and VNC = Open,
ICOM(ON) or
VCOM = 4.5 V,
25°C
Full
COM
ON leakage current
See Figure 16
–200
200
VNO and VNC = Open,
Digital Control Inputs (IN1, IN2)(2)
Input logic high
Input logic low
VIH
VIL
VIO = 1.65 V to 1.95 V
VIO = 1.65 V to 1.95 V
Full
Full
0.65 × VIO
VIO
V
V
0
–2
0.35 × VIO
25°C
Full
2
Input leakage
current
IIH, IIL
VI = VIO or 0
5.5 V
nA
–20
20
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 5-V Supply(1) (continued)
V+ = 4.5 V to 5.5 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Dynamic
SYMBOL
TEST CONDITIONS
TA
V+
MIN
1
TYP MAX UNIT
25°C
Full
5 V
4.5 V
5 V
12.5
9.5
5
25
30
20
25
10
12
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
Turn-on time
Turn-off time
tON
tOFF
tBBM
ns
ns
ns
25°C
Full
1
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
4.5 V
5 V
25°C
Full
1
1
Break-before-make
time
VNC = VNO = V+/2,
CL = 35 pF,
RL = 50 Ω,
See Figure 19
4.5 V
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
Charge injection
QC
25°C
25°C
5 V
5 V
15
37
pC
pF
NO
VNO = V+ or GND,
Switch OFF,
CNO(OFF)
See Figure 17
OFF capacitance
VNC or VNO = V+ or
GND,
Switch ON,
NC, NO
ON capacitance
CNC(ON),
See Figure 17
25°C
5 V
130
pF
CNO(ON)
CCOM(ON)
CI
COM
ON capacitance
VCOM = V+ or GND,
Switch ON,
See Figure 17
See Figure 17
See Figure 20
See Figure 21
See Figure 22
25°C
25°C
25°C
25°C
25°C
25°C
5 V
5 V
5 V
5 V
5 V
5 V
130
6.5
pF
pF
Digital input
capacitance
VI = VIO or GND,
RL = 50 Ω,
Switch ON,
Bandwidth
OFF isolation
Crosstalk
BW
43
MHz
dB
RL = 50 Ω,
f = 1 MHz,
OISO
–63
–63
0.004
RL = 50 Ω,
f = 1 MHz,
XTALK
THD
dB
Total harmonic
distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
%
Supply
25°C
5.5 100
750
Positive supply
current
I+
VI = VIO or GND
5.5 V
nA
Full
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
4
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 3.3-V Supply(1)
V+ = 3 V to 3.6 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
V+
MIN TYP
MAX UNIT
VCOM
VNO
,
Analog signal range
ON-state resistance
0
V+
V
25°C
Full
0.75
0.9
1.2
VNO or VNC = 2 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
ron
3 V
3 V
Ω
ON-state resistance
match between
channels
25°C
0.1
0.15
VNO or VNC = 2 V, 0.8 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
∆ron
Ω
Ω
Full
0.15
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
25°C
0.2
0.1
ON-state resistance
flatness
ron(flat)
3 V
25°C
Full
0.3
0.3
20
VNO or VNC = 0.8 V, 2 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
VNO = 1 V, 3 V,
VCOM = 3 V, 1 V,
VNC = Open,
or
VNC = 1 V, 3 V,
VCOM = 3 V, 1 V,
VNO = Open,
25°C
–20
–50
2
NO, NC
OFF leakage current
INO(OFF)
INC(OFF)
,
Switch OFF,
See Figure 15
3.6 V
nA
Full
50
VNO = 1 V, 3 V,
VNC and VCOM = Open,
or
VNC = 1 V, 3 V,
VNO and VCOM = Open,
25°C
Full
–10
30
2
2
10
30
10
30
NC, NO
ON leakage current
Switch ON,
See Figure 16
INO(ON)
3.6 V
3.6 V
nA
nA
VCOM = 1 V,
VNO and VNC = Open,
ICOM(ON) or
VCOM = 3 V,
25°C
Full
–10
–30
COM
ON leakage current
See Figure 16
VNO and VNC = Open,
Digital Control Inputs (IN1, IN2)(2)
Input logic high
Input logic low
VIH
VIL
VIO = 1.65 V to 1.95 V
VIO = 1.65 V to 1.95 V
Full
Full
0.65 × VIO
VIO
V
V
0
–2
0.35 × VIO
25°C
Full
2
Input leakage current
IIH, IIL
VI = VIO or 0
3.6 V
nA
–20
20
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 3.3-V Supply(1) (continued)
V+ = 3 V to 3.6 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Dynamic
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX UNIT
25°C
Full
3.3 V
3 V
5
3
1
1
1
1
15
9
30
35
20
25
13
15
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
Turn-on time
Turn-off time
tON
tOFF
tBBM
ns
ns
ns
25°C
Full
3.3 V
3 V
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
25°C
Full
3.3 V
3 V
8
Break-before-make
time
VNC = VNO = V+/2,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
Charge injection
QC
25°C
25°C
3.3 V
3.3 V
6.5
38
pC
pF
NO
VNO = V+ or GND,
Switch OFF,
CNO(OFF)
See Figure 17
OFF capacitance
VNC or VNO = V+ or
GND,
Switch ON,
NC, NO
ON capacitance
CNC(ON),
See Figure 17
25°C
3.3 V
133
pF
CNO(ON)
CCOM(ON)
CI
COM
ON capacitance
VCOM = V+ or GND,
Switch ON,
See Figure 17
See Figure 17
See Figure 20
See Figure 21
See Figure 22
25°C
25°C
25°C
25°C
25°C
25°C
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
133
6.5
pF
pF
Digital input
capacitance
VI = VIO or GND,
RL = 50 Ω,
Switch ON,
Bandwidth
OFF isolation
Crosstalk
BW
42
MHz
dB
RL = 50 Ω,
f = 1 MHz,
OISO
–63
–63
0.004
RL = 50 Ω,
f = 1 MHz,
XTALK
THD
dB
Total harmonic
distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
%
Supply
25°C
10
50
Positive supply
current
I+
VI = VIO or GND
3.6 V
nA
Full
300
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
6
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 2.5-V Supply(1)
V+ = 2.25 V to 2.75 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Analog Switch
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP
MAX UNIT
VCOM
VNO
,
Analog signal range
ON-state resistance
0
V+
V
25°C
Full
1
1.3
1.6
0.2
VNO or VNC = 1.8 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
ron
2.25 V
2.25 V
Ω
ON-state resistance
match between
channels
VNO or VNC = 1.8 V,
0.8 V,
ICOM = –100 mA,
25°C
0.15
Switch ON,
See Figure 14
∆ron
Ω
Ω
Full
0.2
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
25°C
0.5
ON-state resistance
flatness
ron(flat)
2.25 V
2.75 V
VNO or VNC = 0.8 V, 1 V,
1.8 V,
ICOM = –100 mA,
25°C
Full
0.25
0.5
0.6
20
Switch ON,
See Figure 14
VNO = 0.5 V, 2.2 V,
VCOM = 2.2 V, 0.5 V,
VNC = Open,
25°C
–20
–50
2
NO, NC
OFF leakage current
INO(OFF)
INC(OFF)
,
Switch OFF,
See Figure 15
or
nA
Full
50
VNC = 0.5 V, 2.2 V,
VCOM = 2.2 V, 0.5 V,
VNO = Open,
VNO = 0.5 V, 2.2 V,
VNC and VCOM = Open,
or
VNC = 0.5 V, 2.2 V,
VNO and VCOM = Open,
25°C
Full
–10
–20
–10
–50
2
2
10
20
10
50
NC, NO
ON leakage current
Switch ON,
See Figure 16
INO(ON)
2.75 V
2.75 V
nA
nA
VCOM = 0.5 V,
VNO and VNC = Open,
ICOM(ON) or
VCOM = 2.2 V,
25°C
Full
COM
ON leakage current
Switch ON,
See Figure 16
VNO and VNC = Open,
Digital Control Inputs (IN1, IN2)(2)
Input logic high
Input logic low
VIH
VIL
VIO = 1.65 V to 1.95 V
VIO = 1.65 V to 1.95 V
Full
Full
0.65 × VIO
VIO
V
V
0
–2
0.35 × VIO
25°C
Full
2
Input leakage current
IIH, IIL
VI = VIO or 0
2.75 V
nA
–20
20
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
Electrical Characteristics for 2.5-V Supply(1) (continued)
V+ = 2.25 V to 2.75 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
Dynamic
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX UNIT
25°C
Full
2.5 V
2.25 V
2.5 V
5
5
2
2
1
1
20
10
11
35
40
20
25
20
25
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
Turn-on time
Turn-off time
tON
tOFF
tBBM
ns
ns
ns
25°C
Full
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
2.25 V
2.5 V
25°C
Full
Break-before-make
time
VNC = VNO = V+/2,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
2.25 V
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
Charge injection
QC
25°C
25°C
2.5 V
2.5 V
5
pC
pF
NO
VNO = V+ or GND,
Switch OFF,
CNO(OFF)
See Figure 17
38
OFF capacitance
VNC or VNO = V+ or
GND,
Switch ON,
NC, NO
ON capacitance
CNC(ON),
See Figure 17
25°C
2.5 V
135
pF
CNO(ON)
CCOM(ON)
CI
COM
ON capacitance
VCOM = V+ or GND,
Switch ON,
See Figure 17
See Figure 17
See Figure 20
See Figure 21
See Figure 22
25°C
25°C
25°C
25°C
25°C
25°C
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
135
6.5
pF
pF
Digital input
capacitance
VI = VIO or GND,
RL = 50 Ω,
Switch ON,
Bandwidth
OFF isolation
Crosstalk
BW
40
MHz
dB
RL = 50 Ω,
f = 1 MHz,
OISO
–63
–63
0.008
RL = 50 Ω,
f = 1 MHz,
XTALK
THD
dB
Total harmonic
distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
%
Supply
25°C
10
25
Positive supply
current
I+
VI = VIO or GND
2.75 V
nA
Full
100
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
8
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
TYPICAL PERFORMANCE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
IN
(V)
V
IN
Figure 1. ron vs VCOM (V+ = 2.5 V)
Figure 2. ron vs VCOM (V+ = 3.3 V)
60
50
40
30
20
10
0
1.0
0.8
0.6
0.4
0.2
0.0
COM (ON)
NC (OFF)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−60 −40
−20
0
20
(5C)
40
60
80
100
V
IN
(V)
T
A
Figure 3. ron vs VCOM (V+ = 5 V)
Figure 4. Leakage Current vs Temperature (V+ = 5 V)
60
50
40
30
20
10
0
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
V
= 2.5 V
+
V
+
= 5 V
V
+
= 3.3 V
3
−60 −40
−20
0
20
(°C)
40
60
80
100
0
1
2
4
5
6
T
A
V
COM
(V)
Figure 5. I+ vs Temperature (V+ = 5 V)
Figure 6. Charge Injection (QC) vs VCOM
9
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0.75-Ω DUAL SPDT ANALOG SWITCH
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SCDS232B–JUNE 2006–REVISED APRIL 2007
TYPICAL PERFORMANCE (continued)
16
14
12
10
8
25
20
15
10
5
t
ON
t
ON
t
OFF
t
OFF
6
0
−60 −40
−20
0
20
T – Temperature 5C
A
40
60
80
100
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
V
+
Figure 7. tON/tOFF vs Supply Voltage
Figure 8. tON/tOFF vs Temperature (V+ = 5 V)
0
−5
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−15
−20
−25
0.01
1
10
100
1000
0.01
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Figure 9. Gain vs Frequency (V+ = 5 V)
Figure 10. Crosstalk vs Frequency (V+ = 5 V)
0
0.006
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.005
0.004
0.003
0.002
10
1k
10k
100k
1M
10
1k
10k
100k
1M
Frequency (Hz)
Frequency (MHz)
Figure 11. OFF Isolation vs Frequency (V+ = 5 V)
Figure 12. Total Harmonic Distortion vs Frequency
(V+ = 2.5 V)
10
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0.75-Ω DUAL SPDT ANALOG SWITCH
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SCDS232B–JUNE 2006–REVISED APRIL 2007
TYPICAL PERFORMANCE (continued)
6
5
4
3
2
1
0
V
V
= 1.65 V, V = 5.5 V
+
IO
= 1.95 V, V = 5.5 V
IO
+
V
IO
V
IO
V
IO
= 1.65 V, V = 3.6 V
+
= 1.95 V, V = 3.6 V
+
= 1.65 V, V = 2.25 V
+
V
IO
= 1.95 V, V = 2.25 V
+
0.2 0.4
0.6 0.8
1.0 1.2
(V)
1.4 1.6
V
IN
Figure 13. VIO Thresholds
11
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0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION
V
+
V
NO
NO
IN
COM
V
COM
+
Channel ON
COM * VNO
W
V
r
+
on
ICOM
I
COM
V
I
V = V or V
I
IH
IL
+
GND
Figure 14. ON-State Resistance (ron)
V
+
V
NO
NO
IN
OFF-State Leakage Current
Channel OFF
COM
V
COM
+
+
V = V or V
IL
I
IH
V
I
+
GND
Figure 15. OFF-State Leakage Current (ICOM(OFF), INC(OFF), ICOM(PWROFF), INC(PWR(FF)
)
V
+
V
NO
NO
IN
COM
ON-State Leakage Current
Channel ON
V
COM
+
V = V or V
IL
I
IH
V
I
+
GND
Figure 16. ON-State Leakage Current (ICOM(ON), INC(ON)
)
12
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0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
+
V
NO
NO
Capacitance
Meter
V
BIAS
= V , V , or GND and
+ IO
V = V or GND
I
IO
COM COM
IN
Capacitance is measured at NO,
COM, and IN inputs during ON
and OFF conditions.
V
BIAS
V
I
GND
Figure 17. Capacitance (CI, CCOM(OFF), CCOM(ON), CNC(OFF), CNC(ON)
)
V
+
TEST
R
L
C
L
V
COM
V
NO
NO
t
50 Ω
50 Ω
35 pF
35 pF
V
ON
+
COM
IN
V
COM
(2)
C
L
R
L
t
V
+
OFF
V
I
V
0
Logic
Input
(V )
I
IO
50%
50%
Logic
(1)
GND
Input
t
ON
t
OFF
Switch
Output
90%
90%
(V
NO
)
(1)
(2)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t < 5 ns, t < 5 ns.
C includes probe and jig capacitance.
L
O
r
f
Figure 18. Turn-On (tON) and Turn-Off Time (tOFF
)
13
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0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
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SCDS232B–JUNE 2006–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
+
V
Logic
Input
(V )
I
IO
V
NC
or V
NO
50%
90%
NC or NO
NC or NO
0
V
COM
COM
Switch
Output
90%
(2)
C
R
L
L
(V
)
COM
IN
V
I
t
BBM
Logic
(1)
V
or V = V /2
NO +
NC
GND
Input
R = 50 Ω
L
C = 35 pF
L
(1)
(2)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t < 5 ns, t < 5 ns.
C includes probe and jig capacitance.
L
O
r
f
Figure 19. Break-Before-Make Time (tBBM
)
V
+
Network Analyzer
50 W
V
NO NO
Channel ON: NO to COM
V = V or V
V
COM
COM
I
IH
IL
Source
Signal
Network Analyzer Setup
V
IN
Source Power = 0 dBm
(632-mV P-P at 50-W load)
I
50 W
+
GND
DC Bias = 350 mV
Figure 20. Bandwidth (BW)
14
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TS5A26542
0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
+
Network Analyzer
50 W
Channel OFF: NO to COM
V = V or GND
V
NO
IN
NO
I
IO
V
COM
COM
Source
Signal
50 W
Network Analyzer Setup
Source Power = 0 dBm
V
I
(632-mV P-P at 50-W load)
50 W
+
GND
DC Bias = 350 mV
Figure 21. OFF Isolation (OISO
)
V
+
Network Analyzer
50 W
V
NO1
NO1
NO2
Channel ON: NO to COM
Network Analyzer Setup
COM1
COM2
Source
Signal
V
NO2
50 W
Source Power = 0 dBm
(632 mV P-P at 50 W load)
V
I
IN
50 W
+
DC Bias = 350 mV
GND
Figure 22. Crosstalk (XTALK
)
15
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0.75-Ω DUAL SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS232B–JUNE 2006–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
IH
V
+
Logic
Input
(V
I)
OFF
ON
OFF
V
IL
R
GEN
NO
IN
COM
V
COM
+
V
COM
∆V
COM
V
GEN
(1)
C
L
V
= 0 to V
= 0
GEN
+
V
I
R
GEN
C = 1 nF
L
Logic
(2)
GND
Q = C × ∆V
C L COM
Input
V = V or V
IL
I
IH
(1)
(2)
C includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t < 5 ns, t < 5 ns.
L
O
r
f
Figure 23. Charge Injection (QC)
V = (V – V /2) or −V /2
Channel ON: COM to NO
= V P-P
R = 600 Ω
I
IO
+
+
L
V
f = 20 Hz to 20 kHz
SOURCE
C = 50 pF
L
SOURCE
+
V /2
+
Audio Analyzer
NO
Source
Signal
COM
IN
(1)
C
L
600 W
V
I
600 W
−V /2
+
(1)
C includes probe and jig capacitance.
L
Figure 24. Total Harmonic Distortion (THD)
16
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TS5A26542YZTR
ACTIVE
DSBGA
YZT
12
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
TS5A26542YZTR
YZT
12
ASEK
180
8
1.5
2.03
0.7
4
8
Q2
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
ASEK
Length (mm) Width (mm) Height (mm)
TS5A26542YZTR
YZT
12
220.0
220.0
34.0
Pack Materials-Page 2
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