TSB12LV21APGF [TI]
IEEE 1394-1995 BUS TO PCI BUS INTERFACE; IEEE1394- 1995总线到PCI总线接口
| 型号： | TSB12LV21APGF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
| 文件： | 总18页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
Supports Provisions of IEEE 1394-1995
Provides PCI Slave Function for Read/Write
Access of Internal Registers
(1394) Standard for High-Performance
†
Serial Bus
Supports the Plug-and-Play (PnP)
Specification
Performs the Function of a 1394 Cycle
Master
Provides an 8-/16-bit Zoom Video (ZV) Port
for the Transferring of Video Data Directly
to an External Motion Video Memory Area
Supports 1394 Transfer Rates of 100, 200
and 400 Mbit/s
Provides Three Sizes of Programmable
FIFOs
Operates from a 3.3-V Power Supply While
Maintaining 5-V Tolerant Inputs
Provides PCI Bus Master Function for
Supporting DMA Operations
High-Performance 176-Pin PQFP (PGF)
Package
Compliant With PCI Specification 2.1
description
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to
transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the
local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and
is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and
receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access
the physical layer control and status registers by the application software.
An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates
the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous
transmit, and isochronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and
target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and
system designers to assign their own unique identification codes. An autoboot mode allows data-moving
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is
connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional
branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels
are provided to accommodate programmable data types. PCLs can be chained together to form a channel
control program that can be developed to support each DMA channel. Data can be stored in either big endian
or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred
to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the
best memory use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
description (continued)
The RAM, ROM, AUX, ZV, and general purpose I/O (GPIO) ports collectively implement the local bus interface.
These ports are mapped into the PCI address can be accessed either through the PCI bus or internal DMA
transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth.
DMA packet control lists or other data that may be stored in external RAM or ROM attached to the local bus
interface. This further reduces PCI use and generally improves performance. The ZV local bus port is designed
to transfer data from 1394 video devices to an external device connected to the PCILynx ZV port. This interface
provides a method of receiving 1394 digital camera packets directly to a ZV-compliant device attached to the
local bus interface.
Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal
states and provides a convenient software debug capability. Programmable interrupts are available to inform
driver software of important events such as 1394 bus resets and DMA-to-PCL transfer completion.
The 3.3-V internal operation provides reduced power consumption while maintaining compatibility with 5-V
signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PGF PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
3.3V V
132
131
130
129
128
127
126
125
124
123
122
121
zv_data_valid
zv_hsync
GND
CC
NC
pci_ad25
pci_ad24
pci_cbez3
GND
zv_ext_clk
3.3V V
CC
zv_vsync
zv_pix_clk
gpio_data0
gpio_data1
gpio_data2
gpio_data3
GND
pci_idselz
3.3V V
CC
9
pci_ad23
pci_ad22
pci_ad21
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
5V V
pci_ad20
GND
CC
120
119
NC
aux_adr0
aux_adr1
aux_adr2
pci_ad19
pci_ad18
pci_ad17
pci_ad16
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
3.3V V
aux_adr3
GND
CC
3.3V V
pci_cbez2
GND
CC
aux_adr4
aux_adr5
aux_adr6
aux_adr7
pci_framez
pci_irdyz
pci_trdyz
pci_devselz
5V V
aux_adr8
CC
3.3V V
pci_stopz
GND
3.3V V
CC
CC
aux_adr9
aux_adr10
aux_adr11
aux_adr12
NC
30
31
32
33
34
35
36
37
38
39
pci_perrz
pci_serrz
pci_par
102
101
100
99
98
97
96
95
94
GND
aux_adr13
3.3V V
pci_cbez1
GND
3.3V V
CC
CC
aux_adr14
aux_adr15
aux_data0
aux_data1
GND
pci_ad15
pci_ad14
pci_ad13
pci_ad12
aux_data2
40
41
42
43
93
92
91
90
5V V
3.3V V
CC
pci_ad11
3.3V V
CC
aux_data3
aux_data4
aux_data5
CC
pci_ad10
pci_ad9
89 GND
44
NC – No internal connection
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
Terminal Functions
Terminal
I/O
Description
Name
3.3V V
No.
1,8,19,26,33,42,49
56,70,75,86,93,100
107,116,128,136,138,
145,157,165,172
I
3.3-V power input
CC
5V V
12,40,60,63
84,109,135,162
I
5-V tolerant power input. When interfacing with a 3.3-V parts, these termi-
nals should be connected to 3.3-V power.
CC
autoboot
159
I
Autoboot to select autoboot mode
Auxiliary port address lines
aux_adr15–0
98,99,101,103–106
108,110–113,115
117–119
O
aux_clk
64
69
O
O
Auxiliary port clock out (output at frequency of PCI clock)
Auxiliary port chip select
aux_csz
aux_data15–0
76–78,80–83,85,87
88,90–92,94,96,97
I/O Auxiliary port bidirectional data bus to external logic
aux_intz
aux_oez
aux_rdy
aux_rstz
aux_wez1–0
GND
61
I
O
I
Auxiliary port interrupt
74
Auxiliary port output enable
Auxiliary port ready indication (from external logic)
Auxiliary port reset out
62
66
O
O
I
71,73
Auxiliary port write strobes (to external logic)
Ground
6,14,21,28,35,45
51,65,72,79,89,95
102,114,121,130,141
150,155,158,160,168
175
gpio_data3–0
link_cyclein
link_cycleout
N/C
122–125
137
I/O Auxiliary port general purpose programmable I/O signals
I
Optional external 8-kHz clock
Cycle timer 8-kHz cycle clock out
Not connected
139
O
2,29,46,120
pci_ad31–0
169–171,173,174,176 I/O PCI multiplexed address/data bus signals
3,4,9–11,13,15–18
36–39,41,43,44,47,50
52–55,57–59
pci_cbez3–0
pci_clk
5,20,34,48
I/O PCI multiplexed command/byte enable signals
PCI system clock
161
25
I
pci_devselz
pci_framez
I/O PCI device select
I/O PCI frame signal
22
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
Terminal Functions (continued)
Terminal
I/O
Description
Name
pci_gntz
No.
164
7
I
PCI bus grant signal (from PCI bus arbiter)
pci_idselz
pci_intaz
I/O PCI initialization device select
OD PCI system interrupt A. This is an open drain signal.
I/O PCI initiator-ready signal
166
23
pci_irdyz
pci_par
32
I/O PCI parity signal
pci_perrz
pci_reqz
30
I/O PCI data-parity-error signal
167
163
31
O
I
PCI master bus request (to PCI bus arbiter)
PCI system reset
pci_resetz
pci_serrz
pci_stopz
pci_trdyz
OD PCI system-error signal. This is an open drain signal.
I/O PCI stop signal
27
24
I/O PCI target-ready signal
phy_clk50
phy_ctl0 –1
phy_data0–7
phy_lreq
156
I
50-MHz system clock (from PHY chip)
142,143
I/O Phy-link bidirectional control lines
I/O Phy-link bidirectional data lines
146–149,151–154
144
67
O
O
O
Phy-link request signal
External RAM chip select
External ROM chip select
ram_csz
rom_csz
68
seeprom_clk
seeprom_data
test_out
133
134
140
132
129
131
126
127
I/O External serial EEPROM data clock
I/O External serial EEPROM read/write data line
O
O
I
Test MUX out
zv_data_valid
zv_ext_clk
zv_hsync
zv_pix_clk
zv_vsync
Zoom port data-valid signal
Zoom port external clock input
Zoom port horizontal-sync output
Zoom port pixel clock
O
O
O
Zoom port vertical-sync output
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
system block diagram
1394 Peripheral Devices
Personal Computer
1394
CD ROM
Serial EEPROM
1394
Laser
Printer
PCILynx-to-Phy
1394
3 Port
Interface
1394
Desktop
Camera
PCILynx
(TSB12LV21A)
Physical
Layer
Interface
1394
Digital
VCR
AUX Port Local Bus
DMA
User
Defined
Function
(AUX)
Flash
PROM
(RPL ROM)
ZV
Port
(Video)
Channel
Control
(SRAM)
1394
Video
Cable
Set-Top
Box
Host Local Bus
PCI Host
Bridge
Host
CPU
Local
Memory
PCI
Agent
PCI
Agent
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
functional block diagram
seeprom_data
aux_clk
Serial EPROM
Interface
aux_rstz
seeprom_clk
32
aux_intz
4
pci_ad31 – pci_ad0
/
4
gpio_data3 – gpio_data0
/
pci_cbez3 – pci_cbez0
/
16
PCI Master
PCI Slave
aux_adr15 – aux_adr0
pci_par
pci_framez
pci_irdyz
pci_trdyz
pci_devselz
pci_stopz
pci_idselz
pci_perrz
pci_serrz
pci_reqz
/
Local Bus
Interface
Logic
16
aux_data15 – aux_data0
aux_oez
/
RAM
ROM
AUX
ZV
2
aux_wez1 – aux_wez0
aux_rdy
/
3
zv_hsync, zv_vsync, zv_pix_clk
zv_data_valid
/
3
PCI Configuration Control
and Status Registers
aux_csz, rom_csz, ram_csz
zv_ext_clk
/
pci_gntz
pci_clk
pci_resetz
pci_intaz
PCI Bus Logic
DMA Control
and
DMA Engine
Status Registers
DMA Logic
General
Receiver
FIFO
Asynchronous
Transmit
FIFO
Isosynchronous
Pointer
Address
Mapping Logic
FIFO Control
and Status
Registers
Transmit
FIFO
FIFO Logic
2
1394 Link Layer Control (LLC) Logic
phy_ctl0 – phy_ctl1
/
8
1394 Packet
Transmit
Timer
Cycle
phy_data0 – phy_data7
/
1394 LLC
Control and
Status Reg-
isters
Phy-Link
Interface
Logic
Control Logic
phy_clk50
phy_lreq
link_cyclein
link_cycleout
CRC Logic
Parallel-to-Serial
Serial-to-Parallel
1394 Packet
Cycle
Receive
Monitor
Control Logic
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(V
= 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.0 V
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
CC(3V) CC
(V
CC(5V) CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+0.5 V
+ 0.5 V
I
CC(5v)
CC(5v)
Output voltage range at any output, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
3
NOM
3.3
5
MAX
3.6
UNIT
V
V
= 3 V
= 5 V
CC
Supply voltage, V
V
CC
4.5
0
5.5
CC
Input voltage, V
V
V
V
I
CC(5v)
Output voltage, V
0
V
O
CC(3V)
0.475 ×
CC(3V)
2
PCI terminals
V
High-level input voltage,
CC(5V)
CC(5V)
V
V
V
IH
All other terminals
PCI terminals
V
0.325 V
Low-level input voltage,
CC(3V)
0.8
V
V
IL
All other terminals
PCI terminals
6
6
Rise time, input,t
ns
r
All other terminals
PCI terminals
6
Fall time, input,t
ns
f
All other terminals
6
Junction temperature, T
0
115
°C
J
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PCI interface switching characteristics, see Figure 1
TEST
CONDITION
PARAMETER
MEASURED
40% to 40%
40% to 40%
MIN
7
TYP
MAX
UNIT
ns
†
t
t
Setup time, pci_xx low or high to pci_clk high
su1
†
Hold time, pci_clk high to pci_xx low or high , pci_gntz low or
high
0
ns
h1
†
t
t
t
Delay time, pci_clk high to pci_xx low or high
40% to 40%
40% to 40%
40% to 40%
2
10
2
11
13
ns
ns
ns
d1
Setup time, pci_gntz low or high to pci_clk high
Delay time, pci_clk high to pci_intaz low or high
su2
d2
†
In this case, pci_xx refers to the following signals; pci_ad31–0, pci_cbez3–0, pci_par, pci_framez, pci_irdyz, pci_trdyz, pci_devselz, pci_stopz,
pci_idselz, pci_perrz, pci_serrz, pci_reqz.
phy-link interface switching characteristics, see Figure 2
TEST
CONDITION
PARAMETER
MEASURED
MIN
TYP
MAX
UNIT
†
t
t
t
t
t
Setup time, phy_xx low or high to phy_clk high
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
4
1
3
5
3
ns
ns
ns
ns
ns
su3
Hold time, phy_clk high to phy_xx, link_cyclein low or high
h2
†
Delay time, phy_clk high to phy_xx, phy_lreq low or high
Setup time, phy_clk high to link_cyclein low or high
Delay time, phy_clk high to lynk_cycleout low or high
11
13
d3
su4
d4
†
In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
local bus switching characteristics, see Figure 3
TEST
CONDITION
PARAMETER
MEASURED
MIN
TYP
MAX
UNIT
Delay time, aux_clk high to aux_adr, aux_data15–0 (write),
aux_oez valid
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
0
0
15
20
ns
ns
d5
†
Delay time, aux_clk high to rom_csz, ram_csz, aux_csz valid
d6
Delay time, aux_wez0, aux_wez1 high (deasserted) to
aux_adr, aux_data15–0 (write), aux_oez, rom_csz, ram_csz,
aux_csz valid
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
0.5
0
ns
ns
d7
Delay time, aux_clk low to aux_wez0, aux_wez1 low
(asserted)
10
d8
Delay time, aux_clk high to aux_wez0, aux_wez1 high
(deasserted)
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
0
2
10
15
ns
ns
d9
Delay time, aux_clk high to gpio_data3–0 valid
d10
Setup time, aux_adr, adr_data15–0 (write), auxoez, rom_csz,
ram_csz, aux_csz valid before aux_wez0, aux_wez1 low
(asserted)
t
1.3 V to 1.3 V
5
ns
su5
Setup time, aux_data15–0 (read), aux_rdyz, gpio_data3–0
valid before aux_clk high
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
10
0
ns
ns
su6
Hold time, aux_data15–0 (read), auxrdyz, gpio_data3–1
invalid after aux_clk high
h3
†
These signals are asserted asynchronously when a ZOOM port transfer imediately preceeds the local bus transfer. In all cases, the setup time
to aux_wez and the number of waitstates remain the same.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle
TEST
CONDITION
PARAMETER
MEASURED
MIN
12
TYP
MAX
UNIT
ns
Setup time, zv_hsync low, zv_vsync, zv_data_valid high before
zv_pix_clk high
t
t
1.3 V to 1.3 V See Figure 4
1.3 V to 1.3 V See Figure 4
su7
Hold time, zv_hsync high, zv_vsync, zv_data_valid low after
zv_pix_clk low
14
ns
h4
t
t
Setup time, aux_data7–0 valid before zv_pix_clk high or low
Hold time, aux_data7–0 valid after zv_pix_clk high or low
1.3 V to 1.3 V See Figure 4
1.3 V to 1.3 V See Figure 4
10
14
ns
ns
su8
h5
Delay time, zv_hsync low, zv_vsync, zv_data_valid high after
zv_pix_clk low
t
1.3 V to 1.3 V See Figure 5
–1
3
5
ns
d11
t
t
t
t
Delay time, aux_data7–0 invalid after zv_pix_clk low
Setup time, zv_hsync low before zv_pix_clk high
Hold time, zv_hsync high after zv_pix_clk high
Setup time, zv_vsync high before zv_pix_clk high
1.3 V to 1.3 V See Figure 5
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
–1
25
14
10
ns
ns
ns
ns
d12
su9
h6
su10
Setup time, aux_data7–0 valid, zv_data_valid high before
zv_pix_clk high
t
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
25
14
ns
ns
su11
h7
Hold time, aux_data7–0 valid, zv_data-valid low after
zv_pix_clk high
t
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
pci_clk
t
d1
t
su1
t
h1
pci_xx
(Bidirectional
(see Note A)
t
d2
pci_intaz
t
su2
t
h1
pci_gntz
NOTE A: In this case, pci_xx refers to the following bidirectional signals; pci_ad31–0, pci_cbez3–0, pci_par, pci_framez,
pci_irdyz, pci_trdyz, pci_devselz, pci_stopz, pci_idselz, pci_perrz, pci_serrz, pci_reqz.
Figure 1. PCI Interface Timing Waveforms
phy_clk
t
d3
t
t
h2
su3
phy_xx
(Bidirectional
(see Note A)
t
d3
phy_lreq
t
d4
link_cycleout
t
t
h2
su4
link_cyclein
NOTE A: In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
Figure 2. Phy-Link Interface Timing Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
OUTPUTS
aux_clk
t
d5
aux_adr15–0
aux_data15–0 (write)
aux_oez
DATA VALID
DATA VALID
(see Note A)
t
d6
t
d7
rom_csz
ram_csz
aux_csz
t
su5
t
d8
t
d9
t
d9
aux_wez0
aux_wez1
t
d10
Wait States = 0
Wait States > 0
gpio_data7–0
INPUTS
DATA VALID
t
su6
t
h3
DATA
VALID
aux_data
aux_rdyz
DATA
VALID
DATA
VALID
gpio_data7–0
NOTE A: These signals are asserted asynchronlusly when a ZOOM port transfer immediately preceeds the local bus transfer. In all cases,
the setup time to aux_wez and the number of waitstates reamins valid.
Figure 3. Local Bus Timing Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
internal
zv_pix_clk
zv_pix_clk
(gated, 8 bit)
t
su7
t
h4
zv_hsync
zv_vsync
zv_data_valid
t
su8
t
h5
t
t
h5
su8
aux_data15–0
(Write)
8-BIT DATA VALID
8-BIT DATA VALID
NOTES: A. The data is in 8-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 4. Zoom Video IF Timing Waveforms (8 Bit, Divide-By-2 Mode)
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Internal
zv_pix_clk
zv_pix_clk
(gated, 16 bit)
t
t
d11
d11
zv_hsync
zv_vsync
zv_data_valid
t
t
d12
d12
aux_data15–0
(16 bit only)
16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-1 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
Figure 5. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-1 Mode)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
Internal
zv_pix_clk
(see Note A)
zv_pix_clk
(gated, 16 bit)
t
t
h6
su9
zv_hsync
t
su10
zv_vsync
zv_data_valid
t
t
h7
su9
aux_data15–0
(Write)
16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk terminal. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 6. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-2 Mode)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
APPLICATION INFORMATION
power supply sequencing
Turning power supplies on and off within a mixed 5-V/3.3-V system is an important consideration. A few basic
rulesneedtobeobservedtoavoiddamagingPCILynxdevices. Checkwiththemanufacturersofallcomponents
used in the 3.3-V to 5-V interface to ensure that no unique device characteristics exist that would lead to more
restrictive rules.
When the 3.3-V supply is turned on before turning on the 5-V supply. PCILynx output buffers in a logic 1
state can supply large amounts of current through their clamp diodes to the 5-V supply terminals (5V V ).
CC
This can lead to excessive power dissipation and violation of current density limits. However, if the 5-V
supply is turned on before the 3.3-V supply, the maximum drain-to-gate voltage of the n-channel transistors
in the 5-V tolerant buffers exceeds the recommended value and the effects of channel-hot carries can be
accelerated.
When turning on the power supply, all 3.3-V and 5-V supplies should start ramping up from 0 V and reach
95% of their end-point values within a 25-ms time window. All bus contention between the PCILynx and
external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping
is to ramp the 3.3-V supply followed by the 5-V supply. This order is not mandatory, but it allows a larger
cumulative number of power-supply events than the reverse order.
When turning off the power supply, all 3.3-V and 5-V supplies should start ramping down from steady state
values and reach 5% of these values within a 25-ms window. All bus contention between the PCILynx and
external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping
is to ramp down the 5-V supply followed by the 3.3-V supply. This order is not mandatory, but it allows a
larger cumulative number of power-supply off events than the reverse order.
A cumulative total of 250 seconds of power supply turn-on and turn-off events is allowed during the
operating lifetime of the PCILynx under worst-case conditions. Worst-case conditions are where the 5-V
supply is ramped up before the 3.3-V supply and the 3.3-V supply is ramped down before the 5-V supply.
If the maximum time window of the 25 ms is used, a total of 10,000 power supply on or off events can occur
as long as the 25-ms time window is observed.
An additional precaution must be observed when the PCILynx is connected to a 5-V IEEE 1394
physical-layer device that is powered from the 1394 cable. In this case, it is possible for the physical-layer
device to have power while the PCILynx does not. It is essential that the physical-layer device must not
supply a high signal on any terminal that connects to the PCILynx while the PCILynx power is off. This is
normally achieved through the use of the link-power status terminal on the physical-layer device.
If any of these precautions and guidelines are not followed, the PCILynx device can experience possible failures
related to overheating, accumulation of channel-hot carriers, and/or metal migration due to excessive current
density.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
MECHANICAL INFORMATION
PLASTIC QUAD FLATPACK
PGF (S-PQFP-G176)
132
89
133
88
0,27
M
0,08
0,17
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°–7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 03/95
NOTES: F. All linear dimensions are in millimeters.
G. This drawing is subject to change without notice.
H. Falls within JEDEC MO-136
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Copyright 1998, Texas Instruments Incorporated
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