TSB12LV21 [TI]
IEEE 1394 LINK LAYER CONTROLLER; IEEE 1394链路层控制器
| 型号： | TSB12LV21 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IEEE 1394 LINK LAYER CONTROLLER |
| 文件： | 总22页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
D
D
D
IEEE Standard for a 1394-1995 Compliant
IEEE Standard for a 1212-1991 Compliant
D
D
D
Provides 4 General-Purpose Input/Outputs
Supports Plug-and-Play (PnP) Specification
Supports IEEE 1394-1995 Link Layer
Control
Generates 32-bit CRC for Transmission of
1394 Packets
D
D
D
D
D
PCI Local Bus Specification Rev. 2.1
Compliant
D
D
D
D
Performs 32-bit CRC Checking on
Reception of 1394 Packets
Supports IEEE 1394 Transfer Rates of 100,
200, and 400 Mb per second
Provides PCI Bus Master Function for
Supporting DMA Operations
3.3-V Core Logic while Maintaining 5-V
Tolerant Inputs
Provides PCI Slave Function for Read/Write
Access of Internal Registers
Performs the Function of 1394 Cycle
Master
Supports Distributed DMA Transfers
Between 1394 and Local Bus RAM, ROM,
AUX, or Zoomed Video
Provides 4K Bytes of Configurable FIFO
RAM
D
D
Advanced Submicron, Low-Power CMOS
Technology
D
Provides 5 Scatter-Gather DMA Channels
Packaged in a 176-Pin PQFP (PGF)
D
Provides Software Control of Interrupt
Events
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 11
Signal Name/Terminal Number Sort Tables . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PCI Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 13
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
description
The TSB12LV21B (PCILynx-2) provides a high-performance IEEE 1394-1995 interface with the capability to
transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to
the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device;
it is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and
receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access
the physical layer control and status registers by the application software. The PCILynx–2 complies with
D
D
D
D
PCI Local Bus Specification, Revision 2.1
IEEE Standard for a 1394-1995 High Performance Serial Bus
IEEE Standard 1212-1991
IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses
An internal 4Kbyte-memory can be configured as multiple variable-size FIFOs, eliminating the need for external
FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and
isynchronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating both as a master
and as a target device. Configuration registers can be loaded from an external serial EEPROM, allowing board
and system designers to assign their own unique identification codes. An autoboot mode allows data-moving
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is
connected to a local bus port. The PCLs implement an instruction set that allows linking, conditional branching,
1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels
accommodate programmable data types. PCLs can be chained together to form a channel control program that
can be developed to support each DMA channel. Data can be stored in either big endian or little endian format,
eliminating the need for the host CPU to perform byte swapping. Data can be transferred either to 4-byte aligned
locations, to provide the highest performance, or to nonaligned locations, to provide the best memory use.
The RAM, ROM, AUX, ZV, and general purpose I/O (GPIO) ports collectively make up the local bus interface.
These ports mapped into the PCI address, can be accessed either through the PCI bus or through internal DMA
transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth.
DMApacket control lists or other data may be stored in external RAM or ROM attached to the local bus interface.
This further reduces PCI bus use and generally improves performance. The ZV local bus port is designed to
transfer data from 1394 video devices to an external device connected to the PCILynx-2 ZV port. This interface
provides a method for receiving 1394 digital camera packets directly from a ZV-compliant device attached to
the local bus interface.
Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal
states and provide a convenient software debug capability. Programmable interrupts are available to inform
driver software of important events, such as 1394 bus resets and DMA-to-PCL transfer completion.
The 3.3-V internal operation provides reduced power consumption, while maintaining compatibility with 5-V
signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
terminal assignment
PGF QUAD FLATPACK PACKAGE
TOP VIEW
seeprom_clk
seeprom_data
133
134
135
136
137
138
139
140
141
142
143
144
aux_data6
aux_data7
3.3V V
CC
au_data8
5VV
CC
aux_data9
aux_data10
aux_data11
aux_data12
89
87
86
85
84
83
82
81
80
5V V
3V V
CC
CC
link_cyclein
3.3V V
CC
link_cycleout
test_out
GND
phy_ctl0
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
GND
aux_data13
aux_data14
aux_data15
phy_ctl1
phy_lreq
3.3V V
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
CC
phy_data0
phy_data1
phy_data2
phy_data3
GND
3.3V V
CC
aux_oe
aux_we0
GND
aux_we1
3.3V V
CC
phy_data4
phy_data5
phy_data6
phy_data7
GND
aux_cs
rom_cs
ram_cs
aux_rst
GND
TSB12LV21B
phy_clk50
aux_clk
3.3V V
CC
5V V
CC
GND/test_enable
autoboot
GND
aux_rdy
aux_int
61
60
59
5V V
CC
pci_clk
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
pci_ad0
pci_ad1
pci_ad2
5V V
CC
58
57
56
55
54
53
52
51
50
49
48
47
pci_reset
pci_gnt
3.3V V
CC
3.3V V
CC
pci_ad3
pci_ad4
pci_ad5
pci_ad6
GND
pci_inta
pci_req
GND
pci_ad31
pci_ad30
pci_ad7
3.3V V
pci_ad29
3.3V V
CC
CC
pci_cbe0
pci_ad8
NC
pci_ad28
pci_ad27
GND
46
45
pci_ad26
GND
Figure 1. PCILynx-2 Terminal Assignment/Pinout
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
pin description table
This sections identifies and classifies the functionality of each pin on the PCILynx–2.
Table 1. Signals Sorted by Pin Number
PIN NO.
1
SIGNAL NAME
PIN NO.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
SIGNAL NAME
3.3V V
PIN NO.
83
SIGNAL NAME
PIN NO.
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
SIGNAL NAME
gpio_data1
gpio_data0
zp_pix_clk
zv_vsync
3.3V V
NC
aux_data9
CC
CC
2
pci_ad10
pci_ad9
GND
84
5.0VV
CC
3
pci_ad25
pci_ad24
pci_cbe3
GND
85
aux_data8
3.3V V
4
86
CC
5
NC
87
aux_data7
aux_data6
GND
3.3V V
CC
6
pci_ad8
pci_cbe0
88
zv_ext_clk
GND
7
pci_idsel
89
8
3.3V V
3.3V V
90
aux_data5
aux_data4
aux_data3
zv_hsync
CC
CC
9
pci_ad23
pci_ad22
pci_ad21
pci_ad7
GND
91
zv_data_valid
seeprom_clk
seeprom_data
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
92
pci_ad6
pci_ad5
pci_ad4
pci_ad3
93
3.3V V
CC
5.0V V
94
aux_data2
GND
5V V
3V V
CC
CC
CC
pci_ad20
GND
95
96
aux_data1
aux_data0
aux_adr15
aux_adr14
link_cyclein
3.3VV
pci_ad19
pci_ad18
pci_ad17
pci_ad16
3.3V V
97
CC
CC
pci_ad2
pci_ad1
pci_ad0
98
link_cylceout
test_out
GND
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
3.3V V
CC
3.3V V
5.0V V
aux_adr13
GND
phy_ctl0
phy_ctl1
phy_lreq
CC
CC
pci_cbe2
GND
aux_int
aux_rdy
aux_adr12
aux_adr11
aux_adr10
aux_adr9
pci_frame
pci_irdy
pci_trdy
pci_devsel
5.0V V
3.3V V
CC
CC
aux_clk
GND
phy_data0
phy_data1
phy_data2
phy_data3
GND
aux_rst
ram_cs
rom_cs
aux_cs
3.3V V
CC
aux_adr8
5.0V V
3.3V V
CC
pci_stop
GND
CC
aux_adr7
aux_adr6
aux_adr5
aux_adr4
GND
phy_data4
phy_data5
phy_data6
phy_data7
GND
NC
3.3V V
CC
pci_perr
pci_serr
pci_par
aux_we1
GND
aux_we0
aux_oe
3.3V V
aux_adr3
phy_clk50
CC
pci_cbe1
GND
3.3V V
3.3V V
3.3V V
CC
CC
CC
aux_data15
aux_data14
aux_data13
GND
aux_adr2
aux_adr1
aux_adr0
NC
test_out/GND
auto_boot
GND
pci_ad15
pci_ad14
pci_ad13
pci_ad12
pci_clk
aux_data12
aux_data11
aux_data10
GND
5.0V V
CC
5.0V V
CC
pci_ad11
gpio_data3
gpio_data2
pci_reset
pci_gnt
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
Table 1. Signals Sorted by Pin Number (Continued)
PIN NO.
165
SIGNAL NAME
3.3V V
PIN NO.
168
SIGNAL NAME
GND
PIN NO.
171
SIGNAL NAME
PIN NO.
174
SIGNAL NAME
pci_ad27
GND
pci_ad29
CC
166
pci_inta
pci_req
169
pci_ad31
pci_ad30
172
3.3V V
175
CC
167
170
173
pci_ad28
176
pci_ad26
Terminal Functions
power supply terminals
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
6, 14, 21, 28, 35, 45,
51, 65, 72, 79, 89,
95, 102, 114, 121,
130, 141, 150, 155,
160, 168, 175
GND
I
Device ground terminals
1, 8, 19, 26, 33, 42,
49, 56, 70, 75, 86,
93, 100, 107, 116,
128, 136, 138, 145,
157, 165, 172
3.3V VCC
5.0V VCC
I
I
3.3-V power supply terminal for core logic
12, 40, 60, 63, 84,
109, 162
5-V power rail for 5-V tolerant Input buffers
PCI system terminals
TERMINAL
NAME NO.
I/O
TYPE
FUNCTION
System PCI bus clock. This signal ranges from 0MHz–-33MHz MHz and provides timing for all transactions
on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.
pci_clk
161
I
pci_reset. When the PCI bus reset is asserted the pci_reset signal causes the PCILynx-2 to 3-state all
output buffers and reset all internal registers. When pci_reset is asserted, the device is completely
nonfunctional. After pci_reset is deasserted, the PCILynx-2 is in its default state.
pci_reset
pci_inta
163
166
I
OD
PCI system interrupt A. This is an open drain signal.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
Terminal Functions (Continued)
PCI address and data terminals
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
pci_ad31 – pci_ad29
pci_ad28
169 – 171
173
pci_ad27
174
pci_ad26
176
pci_ad25
3
pci_ad24
4
pci_ad23 – pci_ad21
pci_ad20
pci_ad19 – pci_ad16
pci_ad15 – pci_ad12
pci_ad11
9 – 11
13
15 – 18
36 – 39
41
Multiplexed PCI address and data signals. During the address phase of a primary bus PCI
cycle, pci_ad31:0 contain a 32-bit address or other destination information. During the data
phase pci_ad31:0 contain data
I/O
pci_ad10
43
pci_ad9
44
pci_ad8
47
pci_ad7
50
pci_ad6 – pci_ad3
pci_ad2 – pci_ad0
52 – 55
57 – 59
pci_cbe3
pci_cbe2
pci_cbe1
pci_cbe0
5
20
34
48
I/O
I/O
PCI Command/Byte enables
PCI bus parity. In all PCI bus read and write cycles the PCILynx–2 calculates even parit-
across the pci_ad31:0 and pci_cbe3:0 signals. As an initiator during PCI cycles, the
PCILynx-2 outputs this parity indicator with a one pci_clk delay. As a target during PCI
cycles, the calculated parity is compared to the initiator’s parity indicator. A miscompare
can result in the assertion of a parity error (pci_perr).
pci_par
32
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
Terminal Functions (Continued)
PCI interface control
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
PCI device select. The PCILynx-2 asserts this signal to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCILynx-2 monitors this signal until a target responds. If no target responds before
time-out occurs, then the PCILynx-2 will terminate the cycle with an initiator abort.
pci_devsel
pci_frame
24
I/O
I/O
PCI cycle frame. This signal is driven by the initiator of a bus cycle. pci_frame is asserted to indicate that a
bus transaction is beginning, and data transfers continue while this signal is asserted. When pci_frame is
deasserted the PCI bus transaction is in the final data phase.
22
PCI bus grant. This signal is driven by the PCI bus arbiter to grant the PCILynx-2 access to the PCI bus
after the current data transaction has completed. This signal may or may not follow a PCI bus request
depending upon the PCI bus parking algorithm.
pci_gnt
pci_idsel
pci_irdy
164
7
I
I
Initialization device select. pci_idsel selects the PCILynx-2 during configuration space accesses. pci_idsel
can be connected to one of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. pci_irdy indicates the PCI bus initiator’s ability to complete the current data phase of the
transaction. A data phase is completed upon a rising edge of pci_clk where both pci_irdy and pci_trdy are
asserted. Until pci_irdy and pci_trdy are both sampled asserted, wait states are inserted.
23
I/O
PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not
match pci_par, when pci_perr is enabled through bit 6 of the command register.
pci_perr
pci_req
30
I/O
O
167
PCI bus request. Asserted by the PCILynx-2 to request access to the PCI bus as an initiator.
PCI system error. Output that is pulsed from the PCILynx-2 when enabled through the command register,
indicating a system error has occurred. The PCILynx-2 needs not be the target of the PCI cycle in order to
assert this signal.
pci_serr
pci_stop
pci_trdy
31
27
24
OD
I/O
I/O
PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. This signal is used for target disconnects and is commonly asserted by target devices
which do not support burst data transfers.
PCI target ready. pci_trdy indicates the primary bus target’s ability to complete the current data phase of
the transaction. A data phase is completed upon a rising edge of pci_clk where both pci_irdy and pci_trdy
are asserted. Until both pci_irdy and pci_trdy are asserted, wait states are inserted.
IEEE 1394 PHY/LINK interface terminals
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
143
phy_ctl1
phy_ctl0
I/O
I/O
PHY-link bidirectional control lines
142
phy_data7 – phy_data4
phy_data3 – phy_data0
154 – 151
149 – 146
PHY-link bidirectional data lines
phy_clk50
phy_lreq
156
144
I
50MHz-System clock from PHY chip
O
PHY-link request signal generated by the PCILynx-2 controller
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
Terminal Functions (Continued)
auxiliary/zoom video port terminals
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
64
aux_clk
aux_rst
aux_int
O
O
I
Auxiliary port clock out. This signal is output at the frequency of the PCI clock.
Auxiliary port reset out
66
61
Auxiliary port interrupt input
aux_adr15 – aux_adr14
aux_adr13
98 – 99
101
aux_adr12 –aux_adr9
aux_adr8
103 – 106
108
O
Auxiliary port address lines output to external logic
aux_adr7 –aux_adr4
aux_adr3
110 – 113
115
aux_adr2 – aux_adr0
117 – 119
aux_data15 – aux_data13
aux_data12 – aux_data9
aux_data8
76 – 78
80 – 83
85
aux_data7 – aux_data6
aux_data5 – aux_data3
aux_data2
87 – 88
90 – 92
94
I/O
Auxiliary port bidirectional data bus to external logic
aux_data1 – aux_data0
96 – 97
aux_cs
aux_oe
aux_rdy
69
74
62
O
O
I
Auxiliary port chip select to external logic
Auxiliary port output enable to enable external logic data onto the auxiliary data bus
Auxiliary port ready indication from external logic
aux_we1
aux_we0
71
73
O
Auxiliary port write strobes to external logic
ram_cs
67
O
O
O
I
External RAM chip select
rom_cs
68
External ROM chip select
zv_data_valid
zv_ext_clk
zv_hsync
zv_pix_clk
zv_vsync
132
129
131
126
127
Zoom video port data valid signal
Zoom video port external clock input
Zoom video port horizontal sync signal
Zoom video port pixel clock for zoomed video data
Zoom video port vertical sync signal
O
I/O
O
miscellaneous
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
Autoboot. Selects autoboot mode. When this terminal is tied high, autoboot mode is
selected.
autoboot
159
I
gpio_data3 – gpio_data2
link_cyclein
122 – 125
137
I/O
I
Auxiliary port general-purpose programmable I/O signals
Optional 8kHz clock for use as the cycle clock
Cycle timer 8kHz clock output
link_cycleout
140
O
seeprom_clk
133
I/O
I/O
External serial EEPROM data clock
seeprom_data
134
External serial EEPROM read/write data line
Enables TEST_OUT for AND tree testing. This pin should be tied to GND if AND tree
testing is not used.
test_enable/GND
test_out
158
140
I
O
Output for AND tree testing
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
system block diagram
The following figure illustrates a typical system implementation of the PCILynx-2.
Personal Computer
Host
CPU
PCI
Host
Bridge
1394 Peripheral Devices
Local
Memory
1394
CD ROM
PCI Bus
1394
Laser
Printer
IDE
Controller
Video
Controller
1394
3 Port
Physical
Layer
1394
Desktop
Camera
PCILynx-2
TSB12LV21B
1394
Digital
VCR
Local Bus
DMA
User
Defined
Function
(AUX)
ZV
Port
(Video)
PCI
Expansion
ROM
1394
Video Cable
Set Top Box
Channel
Control
(SRAM)
Figure 2. System Block Diagram
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
functional block diagram
seeprom_data
aux_clk
aux_rst
aux_int
Serial EPROM
seeprom_clk
Interface
32
pci_ad31 – pci_ad0
/
4
4
gpio_data3 – gpio_data0
aux_adr15 – aux_adr0
/
pci_cbe3 – pci_cbe0
/
16
PCI Master
PCI Slave
pci_par
pci_frame
pci_irdy
pci_trdy
pci_devsel
pci_stop
pci_idsel
pci_perr
pci_serr
pci_req
/
Local Bus
Interface
Logic
16
aux_data15 – aux_data0
aux_oe
/
RAM
ROM
AUX
ZV
2
aux_we1 – aux_we0
aux_rdy
/
3
zv_hsync, zv_vsync, zv_pix_clk
zv_data_valid
/
3
PCI Configuration Control
and Status Registers
aux_cs, rom_cs, ram_cs
zv_ext_clk
/
pci_gnt
pci_clk
pci_reset
pci_inta
PCI Bus Logic
DMA Control
and
DMA Engine
Status Registers
DMA Logic
General
Receiver
FIFO
Asynchronous
Transmit
FIFO
Isosynchronous
Pointer
Address
Mapping Logic
FIFO Control
and Status
Registers
Transmit
FIFO
FIFO Logic
2
1394 Link Layer Control (LLC) Logic
phy_ctl0 – phy_ctl1
/
8
1394 Packet
Transmit
Timer
Cycle
phy_data0 – phy_data7
/
1394 LLC
Control and
Status Reg-
isters
Phy-Link
Interface
Logic
Control Logic
phy_clk50
phy_lreq
link_cyclein
link_cycleout
CRC Logic
Parallel-to-Serial
Serial-to-Parallel
1394 Packet
Cycle
Receive
Monitor
Control Logic
Figure 3. Functional Block Diagram
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
†
absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
V
V
CCP
CC5V
Input voltage range for Universal PCI, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Input voltage range for 5-V tolerant TTL/LVCMOS, V : . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output voltage range for Universal PCI, V
Output voltage range for 5-V tolerant TTL/LVCMOS, V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
CC5V
CCP
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
. . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC5V
O
Input clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
OK
O O CC
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant buffers, use V > V
. For Universal PCI, use V > V
I
CC5V
I
CCP.
For Universal PCI, use V > V
CCP.
2. Applies to external output and bidirectional buffers. For 5-V tolerant buffers, use V > V
O
CC5V.
O
recommended operating conditions (see Note 3)
OPERATION
MIN NOM
MAX
3.6
UNIT
Core voltage, V
Commercial
Commercial
Commercial
3.3
5
3
3
3
3.3
5
V
V
V
V
CC
I/O voltage, V
I/O voltage, V
5.5
CCP
5
5
5.5
CC5V
†
High-level Input voltage, V
2
IH
†
Low-level Input voltage, V
0.8
V
V
IL
Universal PCI
5-V tolerant
0
0
0
0
0
0
V
CCP
Input voltage, V
I
V
CC5V
‡
Output voltage, V
V
V
O
CC
6
Input transition times (t and t ), t
t
ns
°C
°C
r
f
Operating ambient temperature range, T
25
25
70
A
§
Virtual junction temperature, T
115
J
†
‡
§
Applies for external input and bidirectional buffers without hysteresis.
Applies for external output buffers.
These junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
electrical characteristics over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
OPERATION
MIN
MAX
UNIT
3.3 V
5 V
I
I
I
I
I
I
I
I
= –0.5 mA
= –2 mA
= –18 mA
= –14 mA
= 1.5 mA
= 6 mA
0.9 V
OH
OH
OH
OH
OL
OL
OL
OL
CC
2.4
PCI
High-level output voltage
(see Note 4)
V
V
OH
OL
†
‡
TTL/LVCMOS
2.4
2.4
TTL/LVCMOS
3.3 V
5 V
0.1 V
CC
0.5
PCI
V
Low-level output voltage
V
†
TTL/LVCMOS
= 18 mA
= 14 mA
0.5
0.5
20
‡
TTL/LVCMOS
Bushold
Others
V = 0.8 V
I
Input pins
I/O pins
V = GND
–1
I
I
I
Low-level input current
High-level input current
µA
µA
IL
Bushold
Others
V = 0.8 V
400
–20
–20
20
I
V = GND
I
Bushold
Others
V = 2 V
I
Input pins
I/O pins
V = 5.5 V
I
IH
Bushold
Others
V = 2 V
–20
20
I
V = 5.5 V
I
†
‡
All PHY-link pins, aux_clk(64), aux_we1(71), and aux_we0(73).
All other TTL/LVCMOS pins
NOTE 4:
V
is not tested on pci_serr(31) or pci_inta(166) due to open-drain output.
OH
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PCI interface switching characteristics, see Figure 4
TEST
CONDITION
PARAMETER
MEASURED
40% to 40%
40% to 40%
MIN
7
TYP
MAX
UNIT
ns
†
t
t
Setup time, pci_xx low or high to pci_clk high
su1
†
Hold time, pci_clk high to pci_xx low or high , pci_gnt low or
high
0
ns
h1
†
t
t
t
Delay time, pci_clk high to pci_xx low or high
40% to 40%
40% to 40%
40% to 40%
2
10
2
11
13
ns
ns
ns
d1
Setup time, pci_gnt low or high to pci_clk high
Delay time, pci_clk high to pci_inta low or high
su2
d2
†
Inthiscase, pci_xxreferstothefollowingsignals;pci_ad31–0, pci_cbe3–0, pci_par, pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_idsel,
pci_perr, pci_serr, pci_req.
phy-link interface switching characteristics, see Figure 5
TEST
CONDITION
PARAMETER
MEASURED
MIN
TYP
MAX
UNIT
†
t
t
t
t
t
Setup time, phy_xx low or high to phy_clk high
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
4
1
3
5
3
ns
ns
ns
ns
ns
su3
Hold time, phy_clk high to phy_xx, link_cyclein low or high
h2
†
Delay time, phy_clk high to phy_xx, phy_lreq low or high
Setup time, phy_clk high to link_cyclein low or high
Delay time, phy_clk high to link_cycleout low or high
11
13
d3
su4
d4
†
In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
local bus switching characteristics, see Figure 6
TEST
CONDITION
PARAMETER
MEASURED
MIN
TYP
MAX
UNIT
Delay time, aux_clk high to aux_adr, aux_data15–0 (write),
aux_oe valid
t
t
t
t
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
1.3 V to 1.3 V
0
0
15
20
ns
ns
ns
ns
ns
ns
d5
d6
d7
d8
d9
d10
†
Delay time, aux_clk high to rom_cs, ram_cs, aux_cs valid
Delay time, aux_we0, aux_we1 high (deasserted) to aux_adr,
aux_data15–0 (write), aux_oe, rom_cs, ram_cs, aux_cs valid
0.5
0
Delay time, aux_clk low to aux_we0, aux_we1 low (asserted)
10
10
15
Delay time, aux_clk high to aux_we0, aux_we1 high
(deasserted)
0
Delay time, aux_clk high to gpio_data3–0 valid
2
Setup time, aux_adr, adr_data15–0 (write), aux_oe, rom_cs,
ram_cs, aux_cs valid before aux_we0, aux_we1 low
(asserted)
t
1.3 V to 1.3 V
5
ns
su5
Setup time, aux_data15–0 (read), aux_rdy, gpio_data3–0 valid
before aux_clk high
t
t
1.3 V to 1.3 V
1.3 V to 1.3 V
10
0
ns
ns
su6
Hold time, aux_data15–0 (read), aux_rdy, gpio_data3–1
invalid after aux_clk high
h3
†
These signals are asserted asynchronously when a ZOOM port transfer imediately preceeds the local bus transfer. In all cases, the setup time
to aux_we1 and aux_we0 and the number of waitstates remain the same.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle
TEST
CONDITION
PARAMETER
MEASURED
MIN
12
TYP
MAX
UNIT
ns
Setup time, zv_hsync low, zv_vsync, zv_data_valid high before
zv_pix_clk high
t
t
1.3 V to 1.3 V See Figure 4
1.3 V to 1.3 V See Figure 4
su7
Hold time, zv_hsync high, zv_vsync, zv_data_valid low after
zv_pix_clk low
14
ns
h4
t
t
Setup time, aux_data7–0 valid before zv_pix_clk high or low
Hold time, aux_data7–0 valid after zv_pix_clk high or low
1.3 V to 1.3 V See Figure 4
1.3 V to 1.3 V See Figure 4
10
14
ns
ns
su8
h5
Delay time, zv_hsync low, zv_vsync, zv_data_valid high after
zv_pix_clk low
t
1.3 V to 1.3 V See Figure 5
–1
3
5
ns
d11
t
t
t
t
Delay time, aux_data7–0 invalid after zv_pix_clk low
Setup time, zv_hsync low before zv_pix_clk high
Hold time, zv_hsync high after zv_pix_clk high
Setup time, zv_vsync high before zv_pix_clk high
1.3 V to 1.3 V See Figure 5
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
–1
25
14
10
ns
ns
ns
ns
d12
su9
h6
su10
Setup time, aux_data7–0 valid, zv_data_valid high before
zv_pix_clk high
t
1.3 V to 1.3 V See Figure 6
1.3 V to 1.3 V See Figure 6
25
14
ns
ns
su11
h7
Hold time, aux_data7–0 valid, zv_data-valid low after
zv_pix_clk high
t
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PARAMETER MEASUREMENT INFORMATION
pci_clk
t
d1
t
t
su1
h1
pci_xx
(Bidirectional
see Note A)
t
d2
pci_inta
t
t
h1
su2
pci_gnt
NOTE A: In this case, pci_xx refers to the following bidirectional signals; pci_ad31–0, pci_cbe3–0, pci_par, pci_frame, pci_irdy,
pci_trdy, pci_devsel, pci_stop, pci_idsel, pci_perr, pci_serr, pci_req.
Figure 4. PCI Interface Timing Waveforms
phy_clk
t
d3
t
t
su3
h2
phy_xx
(Bidirectional
see Note A)
t
d3
phy_lreq
t
d4
link_cycleout
t
t
h2
su4
link_cyclein
NOTE A: In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
Figure 5. Phy-Link Interface Timing Waveforms
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PARAMETER MEASUREMENT INFORMATION
OUTPUTS
aux_clk
t
d5
aux_adr15–0
aux_data15–0 (write)
aux_oe
DATA VALID
DATA VALID
(see Note A)
t
t
d7
d6
rom_cs
ram_cs
aux_cs
t
su5
t
t
t
d9
d8
d9
aux_we0
aux_we1
t
d10
Wait States = 0
Wait States > 0
gpio_data7–0
DATA VALID
t
su6
INPUTS
t
h3
DATA
VALID
aux_data
aux_rdy
DATA
VALID
DATA
VALID
gpio_data7–0
NOTE A: These signals are asserted asynchronously when a ZOOM port transfer immediately preceeds the local bus transfer. In all cases,
the setup time to aux_we and the number of wait states remains valid.
Figure 6. Local Bus Timing Waveforms
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
internal
zv_pix_clk
zv_pix_clk
(gated, 8 bit)
t
t
h4
su7
zv_hsync
zv_vsync
zv_data_valid
t
t
t
t
h5
su8
h5
su8
aux_data15–0
(Write)
8-BIT DATA VALID
8-BIT DATA VALID
NOTES: A. The data is in 8-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 7. Zoom Video IF Timing Waveforms (8 Bit, Divide-By-2 Mode)
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PARAMETER MEASUREMENT INFORMATION
Internal
zv_pix_clk
zv_pix_clk
(gated, 16 bit)
t
t
d11
d11
zv_hsync
zv_vsync
zv_data_valid
t
t
d12
d12
aux_data15–0
(16 bit only)
16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-1 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
Figure 8. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-1 Mode)
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
Internal
zv_pix_clk
(see Note A)
zv_pix_clk
(gated, 16 bit)
t
t
h6
su9
zv_hsync
t
su10
zv_vsync
zv_data_valid
t
t
h7
su9
aux_data15–0
(Write)
16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk terminal. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 9. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-2 Mode)
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
APPLICATION INFORMATION
power supply sequencing
Turning power supplies on and off within a mixed 5-V/3.3-V system is an important consideration. A few basic
rules need to be observed to avoid damaging PCILynx-2 devices. Check with the manufacturers of all
components used in the 3.3-V to 5-V interface to ensure that no unique device characteristics exist that would
lead to more restrictive rules.
D
When the 3.3-V supply is turned on before turning on the 5-V supply, PCILynx-2 output buffers in a logic
1statecansupplylargeamountsofcurrentthroughtheirclampdiodestothe5-Vsupplyterminals(5VV ).
CC
This can lead to excessive power dissipation and violation of current density limits. However, if the 5-V
supply is turned on before the 3.3-V supply, the maximum drain-to-gate voltage of the n-channel transistors
in the 5-V tolerant buffers exceeds the recommended value and the effects of channel-hot carries can be
accelerated.
D
D
D
D
When turning on the power supply, all 3.3-V and 5-V supplies should start ramping up from 0 V and reach
95% of their end-point values within a 25-ms time window. All bus contention between the PCILynx-2 and
external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping
is to ramp the 3.3-V supply followed by the 5-V supply. This order is not mandatory, but it allows a larger
cumulative number of power supply events than the reverse order.
When turning off the power supply, all 3.3-V and 5-V supplies should start ramping down from steady state
values and reach 5% of these values within a 25-ms window. All bus contention between the PCILynx–2
and external devices is eliminated by the end of the 25-ms time window. The preferred order of supply
ramping is to ramp down the 5-V supply followed by the 3.3-V supply. This order is not mandatory, but it
allows a larger cumulative number of power-supply off events than the reverse order.
A cumulative total of 250 seconds of power supply turnon and turnoff events is allowed during the operating
lifetime of the PCILynx-2 under worst-case conditions. Worst-case conditions are where the 5-V supply is
ramped up before the 3.3-V supply and the 3.3-V supply is ramped down before the 5-V supply. If the
maximum time window of the 25 ms is used, a total of 10,000 power supply on or off events can occur as
long as the 25-ms time window is observed.
An additional precaution must be observed when the PCILynx–2 is connected to a 5-V IEEE 1394
physical-layer device that is powered from the 1394 cable. In this case, it is possible for the physical-layer
device to have power while the PCILynx–2 does not. It is essential that the physical-layer device must not
supply a high signal on any terminal that connects to the PCILynx–2 while the PCILynx-2 power is off. This
is normally achieved through the use of the link-power status terminal on the physical-layer device.
If any of these precautions and guidelines are not followed, the PCILynx-2 device can experience possible
failures related to overheating, accumulation of channel-hot carriers, and/or metal migration due to excessive
current density.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB12LV21B
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
SLLS306– JULY 1998
MECHANICAL INFORMATION
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
0,17
M
0,08
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°–ā7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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TSB12LV21AMPGF
PCILynx - PCI to 1394 3.3V Link Layer with 32-bit PCI I/F, 1K FIFOs 176-LQFP -55 to 125
TI
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