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TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

TUSB1002 USB3.1 10Gbps 双通道线性转接驱动器

1 特性

3 说明

1

•

支持 USB3.1 超高速 (5Gbps) 和超高速+ (10Gbps)

TUSB1002 是业内首款双通道 USB 3.1 超高速+

(SSP) 转接驱动器和信号调节器。该器件采用超低功耗

架构，由 3.3V 电源供电运行时的功耗非常低。它支持

USB3.1 低功耗模式，可进一步降低空闲状态下的功

耗。

•

支持 PCI Express Gen3、SATA Express 和 SATA

Gen3。

•

超低功耗架构

–

有源状态：< 340mW

U2/U3：< 8mW

TUSB1002 实现了一款线性均衡器，最高可容许码间

串扰 (ISI) 引入 16dB 的损耗。当 USB 信号在印刷电

路板 (PCB) 或电缆上传输时，其完整性会在通道损耗

和码间串扰的影响下有所降低。线性均衡器可对通道损

失进行补偿，进而延长通道传输距离，从而使系统符合

USB 规范。凭借双通道和小型封装，TUSB1002 可在

USB3.1 传输路径中灵活放置。

未连接状态：< 2mW

•

可调节电压输出摆幅线性范围高达 1200 mVpp

无主机/设备端要求

16 种线性均衡设置，在速率为 10Gbps 时最高为

16dB

•

可调节直流均衡增益

支持热插拔

TUSB1002 采用 24 引脚 4mm x 4mm VQFN 封装。

它还提供商业级 (TUSB1002) 版本。

与 LVPE502A 和 LVPE512 USB 3.0 转接驱动器引

脚兼容

•

温度范围：0°C 至 70°C

器件信息⁽¹⁾

±6kV 人体模型 (HBM) 静电放电 (ESD)

由 3.3V 单电源供电。

器件型号

TUSB1002

封装

VQFN (24)

封装尺寸（标称值）

4.00mm x 4.00mm

采用 4mm x 4mm VQFN 封装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

•

笔记本和台式机

电视

平板电脑

手机

有源电缆

扩展坞

空白

简化原理图

RXP1

+

RXN1

-

TXP1

TXN1

+

-

+

-

TUSB1002

+

USB 3.1

Host

TXP2

TXN2

RXP2

RXN2

+

-

+

-

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSEU4

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 17

7.5 U0 Mode.................................................................. 17

7.6 U1 Mode.................................................................. 18

7.7 U2/U3 Mode............................................................ 18

Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical USB3.1 Application .................................... 19

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics, Power Supply .................. 7

6.6 Electrical Characteristics........................................... 7

6.7 Power-Up Requirements........................................... 9

6.8 Timing Requirements................................................ 9

6.9 Switching Characteristics.......................................... 9

6.10 Typical Characteristics.......................................... 11

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

8

9

8.3 Typical SATA, PCIe and SATA Express

Application................................................................ 22

Power Supply Recommendations...................... 25

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 26

11 器件和文档支持 ..................................................... 27

11.1 社区资源................................................................ 27

11.2 商标....................................................................... 27

11.3 静电放电警告......................................................... 27

11.4 Glossary................................................................ 27

12 机械、封装和可订购信息....................................... 27

7

4 修订历史记录

Changes from Revision D (October 2017) to Revision E

Page

•

从特性、说明和器件信息中删除了 TUSB1002I 工业............................................................................................................ 1

Deleted TUSB1002I Operating free-air temperature from the Recommended Operating Conditions ................................... 6

Deleted TUSB1002I from the Thermal Information table ....................................................................................................... 6

Changes from Revision C (August 2017) to Revision D

Page

•

Changed pin 8 From: RXIN To: RX1N in the RGE pin image................................................................................................ 4

Changes from Revision B (August 2017) to Revision C

Page

•

在特性中将“14 种线性均衡设置，在速率为 10Gbps 时最高为 15dB”更改成了“16 种线性均衡设置，在速率为 10Gbps

时最高为 16 dB”...................................................................................................................................................................... 1

Deleted the RMQ package option from the Pin Configuration and Functions section .......................................................... 4

Deleted the RMQ package from the Pin Functions table ...................................................................................................... 4

Changed the description of pin 7 From: R = Test Mode To: R = PCIe / Test Mode. in the Pin Functions table .................. 5

Deleted the RMQ column from Thermal Information table .................................................................................................... 6

Added Differential crosstalk between TX and RX signal pairs. ............................................................................................. 7

From: E_{Q(GAIN-10Gbps)}15dB To: E_{Q(GAIN-10Gbps)}16dB.................................................................................................................. 7

EQ setting 15 changed from Reserved to 10.4 / 16.0 ......................................................................................................... 16

EQ setting 16 changed from Reserved to 10.6 / 16.3 ......................................................................................................... 16

Added the PCIe/SATA/SATA Express Redriver Operation section. ................................................................................... 17

Added the Typical SATA, PCIe, and SATA Expess Application section ............................................................................. 22

•

2

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

Changes from Revision A (May 2016) to Revision B

Page

•

向简化原理图的 RXP2 和 RXN2 引脚添加了一个电容器........................................................................................................ 1

Added a capacitor to the RXP2 and RXN2 pins of Figure 17 .............................................................................................. 19

Updated the A/C coupling Capacitor section of Table 4 ..................................................................................................... 19

Changed text in the Detailed Design Procedure From: No A/C coupling capacitors are placed on the RX2P/N. To:

330nF A/C coupling capacitors along with 220k resistors are placed on the RX2P and RX2N. Inclusion of these

330nF capacitors and 220k resistors is optional but highly recommended. If not implemented, then RX2P/N should

be DC-coupled to the USB receptacle. ................................................................................................................................ 20

•

Added 330nF AC capacitors (C12 and C13) on RX2P and RX2N in Figure 18 .................................................................. 20

Changes from Original (May 2016) to Revision A

Page

•

已将器件状态由“产品预览”改为“量产数据”.............................................................................................................................. 1

3

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

5 Pin Configuration and Functions

RGE Package

24-Pin VQFN

Top View

18

13

17 16 15 14

RX2P

RX2N

19

20

21

22

23

24

12

11

TX2P

TX2N

+

-

GND

10

9

GND

TX1P

RX1P

RX1N

+

-

TX1N

8

RSVD1

7

MODE

1

2

3

4

5

6

Pin Functions

INTERNAL PULLUP

PULLDOWN

TYPE

DESCRIPTION

NAME

RGE

Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive

signals for Channel 1

RX1P

9

90Ω Differential

Input

Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative

signals for Channel 1

RX1N

RX2P

RX2N

TX1P

TX1N

TX2P

TX2N

8

Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive

signals for Channel 2

19

20

22

23

12

11

90Ω Differential

Input

Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative

signals for Channel 2.

Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive

signals for Channel 1.

90Ω Differential

Output

Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative

signals for Channel 1.

Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive

signals for Channel 2.

90Ω Differential

Output

Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative

signals for Channel 2.

CH1_EQ1. Configuration pin used to control Rx EQ level for RX1P/N. The state

of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of

timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings.

CH1_EQ1

CH1_EQ2

CH2_EQ1

CH2_EQ2

2

3

I (4-level)

CH1_EQ2. Configuration pin used to control Rx EQ level for RX1P/N. The state

of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of

timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings.

PU (approx 45K)

PD (approx 95K)

CH2_EQ1. Configuration pin used to control Rx EQ level for RX2P/N. The state

of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of

timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings.

16

17

CH2_EQ2. Configuration pin used to control Rx EQ level for RX2P/N. The state

of this pin is sampled after the rising edge of EN. Refer to Figure 2 for details of

timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings.

4

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

Pin Functions (continued)

INTERNAL PULLUP

TYPE

DESCRIPTION

PULLDOWN

NAME

RGE

EN. Places TUSB1002 into shutdown mode when asserted low. Normal

operation when pin is asserted high. When in shutdown, TUSB1002’s receiver

terminations will be high impedance and tx/rx channels will be disabled.

EN

5

I (2-level)

PU (approx 400 K)

CFG1. This pin along with CFG2 will select VOD linearity range and DC gain

for both channels 1 and 2. The state of this pin is sampled after the rising edge

of EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity

range and DC gain options.

CFG1

4

I (4-level)

PU (approx 45K)

PD (approx 95K)

CFG2. This pin along with CFG1 will set VOD linearity range and DC gain for

both channels 1 and 2. The state of this pin is sampled after the rising edge of

EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity

range and DC gain options.

CFG2

15

MODE. This pin is for selecting different modes of operation. The state of this

pin is sampled after the rising edge of EN. Refer to Figure 2 for details of

timing.

PU (approx 45 K)

PD (approx 95K)

MODE

7

I (4-level)

0 = Test Mode. TI Internal Use Only.

R = PCIe / Test Mode. PCIe Mode and TI Internal use only

F = USB3.1 Dual Channel Operation enabled (TUSB1002 normal mode).

1 = USB3.1 Single-channel operation.

RSVD1. Under normal operation, this pin will be driven low by TUSB1002.

Recommend leaving this pin unconnected on PCB.

RSVD1

24

O

SLP_S0#. This pin when asserted low will disable Receiver Detect functionality.

While this pin low and TUSB1002 is in U2/U3, TUSB1002 disables LOS and

LFPS detection circuitry and Rx termination for both channels will remain

enabled. If this pin is low and TUSB1002 is in Disconnect state, the Rx detect

functionality is disabled and Rx termination for both channels will be disabled. If

the system SoC does not support a GPIO that indicates system sleep state,

then it is recommended to leave this pin unconnected.

SLP_S0#

14

I (2-level)

PU (approx 400 K)

0 – Rx Detect disabled

1 – Rx Detect enabled

NC

No Connect. Leave unconnected on PCB.

3.3 V (±10%) Supply.

VCC

1, 13

Power

GND

6, 10, 18,

21

GND

Ground

Thermal pad

Thermal pad. Recommend connecting to a solid ground plane.

5

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply Voltage Range⁽²⁾, V_CC

–0.3

4

V

Differential Voltage between RX1P/N and

RX2P/N.

±2.5

V

IO Voltage Range

Voltage at RX1P/N and RX2P/N.

Voltage on Control IO pins

–0.5

V_CC+ 0.5

105

V

Maximum junction temperature, T_J

Storage temperature, T_stg

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the GND terminal.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±6000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101

or ANSI/ESDA/JEDEC JS-002⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

3.6

50

UNIT

V

3.3 V Supply Voltage

3

3.3

V_CC

Supply Ramp requirement

Supply Noise on V_CCpins

Operating free-air temperature

ms

mV

°C

V_(PSN)

T_A

100

70

0

6.4 Thermal Information

TUSB1002

THERMAL METRIC⁽¹⁾

RGE (VQFN)

24 PINS

38.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

41.6

16.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.0

ψ_JB

16.4

R_θJC(bot)

6.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

6.5 Electrical Characteristics, Power Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TUSB1002 power under normal operation

in U0 operating a SuperSpeedPlus

datarate with linear range set to 1200mV.

At 10 Gbps; V_CCsupply stable; V_CC= 3.3

V; V_OD= 1200 mVpp; Pattern = CP9

P_{(U0_SSP_1200mV)}

P_{(U0_SSP_1000mV)}

P_{(U0_SSP_900mV)}

340

mW

TUSB1002 power under normal operation

in U0 operating a SuperSpeedPlus

datarate with linear range set to 1000mV.

At 10 Gbps; V_CCsupply stable; V_CC= 3.3

V; V_OD= 1000 mVpp; Pattern = CP9

325

298

mW

TUSB1002 power under normal operation

in U0 operating a SuperSpeedPlus

datarate with linear range set to 900mV.

At 10 Gbps; V_CCsupply stable; V_CC= 3.3

V; V_OD= 900 mVpp; Pattern = CP9

TUSB1002 power under normal operation

in U0 operating a SuperSpeed datarate.

At 5 Gbps; V_CCsupply stable; V_CC= 3.3 V;

V_OD= 1200 mVpp; Pattern = CP0.

P_{(U0_SS_1200mV)}

P_(U1)

340

8

mW

In U1; VCC supply stable; V_CC= 3.3 V;

V_OD= 1200 mVpp

TUSB1002 power when U1.

Both channels 1 and 2 in U2/U3; VCC

supply stable; V_CC= 3.3 V;

P_(U2U3)

TUSB1002 power when in U2/U3.

TUSB1002 power when in U2/U3 and

SLP_S0# is low.

Both channels 1 and 2 in U2/U3; VCC

supply stable; V_CC= 3.3 V;

P_{(U2U3_SLP)}

0.850

2

P_{(DISCONNECT_NON}TUSB1002 power when no USB device

RX1 and RX2 termination disabled; VCC

supply stable; V_CC= 3.3 V

detected on both TX1P/N or TX2P/N.

E)

TUSB1002 power when a USB device

P_{(DISCONNECT_ONE}

Either RX1 or RX2 termination enabled

both not both enabled; VCC supply stable;

V_CC= 3.3 V

detected on either TX1P/N or TX2P/N but

5

mW

)

not both.

TUSB1002 power when no USB device

P_{(DISCONNECT_SLP)}detected on either TX1P/N or TX2P/N and

SLP_S0# is low..

RX1 and RX2 termination disabled; VCC

supply stable; V_CC= 3.3 V

0.850

0.6

mW

TUSB1002 power when EN is asserted

P_(SHUTDOWN)

VCC supply stable; V_CC= 3.3 V, EN = 0

low.;

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-Level Inputs (MODE, CFG1, CFG2,CH1_EQ1, CH1_EQ2, CH2_EQ1, CH2_EQ2 )

I_IH

High level input current

Low level input current

Threshold 0 / R

V_CC= 3.6 V; V_IN= 3.6 V

V_CC= 3.6 V; V_IN= 0 V

20

80

μA

V

I_IL

–160

–40

V_TH

0.55

1.65

2.8

45

Threshold R/ Float

V_CC= 3.3 V

V

Threshold Float / 1

V

R_PU

Internal pull-up resistance

Internal pull-down resistance

kΩ

R_PD

95

EN, SLP_S0# Input

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_CC= 3. V

1.7

0

VCC

0.7

10

V

V_CC= 3.3 V

V

V_CC= 3.6 V, EN = 3.6 V

V_CC= 3.6 V, EN = 0 V

–10

–15

µA

kΩ

I_IL

15

Internal pull-up resistance for EN and

SLP_S0#.

400

R_(EN-PU)

USB3.1 RECEIVER INTERFACE (RX1P/N AND RX2P/N)

SDD11 10 MHz at 90 Ω

SDD11 2 GHz at 90 Ω

SDD11 5 – 10 GHz at 90 Ω

0.5 – 5 GHz at 90 Ω

–19

–14

–7

dB

R_L(RX-DIFF)

RX Differential return loss

R_L(RX-CM)

X-TALK

RX Common mode return loss

–10

Differential crosstalk between TX and

RX signal pairs.

-50

dB

E_{Q(GAIN-10Gbps)}

E_Q(DC0)

Equalization Gain

50 mVpp At 5 GHz

16

dB

500 mVpp V_IDat 100 MHz; 1200mV

Linear Range Setting; Refer to Table 3

-0.15

DC Equalization Gain at 0dB setting.

7

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

500 mVpp V_IDat 100 MHz; 1200mV

Linear Range Setting;

0.80

dB

E_Q(DC1)

E_Q(DC2)

E_Q(DC-1)

E_Q(DC-2)

DC Equalization Gain at +1dB setting.

500 mVpp V_IDat 100 MHz; 1000mV

Linear Range Setting;

1.5

–1.1

dB

DC Equalization Gain at +2dB setting.

DC Equalization Gain at -1dB setting.

DC Equalization Gain at -2dB setting.

500 mVpp V_IDat 100 MHz; 1200mV

Linear Range Setting;

500 mVpp V_IDat 100 MHz; 1200mV

Linear Range Setting;

–2.05

Input differential peak-peak voltage

swing range.

V_{(DIFF_IN)}

2000

1.85

mV

V

V_(RX-DC-CM)

RX DC common mode voltage

1.65

18

2.0

30

Measured at connector. Present when

R_(RX-CM-DC)

Receiver DC common mode impedance SuperSpeed USB device detected on

TXP/N

Ω

Measured at connector. Present when

SuperSpeed USB device detected on

TXP/N; SLP_S0# = 1;

R_(RX-DIFF-DC)

Receiver DC differential impedance

72

30

120

Measured at connector. Present when

no SuperSpeed USB device detected

on TXP/N or while V_CCis ramping

Z_{(RX-HIGH-IMP-DC-}

DC input CM input impedance when

termination is disabled.

KΩ

mV

POS)

V_(RX-

Input differential peak-to-peak Signal

Detect Assert level

at 10 Gbps. No loss input channel and

PRBS7 pattern

92

62

SIGNAL_DET_DIFF-

PP)

V_{(RX-IDLE_DET_DIFF-}Input differential peak-to-peak Signal

at 10 Gbps. No loss input channel and

PRBS7 pattern

mV

Detect De-assert Level

PP)

V_{(RX-LFPS-DET-DIFF-}LFPS Detect threshold. Below min is

Measured at connector. Below min is

squelched

100

300

noise.

P-P)

V_(RX-CM-AC-P)

Peak RX AC common mode voltage

Rx Input capacitance for return loss

Measured at package pin

At package pin

150

0.5

mV

pF

C_{(RX-PARASITIC)}

USB3.1 Transmitter Interface (TX1P/N and TX2P/N)

SDD22 10MHz – 2 GHz at 90 Ω

SDD22 5 GHz at 90 Ω

–15

–11

–7

dB

R_L(TX-DIFF)

TX Differential return loss

SDD22 5 - 10 GHz at 90 Ω

0.05 – 5 GHz at 90 Ω

R_L(TX-CM)

TX Common Mode return loss

–9

CFG1 pin = F or 1; Refer to Table 3

Measured at -1dB compression point =

20log (VOD/VOD_linear)

Differential peak-to-peak TX voltage

swing linear dynamic range

V_{(TX-DIFF-PP_1200)}

1200

1000

900

1450

mV

CFG1 pin = R; Refer to Table 3

Measured at -1dB compression point =

20log (VOD/VOD_linear)

Differential peak-to-peak TX voltage

swing linear dynamic range

V_{(TX-DIFF-PP_1000)}

CFG1 pin = 0; Refer to

Table 3Measured at -1dB compression

point = 20log (VOD/VOD_linear)

Differential peak-to-peak TX voltage

swing linear dynamic range

V_{(TX-DIFF-PP_900)}

mV

The amount of voltage change allowed

during Receiver Detection.

V_{(TX-RCV-DETECT)}

600

Transmitter idle common-mode voltage

V_{(TX-CM-IDLE-DELTA)}change while in U2/3 and not actively

transmitting LFPS.

–600

V_(TX-DC-CM)

TX DC common mode voltage

1200mVpp Linear Range setting.

At package pin.

0

1.85

2

V

V_{(TX-IDLE-DIFF-AC-}

AC Electrical Idle differential peak-to-

peak output voltage

10

mV

PP)

DC Electrical Idle differential output

voltage

At package pin. After low pass filter to

remove AC component.

V_{(TX-IDLE-DIFF_DC)}

0

14

80

mV

1200mVpp linear range; CHx_EQ

setting matches input channel insertion

loss;

Transmitter AC common mode peak-

peak voltage in U0

V_{(TX-CM-AC-PP)}

V_{(TX-CM-DC-ACTIVE-}Absolute DC common mode voltage

At package pin.

200

between U1 and U0.

IDLE-DELTA)

I_(TX-SHORT)

R_(TX-DC)

TX short-circuit current limit

106

30

mA

TX DC common mode impedance

At package pin

18

Ω

8

TUSB1002

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

120

0.7

UNIT

Ω

R_(TX-DIFF-DC)

TX DC differential impedance

TX input capacitance for return loss

72

90

C_{(TX-PARASTIC)}

At package pin

pF

External AC Coupling capacitor on

differential pairs.

C_{(AC-COUPLING)}

75

265

nF

6.7 Power-Up Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

Internal Power Good asserted high when V_CC

is at 2.5 V

µs

t_{d_pg}

See Figure 2

5

t_{cfg_su}

CFG⁽¹⁾pins setup before internal Reset⁽²⁾high See Figure 2

0

s

t_{cfg_hd}

CFG⁽¹⁾pins hold after internal Reset⁽²⁾high

See Figure 2

500

µs

ms

t_{VCC_RAMP}

V_CCsupply ramp requirement

50

(1) Following pins comprise CFG pins: MODE, CFG1, CFG2, CH1_EQ1, CH1_EQ2, CH2_EQ1, and CH2_EQ2.

(2) Internal reset is the AND of EN pin and internal Power Good.

6.8 Timing Requirements

MIN

NOM

MAX

UNIT

SuperSpeed (SS) and SuperSpeedPlus(SSP)

t_IDLEEntry

Delay from U0 to electrical idle.

See Figure 1

150

ps

U1 exit time: break in electrical idle to the

transmission of LFPS.

t_{IDLEExit_U1}

U2/U3 exit time: break in electrical idle to

transmission of LFPS

t_{IDLEExit_U2U3}

t_DIFF-DLY

See Figure 1

EN = H

2.3

3.75

150

7

µs

ps

Differential propagation delay

Time when V_CCreach 2.5 V to device

active and performing Rx.Detect.

t_PWRUPACTIVE

ms

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USB3.1 Transmitter Interface (TX1P/N, TX2P/N)

20% to 80% of differential output;

1200mVpp linear range setting

t_TX-RISE-FALL

t_RF-MISMATCH

t_TX-DJ

Transmitter rise/fall time

40

0.01

0.08

ps

UI

20% to 80% of differential output;

1200mVpp linear range setting;

1000mVpp VID;

Transmitter rise/fall mismatch

Residual deterministic jitter

@10Gbps; 1200mVpp Linear

Range Setting

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SSRXP

V

CM

RX-LFPS-DET-DiFF-PP

SSRXN

T

IDLEENTRY

IDLEEXIT

SSTXP

V

CM

SSTXN

Figure 1. Idle Entry and Exit Latency

VCC

T

d_pg

Internal Power

Good

T

cfg_su

Internal

Reset

EN pin

T

cfg_hd

CFG pins

Figure 2. Power-Up Diagram

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6.10 Typical Characteristics

V_CC= 3.3V , 25°C, 200 mVpp V_IDsine wave, Z_O= 100 Ω, RGE package

20

15

10

5

20

15

10

5

EQ1_DC0_1200mV

EQ3_DC0_1200mV

EQ5_DC0_1200mV

EQ7_DC0_1200mV

EQ9_DC0_1200mV

EQ11_DC0_1200mV

EQ13_DC0_1200mV

EQ2_DC0_1200mV

EQ4_DC0_1200mV

EQ6_DC0_1200mV

EQ8_DC0_1200mV

EQ10_DC0_1200mV

EQ12_DC0_1200mV

EQ14_DC0_1200mV

0

-5

0.01

0.1

1

10

0.01

0.1

1

10

Frequency (GHz)

D001

D002

Figure 3. 1200 mV DC0 Gain Odd EQ Settings Curves

Figure 4. 1200 mV DC0 Even EQ Settings Curves

20

15

10

5

10

EQ1_DC0_1000mV

EQ3_DC0_1000mV

EQ5_DC0_1000mV

EQ7_DC0_1000mV

EQ9_DC0_1000mV

EQ11_DC0_1000mV

EQ13_DC0_1000mV

EQ1_DC0_1200mV

EQ1_DC1_1200mV

EQ1_DC-1_1200mV

EQ1_DC-2_1200mV

5

0

-5

0.01

0.1

1

10

0.01

0.1

1

10

Frequency (GHz)

D003

D004

Figure 5. 1200 mV DC Gain Adjustments Curves

Figure 6. 1000 mV DC0 Gain Odd EQ Settings Curves

20

15

10

5

10

EQ2_DC0_1000mV

EQ4_DC0_1000mV

EQ6_DC0_1000mV

EQ10_DC0_1000mV

EQ12_DC0_1000mV

EQ1_DC0_1000mV

EQ1_DC2_1000mV

EQ1_DC-1_1000mV

5

0

-5

0.01

0.1

1

10

0.01

0.1

1

10

Frequency (GHz)

D005

D006

Figure 7. 1000 mV DC0 Gain Even EQ Settings Curves

Figure 8. 1000 mV DC Gain Adjustments Curves

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Typical Characteristics (continued)

V_CC= 3.3V , 25°C, 200 mVpp V_IDsine wave, Z_O= 100 Ω, RGE package

20

15

10

5

20

15

10

5

EQ1_DC0_900mV

EQ3_DC0_900mV

EQ5_DC0_900mV

EQ7_DC0_900mV

EQ9_DC0_900mV

EQ11_DC0_900mV

EQ13_DC0_900mV

EQ2_DC0_900mV

EQ4_DC0_900mV

EQ6_DC0_900mV

EQ8_DC0_900mV

EQ10_DC0_900mV

EQ12_DC0_900mV

EQ14_DC0_900mV

0

-5

0.01

0.1

1

10

0.01

0.1

1

10

Frequency (GHz)

D007

Figure 9. 900 mV DC0 Gain Odd EQ Settings Curves

Figure 10. 900 mV DC0 Gain Even EQ Settings Curves

0

10

5

EQ1_DC0_900mV

EQ1_DC1_900mV

-5

-10

-15

-20

-25

-30

-35

-40

0

-5

0.01

0.1

1

10

0.01

0.1

1

10

Frequency (GHz)

D009

D012

Figure 11. 900 mV DC Gain Adjustment Curves

Figure 12. SDD11 Return Loss

0

-5

1.6

1.4

1.2

1

-10

-15

-20

-25

-30

-35

-40

0.8

0.6

0.4

0.2

0

DC0_EQ1_900mV

DC0_EQ1_1000mV

DC0_EQ1_1200mV

0.01

0.1

1

10

0

0.5

1

1.5

Frequency (GHz)

VID (V)

D013

D010

Figure 13. SDD22 Return Loss

Figure 14. 5-GHz Sine Wave VID vs VOD Linearity Range

Setting

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Typical Characteristics (continued)

V_CC= 3.3V , 25°C, 200 mVpp V_IDsine wave, Z_O= 100 Ω, RGE package

1.4

1.2

1

0.8

0.6

0.4

0.2

0

DC0_EQ1_900mV

DC0_EQ1_1000mV

DC0_EQ1_1200mV

0

0.5

1

1.5

VID (V)

D011

Figure 15. 100-MHz Sine Wave VID vs VOD Linearity Range Setting

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7 Detailed Description

7.1 Overview

The TUSB1002 is the industry’s first, dual lane USB 3.1 SuperSpeedPlus redriver. As signals traverse through a

channel (like FR4 trace) the amplitude of the signal is attenuated. The attenuation varies depending on the

frequency content of the signal. Depending the length of the channel this attenuation could be large enough

resulting in signal integrity issues at a USB 3.1 receiver. By placing a TUSB1002 between USB3.1 host and

device the attenuation effect of the channel can eliminated or minimized. The result is a USB3.1 compatible eye

at the devices receiver. With up to 16 receiver equalization settings, the TUSB1002 can support many different

channel loss combinations. The TUSB1002 offers low power consumption on a single 3.3 V supply with its ultra

low power architecture. It supports the USB3.1 low power modes which further reduces idle power consumption.

The TUSB1002 settings are configured through pins. In addition to equalization adjustment, the TUSB1002

provides knobs for adjusting DC gain and voltage output linearity range.

7.2 Functional Block Diagram

3.3V (+/-10%)

2.5V

VCC

Power

Management

1.2V

PG

GND

VCC

400K

EN

V

term

50

V_Iterm

RXTERM_EN

TX1P

TX1N

RX1P

RX1N

TX

RX

TXEN1

IDLE1

RXDET1

LFPS

LOSZ1

LFPS1

Rx

Detect

LOS

LFPS1

LOSZ1

MODE

CFG1

CFG2

SLP_S0#

Digital FSM

CH1_EQ1

CH1_EQ2

RSVD1

LFPS2

LOSZ2

CH2_EQ1

CH2_EQ2

V

term

V

Iterm

50

RXTERM_EN

TX2P

TX2N

RX2P

RX2N

TX

RX

TXEN2

IDLE2

RXDET2

LFPS

LFPS2

Rx

Detect

LOSZ2

LOS

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7.3 Feature Description

7.3.1 4-Level Control Inputs

The TUSB1002 has (MODE, CFG1, CFG2, CH1_EQ1, CH1_EQ2, CH2_EQ1, and CH2_EQ2) 4-level inputs pins

that are used to control the equalization gain and the output voltage swing dynamic range. These 4-level inputs

use a resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an

internal 45 kΩ pull-up and a 95 kΩ pull-down. These resistors, together with the external resistor connection

combine to achieve the desired voltage level.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTINGS

Option 1: Tie 1 KΩ 5% to GND.

Option 2: Tie directly to GND.

0

R

F

Tie 20 KΩ 5% to GND.

Float (leave pin open)

Option 1: Tie 1 KΩ 5% to V_CC

.

1

Option 2: Tie directly to V_CC

.

NOTE

In order to conserve power, the TUSB1002 disables 4-level input’s internal pull-up/pull-

down resistors after the state of 4-level pins have been sampled on rising edge of EN. A

change of state for any four level input pin is not applied to TUSB1002 until after EN pin

transitions from low to high.

7.3.2 Linear Equalization

With a linear equalizer, the TUSB1002 can electrically shorten a particular channel allowing for longer run

lengths.

Figure 16. Linear Equalizer

With a TUSB1002, the 28 in trace can be made to have similar insertion loss as the 12 inch trace.

The receiver equalization level for each channel is determined by the state of the CHx_EQ1 and CHx_EQ2 pins,

where x = 1 or 2.

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Table 2. EQ Configuration Options for 1200mV Linearity 0 dB DC Gain Setting

EQ GAIN at 2.5GHz / 5

GHz (dB)

EQ SETTING #

CHx_EQ2 PIN LEVEL

CHx_EQ1 PIN LEVEL

1

2

0

R

F

1

1.9 / 5.5

2.8 / 7.1

3

0

3.5 / 8.2

4

0

4.4 / 9.3

5

R

F

1

0

5.0 / 10.2

5.8 / 11.1

6.4 / 11.8

7.1 / 12.6

7.6 / 13.1

8.2 / 13.8

8.7 / 14.3

9.2 / 14.8

9.6 / 15.2

10.1 / 15.6

10.4 / 16.0

10.6 / 16.3

6

R

F

1

7

8

9

0

10

11

12

13

14

15

16

R

F

1

0

1

R

F

1

7.3.3 Adjustable VOD Linear Range and DC Gain

The CFG1 and CFG2 pins can be used to adjust the TUSB1002 output voltage swing linear range and receiver

equalization DC gain. Table 3 details the available options.

For best performance, the TUSB1002 should be operated within its defined VOD linearity range. The gain of the

incoming VID should be kept to less than or equal to the TUSB1002 VOD linear range setting. The can be

determined by Equation 1:

VID at 5 GHz = VOD x (10 ^-(Gv/20)

)

where

•

Gv = TUSB1002 Gain and VOD = TUSB100 VOD linearity setting.

(1)

For example, for a VOD linearity range setting of 1200 mV, the maximum incoming VID signal at 5 GHz with a

CHx_EQ[1:0] setting of 1 (5.5 dB) is 1200 x (10 ^-(5.5/20)) = 637 mVpp. The TUSB1002 can be operated outside its

VOD linear range but jitter will be higher.

Table 3. VOD Linear Range and DC Gain

CH1 V_ODLINEAR

RANGE (mVpp)

CH2 V_ODLINEAR

RANGE (mVpp)

SETTING #

CFG1 PIN LEVEL

CFG2 PIN LEVEL

CH1 DC GAIN (dB) CH2 DC GAIN (dB)

1

2

0

R

F

1

+1

0

+1

0

900

3

0

900

4

0

+1

0

+1

0

900

5

R

F

1

0

1000

1200

1000

1200

6

R

F

1

+1

0

7

-1

+2

-1

-2

0

8

+2

-1

-2

0

9

0

10

11

12

13

14

15

16

R

F

1

+1

-1

0

+1

0

1

R

F

1

-1

+1

0

1

0

1

+1

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7.3.4 Receiver Detect Control

The SLP_S0# pin offers system designers the ability to control the TUSB1002 Rx.Detect functionality during

Disconnect and U2/U3 states and therefore achieving lower consumption in these states. When the system is in

a low power state (Sx where x = 1, 2, 3, 4, or 5), system can assert SLP_S0# low to disable TUSB1002 receiver

detect functionality. While SLP_S0# is asserted low and USB 3.1 interface is in U3, the TUSB1002 keeps

receiver termination active. The TUSB1002 will not respond to any LFPS signaling while in this state. This means

that system wake from U3 is not supported while SLP_S0# is asserted low. If the TUSB1002 is in Disconnect

state when SLP_S0# is asserted low, then TUSB1002 disables both channels receiver termination. When

SLP_S0# is asserted high, the TUSB1002 resumes normal operation of performing far-end receiver termination

detection.

7.3.5 USB3.1 Dual Channel Operation (MODE = “F”)

The TUSB1002 in dual-channel operation waits for far-end terminations on both channels 1 and 2 before

transitioning to fully active state (U0 mode). This mode of operation, defined as MODE pin = ‘F’, is the most

common configuration for USB3.1 Source (DFP) and Sink (UFP) applications.

7.3.6 USB3.1 Single Channel Operation (MODE = “1”)

In some applications, like Type-C USB3.1 active cables, only one of the two channels may be active. For this

application, setting MODE pin = ‘1’, enables single-channel operation. In this mode of operation, the TUSB1002

attempts far-end termination on both channels 1 and 2. The channel which has a far-end termination detected

will be enabled while the remaining channel will be disabled. If far-end termination is detected on both channels,

then TUSB1002 behaves in dual channel operation (both channels enabled).

7.3.7 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )

The TUSB1002 can be used as a PCI Express (PCIe) Gen3, SATA Gen3, or SATA Express redriver. When

TUSB1002's MODE pin = “R”, CFG1 pin = "0", and CFG2 pin = "0", the TUSB1002 will enable both channels

(upstream and downstream) receiver and transmitter paths upon detecting far-end termination on both TX1 and

TX2. Both upstream and downstream paths will remain enabled until EN pin is de-asserted low. All USB3.1

power management functionality is disabled in this mode. In this mode the TUSB1002 is transparent to PCIe link

power management (L0s, L1) and SATA interface power states. Once far-end termination is detected on both

TX1 and TX2, the TUSB1002 power will be at P_{(U0_SSP_1200mV)}regardless of the PCIe or SATA power state. To

save power during system S3/S4/S5 states it is suggested to de-assert the EN pin to conserve power.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The Shutdown mode is entered when EN pin is low and VCC is active and stable. This mode is the lowest power

state of the TUSB1002. While in this mode, the TUSB1002 receiver terminations is disabled.

7.4.2 Disconnect Mode

Next to Shutdown Mode, the Disconnect mode is the lowest power state of the TUSB1002. The TUSB1002

enters this mode when exiting Shutdown mode. In this state, the TUSB1002 periodically checks for far-end

receiver termination on both SSTX1 and SSTX2. Upon detection of the far-end receiver’s termination on both

ports, the TUSB1002 transitions to a fully active mode called U0 mode.

When SLP_S0# is asserted low and the TUSB1002 is in Disconnect mode, the TUSB1002 remains in

Disconnect mode and never perform far-end receiver detection. This allows even lower TUSB1002 power

consumption while in the Disconnect mode. Once SLP_S0# is asserted high, the TUSB1002 again starts

performing far-end receiver detection so it can know when to exit the Disconnect mode.

7.5 U0 Mode

The U0 mode is the highest power state of the TUSB1002. Anytime high-speed traffic (SuperSpeed or

SuperSpeedPlus) is being received, the TUSB1002 remains in this mode. The TUSB1002 only exits this mode if

electrical idle is detected on both SSRX1 and SSRX2. While in this mode, the TUSB1002 hs speed receivers

and transmitters are powered and active.

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7.6 U1 Mode

The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1002’s

receiver termination remains enabled and the TXP/N DC common mode is maintained.

7.7 U2/U3 Mode

Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB1002

periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on

either CH1 or CH2, the TUSB1002 leaves the U2/U3 mode and transition to the Disconnect mode. It also

monitors the SSRX1 and SSRX2 for a valid LFPS. Upon detection of a valid LFPS, the TUSB1002 immediately

transitions to the U0 mode.

When SLP_S0# is asserted low and the TUSB1002 is in U2/U3 mode, the TUSB1002 remains in U2/U3 state

and never perform far-end receiver detection. While in this state, the TUSB1002 ignores LFPS signaling. This

allows even lower TUSB1002 power consumption while in the U2/U3 mode. Once SLP_S0# is asserted high, the

TUSB1002 again starts performing far-end receive as well as monitor LFPS so it can know when to exit the

U2/U3 mode.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TUSB1002 is a linear redriver designed specifically to compensation for ISI jitter caused by attenuation

through a passive medium like traces and cables. Because the TUSB1002 has two independent channels, it can

be optimized to correct ISI in both the upstream and downstream direction through 16 different equalization

choices. Placing the TUSB1002 between a USB3.1 Host/device controller and a USB3.1 receptacle can correct

signal integrity issues resulting in a more robust system.

8.2 Typical USB3.1 Application

Downstream

B

A

C

D

FR4 Trace

of Length Y

FR4 Trace

of Length X

C

RXP1

TXP1

TXN1

+

-

+

-

+

RXN1

-

TUSB1002

USB 3.1

Host

C

TXP2

TXN2

RXP2

RXN2

+

-

+

-

+

-

Upstream

Figure 17. TUSB1002 in USB3.1 Host Application

8.2.1 Design Requirements

For this design example, use the parameters shown in Table 4.

Table 4. Design Parameters

PARAMETER

VALUE

VCC supply (3 V to 3.6 V)

3.3 V

MODE = F (Floating) for USB3.1 Dual Channel

100 nF

Mode of Operation (Dual or Half Channel)

TX1, TX2, RX1 A/C coupling Capacitor (75 nF to 265 nF)

RX2 A/C coupling Capacitor (297 nF to 363 nF)

Suggest 330 nF ±10%

RX2 pull-down resistors on USB receptacle side of AC capacitor

(200K to 242K ohms)

220k

A to B FR4 Length (inches)

A to B FR4 Trace Width (mils)

8

4

C to D FR4 length (inches)

2

C to D FR4 Trace Width (mils)

USB3.1 Host Sleep GPIO Support

DC Gain (-2, -1, 0, +1, +2)

4

No (SLP_S0# pin floating)

0 dB (CFG[2:1] pins floating)

1200 mV (CFG[2:1] pins floating)

Linear Range (900 mV, 1000 mV, or 1200 mV)

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8.2.2 Detailed Design Procedure

The TUSB1002 differential receivers and transmitters have internal BIAS and termination. For this reason, the

TUSB1002 must be connected to the USB3.1 host and receptacle through external A/C coupling capacitors. In

this example as depicted in Table 4, 100 nF capacitors are placed on TX2P and TX2N, RX1P and RX1N, and

TX1P and TX1N. 330 nF A/C coupling capacitors along with 220k resistors are placed on the RX2P and RX2N.

Inclusion of these 330nF capacitors and 220k resistors is optional but highly recommended. If not implemented,

then RX2P/N should be DC-coupled to the USB receptacle.

CH2_EQ2

CH2_EQ1

USB_VBUS

CFG2

J1

VCC_3P3V

1

VBUS

2

DM

HOST_DM

HOST_DP

3

4

U1

DP

GND

C12

C13

TX2P

RX2P

C1

C2

19

20

21

12

11

SSRXN

HOST_RXP

HOST_RXN

330nF

100nF

CONNECT TO

USB3.1 HOST

RX2N

GND

6

7

8

9

TX2N

GND

SSRXP

GND

10

9

C3

C5

C4

C6

TUSB1002

24-PIN RGE

HOST_TXP

HOST_TXN

SSTXN

22

23

TX1P

TX1N

RX1P

RX1N

100nF

5

SSTXP

8

10

11

SHIELD0

SHIELD1

24

25

MODE

7

RSVD1

GND

R16

220k

R15

220k

VCC_3P3V

1

2

3

4

5

6

USB3_TYPEA_CONNECTER

R2

DNI

C7

100nF

VCC_3P3V

C8

0.001uF

C11

100nF

R1

1M

C10

C9

10uF

100nF

CFG1

CH1_EQ2

CH1_EQ1

Figure 18. Host Implementation Schematic

The USB3.1 Dual channel operation is used in this example. Mode pin should be left floating (unconnected)

when using this mode.

In this example, the USB3.1 Host does not support a GPIO for indicating system Sx state or low power states

and therefore the SLP_S0# pin can be left floating.

The TUSB1002 compensates for channel loss in both the upstream (D to C) and downstream direction (A to B).

This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as

close possible to the channel insertion loss. In this particular example, CH1_EQ[2:1] is for path A to B which is

the channel between USB3.1 host and the TUSB1002, and CH2_EQ[2:1] is for path C to D which is the channel

between TUSB1002 and the USB3.1 receptacle.

The TUSB1002 supports 5 levels of DC gain that are selected by the CFG[2:1] pins. Typically, the DC gain

should be set to 0 dB but may need to be adjusted to correct any one of the following conditions:

1. Input V_IDtoo high resulting in V_ODbeing greater than USB 3.1 defined swing. For this case, a negative DC

gain should be used.

2. Input V_IDtoo low resulting in V_ODbeing less than USB 3.1 defined swing. For this case, a positive DC gain

should be used.

3. Low frequency discontinuities in the channel resulting in DC component of the signal clipping the vertical eye

mask. For this case, a positive DC gain should be used.

It is assumed in this example the incoming V_IDis at the nominal defined USB3.1 range and the channel is linear

across frequency. The CFG1 and CFG2 pins can both be left floating if these assumptions are true.

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In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular

channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for

the entire 8 inches of trace. An additional 1.5 dB of loss is added due to package of the USB3.1 Host,

TUSB1002, and the A/C coupling capacitor. This brings the entire channel loss at 5 GHz to 6.7 dB + 1.5 dB = 8.2

dB. A typical USB 3.1 host/device will have around 3 dB of transmitter de-emphasis. Transmitter de-emphasis

pre-compensates for the loss of the output channel. With 3 dB of de-emphasis, the total equalization required by

the TUSB1002 is in the 5.2 dB (8.2 dB - 3 dB) range. The channel A-B for this example is connected to

TUSB1002's RX1P/N input and therefore CH1_EQ[2:1] pins are used for adjusting TUSB1002 RX1P/N

equalization settings. The CH1_EQ[2:1] pins should be set such that TUSB1002 equalization is between 5dB

and 8dB.

The channel C-D has a trace length of 4 inches with a 4mil trace width. Assuming 0.83 dB per inch of insertion

loss, the 4 inch trace will equate to about 3.32 dB of loss at 5 GHz. An additional 2dB of loss needs to be added

due to package, A/C coupling capacitor, and the USB 3.1 receptacle. The total loss is around 5.32 dB. Because

channel C-D includes a USB 3.1 receptacle, the actual total loss could be much greater than 5.32dB due to the

fact that devices plugged into the receptacle will also have loss. The device plugged into receptacle will have

either a short or long channel. USB3.1 standard defines total loss limit of 23dB that is distributed as 8.5 dB for

Host, 8.5dB for device, and 6.0dB for cable. With variable channel of devices plugged into the USB3.1

receptacle, configuring TUSB1002's RX2P/N equalization settings is not as straight forward as Channel A-B.

Engineer can not set TUSB1002 CH2_EQ[2:1] pins to the largest equalization setting to accommodate the

largest allowed USB3.1 device/cable loss of 14.5 dB. Doing so will result in TUSB1002 operating outside its

linear range when a device with short channel is plugged into the receptacle. For this reason, it is recommended

to configure TUSB1002 CH2_EQ[2:1] pins to equalize a shorter device channel. This will result in requiring

USB3.1 host to compensate for remaining channel loss for the worse case USB3.1 channel of 14.5 dB. The

definition of a short device channel is not specified in USB 3.1 specification. Therefore, an engineer must make

their own loss estimate of what constitutes a short device channel. For particular example, we will assume the

short channel is around 3 to 5 dB. The device's channel loss will need to be added to estimated Channel C-D

loss minus the typical 3db of de-emphasis. This means CH2_EQ[2:1] pins should be configured to handle a loss

of 5 to 7 db.

8.2.3 Application Curves

0

-5

-10

-15

-20

-25

-30

0

2

4

6

8

10

12

14

16

18 20

Frequency (GHz)

D100

Freq = 5 GHz

dB(SDD21) = –6.666

Figure 19. Insertion Loss for 8inch 4 mil FR4 Trace

21

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

8.3 Typical SATA, PCIe and SATA Express Application

Downstream

A

B

C

D

FR4 trace

of length X

of length Y

RXP2

TXP2

+

-

+

-

+

-

+

-

TXN2

RXN2

SATA/PCIe/

SATA Express

Host

SATA/PCIe/

SATA Express

Device

TUSB1002

RXP1

RXN1

TXP1

TXN1

+

-

+

-

+

-

+

-

Upstream

Figure 20. SATA/PCIe/SATA Express Typical Application

8.3.1 Design Requirements

Table 5. Design Parameters

PARAMETER

VALUE

3.3 V

Yes

VCC supply (3 V to 3.6 V)

PCIe Support Required (Yes/No)

SATA Express Support Required (Yes/No)

Yes

Yes, then ferrite beads (FB1 and FB2) and 49.9-ohm required.

No, then ferrite bead (FB1 and FB2) and 49.9-ohm not required.

SATA Support Required (Yes/No)

TX1, TX2, RX2 A/C coupling Capacitor (176 nF to 265 nF)

RX1 A/C coupling Capacitor (297 nF to 363 nF)

A to B FR4 Length (inches)

220 nF ±10%

Optional. But if implemented suggest 330 nF ±10%

8

4

2

4

A to B FR4 Trace Width (mils)

C to D FR4 length (inches)

C to D FR4 Trace Width (mils)

This feature not supported when MODE = "R", CFG1 = "0", and

CFG2 = "0".

USB3.1 Host Sleep GPIO Support

DC Gain (-2, -1, 0, +1, +2)

Not configurable when MODE = "R", CFG1 = "0", and CFG2 = "0".

Will always default to 0 dB

Not configurable when MODE = "R", CFG1 = "0", and CFG2 = "0".

Will always default to 1200mV

Linear Range (900 mV, 1000 mV, or 1200 mV)

8.3.2 Detailed Design Procedure

The MODE pin = "R", CFG1 = "0", and CFG2 = "0" will place the TUSB1002 into PCIe mode. In this mode, the

TUSB1002 will have its DC gain fixed at 0dB and its linearity range fixed at 1200mV. The TUSB1002 will perform

far-end receiver termination detection and enable both upstream and downstream paths when far-end

termination is detected on both TX1 and TX2.

The AC coupling capacitor range defined for a SATA device is a lot smaller than the AC-coupling capacitor range

defined for SATA Express and PCI Express (PCIe) as indicated by Figure 21. The AC-coupling capacitor range

defined for SATA Express and PCI Express is within the same range as the AC-coupling capacitor range defined

by USB 3.1. The TUSB1002 will be able to detect PCIe and SATA Express device's receiver termination. But the

SATA's 12nF (max) AC-coupling capacitor will prevent TUSB1002 from detecting the SATA device's receiver

termination. To correct this problem, a ferrite bead along with 49.9 ohm resistor must be placed between C_TX2

and miniCard/mSATA socket. These components can be isolated from the high-speed channel when PCIe or

22

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

SATA Express is active by using an NFET as shown in Figure 22. The NFET should be enabled whenever a

SATA device is present. The ferrite bead chosen must present at least 600 ohms impedance at 100MHz so as to

not impact high-speed signalling. It is recommended to use Murata BLM03AG601SN1 or BLM03HD601SN1D or

a ferrite bead with similar characteristics from a different vendor. For applications which only require support for

PCIe and SATA Express and do not need to support SATA, the ferrite beads and 49.9 ohm resistors are not

needed.

12nF (max)

176nF t 265nF

+

-

+

-

+

-

SATA

Express

Device

SATA

Device

PCIe

Device

+

-

+

-

+

-

75nF t 265nF

Figure 21. AC-Coupling capacitor Implementation for SATA, SATA Express, and PCIe Devices

The TUSB1002's power will be at P_{(U0_SSP_1200mV)}when both its upstream and downstream paths are enabled. In

order to save system power in system S3/S4/S5 states, it is suggested to control TUSB1002's EN pin. Anytime

the system enters a low power state (S3, S4, or S5), it is suggested to de-assert the EN pin. While EN pin is de-

asserted, the TUSB1002 will consume P_(SHUTDOWN). Assertion of this pin is necessary anytime the system exits a

lower power state.

The TUSB1002 compensates for channel loss in both the upstream (C to D) and downstream direction (A to B).

This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as

close possible to the channel insertion loss. In this particular example, CH2_EQ[2:1] is for path A to B which is

the channel between PCIe/SATA/SATA Express host and the TUSB1002, and CH1_EQ[2:1] is for path C to D

which is the channel between TUSB1002 and the miniCard/mSATA socket.

In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular

channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for

the entire 8 inches of trace as depicted in Figure 19. An additional 1.5 dB of loss is added due to package of the

PCIe/SATA/SATA Express Host, TUSB1002, and the A/C coupling capacitor. This brings the entire channel loss

at 5 GHz to 6.7 dB + 1.5 dB = 8.2 dB. The channel A-B for this example is connected to TUSB1002 RX2P/N

input and therefore CH2_EQ[2:1] pins are used for adjusting TUSB1002 RX2P/N equalization settings. The

CH2_EQ[2:1] pins should be set such that TUSB1002 equalization is between 5dB and 8dB. A value closer to 5

dB maybe best if Host has transmitter de-emphasis.

A similar method should be used for the upstream path (C to D). In this particular example, C to D has a trace

length of 2 inches with a 4-mil trace width. This equates to approximately 1.5 dB at 5 GHz. The SATA/SATA

Express/PCIe device will have its own channel loss. This loss can be added to the C to D channel loss. For this

example, we will assume a value of 5dB is acceptable to compensate for C to D channel loss as well as loss

associated with the SATA/SATA Express/PCIe device. The CH1_EQ[2:1] pins should be set such that

TUSB1002 equalization is 5dB.

23

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

VCC (3.3V)

R_EQ2A

R_EQ2B

100nF

10 µF

100nF

VCC (3.3V)

R_EQ2C

R_EQ2D

SATA_EN

10YQ

49.9Q

FB2

FB1

C_RX2

C_TX2

TX2P

TX2N

GND

RX1P

RX1N

MODE

RX2P

RX2N

GND

TX1P

TX1N

RSVD1

+

-

SATA/PCIe/

SATA Express

Host

TUSB1002

+

-

C_RX1

C_TX1

20YQ

VCC (3.3V)

0-Q

GPIO (S3/S3/S5 indicator)

R_EQ1A

R_EQ1B

VCC (3.3V)

R_EQ1C

R_EQ1D

Figure 22. Example SATA/PCIe/SATA Express Schematic

24

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

8.3.3 Application Curves

Figure 23. PCIe Gen1 TX Eye Diagram

Figure 24. PCIe Gen 3 TX Eye Diagram

9 Power Supply Recommendations

The TUSB1002 has two V_CCsupply pins. It is recommended to place a 100 nF de-coupling capacitor near each

of the V_CCpins. It is also recommended to have at least one bulk capacitor of at least 10 µF on the V_CCplane

near the TUSB1002.

10 Layout

10.1 Layout Guidelines

•

RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).

Keep away from other high speed signals.

Intra-pair routing should be kept to within 2 mils.

Length matching should be near the location of mismatch

Each pair should be separated at least by 3 times the signal trace width.

The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left

and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This

minimizes any length mismatch causes by the bends; ad therefore, minimize the impact bends have on EMI.

•

Route all differential pairs on the same of layer.

The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.

Keep traces on layers adjacent to ground plane.

Do NOT route differential pairs over any plane split.

Adding Test points causes impedance discontinuity; and therefore, negatively impact signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a manner

that causes a stub on the differential pair.

25

TUSB1002

ZHCSF18E –MAY 2016–REVISED MAY 2019

www.ti.com.cn

10.2 Layout Example

Example 4 layer PCB Stackup

Top Layer 1 (Signal)

Inner Layer 2 (GND)

Inner Layer 3 (VCC)

Bottom Layer 4 (Signal)

Place near TUSB1002.

Via to layer 2 (GND)

Via to layer 3 (VCC)

Place near TUSB1002

or USB 3.1 receptacle

18

13

19

12

24

7

Place near TUSB1002

or USB 3.1 receptacle

1

6

Place near TUSB1002.

Figure 25. Example Layout

26

TUSB1002

www.ti.com.cn

ZHCSF18E –MAY 2016–REVISED MAY 2019

11 器件和文档支持

11.1 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.2 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

27

PACKAGE MATERIALS INFORMATION

www.ti.com

16-May-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB1002RGER

TUSB1002RGET

VQFN

RGE

24

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-May-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB1002RGER

TUSB1002RGET

VQFN

RGE

24

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

A

4.1

3.9

B

4.1

3.9

PIN 1 INDEX AREA

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ

(0.2) TYP

2X 2.5

12

7

20X 0.5

6

13

25

2X

SYMM

2.5

1

18

0.30

PIN 1 ID

(OPTIONAL)

24X

0.18

24

19

0.1

0.05

C A B

C

SYMM

0.48

0.28

24X

4219016 / A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

2.7)

(

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

25

SYMM

(3.825)

2X

(1.1)

ꢆꢄꢂꢁꢇꢀ9,$

TYP

6

13

(R0.05)

7

12

2X(1.1)

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

SYMM

(3.825)

(0.694)

TYP

6

13

25

(R0.05) TYP

METAL

TYP

7

12

(0.694)

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

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型号：	TUSB1002RGET
厂家：	TEXAS INSTRUMENTS
描述：	USB3.1 10Gbps 双通道线性转接驱动器 \| RGE \| 24 \| 0 to 70 驱动接口集成电路驱动器
文件：	总36页 (文件大小：2886K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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