TUSB1004IRNQT [TI]
10 Gbps USB 3.2 4 通道自适应线性转接驱动器 | RNQ | 40 | -40 to 85;
| 型号： | TUSB1004IRNQT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10 Gbps USB 3.2 4 通道自适应线性转接驱动器 | RNQ | 40 | -40 to 85 驱动 驱动器 |
| 文件： | 总53页 (文件大小：2172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSB1004
ZHCSMM7 –APRIL 2022
TUSB1004 USB 3.2 10 Gbps 四通道自适应线性转接驱动器
1 特性
说明
TUSB1004 是一款 10 Gbps USB 3.2 四通道线性转接
驱动器，适用于 USB Type-A 应用。TUSB1004 用于
驻留在主机和 USB 插座之间或 USB 器件和 USB 插座
之间。TUSB1004 支持第 2 代 USB 3.2 (10 Gbps) 和
第 1 代 USB 3.2 (5 Gbps) 以及 USB 3.2 低功耗状态
（断开、U1、U2 和U3）。
• USB 3.2 5 Gbps 和10 Gbps 支持
– 两个独立的USB 3.2 端口
• 高级USB 电源管理
– 有源：550 mW（典型值）
– 断开：1.7 mW
– 已禁用(EN = L)：0.130 mW
• 16 种EQ 设置在5 GHz 下高达12 dB
• 为面向USB 连接器的端口选择自适应或固定接收器
均衡
TUSB1004 具有创新的自适应接收器均衡 (AEQ) 功
能。AEQ 功能将自动确定其认为的 TUSB1004 和插入
USB 连接器的 USB 器件之间的最优 ISI 补偿设置，从
而提高互操作性。
• 为面向系统的端口选择线性或限幅转接驱动器
（SSRX 1/2 变送器）
TUSB1004 由 3.3V 单电源供电运行，并采用 40 引脚
WQFN 封装。
• 低于1V VTX-CM 和VRX-CM
• 通过I2C 或引脚搭接进行配置
• 在1.8V 或3.3V I2C 电平之间进行选择
• 由3.3V 单电源供电运行
器件信息(1)
器件型号
TUSB1004
封装
WQFN (40)
封装尺寸（标称值）
4.00mm × 6.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 笔记本电脑和台式机
• 扩展坞
• 数据存储
空白
• 联网外设和打印机
USB 3.2 Host
TUSB1004
TXp
TXn
SSTX2P
SSTX2n
CTX2p
CTX2n
SSTX2p
SSTX2n
RXp
RXn
SSRX2p
SSRX2n
CRX2p
CRX2n
SSRX2p
SSRX2n
CTX1p
CTX1n
TXp
TXn
SSTX1p
SSTX1n
SSTX1p
SSTX1n
CRX1p
CRX1n
RXp
RXn
SSRX1p
SSRX1n
SSRX1p
SSRX1n
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFL3
TUSB1004
ZHCSMM7 –APRIL 2022
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Table of Contents
7.6 Register Map.............................................................31
8 Application and Implementation..................................41
8.1 Application Information............................................. 41
9 Typical Application........................................................41
10 Design Requirements..................................................42
11 Detailed Design Procedure.........................................42
11.1 USB SSTX1/2 Receiver Configuration....................44
11.2 USB CRX1/2 Receiver Configuration......................44
12 Application Curves......................................................45
13 Power Supply Recommendations..............................45
14 Layout...........................................................................45
14.1 Layout Guidelines................................................... 45
14.2 Layout Example...................................................... 46
15 Device and Documentation Support..........................47
15.1 接收文档更新通知................................................... 47
15.2 支持资源..................................................................47
15.3 Trademarks.............................................................47
15.4 Electrostatic Discharge Caution..............................47
15.5 术语表..................................................................... 47
16 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 6
5.1 Absolute Maximum Ratings........................................ 6
5.2 ESD Ratings............................................................... 6
5.3 Recommended Operating Conditions.........................6
5.4 Thermal Information....................................................6
5.5 Power Supply Characteristics.....................................7
5.6 Control I/O DC Electrical Characteristics....................7
5.7 USB Electrical Characteristics.................................... 9
5.8 Timing Requirements................................................ 11
5.9 Switching Characteristics..........................................12
5.10 Typical Characteristics............................................13
6 Parameter Measurement Information..........................15
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................24
7.5 Programming............................................................ 26
Information.................................................................... 47
3 Revision History
DATE
REVISION
NOTES
April 2022
*
Initial Release
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4 Pin Configuration and Functions
CTX2p
CTX2n
9
40
39
38
37
36
35
34
33
32
31
30
29
SSTX2p
SSTX2n
NC
10
11
12
13
14
15
16
17
18
19
20
CEQ0
CRX2p
CRX2n
SSRX2p
SSRX2n
VIO_SEL
SSTX1p
SSTX1n
MODE
SSEQ0/A0
CTX1p
CTX1n
NC
Thermal
pad
SSRX1p
SSRX1n
VCC
CRX1p
CRX1n
CEQ1
Not to scale
图4-1. TUSB1004 RNQ Package, 40-Pin WQFN (Top View)
表4-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
VCC
1
P
3.3 V supply
In I2C mode, this pin along with A0 pin selects the 7-bit I2C target address (refer to 表7-7).
In pin-strap mode, this pin along with SSEQ0 selects the receiver EQ for SSTX1 and/or
SSTX2 (refer to 表7-3).
4-level I
(PU/PD)
SSEQ1/A1
EQCFG
2
3
In pin-strap mode, this controls how CEQ[1:0] pins and SSEQ[1:0] are used. Refer to 节
7.4.2 for details. In I2C mode, this pin is for TI internal test and must be left floating for
normal operation.
4-level I
(PU/PD)
SLP_S0#
4
SLP_S0#. This pin will control whether or not Rx.Detect function is enabled. If this pin is
low and device is in Disconnect state, Rx termination will be disabled. If this pin is low and
device is U2/U3 state, Rx termination will be enabled.
1: Rx.Detect Enabled.
I
(PU)
0: Rx.Detect Disabled.
NC
5
6
7
8
No internal connection.
VCC
P
O
O
3.3 V supply
TESTOUT1
TESTOUT2
For internal TI test only. For normal operation this pin should be left unconnected.
For internal TI test only. For normal operation this pin should be left unconnected.
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表4-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
SSTX2p
9
Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
I
I
SSTX2n
10
Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
NC
11
12
No internal connection.
SSRX2p
Differential positive output for USB port 2. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
O
SSRX2n
VIO_SEL
13
14
Differential negative output for USB port 2. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
Selects the input thresholds for I2C (SDA and SCL).
"0": I2C 3.3 V
"R": I2C 1.8 V
"F": I2C 3.3 V.
"1": I2C 1.8 V.
4-level I
(PU/PD)
SSTX1p
SSTX1n
MODE
15
16
17
18
19
Differential positive input for USB port 1. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
I
I
Differential negative input for USB port 1. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
This pin selects whether device is in I2C mode or pin-strap mode. Refer to 表7-4 for
details.
4-level I
(PU/PD)
SSRX1p
SSRX1n
Differential positive output for USB port 1. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
Differential negative output for USB port 1. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
P
VCC
20
21
3.3 V supply
TEST2/SCL
In I2C mode, this pin functions as I2C clock.
I
In pin-strap mode, this pin is used for TI internal test and should be pull-down or tied to
GND for normal operation.
AEQENZ/SDA
AEQCFG
22
23
In I2C mode, this pin functions as I2C data. In pin-strap mode, this pin controls whether or
not AEQ is enabled.
0: AEQ enabled
1: AEQ disabled
I/O
In pin-strap mode, this pin controls the FULLAEQ_UPPER_EQ limit. In I2C mode, this
function is controlled by the FULLAEQ_UPPER_EQ register.
"0": FULLAEQ_UPPER_EQ = Ah
4-level I
(PU/PD)
"R": FULLAEQ_UPPER_EQ = Fh
"F": FULLAEQ_UPPER_EQ = 8h
"1": FULLAEQ_UPPER_EQ = Ch
NC
NC
EN
24
25
26
No internal connection
No internal connection
When low, the differential receiver's termination will be disabled and differential drivers will
be disabled. On rising edge of EN, device will sample four-level inputs and function based
on the sampled state of the pins. This pin has a internal 500k pull-up to VCC. Please note
this pin will also reset internal configuration registers.
I
(PU)
TEST1
VCC
27
28
29
I
TI Test1. Under normal operations this pin shall be connected directly or pulled up to VCC.
3.3 V supply
P
CEQ1
In pin-strap mode, this pin along with CEQ0 selects the receiver EQ for CRX1 and/or
CRX2 (Refer to 表7-2).
4-level I
(PU/PD)
CRX1n
30
Differential negative input for USB port 1. Should be connected to SSRXn pin of USB
connector. Connection can be DC-coupled to USB connector. Optionally, connection can
be through an external 330 nF AC-coupling capacitor.
I
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表4-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
CRX1p
31
Differential positive input for USB port 1. Should be connected to SSRXp pin of USB
connector. Connection can be DC-coupled to USB connector. Optionally, connection can
be through an external 330 nF AC-coupling capacitor.
I
NC
32
33
No internal connection.
CTX1n
Differential negative output for USB port 1. Should be connected to SSTXn pin of USB
connector through an external 220 nF AC-coupling capacitor.
O
O
CTX1p
34
35
Differential positive output for USB port 1. Should be connected to SSTXp pin of USB
connector through an external 220 nF AC-coupling capacitor.
In I2C mode, this pin along with A1 pin selects the 7-bit I2C target address (refer to 表7-7).
In pin-strap mode, this pin along with SSEQ1 selects the receiver EQ for SSTX1 and/or
SSTX2 (refer to 表7-3).
SSEQ0/A0
4-level I
(PU/PD)
CRX2n
CRX2p
36
37
Differential negative input for USB port 2. Should be connected to SSRXn pin of USB
connector. Connection can be DC-coupled to USB connector. Optionally, connection can
be through an external 330 nF AC-coupling capacitor.
I
I
Differential positive input for USB port 2. Should be connected to SSRXp pin of USB
connector. Connection can be DC-coupled to USB connector. Optionally, connection can
be through an external 330 nF AC-coupling capacitor.
CEQ0
38
39
40
In pin-strap mode, this pin along with CEQ1 selects the receiver EQ for CRX1 and/or
CRX2 (Refer to 表7-2).
4-level I
(PU/PD)
CTX2n
Differential negative output for USB port 2. Should be connected to SSTXn pin of USB
connector through an external 220 nF AC-coupling capacitor.
O
CTX2p
Differential positive output for USB port 2. Should be connected to SSTXp pin of USB
connector through an external 220 nF AC-coupling capacitor.
O
G
Thermal Pad
Thermal pad. Connect to a solid ground plane.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, PD = Internal Pull-down, PU = Internal Pull-up.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage Range
VCC
4
V
–0.3
Differential voltage between positive and negative
inputs
-2.5
2.5
V
Voltage Range at any input or output pin
Voltage at differential inputs
CMOS Inputs
4
4
V
–0.5
–0.5
V
TUSB1004
105
125
150
°C
°C
°C
Maximum junction temperature, TJ
Storage temperature, Tstg
TUSB1004I
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
5.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
MAX
3.6
UNIT
Main power supply
3.3
V
VCC
Main supply ramp requirement
0.1
50
ms
Supply that external resistors are pulled up to for both SDA and SCL
pins
V(I2C)
1.7
3.6
V
V(PSN)
Supply Noise on VCC pins (less than 4MHz)
TUSB1004 Operating free-air temperature
TUSB1004I Operating free-air temperature
50
70
85
mVpp
°C
0
TA
-40
°C
5.4 Thermal Information
TUSB1004
THERMAL METRIC(1)
RNQ (WQFN)
40 PINS
31.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.8
Junction-to-board thermal resistance
12.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
12.2
ψJB
RθJC(bot)
4.3
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
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5.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Link in U0 with GEN2 data transmission;
EQ control pins = NC; PRBS7 pattern at
10 Gbps, VID = 1000 mVPP ; Linear redriver
mode; LINR_L3;
Average active power
USB Only for both port1 and port2
PACTIVE-USB-2Ports
550
mW
EN = H;
Link in U0 with GEN2 data transmission;
EQ control pins = NC; PRBS7 pattern at
10 Gbps, VID = 1000 mVPP ; LINR_L3;
EN = H;
Average active power
USB Only for single port.
PACTIVE-USB-1Port
275
mW
Average power with no connection
with SLP_S0#
No USB3.2 GEN2 device is connected to
CTX1; EN = H; SLP_S0#;
PNC-USB-SLP#
0.13
1.5
mW
mW
No USB3.2 GEN2 device is connected to
CTX1;
PNC-USB-1Port
Average power with no connection
EN = H;
Average power with no connection
for both ports in disconnecton
No USB3.2 device is connected to CTX1
and CTX2;
PNC-USB-2Ports
PU2U3-2Ports
PU2U3-SLP#
1.7
2.8
mW
mW
mW
Average power in U2/U3 for both
ports
Link in U2 or U3; EN = H;
Average power in U2/U3 with
SLP_S0#
Link in U2 or U3; EN = H; SLP_S0# = L;
Link in U2 or U3; EN = H;
0.24
PU2U3-1Port
PDISABLED-I2C
PDISABLED
Average power in U2/U3
1.9
0.108
0.130
mW
mW
mW
Device Disabled power in I2C mode MODE = "F"; EN = H; CTLSEL = 0h;
Device Disabled power in pin-strap MODE != "F"; EN = L;
5.6 Control I/O DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-level Inputs
4-Level VTH
4-Level VTH
4-Level VTH
Threshold 0 / R
VCC = 3.3 V
0.55
1.65
2.7
V
V
V
Threshold R/ Float
Threshold Float / 1
VCC = 3.3 V
VCC33 = 3.3 V
High level input current with internal
resistors disabled.
IIH
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
-5
-1
5
1
µA
µA
µA
µA
Low level input current with internal
resistors disabled
IIL
High level input current with internal
resistors enabled.
IIH-REN
IIL-REN
20
60
-40
Low level input current with internal
resistors enabled.
–100
RPU
RPD
Internal pull-up resistance
48
98
kΩ
kΩ
Internal pull-down resistance
2-State CMOS Input (EN, SLP_S0#)
VIH
VIL
High-level input voltage
Low-level input voltage
1.2
3.6
0.6
V
V
-0.3
Internal pull-up resistance (EN,
SLP_S0#)
RPU
IIH
250
-5
400
550
5
kΩ
µA
µA
VIN = 3.6 V; MODE != "F"; VIO_SEL = "0"
or "R";
High-level input current (EN, SLP_S0#)
Low-level input current (EN, SLP_S0#)
VIN = GND, VCC = 3.6 V; MODE !=
"F"; VIO_SEL = "0" or "R";
IIL
11
–11
I2C Control Pins (SCL, SDA)
High-level input voltage when configured
VIH_1p8V
MODE = "F"; VIO_SEL = "R" or "1";
MODE = "F"; VIO_SEL = "R" or "1";
1.2
3.6
0.6
V
V
for 1.8V I2C level
Low-level input voltage when configured
for 1.8V I2C level
VIL_1p8V
-0.3
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5.6 Control I/O DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage when configured
for 3.3V I2C level
VIH_3p3V
VIL_3p3V
MODE = "F"; VIO_SEL = "0" or "F";
2.0
3.6
V
Low-level input voltage when configured
for 3.3V I2C level
MODE = "F"; VIO_SEL = "0" or "F";
-0.3
0.8
0.4
V
VOL
Low-level output voltage
Low-level output current
Input current
MODE = "F"; IOL = 6 mA
0
20
V
IOL
MODE = "F"; VOL = 0.4 V
mA
µA
pF
II(I2C)
CI(I2C)
0.1 x V(I2C) < Input voltage < 3.3 V
1
–1
Input capacitance
10
C(I2C_FM+_BUS
I2C bus capacitance for FM+ (1MHz)
150
150
910
pF
pF
Ω
)
C(I2C_FM_BUS) I2C bus capacitance for FM (400kHz)
External resistors on both SDA and SCL
R(EXT_I2C_FM+)
C(I2C_FM+_BUS) = 150 pF
C(I2C_FM_BUS) = 150 pF
620
620
820
when operating at FM+ (1MHz)
External resistors on both SDA and SCL
R(EXT_I2C_FM)
1500
2200
Ω
when operating at FM (400kHz)
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5.7 USB Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB Gen 2 Differential Receiver (CRX1p/n, CRX2p/n, SSTX1p/n, SSTX2p/n)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
Input differential peak-peak voltage
swing linear dynamic range
V(RX-DIFF-PP)
1200
0
mVpp
V
Common-mode voltage bias in the
receiver (DC)
V(RX-DC-CM)
Max Instantaneous RX DC common
mode voltage change under all
operating conditions (OFF to ON,
Disabled to USB, etc…)
Measured at non-device side of AC
coupling capacitor with 200-kΩ load.
VRX_CM-INST
-300
500
mV
R(RX-DIFF-DC)
R(RX-CM-DC)
Differential input impedance (DC)
Present after a GEN2 device is detected.
Present after a GEN2 device is detected.
72
18
90
120
30
Ω
Ω
Receiver DC common mode
impedance
Present when no GEN2 device is detected
on transmitter.
Measured over the range of 0 –500 mV
with respect to GND.
Common-mode input impedance with
termination disabled (DC)
Z(RX-HIGH-IMP-DC-POS)
25
kΩ
Input differential peak-to-peak signal
detect assert level
V(SIGNAL-DET-DIFF-PP)
V(RX-IDLE-DET-DIFF-PP)
V(RX-LFPS-DET-DIFF-PP)
At 10 Gbps, no input loss, PRBS7 pattern
At 10 Gbps, no input loss, PRBS7 pattern
Below the minimum is squelched
75
55
mV
mV
mV
Input differential peak-to-peak signal
detect de-assert Level
Low frequency periodic signaling
(LFPS) detect threshold
100
300
V(RX-CM-AC-P)
C(RX)
Peak RX AC common-mode voltage
RX input capacitance to GND
Measured at package pin
At 5 GHz;
150
1
mV
pF
dB
dB
dB
-22
-20
-12
50 MHz –1.25 GHz at 85 Ω;
5 GHz at 85 Ω;
RL(RX-DIFF)
Differential return Loss
RL(RX-CM)
EQ_SSTX15
Common-mode return loss
50 MHz –5 GHz at 85 Ω;
SSTX1->CTX1 Receiver equalization SSEQ1_SEL = 15; Gain at 5 GHz minus
at 5 GHz
13.6
12.7
dB
dB
nF
nF
Gain at 10 MHz;
CRX1 -> SSRX1 Receiver
equalization at 5 GHz
CEQ1_SEL = 15; Gain at 5 GHz minus
Gain at 10 MHz;
EQ_RX15
CAC-USB1
CAC-USB2
Required external AC capacitor on
SSTX1/2
75
265
363
Optional external AC capacitor on
CRX1 and CRX2.
297
USB Gen 2 Differential Transmitter (CTX1p/n, CTX2p/n, SSRX1p/n, SSRX2p/n)
Transmitter dynamic differential
voltage swing range.
VTX(DIFF-PP)
EQ15; VID = 1Vpp; LINR_L3
1200
mVpp
mV
Amount of voltage change allowed
during receiver detection
VTX(RCV-DETECT)
600
800
Max Instantaneous TX DC common
mode voltage change under operating
condition: OFF to ON, ON to OFF,
during Rx.Detect; Disconnect to U0,
U2/U3 to Disconnect.
Measured single-ended at non-device side
of AC coupling capacitor with 200-kΩ
load.
VTX-CM-INST-ONOFF
-500
mV
mV
Transmitter idle common-mode
voltage change while in U2/U3 and not
actively transmitting LFPS
VTX(CM-IDLE-DELTA)
600
–300
Common-mode voltage bias in the
transmitter (DC)
VTX(DC-CM)
0.5
0.76
1
100
10
V
Max mismatch from Txp + Txn for both
time and amplitude
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active
mVpp
mV
AC electrical idle differential peak-to-
VTX(IDLE-DIFF-AC-PP)
At package pins
At package pin
0
peak output voltage
VTX(CM-DC-ACTIVE-
Absolute DC common-mode voltage
between U1 and U0
200
120
mV
IDLE-DELTA)
RTX(DIFF)
Differential impedance of the driver
80
90
Ω
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5.7 USB Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured with respect to AC ground over
0–500 mV
Common-mode impedance of the
driver
RTX(CM)
18
30
Ω
SSRX differential peak-to-peak
VSSRX-LIMITED-VODL0 voltage when configured for limited
redriver and LINR_L0
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 0;
750
900
mVpp
mVpp
mVpp
mVpp
SSRX differential peak-to-peak
VSSRX-LIMITED-VODL1 voltage when configured for limited
redriver and LINR_L1
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 0;
SSRX differential peak-to-peak
VSSRX-LIMITED-VODL2 voltage when configured for limited
redriver and LINR_L2
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 0;
1000
1100
SSRX differential peak-to-peak
VSSRX-LIMITED-VODL3 voltage when configured for limited
redriver and LINR_L3
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 1;
TX_DEEPHASIS = 2'b00;
USB_SSRX_VOD = 2'b00 (LINR_L3);
Refer to 图6-7
SSRX de-emphasis when configured
for limited redriver and de-emphasis
enabled.
VSSRX-DE-RATIO0
-1.8
-2.1
-3.2
-3.8
1.6
dB
dB
dB
dB
dB
dB
dB
dB
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 1;
TX_DEEPHASIS = 2'b01;
USB_SSRX_VOD = 2'b00
(LINR_L3); Refer to 图6-7
SSRX de-emphasis when configured
for limited redriver and de-emphasis
enabled.
VSSRX-DE-RATIO1
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 1;
TX_DEEPHASIS = 2'b10;
USB_SSRX_VOD = 2'b00
(LINR_L3); Refer to 图6-7
SSRX de-emphasis when configured
for limited redriver and de-emphasis
enabled.
VSSRX-DE-RATIO2
TX_PRESHOOT_EN = 0;
TX_DEEMPHASIS_EN = 1;
TX_DEEPHASIS = 2'b11;
USB_SSRX_VOD = 2'b00
(LINR_L3); Refer to 图6-7
SSRX de-emphasis when configured
for limited redriver and de-emphasis
enabled.
VSSRX-DE-RATIO3
TX_PRESHOOT_EN = 1;
TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT = 2'b00;
USB_SSRX_VOD = 2'b00 (LINR_L3);
Refer to 图6-6
SSRX pre-shoot level when configured
for limited redriver and pre-shoot
enabled.
VSSRX-PRESH-RATIO0
VSSRX-PRESH-RATIO1
VSSRX-PRESH-RATIO2
VSSRX-PRESH-RATIO3
TX_PRESHOOT_EN = 1;
TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT = 2'b01;
USB_SSRX_VOD = 2'b00 (LINR_L3);
Refer to 图6-6
SSRX pre-shoot level when configured
for limited redriver and pre-shoot
enabled.
2.1
TX_PRESHOOT_EN = 1;
TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT = 2'b10;
USB_SSRX_VOD = 2'b00 (LINR_L3);
Refer to 图6-6
SSRX pre-shoot level when configured
for limited redriver and pre-shoot
enabled.
2.5
TX_PRESHOOT_EN = 1;
TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT = 2'b11;
USB_SSRX_VOD = 2'b00 (LINR_L3);
Refer to 图6-6
SSRX pre-shoot level when configured
for limited redriver and pre-shoot
enabled.
3.0
ITX(SHORT)
CTX(PARASITIC)
RLTX(DIFF)
RLTX(CM)
TX short circuit current
TX± shorted to GND
60
mA
pF
dB
dB
TX input capacitance for return loss
Differential return loss
At package pins, at 5 GHz
50 MHz –1.25 GHz at 85 Ω
50 MHz –5 GHz at 85 Ω
1.25
-28
-12
Common-mode return loss
External required AC coupling
capacitor
CTX-AC(COUPLING)
75
265
-40
nF
AC Characteristics
Crosstalk_CRXTX
Differential crosstalk between CTX1/2
and CRX1/2 signal pairs
85 Ω; At 5 GHz; SSEQ[1:0] = 0; CEQ[1:0]
= 0;
dB
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5.7 USB Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-frequency -1dB compression
point at LINR_L0 setting.
20 MHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
CPLF-LINRL0
CPHF-LINRL0
CPLF-LINRL1
CPHF-LINRL1
CPLF-LINRL2
CPHF-LINRL2
CPLF-LINRL3
750
mVpp
High-frequency -1dB compression
point at LINR_L0 setting.
5 GHz clock pattern; VID is 200mV to
1200mV in 10mV steps;
650
850
mVpp
mVpp
mVpp
mVpp
mVpp
mVpp
Low-frequency -1dB compression
point at LINR_L1 setting.
20 MHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
High-frequency -1dB compression
point at LINR_L1 setting.
5 GHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
750
Low-frequency -1dB compression
point at LINR_L2 setting.
20 MHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
950
High-frequency -1dB compression
point at LINR_L2 setting.
5 GHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
850
Low-frequency -1dB compression
point at LINR_L3 setting.
20 MHz clock pattern; VID is 200 mV to
1200 mV in 10mV steps;
1050
High-frequency -1dB compression
point at LINR_L3 setting.
5 GHz clock pattern; VID is 200 mV to
1200 mV in 10 mV steps;
CPHF-LINRL3
fLF
tTX_DJ_SSTX2-CTX2
900
20
mVpp
kHz
Low frequency cutoff
200 mVPP< VID < 1200 mVPP
50
Optimal EQ setting; 12-in prechannel
(SDD21 = -11.2 dB); 1.6-in post channel
(SDD21 = -1.8 dB); PRBS7; 10 Gbps
TX output deterministic residual jitter
SSTX2-> CTX2.
.05
.05
UI
UI
Optimal EQ setting; 12-in prechannel
(SDD21 = -11.2 dB); 1.6-in post channel
(SDD21 = -1.8 dB); PRBS7; 10 Gbps
TX output deterministic residual jitter
SSTX1-> CTX1.
tTX_DJ_SSTX1-CTX1
5.8 Timing Requirements
MIN
NOM
MAX
UNIT
USB3.1
tIDLEEntry
Delay from U0 to electrical idle
10
1
ns
ns
Refer to 图6-4.
Refer to 图6-4.
U1 exit time: break in electrical idle to the
transmission of LFPS
tIDELExit_U1
U2/U3 exit time: break in electrical idle to
transmission of LFPS
tIDLEExit_U2U3
10
10
µs
Refer to 图6-4.
tRXDET_INTVL
tIDLEExit_DISC
tExit_SHTDN
RX detect interval while in Disconnect
Disconnect Exit Time
12
ms
µs
Shutdown Exit Time
0.75
400
ms
Maximum time to obtain optimum EQ setting
when operating in Full AEQ mode.
tAEQ_FULL_DONE
µs
Maximum time to determine appropriate EQ
setting when operating in Fast AEQ mode.
tAEQ_FAST_DONE
tDIFF_DLY
60
µs
ps
Differential Propagation Delay
300
Refer to 图6-3.
20%-80% of differential voltage
measured 1.7 inch from the
output pin; Refer to 图6-5.
tR, tF
Output Rise/Fall time
30
ps
ps
20%-80% of differential voltage
measured 1.7 inch from the
output pin
tRF_MM
Output Rise/Fall time mismatch
2.6
Power-up
tEN_LOW
tCFG_SU
EN pin held low after supply reaches VCC(min)
5
250
500
ms
µs
µs
Refer to 图6-1
Refer to 图6-1
Refer to 图6-1
CFG(1) high
CFG(1) high
tCFG_HD
(1) Following pins comprise CFG pins: MODE, CEQ[1:0], SSEQ[1:0], EQCFG, AEQCFG
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5.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C
fSCL
I2C clock frequency
1
MHz
µs
Bus free time between START and
STOP conditions
tBUF
0.5
Refer to 图6-2
Hold time after repeated START
condition. After this period, the first
clock pulse is generated
tHD_STA
0.26
µs
Refer to 图6-2
tLOW
tHIGH
Low period of the I2C clock
High period of the I2C clock
0.5
µs
µs
Refer to 图6-2
Refer to 图6-2
0.26
Setup time for a repeated START
condition
tSU_STA
0.26
µs
Refer to 图6-2
tHD_DAT
tSU_DAT
Data hold time
Data setup time
0
µs
ns
Refer to 图6-2
Refer to 图6-2
50
Rise time of both SDA and SCL
signals
tR
120
120
ns
Refer to 图6-2
tF
Fall time of both SDA and SCL signals
Setup time for STOP condition
20 × (V(I2C)/5.5 V)
0.26
ns
µs
pF
Refer to 图6-2
Refer to 图6-2
tSU_STO
Cb
Capacitive load for each bus line
150
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5.10 Typical Characteristics
图5-1. USB CRX1 EQ Settings Curves
图5-2. USB SSTX1 EQ Settings Curves
at 85 Ω(from simulation)
at 85 Ω(from simulation)
图5-3. CRX1 Input Return Loss Performance
at 85 Ω(from simulation)
图5-4. CTX1 Output Return Loss Performance
at 85 Ω(from simulation)
图5-5. USB SSRX1 VOD Linearity Settings
图5-6. USB SSRX1 VOD Linearity Settings
at 20 MHz and EQ = 0
at 5 GHz and EQ = 0
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5.10 Typical Characteristics (continued)
图5-7. USB CTX1 VOD Linearity Settings
图5-8. USB CTX1 VOD Linearity Settings
at 20 MHz and EQ = 0
at 5 GHz and EQ = 0
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6 Parameter Measurement Information
VCC (min)
VCC
tEN_LOW
VIH(min)
EN pin
VIL(max)
tCFG_SU
tCFG_HD
CFG pins
图6-1. Power-On Timing Requirements
t
t
r
t
SU_DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
cont.
t
t
HD_DAT
VD_DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
cont.
t
HD_STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD_ACK
t
t
t
t
SU_STO
SU_STA
HD_STA
SP
70 %
30 %
Sr
P
S
th
9
clock
图6-2. I2C Timing Diagram Definitions
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IN
T
T
DIFF_DLY
DIFF_DLY
OUT
图6-3. USB Propagation Delay
IN+
V
Vcm
RX-LFPS-DET-DIFF-PP
IN-
T
T
IDLEEntry
IDLEExit
OUT+
Vcm
OUT-
图6-4. Electrical Idle Exit and Entry Delay
80%
20%
t
r
t
f
图6-5. Output Rise and Fall Times
VSSRX-LIMITED-VODL3
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 0;
TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 1;
TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2;
TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 3;
图6-6. SSRX Limited Pre-Shoot only
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VSSRX-LIMITED-VODL3
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEMPHASIS = 0;
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEMPHASIS = 1;
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEMPHASIS = 2;
TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEMPHASIS = 3;
图6-7. SSRX Limited De-Emphasis Only
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7 Detailed Description
7.1 Overview
The TUSB1004 is a 10 Gbps USB 3.2 quad channel linear redriver for USB Type-A applications. The TUSB1004
is intended to reside between a Host and a USB receptacle or between a USB device and a USB receptacle.
The TUSB1004 supports both USB 3.2 Gen2 (10 Gbps) and Gen1 (5 Gbps) as well as USB 3.2 low power
states (Disconnect, U1, U2, and U3).
The TUSB1004 supports up to 16 receiver equalization settings controlled by either pin-strap pins or through I2C
registers. The USB connector facing receivers (CRX1 and CRX2) support three equalization modes: Fixed EQ,
Fast AEQ, and Full AEQ. Selection between these modes is done through either pin-strap pins or through I2C
regisrers. The other receivers (SSTX1/2) only support Fixed EQ.
The TUSB1004 operates as a linear redriver for signals traversing from the SSTX1/2 receivers towards CTX1/2
transmitters. It can operate as either a linear redriver or limited redriver for signals traversing from CRX1/2
receivers towards SSRX1/2 transmitters. TUSB1004 defaults to linear redriver but can be enabled for limited
redriver by I2C register. When enabled for limited redriver, the SSRX1/2 transmitter support four levels of pre-
shoot and four-levels of de-emphasis.
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7.2 Functional Block Diagram
GND
VIterm
SSRXTERM_EN2
SSTX2P
CTX2P
CTX2N
TX
RX
Channel A
SSTX2N
CTXEN2
CIDLE2
LFPS
SSLOSZ2
SSLFPS2
Rx
Detect
CRXDET2
LOS
GND
LANE 2
VIterm
CRXTERM_EN2
SSRX2P
SSRX2N
CRX2P
CRX2N
TX
RX
Channel B
Channel C
SSTXEN2
SSIDLE2
LFPS
LOS
CLFPS2
CLOSZ2
Rx
Detect
SSRXDET2
GND
VIterm
SSRXTERM_EN1
SSTX1P
SSTX1N
CTX1P
CTX1N
TX
RX
CTXEN1
CIDLE1
LFPS
SSLOSZ1
SSLFPS1
Rx
CRXDET1
Detect
LOS
LANE 1
GND
VIterm
CRXTERM_EN1
SSRX1P
SSRX1N
CRX1P
CRX1N
TX
RX
Channel D
SSRXEN1
SSIDLE1
LFPS
LOS
CLFPS1
CLOSZ1
Rx
Detect
SSRXDET1
SSEQ0/A0
SSEQ1/A1
TEST1
CEQ0
CEQ1
MODE
Control &
Status
Registers
AEQENZ/SDA
TEST2/SCL
VIO_SEL
AEQCFG
EQCFG
I2C
Target
VCC
500k
POR
EN
TESTOUT1
TESTOUT2
SLP_S0#
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7.3 Feature Description
7.3.1 4-Level Inputs
The TUSB1004 has 4-level inputs pins that are used to control the receiver equalization gain, transmitter voltage
swing, and place TUSB1004 into different modes of operation. These 4-level inputs utilize a resistor divider to
help set the 4 valid levels and provide a wider range of control settings. There are internal pull-up and pull-down
resistors. These resistors, together with the external resistor connection combine to achieve the desired voltage
level.
表7-1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
R
F
1
Tie 1-kΩ 5% to GND.
Tie 20-kΩ 5% to GND.
Float (leave pin open)
Tie 1-kΩ 5% to VCC
.
备注
All 4-level inputs are latched after the rising edge of EN pin. After these pins are sampled, the internal
pull-up and pull-down resistors will be isolated in order to save power.
7.3.2 USB Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB1004. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TUSB1004 receivers. Two 4-level
inputs pins enable up to 16 possible equalization settings when in pin-strap mode. The TUSB1004's USB 3.2
host, hub, and device receivers (SSTX1/2) and USB 3.2 USB connector receivers (CRX1/2) each have their own
two 4-level inputs. The TUSB1004 also provides the flexibility of adjusting settings through I2C registers.
The TUSB1004's USB host, hub, and device facing port receiver (SSTX1/2) only support Fixed EQ (FEQ). The
TUSB1004 implements three different equalizer features for the USB connector facing port receivers (CRX1 and
CRX2): Fixed EQ (FEQ), Fast Adaptive EQ (Fast AEQ), and Full Adaptive EQ (Full AEQ). In Fixed EQ
operation, a single setting is used for all possible devices (with and without cable) inserted into the USB
receptacle. The Fast AEQ feature will distinguish between a short channel and a long channel. A short channel
represents a low loss use case of a USB 3.2 device plugged directly into USB receptacle without a cable. A long
channel represents the high loss use case of the USB 3.2 device plugged into the receptacle through a USB
cable. In Fast AEQ mode, TUSB1004 will select between two pre-determined settings based on whether or not
channel is short or long. When TUSB1004 is configured for Full AEQ, the TUSB1004 will automatically
determine what it believes is the best equalization setting each time a USB device is inserted into the USB
receptacle. In Full AEQ mode, the TUSB1004 will attempt to determine the best settings regardless if the
channel is short, long, or somewhere in between.
备注
Adaptive EQ is only supported on CRX1 and CRX2. Adaptive EQ must only be used when CRX1 and
CRX2 is connected to a USB receptacle. If CRX1 and CRX2 is connected directly (not through a USB
receptacle) to a USB Host, USB Hub or USB Device, then adaptive EQ must be disabled. AEQ should
never be enabled in a active cable application. If daisy chaining multiple TUSB1004, AEQ should only
be enabled on the TUSB1004 that is near the USB receptacle.
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7.3.2.1 Linear EQ Configuration
Each of the TUSB1004 receiver lanes have individual controls for receiver equalization. The receiver
equalization gain value can be controlled either through I2C registers or through pin-straps. 表 7-2 and 表 7-3
details the gain value for each available combination when TUSB1004 is in pin-strap mode. These same options
are also available in I2C mode by updating registers CEQ1_SEL, CEQ2_SEL, SSEQ2_SEL, and SSEQ1_SEL.
表7-2. USB Connector Facing Port Receiver (CRX1 and CRX2 pins) Equalization Control
Register(s): CEQ1_SEL or
CEQ2_SEL
Equalization Setting #
EQ Gain at 5 GHz minus Gain
CEQ1 PIN Level
CEQ0 PIN Level
at 100 MHz
(dB)
0
1
0
0
0
R
F
1
-0.4
1.9
2
0
3.5
3
0
5.0
4
R
R
R
R
F
F
F
F
1
0
6.1
5
R
F
1
7.2
6
8.0
7
8.8
8
0
9.6
9
R
F
1
10.2
10.7
11.2
11.6
12.0
12.4
12.7
10
11
12
13
14
15
0
1
R
F
1
1
1
表7-3. USB Host Facing Port Receiver (SSTX1 and SSTX2 pins) Equalization Control
EQ Gain at 5 GHz minus
Register(s): SSEQ1_SEL or SSEQ2_SEL
Equalization Setting #
SSEQ1 PIN LEVEL
SSEQ0 PIN LEVEL
Gain at 100 MHz
(dB)
0
1
0
0
0
R
F
1
0.6
2.8
2
0
4.5
3
0
6.0
4
R
R
R
R
F
F
F
F
1
0
7.0
5
R
F
1
8.0
6
9.0
7
10.0
10.6
11.2
11.7
12.2
12.5
13.0
13.3
13.6
8
0
9
R
F
1
10
11
12
13
14
15
0
1
R
F
1
1
1
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7.3.2.2 Full Adaptive Equalization
The Full AEQ mode attempts to find what it believes is the best equalization value for CRX1 and CRX2 receivers
by starting at the lowest EQ value and sweeping through all EQ combinations up to the value programmed into
FULLAEQ_UPPER_EQ field. The default is to sweep through nine EQ values (zero to eight). The number of EQ
combinations can be adjusted by programming FULLAEQ_UPPER_EQ register. The TUSB1004 also provides
the ability to add or subtract some over/under equalization to compensate for channel in front of TUSB1004 by
programming OVER_EQ_CTRL field to a non-zero value. If OVER_EQ_SIGN = 0, the TUSB1004 will add the
value programmed into OVER_EQ_CTRL to the EQ value determined by the full adaptation. If OVER_EQ_SIGN
= 1, the TUSB1004 will subtract the value programmed into OVER_EQ_CTRL from the EQ value determined by
the full adaptation. For example, if full adaptation determines the best equalization value to be 4 and
OVER_EQ_CTRL is 2 and OVER_EQ_SIGN = 0, the EQ setting used by TUSB1004 will be 6. The TUSB1004
hardware will always limit the sum of OVER_EQ_CTRL and the determined optimal EQ from full adaptation to be
less than or equal to 15.
备注
Full AEQ is supported in both pin-strap and I2C mode. In pin-strap mode, enable or disable of Full
AEQ is determined by the state of AEQENZ pin.
7.3.2.3 Fast Adaptive Equalization
The Fast AEQ mode is used to distinguish two channels (short channel and a long channel) and choose the
appropriate receiver equalization setting for that channel. Because Fast AEQ only distinguishes between two
choices, the AEQ time is a lot shorter than Full AEQ mode which minimizes impact to USB link training.
When Fast AEQ is enabled and channel is determined to be short, the TUSB1004 will use the value
programmed into the CEQx_SEL, where x = 1 or 2. If the TUSB1004 determines channel is not short, the
TUSB1004 will switch to EQ value programmed into LONG_EQx register, where x = 1 or 2. During initial system
evaluation, it is recommended to perform both short and long channel USB 3.1 RX JTOL Gen2 testing and
program CEQx_SEL and LONG_EQx to the value which produced the best results for each channel
configuration.
The TUSB1004 will determine short and long based on the estimate eye height. The value programmed into
FASTAEQ_LIMITS register will determine the eye height limits. Software can change the defaults of this register
to lower or raise the limits.
备注
Fast AEQ is only supported in I2C mode.
EQ_OVERRIDE field must be set for values programmed into CEQx_SEL and LONG_EQx to be
used.
7.3.3 USB Transmitter
7.3.3.1 Linearity VOD
Linearity VOD defines the linearity range of the TUSB1004. When TUSB1004 is in linear VOD mode, the output
VOD is a linear function of the input VID. For example, if the signal at TUSB1004's input (VID) is at 600 mVpp
then the TUSB1004's output VOD will be around 600 mVpp. Linearity VOD mode is the default operation of the
TUSB1004. Linear VOD mode is supported on SSRX1/2 and CTX1/2 transmitters.
The TUSB1004 provides four different linearity VOD settings. All four settings are available in I2C mode through
register control. In pin-strap mode, the linearity is fixed at the highest setting.
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7.3.3.2 Limited VOD
Limited VOD mode is used to set the actual VOD level and is used when TUSB1004 is configured in limited
redriver mode. In this mode the VOD is no longer a linear function of the input VID. For example, if the signal at
TUSB1004's input (VID) is at 600 mVpp then the TUSB1004's output VOD will be around 1000 mVpp (assuming
LINR_L3 is selected). The limited redriver mode is only supported on the SSRX1/2 transmitter. The TUSB1004
provides four different limited VOD settings. All four settings are available through register control.
备注
Limited redriver mode is disabled by default and can only be enabled by setting the
SSRX_LIMIT_ENABLE register. Once enabled, the VOD level for SSRX1/2 transmitters is controlled
by the USB_SSRX12_VOD register
7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
The TUSB1004 in limited redriver mode offers pre-shoot and de-emphasis controls for SSRX1/2 transmitter. The
TUSB1004 offers four pre-shoot levels and four de-emphasis levels. These levels can be changed by modifying
I2C registers.
SSRX1 transmitter equalization is controlled by TX1_PRESHOOT and TX1_DEEMPHASIS fields. When
SSRX_LIMIT_ENABLE = 1 and TX1_PRESHOOT_EN = 1, the TX1_PRESHOOT field selects between four
different pre-shoot levels. When SSRX_LIMIT_ENABLE = 1 and TX1_DEEMPHASIS_EN = 1, the
TX1_DEEMPHASIS field selects between four different de-emphasis levels.
SSRX2 transmitter equalization is controlled by TX2_PRESHOOT and TX2_DEEMPHASIS fields. When
SSRX_LIMIT_ENABLE = 1 and TX2_PRESHOOT_EN = 1, the TX2_PRESHOOT field selects between four
different pre-shoot levels. When SSRX_LIMIT_ENABLE = 1 and TX2_DEEMPHASIS_EN = 1, the
TX2_DEEMPHASIS field selects between four different de-emphasis levels.
备注
Transmitter equalization control is not supported in pin-strap mode.
7.3.4 USB 3.1 x2 Description
The TUSB1004 will operate as two independent USB state machines. The TUSB1004 is intended to be used in
applications that support USB stacked standard A connectors or two standard-A connectors that are in close
proximity to each other.
In pin-strap mode the TUSB1004 will enable both lanes for USB operation immediately following EN pin high. In
I2C mode, software must program register offset 0xD to a 0x03 and it also must program CTLSEL field (located
in offset 0xA) to a 1 for both lanes to be enabled for USB operation.
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7.3.5 USB Polarity Inversion
The USB 3.2 standard requires all host, hubs, and devices support USB polarity inversion detection and
correction. For this reason, polarity between TUSB1004 and USB connector as well as between USB Host/
Device and TUSB1004 does not have to be maintained. Not maintaining polarity will simplify layout by
eliminating the need to swap P and N in the layout. The 图 7-1 shows example in which polarity between USB
host and redriver is not maintained.
USB 3.2
redriver
Host/Device
TXp
TXn
SSTXn
SSTXp
CTXp
CTXn
SSTXp
SSTXn
RXp
RXn
SSRXn
SSRXp
CRXp
CRXn
SSRXp
SSRXn
Polarity inverted
图7-1. Polarity Inversion Example
7.3.6 Receiver Detect Control
The SLP_S0# pin offers system designers the ability to control the TUSB1004 Rx.Detect functionality during
Disconnect and U2/U3 states and therefore achieving lower consumption in these states. When the system is in
a low power state (Sx where x = 1, 2, 3, 4, or 5), system can assert SLP_S0# low to disable TUSB1004 receiver
detect functionality. While SLP_S0# is asserted low and USB 3.2 interface is in U3, the TUSB1004 keeps
receiver termination active. The TUSB1004 will not respond to any LFPS signaling while in this state. This
means that system wake from U3 is not supported while SLP_S0# is asserted low. If the TUSB1004 is in
Disconnect state when SLP_S0# is asserted low, then TUSB1004 disables all channels receiver termination and
disables receiver detect functionality. When SLP_S0# is asserted high, the TUSB1004 resumes normal
operation of performing far-end receiver termination detection.
备注
As there is a single SLP_S0# pin, this pin when asserted low impact both port 1 (CRX1, CTX1,
SSRX1, SSTX1) and port 2 (CRX2, CTX2, SSRX2, SSTX2).
7.4 Device Functional Modes
7.4.1 MODE Pin
The MODE pin selects between between I2C mode and pin-strap mode. Refer to 表7-4 for details.
In I2C mode, the TUSB1004 supports either 1.8-V LVCMOS or 3.3-V LVCMOS signalling based on the sampled
state of VIO_SEL pin.
表7-4. MODE pin Function
MODE pin level
Description
Pin-strap mode.
Reserved
0
R
F
1
I2C Mode
Reserved.
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7.4.2 Rx EQ Configuration in Pin-Strap Mode
The TUSB1004 configured in pin-strap mode uses the follow pins to control the EQ setting for each of its
receivers: EQCFG pin, SSEQ[1:0] pins, CEQ[1:0] pins.
表7-5. Pin-strap: SSTX1 and SSTX2 Receiver EQ Configuration
SSTX Receiver
SSEQ[1:0] pin level
Gain at 5 GHz
EQCFG pin level
SSEQ0 = "0"
3 dB
"1" or "R"
SSEQ0 = "R"
SSEQ0 = "F"
6 dB
"1" or "R"
9 dB
"1" or "R"
SSTX1
SSEQ0 = "1"
12 dB
"1" or "R"
16 possible settings based on
SSEQ0 and SSEQ1
"0" or "F"
Refer to 表7-3.
SSEQ1 = "0"
SSEQ1 = "R"
SSEQ1 = "F"
SSEQ1 = "1"
3 dB
"1" or "R"
"1" or "R"
"1" or "R"
"1" or "R"
"0" or "F"
6 dB
9 dB
SSTX2
12 dB
16 possible settings based on
SSEQ0 and SSEQ1
Refer to 表7-3.
The following table describes receiver equalization controls for the receivers facing the USB connector.
表7-6. Pin Strap: CRX1 and CRX2 EQ Configuration with AEQ Disabled
CRX Receiver
CEQ[1:0] pin level
Gain at 5 GHz
EQCFG pin level
CEQ0 = "0"
3 dB
"0" or "R"
CEQ0 = "R"
6 dB
"0" or "R"
CEQ0 = "F"
9 dB
"0" or "R"
CRX1
CEQ0 = "1"
12 dB
"0" or "R"
16 possible settings based on
CEQ0 and CEQ1
"F" or "1"
Refer to 表7-2.
CEQ1 = "0"
CEQ1 = "R"
CEQ1 = "F"
CEQ1 = "1"
3 dB
"0" or "R"
"0" or "R"
"0" or "R"
"0" or "R"
"F" or "1"
6 dB
9 dB
CRX2
12 dB
16 possible settings based on
CEQ0 and CEQ1
Refer to 表7-2.
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7.4.3 USB 3.2 Power States
The TUSB1004 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB 3.1 interface. Depending on the state of the USB
3.2 interface, the TUSB1004 can be in one of four primary modes of operation when USB 3.1 is enabled:
Disconnect, U2/U3, U1, and U0 (Active).
The Disconnect state is the state in which TUSB1004 has not detected far-end termination on both upstream
facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of
the four states. The TUSB1004 remains in this state until far-end receiver termination has been detected on both
UFP (SSRX) and DFP (CTX). The TUSB1004 immediately exits this mode and enters U0 once far-end
termination is detected.
Once in U0 state, the TUSB1004 will redrive all traffic received on the port in both directions. U0 is the highest
power mode of all USB 3.2 power states. The TUSB1004 remains in U0 state until electrical idle occurs on both
UFP and DFP. Upon detecting electrical idle, the TUSB1004 immediately transitions to U1.
The U1 state is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1004 UFP
and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect state, the U2/U3 state is next lowest power state. While in this state, the TUSB1004
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB1004 leaves the U2/U3 state and transitions to the Disconnect state. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1004 immediately transitions to the U0
state. In U2/U3 state, the TUSB1004 receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
7.4.4 Disabling U1 and U2
In systems which have U1 and U2 disabled, it may be necessary to disable U1 and U2 in TUSB1004. In I2C
mode this can be accomplished by setting the USB3_U1_DISABLE field. In pin-strap mode U1 and U2 is
enabled by default and can't be disabled.
7.5 Programming
7.5.1 Pseudocode Examples
7.5.1.1 Fixed EQ with Linear Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x11), // Linear redriver, EQ_OVERRIDE and USB 3.2
(0x1C, 0x80), // Disable AEQ enable.
(0x32, 0xC0), // VOD control
(0x20, 0x44), // USB connector CRx1/CRx2 EQ setting
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
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7.5.1.2 Fixed EQ with Limited Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x91), // Limited redriver, EQ_OVERRIDE and USB 3.2
(0x0B, 0x6F), // SSRX1 limited. Preshoot and de-emphasis.
(0x0C, 0x6C), // SSRX2 limited. Preshoot and de-emphasis.
(0x1C, 0x80), // Disable AEQ enable.
(0x32, 0xC0), // VOD control
(0x20, 0x44), // USB connector CRx1/CRx2 EQ setting
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
7.5.1.3 Fast AEQ with Linear Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x11), // Linear redriver, EQ_OVERRIDE and USB 3.2
(0x1C, 0x81), // Fast AEQ enable.
(0x32, 0xC0), // VOD control
(0x1D, 0x10), // Over EQ adjustment
(0x1E, 0x77), // USB connector CRx1/CRx2 long channel EQ setting
(0x20, 0x11), // USB connector CRx1/CRx2 short channel EQ setting
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
7.5.1.4 Fast AEQ with Limited Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x91), // Limited redriver, EQ_OVERRIDE and USB 3.2
(0x0B, 0x6F), // SSRX1 limited. Preshoot and de-emphasis.
(0x0C, 0x6C), // SSRX2 limited. Preshoot and de-emphasis.
(0x32, 0xC0), // VOD control
(0x1C, 0x81), // Fast AEQ enable.
(0x1D, 0x10), // Over EQ adjustment
(0x1E, 0x77), // USB connector CRx1/CRx2 long channel EQ setting
(0x20, 0x11), // USB connector CRx1/CRx2 short channel EQ setting
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
7.5.1.5 Full AEQ with Linear Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x11), // Linear redriver, EQ_OVERRIDE and USB 3.2
(0x32, 0xC0), // VOD control
(0x1C, 0x85), // Full AEQ enable. Set upper EQ limit to 0x8.
(0x1D, 0x10), // Over EQ adjustment
(0x20, 0x11), // USB connector CRx1/CRx2 EQ. Not used in Full AEQ.
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
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7.5.1.6 Full AEQ with Limited Redriver Mode
// (address, data)
// Initial power-on configuration.
(0x0D, 0x03), // Enable both lanes 1 and 2.
(0x0A, 0x91), // Limited redriver, EQ_OVERRIDE and USB 3.2
(0x0B, 0x6F), // SSRX1 limited. Preshoot and de-emphasis.
(0x0C, 0x6C), // SSRX2 limited. Preshoot and de-emphasis.
(0x32, 0xC0), // VOD control
(0x1C, 0x85), // Full AEQ enable.
(0x1D, 0x10), // Over EQ adjustment
(0x20, 0x11), // USB connector CRx1/CRx2 short channel EQ setting. Not used for Full AEQ.
(0x21, 0x55), // SSTX1 and SSTX2 receiver EQ
7.5.2 TUSB1004 I2C Address Options
For further programmability, the TUSB1004 can be controlled using I2C. The SCL and SDA pins are used for I2C
clock and I2C data respectively.
表7-7. TUSB1004 I2C Target Address
SSEQ1/A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 0
(W/R)
7-bit Address
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
R
F
1
44h
45h
46h
47h
20h
21h
22h
23h
10h
11h
12h
13h
Ch
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
Dh
1
Eh
1
Fh
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7.5.3 TUSB1004 I2C Target Behavior
Register O set
Target Address
Data wri en
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Start
Ack
Write
图7-2. I2C Write with Data
The following procedure should be followed to write data to TUSB1004 I2C registers (refer to 图7-2):
1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB1004 acknowledges the address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data,
MSB-first.
4. The TUSB1004 acknowledges the sub-address cycle.
5. The controller presents the first byte of data to be written to the I2C register.
6. The TUSB1004 acknowledges the byte transfer.
7. The controller may continue presenting additional bytes of data to be written, with each byte transfer
completing with an acknowledge from the TUSB1004.
8. The controller terminates the write operation by generating a stop condition (P).
Data from o set 0x00
or
Target Address
last read address + 1
S
A6
A5
A4
A3
A2
A1
A0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Start
Stop
Ack
Read
图7-3. I2C Read Without Repeated Start
The following procedure should be followed to read the TUSB1004 I2C registers without a repeated Start (refer
图7-3).
1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R”bit to indicate a read cycle.
2. The TUSB1004 acknowledges the 7-bit address cycle.
3. Following the acknowledge the controller continues sending clock.
4. The TUSB1004 transmit the contents of the memory registers MSB-first starting at register 00h or last read
register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB1004 shall start at the
register offset specified in the write.
5. The TUSB1004 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB1004 transmits the next byte of data as long as controller provides the clock.
If a NAK is received, the TUSB1004 stops providing data and waits for a stop condition (P).
7. The controller terminates the write operation by generating a stop condition (P).
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Register O set Xh
Target Address
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
Sr
Start
Ack
Write
Repeated Start
Data from Register Xh
Target Address
Data from Register Xh + 1
P
S
A6
A5
A4
A3
A2
A1
A0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Stop
Read
图7-4. I2C Read with Repeated Start
The following procedure should be followed to read the TUSB1004 I2C registers with a repeated Start (refer 图
7-4).
1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB1004 acknowledges the 7-bit address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data,
MSB-first.
4. The TUSB1004 acknowledges the register offset cycle.
5. The controller presents a repeated start condition (Sr).
6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a one-value “W/R”bit to indicate a read cycle.
7. The TUSB1004 acknowledges the 7-bit address cycle.
8. The TUSB1004 transmit the contents of the memory registers MSB-first starting at the register offset.
9. The TUSB1004 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB1004 transmits the next byte of data as long as controller provides the clock.
If a NAK is received, the TUSB1004 stops providing data and waits for a stop condition (P).
11. The controller terminates the read operation by generating a stop condition (P).
Register O set
Target Address
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
P
Start
Ack
Write
Stop
图7-5. I2C Write Without Data
The following procedure should be followed for setting a starting sub-address for I2C reads (refer to 图7-5).
1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB1004 acknowledges the address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data,
MSB-first.
4. The TUSB1004 acknowledges the register offset cycle.
5. The controller terminates the write operation by generating a stop condition (P).
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备注
After initial power-up, if no register offset is included for the read procedure (refer to 图 7-3), then
reads start at register offset 00h and continue byte by byte through the registers until the I2C controller
terminates the read operation. During a read operation, the TUSB1004 auto-increments the I2C
internal register address of the last byte transferred independent of whether or not an ACK was
received from the I2C controller.
7.6 Register Map
7.6.1 TUSB1004 Registers
表 7-8 lists the memory-mapped registers for the TUSB1004 registers. All register offset addresses not listed in
表7-8 should be considered as reserved locations and the register contents should not be modified.
表7-8. TUSB1004 Registers
Offset Acronym
Register Name
Section
节7.6.1.1
节7.6.1.2
节7.6.1.3
节7.6.1.4
节7.6.1.5
节7.6.1.6
节7.6.1.7
节7.6.1.8
节7.6.1.9
节7.6.1.10
节7.6.1.11
节7.6.1.12
节7.6.1.13
节7.6.1.14
节7.6.1.15
节7.6.1.16
节7.6.1.17
节7.6.1.18
节7.6.1.19
8h
Ah
Rev_ID
Revision ID Register
General_1
General Register
Bh
TX1EQ_CTRL
TX2EQ_CTRL
USB_MODE
TX1 EQ Control
Ch
TX2 EQ Control
Dh
USB Mode control
1Ch
1Dh
1Eh
20h
21h
22h
24h
25h
32h
3Bh
3Ch
50h
51h
52h
AEQ_CONTROL1
AEQ_CONTROL2
AEQ_LONG
AEQ Controls
AEQ Controls
AEQ setting for Long channel
EQ control for CRX1 and CRX2 receivers
EQ Control for SSTX1 and SSTX2 receiver
Misc USB3 Controls
USBC_EQ
SS_EQ
USB3_MISC
USB1_STATUS
USB2_STATUS
VOD_CTRL
USB1 state machine status
USB2 state machine status
VOD Linearity and AEQ Controls
Full and Fast AEQ status
Full and Fast AEQ status
AEQ1_STATUS
AEQ2_STATUS
AEQ_CONTROL_AUX1
AEQ_CONTROL_AUX2
AEQ_CONTROL_AUX3
Complex bit access types are encoded to fit into small table cells. 表 7-9 shows the codes that are used for
access types in this section.
表7-9. TUSB1004 Access Type Codes
Access Type
Code
Description
Read Type
H
H
R
Set or cleared by hardware
Read
R
RH
R
H
Read
Set or cleared by hardware
Write Type
W
W
Write
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表7-9. TUSB1004 Access Type Codes (continued)
Access Type
Code
Description
W1C
W
Write
1C
1 to clear
W1S
W
Write
1S
1 to set
WtoP
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 Rev_ID Register (Offset = 8h) [Reset = 01h]
Rev_ID is shown in 表7-10.
Return to the 表7-8.
表7-10. Rev_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
REVISION_ID
RH
1h
Device Revision
7.6.1.2 General_1 Register (Offset = Ah) [Reset = 00h]
General_1 is shown in 表7-11.
Return to the 表7-8.
This register is used to enable USB. Software should set EQ_OVERRIDE bit in order for EQ registers to be used
instead of pins.
表7-11. General_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SSRX_LIMIT_ENABLE
R/W
0h
Limited redriver mode enable for SSRX transmitter.
0h = Linear Redriver
1h = Limited Redriver
6
5
4
RESERVED
R
0h
0h
0h
Reserved
Reserved
RESERVED
R
EQ_OVERRIDE
R/W
Setting this field will allow software to use EQ settings from registers
instead of value sampled from pins.
0h = EQ settings based on sampled state of EQ pins.
1h = EQ settings based on programmed value of each of the EQ
registers.
3
2
RESERVED
RESERVED
CTLSEL
R
0h
0h
0h
Reserved
Reserved
R/W
R/W
1-0
Controls whether USB is enabled or not. Program USB_MODE field
before enabling USB operation.
0h = Disabled
1h = USB enabled.
2h = Disabled
3h = USB enabled
7.6.1.3 TX1EQ_CTRL Register (Offset = Bh) [Reset = 6Fh]
TX1EQ_CTRL is shown in 表7-12.
Return to the 表7-8.
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This register controls the pre-shoot and de-emphasis levels for SSRX1 when limited redriver mode is enabled.
表7-12. TX1EQ_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SSRX1_PRESHOOT
R/W
1h
SSRX1 TX preshoot level (pre-cursor).
0h = 1.5 dB
1h = 2 dB
2h = 2.3 dB
3h = 2.8 dB
5
SSRX1_PRESHOOT_EN R/W
1h
1h
SSRX1 TX preshoot (pre-cursor) enabled. Valid only when
SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0 dB)
1h = Enabled
4-3
SSRX1_DEEMPHASIS
R/W
SSRX1 TX de-emphasis level (post-cursor)
0h = -1.5 dB
1h = -2.1 dB
2h = -3.2 dB
3h = -3.8 dB
2
SSRX1_DEEMPHASIS_E R/W
N
1h
3h
SSRX1 TX de-emphasis (post-cursor) enable. Valid only when
SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0 dB)
1h = Enabled
1-0
RESERVED
R/W
Reserved
7.6.1.4 TX2EQ_CTRL Register (Offset = Ch) [Reset = 6Ch]
TX2EQ_CTRL is shown in 表7-13.
Return to the 表7-8.
This register controls the pre-shoot and de-emphasis levels for SSRX2 when limited redriver mode is enabled.
表7-13. TX2EQ_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SSRX2_PRESHOOT
R/W
1h
SSRX2 TX preshoot level (pre-cursor).
0h = 1.5 dB
1h = 2 dB
2h = 2.3 dB
3h = 2.8 dB
5
SSRX2_PRESHOOT_EN R/W
1h
1h
SSRX2 TX preshoot (pre-cursor) enabled. Valid only when
SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0 dB)
1h = Enabled
4-3
SSRX2_DEEMPHASIS
R/W
SSRX2 TX de-emphasis level (post-cursor)
0h = -1.5 dB
1h = -2.1 dB
2h = -3.2 dB
3h = -3.8 dB
2
SSRX2_DEEMPHASIS_E R/W
N
1h
0h
SSRX2 TX de-emphasis (post-cursor) enable. Valid only when
SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0 dB)
1h = Enabled
1-0
RESERVED
R
Reserved
7.6.1.5 USB_MODE Register (Offset = Dh) [Reset = 02h]
USB_MODE is shown in 表7-14.
Return to the 表7-8.
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Selects the USB mode of operation
表7-14. USB_MODE Register Field Descriptions
Bit
7-3
2
Field
Type
Reset
Description
RESERVED
PCIE_EN
R
0h
Reserved
R/W
0h
Controls whether or not PCIE is enabled.
0h = PCIe Disabled.
1h = PCIe Eabled.
1
0
RESERVED
USB_MODE
RH/W
R/W
1h
0h
Reserved
During initalization, software must program this field to 1 to enable
both lanes 1 and 2 for USB operation.
7.6.1.6 AEQ_CONTROL1 Register (Offset = 1Ch) [Reset = 85h]
AEQ_CONTROL1 is shown in 表7-15.
Return to the 表7-8.
This register is used to enable adaptive EQ and select between Fast and Full adaptive EQ.
表7-15. AEQ_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FULLAEQ_UPPER_EQ
R/W
8h
This field sets the maximum EQ value to check for full AEQ mode
when in I2C mode.
3
USB3_U1_DISABLE
AEQ_MODE
R/W
R/W
0h
2h
This field when set will cause entry to U3 instead of U1 when
electrical idle is detected.
0h = U1 entry after electrical idle.
1h = U3 entry after electrical idle.
2-1
Selects Adaption mode (Fast, or one of three Full modes).
0h = Fast AEQ.
1h = Full AEQ, with hits counted at mideye for every EQ iteration
(using current EQ setting).
2h = Full AEQ, algorithm II.
3h = Full AEQ, with hits counted at mideye only for first EQ iteration
(using EQ set to the MID_HC_EQ value).
0
AEQ_EN
R/W
1h
Controls whether or not adaptive EQ for USB downstream facing
port is enabled.
0h = AEQ disabled
1h = AEQ enabled
7.6.1.7 AEQ_CONTROL2 Register (Offset = 1Dh) [Reset = 10h]
AEQ_CONTROL2 is shown in 表7-16.
Return to the 表7-8.
This register allows for controls for the Fast AEQ limits as well as adding or reducing final EQ value used by the
Full AEQ function.
表7-16. AEQ_CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OVER_EQ_SIGN
R/W
0h
Selects the sign for OVER_EQ_CTRL field.
0h = positive
1h = negative
6
RESERVED
R
0h
Reserved
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表7-16. AEQ_CONTROL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-3
FASTAEQ_LIMITS
R/W
2h
Selects the upper/lower limits of DAC for determining short vs long
channel.
0h = ± 0 mV
1h = ± 40 mV
2h = ± 80 mV
3h = ± 120 mV
4h = ± 160 mV
5h = ± 200 mV
6h = ± 240 mV
7h = ± 280 mV
2-0
OVER_EQ_CTRL
R/W
0h
This field will increase or decrease the AEQ by value programmed
into this field. For example, full AEQ value is 6 and this field is
programmed to 2 and OVER_EQ_SIGN = 0, then EQ value used will
be 8. This field is only used in Full AEQ mode.
0h = 0 or -8
1h = 1 or -7
2h = 2 or -6
3h = 3 or -5
4h = 4 or -4
5h = 5 or -3
6h = 6 or -2
7h = 7 or -1
7.6.1.8 AEQ_LONG Register (Offset = 1Eh) [Reset = 77h]
AEQ_LONG is shown in 表7-17.
Return to the 表7-8.
This register is used to program the EQ used for long channel setting when Fast AEQ is enabled.
表7-17. AEQ_LONG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LONG_CEQ2
R/W
7h
When AEQ_EN = 1 and AEQ_MODE = x0 (i.e., Fast), selects EQ
setting for USB connector port2 (CRX2) when long channel is
detected. The user should program this field with the value that
provides the best Rx JTOL results for a long channel configuration.
3-0
LONG_CEQ1
R/W
7h
When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for
USB connector port1 (CRX1) when long channel is detected. The
user should program this field with the value that provides the best
Rx JTOL results for a long channel configuration.
7.6.1.9 USBC_EQ Register (Offset = 20h) [Reset = 00h]
USBC_EQ is shown in 表7-18.
Return to the 表7-8.
This register controls the receiver equalization setting for the connector receiver (CRX1 and CRX2).
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表7-18. USBC_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CEQ2_SEL
RH/W
0h
If AEQ_EN = 0, this field selects EQ for USB CRX2 receiver which
faces the USB-C™ receptacle. When EQ_OVERRIDE = 0b, this field
reflects the sampled state of CEQ[1:0] pins. When EQ_OVERRIDE =
1b, software can change the EQ setting for CRX2p/n pins based on
value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0,
selects EQ setting for USB connector port2 (CRX2) when short
channel is detected. The user should program this field with the
value that provides the best Rx JTOL results for a short channel
configuration.
3-0
CEQ1_SEL
RH/W
0h
If AEQ_EN = 0, this field selects EQ for USB CRX1 receiver which
faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field
reflects the sampled state of CEQ[1:0] pins. When EQ_OVERRIDE =
1b, software can change the EQ setting for CRX1p/n pins based on
value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0,
selects EQ setting for USB connector port1 (CRX1) when short
channel is detected. The user should program this field with the
value that provides the best Rx JTOL results for a short channel
configuration.
7.6.1.10 SS_EQ Register (Offset = 21h) [Reset = 00h]
SS_EQ is shown in 表7-19.
Return to the 表7-8.
This register controls the receiver equalization setting for the SSTX1 and SSTX2.
表7-19. SS_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SSEQ2_SEL
RH/W
0h
This field selects EQ for USB3 SSTX2 receiver which faces the USB
host. When EQ_OVERRIDE = 0b, this field reflects the sampled
state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can
change the EQ setting for SSTX2p/n pins based on value written to
this field.
3-0
SSEQ1_SEL
RH/W
0h
This field selects EQ for USB SSTX1 receiver which faces the USB
host. When EQ_OVERRIDE = 0b, this field reflects the sampled
state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can
change the EQ setting for SSTX1p/n pins based on value written to
this field.
7.6.1.11 USB3_MISC Register (Offset = 22h) [Reset = 04h]
USB3_MISC is shown in 表7-20.
Return to the 表7-8.
表7-20. USB3_MISC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RXD_START_TERM
R/W
0h
Termination setting at start of RX detection following warm reset and
at entry to SS.Inactive.
0h = Maintain termination.
1h = Turn off termination. Avoid compliance failures due to race
between local and remote rxd in case of disconnect. If connection
remains next state was polling regardless.
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表7-20. USB3_MISC Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-5
U23_RXDET_INTERVAL R/W
0h
This field controls the Rx.Detect interval for the downstream facing
port (CTX1P/N and CTX2P/N) when in U2/U3.
0h = 48 ms
1h = 84 ms
2h = 120 ms
3h = 156 ms
4
DISABLE_U2U3_RXDET R/W
DFP_RXDET_INTERVAL R/W
0h
1h
Controls whether or not Rx.Detect is performed in U2/U3 state.
0h = Rx.Detect in U2/U3 enabled.
1h = Rx.Detect in U2/U3 disabled.
3-2
This field controls the Rx.Detect interval for the downstream facing
port (CTX1P/N and CTX2P/N).
0h = 4 ms
1h = 6 ms
2h = 36 ms
3h = 84 ms
1
0
DIS_WARM_RESET_RXD R/W
0h
0h
Disables receiver detection following warm reset if device starts
polling during warm reset.
0h = whether receiver detection is done following warm reset
depends on other settings.
1h = if USB FSM detects that device started polling during warm
reset, it will not do receiver detection.
USB_COMPLIANCE_CTR R/W
L
Controls whether compliance mode detection is determined by FSM
or disabled
0h = Compliance mode determined by FSM.
1h = Compliance mode disabled.
7.6.1.12 USB1_STATUS Register (Offset = 24h) [Reset = 01h]
USB1_STATUS is shown in 表7-21.
Return to the 表7-8.
表7-21. USB1_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
USB1_FASTAEQ_STAT
RH
0h
When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates
whether short or long EQ setting is used. When AEQ_EN = 0, this
field will always default to 0h.
0h = Short channel EQ used.
1h = Long channel EQ used.
6
5
4
3
RESERVED
RESERVED
RESERVED
CM_ACTIVE1
RH/W1C
RH
0h
0h
0h
0h
Reserved
Reserved
Reserved
RH
RH
Compliance mode status.
0h = Not in USB3.1 compliance mode.
1h = In USB3.1 compliance mode.
2
1
0
U0_STAT1
RH
RH
RH
0h
0h
1h
U0 Status. Set if enters U0 state.
U2U3_STAT1
DISC_STAT1
U2/U3 Status. Set if enters U2/U3 state.
Disconnect Status. Set if enters Disconnect state.
7.6.1.13 USB2_STATUS Register (Offset = 25h) [Reset = 01h]
USB2_STATUS is shown in 表7-22.
Return to the 表7-8.
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表7-22. USB2_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
USB2_FASTAEQ_STAT
RH
0h
When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates
whether short or long EQ setting is used. When AEQ_EN = 0, this
field will always default to 0h.
0h = Short channel EQ used.
1h = Long channel EQ used.
6
5
4
3
RESERVED
RESERVED
RESERVED
CM_ACTIVE2
RH/W1C
RH
0h
0h
0h
0h
Reserved
Reserved
Reserved
RH
RH
Compliance mode status.
0h = Not in USB3.1 compliance mode.
1h = In USB3.1 compliance mode.
2
1
0
U0_STAT2
RH
RH
RH
0h
0h
1h
U0 Status. Set if enters U0 state.
U2U3_STAT2
DISC_STAT2
U2/U3 Status. Set if enters U2/U3 state.
Disconnect Status. Set if enters Disconnect state.
7.6.1.14 VOD_CTRL Register (Offset = 32h) [Reset = C0h]
VOD_CTRL is shown in 表7-23.
Return to the 表7-8.
This register controls the transmitters output linearity range for both UFP and DFP. When device is configured for
limited redriver (SSRX_LIMIT_ENABLE field is set), USB_SSRX_VOD controls the VOD level for SSRX limited
driver.
表7-23. VOD_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
LFPS_VOD
R/W
3h
VOD linearity control for SSRX1, SSRX2, CTX1, and CTX2 when
LFPS is being transmitted.
0h = LINR_L3 (highest)
1h = LINR_L2
2h = LINR_L1
3h = LINR_L0 (lowest)
5-4
3-2
RESERVED
R
0h
0h
Reserved
USB_CTX12_VOD
R/W
VOD linearity control for USB connector facing ports (CTX1 and
CTX2).
0h = LINR_L3 (highest)
1h = LINR_L2
2h = LINR_L1
3h = LINR_L0 (lowest)
1-0
USB_SSRX12_VOD
R/W
0h
VOD linearity control for USB upstream facing port (SSRX1/2). When
SSRX_LIMIT_ENABLE = 1, then this field controls the limited VOD
for SSRX.
0h = LINR_L3 (highest)
1h = LINR_L2
2h = LINR_L1
3h = LINR_L0 (lowest)
7.6.1.15 AEQ1_STATUS Register (Offset = 3Bh) [Reset = 00h]
AEQ1_STATUS is shown in 表7-24.
Return to the 表7-8.
This register provides the status of AEQ function.
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表7-24. AEQ1_STATUS Register Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
Reserved
Reserved
RESERVED
R
0h
RESERVED
RH
RH
0h
3-0
AEQ1_EQ_STAT
0h
Optimal EQ determined by FSM after the completion of Full AEQ.
This field will also indicate EQ used for Fast AEQ. This field will
include the value programmed into OVER_EQ_CTRL field.
7.6.1.16 AEQ2_STATUS Register (Offset = 3Ch) [Reset = 00h]
AEQ2_STATUS is shown in 表7-25.
Return to the 表7-8.
This register provides the status of AEQ function.
表7-25. AEQ2_STATUS Register Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
RESERVED
RESERVED
AEQ2_EQ_STAT
R
0h
Reserved
RH
RH
0h
0h
Reserved
3-0
Optimal EQ determined by FSM after the completion of Full AEQ.
This field will also indicate EQ used for Fast AEQ. This field will
include the value programmed into OVER_EQ_CTRL field.
7.6.1.17 AEQ_CONTROL_AUX1 Register (Offset = 50h) [Reset = 00h]
AEQ_CONTROL_AUX1 is shown in 表7-26.
Return to the 表7-8.
表7-26. AEQ_CONTROL_AUX1 Register Field Descriptions
Bit
7-6
5-2
1-0
Field
Type
Reset
Description
Reserved
Reserved
Reserved
RESERVED
RESERVED
RESERVED
R
0h
R
0h
R
0h
7.6.1.18 AEQ_CONTROL_AUX2 Register (Offset = 51h) [Reset = 07h]
AEQ_CONTROL_AUX2 is shown in 表7-27.
Return to the 表7-8.
表7-27. AEQ_CONTROL_AUX2 Register Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
RESERVED
EQ_MERGE
R
0h
Reserved
R/W
0h
Initial EQ result merge control. This field controls how the EQ results
from the positive and negative VOD offsets steps are merged to
produce the initial EQ value. This field is applicable only when the
AEQ_MODE field is set to 2'b10.
0h = Use max of pos/neg VOD EQs
1h = Use min of pos/neg VOD EQs
3-0
MID_HC_EQ
R/W
7h
Sets EQ value during the mid-eye hit-count capture step. This field is
applicable only when the AEQ_MODE field is set to 2'b10 or 2'b11.
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7.6.1.19 AEQ_CONTROL_AUX3 Register (Offset = 52h) [Reset = 86h]
AEQ_CONTROL_AUX3 is shown in 表7-28.
Return to the 表7-8.
表7-28. AEQ_CONTROL_AUX3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
HC_EQ_THR
R/W
4h
Sets the hit-count threshold during the EQ search steps. The
algorithm will find the minimum EQ setting such that the hit-count is
at or above value N_eq, where: N_eq = HC_me * (128-
HC_EQ_THR)/128 and HC_me is the mid-eye hit-count. This field is
applicable only when the AEQ_MODE field is set to 2'b10.
4
RESERVED
R
0h
6h
Reserved
3-0
HC_VOD_THR
R/W
Sets the hit-count threshold during the VOD search steps. The
algorithm will find the maximum DAC VOD setting such that the hit-
count is at or above the threshold value N_vod, where: N_vod =
HC_me * HC_VOD_THR/128 and HC_me is the mid-eye hit-count.
This field is applicable only when the AEQ_MODE field is set to
2'b10.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TUSB1004 is a linear redriver designed specifically to compensate for intersymbol interference (ISI) jitter
causes by signal attenuation through a passive medium like PCB traces or cables. Placing the TUSB1004
between the USB connector and a USB 3.2 host, hub, and device can correct signal integrity issues resulting in
a more robust system.
9 Typical Application
A
B
C
D
PCB Trace of Length XAB
PCB Trace of Length XCD
CAC-USB1
SSTX2P
SSTX2N
SSRX2P
CAC-USB1
RESD
CTX2P
SSRX2N
CTX2N
CRX2P
CRX2N
Optional
CAC-USB2
LAC-CAP
USB3.2
Host
LESD
TUSB1004
LAC-CAP
CAC-USB1
SSTX1N
CAC-USB1
SSTX1P
SSRX1N
SSRX1P
RESD
CTX1N
CTX1P
CRX1N
CRX1P
Optional
CAC-USB2
LR_ESD
PCB Trace of Length XCE
C
E
图9-1. Typical USB Host Application
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10 Design Requirements
For this design example, use the parameters shown in 表10-1.
表10-1. Design Parameters
PARAMETER
VALUE
10 Gbps USB 3.2 pre-channel A to B PCB trace length, XAB
.
2 inches <= XAB <= 12 inches -
MAX(XCD or XCE
)
Refer to 图9-1.
10 Gbps USB post-channel C to D PCB trace length, XCD and
up to 4 inches
XCE. Refer to 图9-1.
Minimum distance of the AC capacitors from TUSB1004, LAC-
0.4 inches
1.0 inches
0.25 inches
CAP
Maximum distance of ESD component from the USB
receptacle, LESD
Maximum distance of series resistor (RESD) from ESD
component, LR_ESD
.
CAC-USB1 AC-coupling capacitor (75 nF to 265 nF)
CAC-USB2 AC-coupling capacitor (297 nF to 363 nF)
220 nF
Options:
•
•
RX1 and RX2 are DC-coupled to
USB receptacle
330 nF AC-couple with RRX resistor
No used
Optional RRX resistor (220-kΩ± 5%)
RESD (0-Ω to 2.2-Ω)
1-Ω
VCC supply (3-V to 3.6-V)
I2C Mode or Pin-strap Mode
1.8-V or 3.3-V I2C Interface
3.3-V
Pin-strap mode (MODE = "0")
3.3-V I2C. VIO_SEL pin to Float "F".
11 Detailed Design Procedure
A typical usage of the TUSB1004 device is shown in 图 11-1. The device can be configured either through its
GPIO pins (SSEQ[1:0] and CEQ[1:0] pins) or through its I2C interface. In the example shown below, the
TUSB1004 is configured in pin-strap mode with adaptive EQ (AEQ) enabled. The MODE pin is pull-down to
GND through a 1-kΩ resistor. The AEQENZ is pull-down to GND which will enable AEQ for CRX1 and CRX2
receivers. Because AEQ is enabled, CEQ[1:0] pins can be left floating. The SSEQ[1:0] in this example is also
floating but they need to configured to match the loss of the pre-channel (XAB).
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3.3V
100nF
100nF
100nF
10mF
100nF
USB 3.2 Host
9
SSTXP
CAC-USB1
CAC-USB1
8
RESD
SSTXN
CTX2P
SSTX2P
SSTX2N
SSTX2P
SSTX2N
7
GND
CTX2N
6
SSRXP
RESD
5
SSRX2P
SSRX2N
CRX2P
CRX2N
SSRX2P
SSRX2N
SSRXN
4
GND
CAC-USB2
3
CAC-USB1
RRX
DP
SSTX1P
SSTX1N
SSTX1P
SSTX1N
2
DM
Optional
1
VBUS
Optional
SSRX1P
SSRX1N
SSRX1P
SSRX1N
GPIO0
9
SLP_S0#
SSTXP
CAC-USB1
RESD
8
TESTOUT1
TESTOUT2
CTX1P
CTX1N
SSTXN
7
GND
RESD
6
SSRXP
CRX1P
CRX1N
5
SSRXN
CAC-USB2
4
3.3V
DNI
1-kQ
GND
RRX
Optional
3
MODE
DP
MODE
MODE
SSEQ0
2
SSEQ0
SSEQ1
DM
SSEQ0/A0
SSEQ1/A1
CEQ0
Optional
1
VBUS
3.3V
3.3V
CEQ0
CEQ1
DNI
DNI
DNI
DNI
TEST2/SCL
AEQENZ/SDA
EN
SSEQ1
CEQ1
AEQENZ
AEQCFG
EQCFG
AEQCFG
EQCFG
VIO_SEL
TEST1
CEN
3.3V
3.3V
VIO_SEL
TEST1
DNI
DNI
DNI
DNI
CEQ0
CEQ1
TP
TUSB1004
3.3V
3.3V
3.3V
3.3V
3.3V
10-kQ
DNI
DNI
DNI
DNI
DNI
DNI
DNI
AEQENZ
AEQCFG
EQCFG
VIO_SEL
TEST1
DNI = DO NOT INSTALL
1-kQ
图11-1. Application Circuit
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11.1 USB SSTX1/2 Receiver Configuration
Configuring the TUSB1004 involves understanding the insertion loss (SDD21) of the pre-channel (XAB). The
TUSB1004's SSEQ[1:0] pins if pin-strap mode, or if I2C mode, SSEQ2_SEL and SSEQ1_SEL registers should
be set to the level of the pre-channel insertion loss at 5 GHz. A good rule for FR4 trace insertion loss at 5 GHz is
≈-1 dB per inch. Using this rule, if the pre-channel for USB (XAB) is 8-inches, the TUSB1004 SSEQ should be
programmed to -8 dB.
11.2 USB CRX1/2 Receiver Configuration
11.2.1 Fixed Equalization
In Fixed EQ operation, a single EQ setting is used for all possible devices inserted into the USB receptacle (with
or without an USB cable). It is recommended to set TUSB1004 CEQ[1:0] pins if pin-strap mode, or CEQ1_SEL
and CEQ2_SEL if I2C mode to about 4 db to 5 dB greater than loss of the post channel (XCD). For example, if
post channel is 0.5 inches, then assuming -1 dB per inch at 5 GHz, CEQ1_SEL and CEQ2_SEL should be
programmed to 4.5 to 5.5 dB. It is recommended to perform USB 3.1 Rx JTOL long and short channel tests to
optimize the setting. Depending of the USB 3.2 Host, a single EQ setting which satisfies both the long and short
channel tests may not be possible. If this is the case, then it is recommended to use AEQ mode.
11.2.2 Full Adaptive Equalization
In Full AEQ mode, the TUSB1004 will determine the best settings regardless if the channel is short, long or
somewhere in between. In pin-strap mode, the Full AEQ is enabled based on the state of AEQENZ pin. In I2C
mode, the Full AEQ feature is enabled by default. Full AEQ is enabled when AEQ_MODE = 1, 2, or 3, and
AEQ_EN = 0x1.
11.2.3 Fast Adaptive Equalization
Fast Adaptive EQ will distinguish between a short and long channel and select a pre-determined EQ setting
based on which channel is detected. Fast AEQ is available only I2C mode. Fast AEQ is enabled when
AEQ_MODE = 0 and AEQ_EN = 1.
The EQ setting used for short channel should be programmed into CEQ1_SEL and CEQ2_SEL registers. It is
recommended to program these registers about 1 dB to 2 dB more than the loss of post channel (XCD). For
example, if post channel is 0.5 inches, then assuming -1dB insertion loss per inch at 5 GHz, CEQ1_SEL and
CEQ2_SEL should be programmed to 1.5 to 2.5 dB. It is recommended to perform USB 3.2 Rx JTOL Short
channel test to find the optimal short channel setting.
The EQ setting used for long channel should be programmed into LONG_CEQ1 and LONG_CEQ2. It is
recommended to program these registers about 4 to 5 dB more than the loss of post channel (XCD). For
example, if post channel is 0.5 inches, then assuming -1 dB per inch at 5 GHz, LONG_CEQ1 and LONG_CEQ2
should be programmed to 4.5 to 5.5 dB. It is recommended to perform USB 3.2 Rx JTOL Long channel test to
find the optimal long channel setting.
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12 Application Curves
图12-1. 10 Gbps Input Eye At SSTX1
After 12.5 dB at 5 GHz Pre-channel
图12-2. 10 Gbps Output Eye at CTX1
After 1.2 dB at 5 GHz Post-Channel
13 Power Supply Recommendations
The TUSB1004 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1 μF de-coupling capacitor should be used on each power pin. The de-coupling capacitor
should be placed close as possible to the power pin. It is also recommended to have a single bulk capacitor of 1
μF to 10 μF.
14 Layout
14.1 Layout Guidelines
1. SSTX1P/N, SSRX1P/N, SSTX2P/N, SSRX2P/N, CRX1P/N, CRX2PN, CTX1P/N, and CTX2P/N pairs should
be routed with controlled 90-Ωdifferential impedance (±10%).
2. There is no inter-pair length match requirement.
3. Keep away from other high speed signals.
4. Intra-pair routing (between P and N) should be kept to less than 5 mils.
5. Length matching should be near the location of mismatch.
6. Each pair should be separated at least by 3 times the signal trace width.
7. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥135 degrees.
This will minimize any length mismatch caused by the bends and therefore minimize the impact bends have
on EMI.
8. Route all differential pairs on the same of layer.
9. The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.
10. Keep traces on layers adjacent to ground plane.
11. Do not route differential pairs over any plane split.
12. Adding test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
13. Highly recommended to have reference plane void under USB-C receptacle's super speed pins to minimize
the capacitance effect of the receptacle.
14. Highly recommended to have reference plane void under the AC-coupling capacitances.
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14.2 Layout Example
GND
1
9
40
CTX2p/n
SSTX2p/n
SSRX2p/n
CEQ0
CRX2p/n
CTX1n/p
VIO_SEL
SSEQ0/A0
GND
SSTX1p/n
SSRX1p/n
MODE
CRX1n/p
GND
CEQ1
20
29
VCC
GND
图14-1. Layout Example
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15 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
15.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
15.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
15.3 Trademarks
USB-C™ is a trademark of Universal Serial Bus Implementers Forum.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
15.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
15.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
16 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB1004IRNQR
TUSB1004IRNQT
TUSB1004RNQR
TUSB1004RNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
TSB04
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TSB04
TSB04
TSB04
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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