TUSB2E111YCGR [TI]
USB 2.0-eUSB2 单端口中继器 | YCG | 15 | -20 to 85;
| 型号： | TUSB2E111YCGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB 2.0-eUSB2 单端口中继器 | YCG | 15 | -20 to 85 中继器 |
| 文件： | 总56页 (文件大小：2001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSB2E11
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
TUSB2E11 USB 2.0-eUSB2 中继器
1 特性
3 说明
• 兼容USB 2.0 和eUSB2（1.2 版）
• 低速、全速、高速信令
TUSB2E11 是一款支持器件和主机模式的 USB 兼容
eUSB2 至USB 2.0 中继器。
• 20ps 卓越高速总抖动
器件支持 USB 低速 (LS)、全速 (FS) 和高速 (HS) 信
号。
• 寄存器访问协议接收器功能
• 支持主机和器件模式（双重角色器件）
• 自动检测I2C 或自举引脚选项
该器件采用多项专利设计，可提供强大的互操作性、性
能和电源。
– 用于USB 2.0 高速通道补偿设置的三个自举引
脚
– I2C 器件接口支持更多配置
对于没有 I2C 接口的系统，该器件提供 8 个单独的设
置，带有三个适用于高达 20Ω的USB 2.0 通道等效串
联电阻(ESR) 的自举引脚。器件变体可用于高达 10 英
寸的不同级别的eUSB2 布线长度补偿。
• 器件变体
– eUSB2 1.0V 或1.2V 信令接口
– 适用于不同产品外形尺寸的eUSB2 布线损耗补
偿水平
– 1.2V 或1.8V I2C 接口
I2C 接口可提高灵活性，支持微调器件的 RX 均衡性和
TX 振幅、压摆率和预加重，以便通过电气合规性测试
并补偿通道损耗。
• 支持可选电池充电和检测
– BC 1.2 CDP 或DCP 分频器模式广播
– 数据感知USB Type-C™ 兼容BC 1.2 SDP、
CDP 和DCP 分频器模式检测
可通过 3 个 GPIO 引脚提供各种调试选项，这些引脚
可配置来监控各种 USB 总线状态或中断，以及提供
SoC 调试功能的 CTA-936 UART 模式。GPIO0 和
GPIO1 可用作通用I2C 至GPIO 桥接器件。
– 充电器广播或检测之间的双重角色自动切换
• 支持CTA-936 USB Carkit UART
• 支持自动恢复ECR 以及L2 中断恢复模式
• 可选GPIO：中断GPIO2、调试、I2C ↔ GPIO0/1
• I2C 可访问调试功能适用于制造测试
器件信息(1)
封装尺寸（标称值）
器件型号
TUSB2E11
封装
DSBGA (15)
1.30 mm × 2.00 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 笔记本电脑和台式机
• 手机
• 平板电脑
• 可穿戴设备
• 便携式电子产品
Connector
I2C
Repeater
UART
Target Level shifter Controller/detector
I2C
BC 1.2
GPIO
Port
protection
(optional)
AP
USB
USB
RESETB
eUSB2
eUSB2 œ USB 2.0
Repeater
VDD3V3
VDD1V8
VSS
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFI4
TUSB2E11
www.ti.com.cn
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
Table of Contents
8.6 I2C Target Interface...................................................30
9 Register Access Protocol (RAP)..................................32
10 Register Map................................................................33
10.1 TUSB2E11 Registers..............................................33
11 Application and Implementation................................ 45
11.1 Application Information............................................45
11.2 Typical Application.................................................. 45
12 Power Supply Recommendations..............................49
12.1 Power Up Reset......................................................49
13 Layout...........................................................................49
13.1 Layout Guidelines................................................... 49
13.2 Example Layout for Application with 1.8 V I2C
Variant......................................................................... 50
14 Device and Documentation Support..........................51
14.1 Device Support....................................................... 51
14.2 Documentation Support.......................................... 51
14.3 接收文档更新通知................................................... 51
14.4 支持资源..................................................................51
14.5 Trademarks.............................................................51
14.6 Electrostatic Discharge Caution..............................51
14.7 术语表..................................................................... 51
15 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Version Comparison...........................................3
5.1 Device Variants...........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 9
7.1 Absolute Maximum Ratings........................................ 9
7.2 ESD Ratings............................................................... 9
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information..................................................10
7.5 Electrical Characteristics...........................................10
7.6 Switching Characteristics..........................................17
7.7 Timing Requirements................................................19
7.8 Typical Characteristics..............................................21
7.9 Parameter Measurement Information....................... 22
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................24
8.4 Device Functional Modes..........................................24
8.5 Manufacturing Test Modes........................................28
Information.................................................................... 51
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2021) to Revision A (June 2022)
Page
• 首次公开发布数据表........................................................................................................................................... 1
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5 Device Version Comparison
表5-1. Device Register Comparison Table
Register Address
B0 default
0x73h
0x38h
0x90h
0x04h
0x00h
0x0Bh
0x40h
0x02h
0x02h
0x00h
0x00h
0x00h
0xC0h
0x00h
0x32h
B1 default
0x7Ch
0x3Ch
0x92h
0x83h
0x00h
0x0Bh
0x60h
0x02h
0x03h
0x00h
0x00h
0x00h
0xC0h
0x00h
0x32h
0x70h
0x71h
0x72h
0x73h
0x77h
0x78h
0x79h
0x50h
0xB0h
0xB2h
0xB3h
0xB4h
0xB6h
0x60h
0xF5h
表10-5
表10-6
表10-7
表10-8
表10-9
表10-10
表10-11
表10-12
表10-13
表10-14
表10-15
表10-16
表10-17
表10-21
表10-22
表5-2. Device Feature Comparison Table
Features
B0
B1
Low Power Mode (RESETB = low)
Auto-resume ECR
not supported
not supported
supported (9 µW)
supported (enabled by default) [see register
0x78h]
L2 State Interrupt Resume
supported
supported
5.1 Device Variants
For more information and availability of device variants such as eUSB2 1.0 signaling interface, 1.2 V I2C
interface, and 1.2 V GPIO interface please contact support.
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6 Pin Configuration and Functions
1
2
3
eDP
eDN
VSS
A
B
C
D
E
GPIO0
GPIO1
RESETB
DP
VDD3V3
GPIO2
VDD1V8
DN
SDA
SCL
VSS
VDD1V8
RESETB
USB
eUSB2
GND
I/O
VDD1V8
VDD3V3
图6-1. TUSB2E11 YCG Package, 15-Pin DSBGA (Top View)
表6-1. Pin Functions
PIN
TYPE(2)
REST
STATE
ASSOCIATED ESD
SUPPLY
DESCRIPTION
NAME
VDD3V3
VDD1V8
VSS
NO.
B2
PWR
PWR
GND
N/A
N/A
N/A
N/A
3.3 V Supply Voltage
1.8 V Supply Voltage
GND
D2, E3
A3, D3
N/A
N/A
•
•
Active Low Reset
Upon de-assertion of RESETB, repeater will be enabled and be
in eUSB2 default mode awaiting configuration from eDSPr or
eUSPr.
RESETB
D1
I
N/A
VDD1V8
•
If RESETB is not actively controlled, a pull-up resistor 100 kΩ
to VDD1V8 is required.
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表6-1. Pin Functions (continued)
ASSOCIATED ESD
SUPPLY
PIN
TYPE(2)
REST
STATE
DESCRIPTION
NAME
NO.
Internal
SCL
SDA
Mode
pulldown 1
MΩtypical
(disabled
Low
Non-I2C
USB
Repeater
See 表6-4 for more
details
SCL
C3
I
VDD1V8
VDD1V8
I2C Clock
after reset)(1)
Device
Mode
Matrix
Bidirectional
12C data
Open drain
I/O
High
Low
Non-I2C
UART
mode
SDA
B3
I/O
Hi-Z(1)
Repeater
High
High
I2C
Enabled
•
In I2C mode GPIO2 will be an open drain active low level
interrupt output. Connect GPIO2 to input of APU and a pull-up
resistor to use interrupt features
Internal
•
•
•
In non I2C mode GPIO2 defaults to USB configuration input at
pulldown 1
MΩtypical
(disabled
after reset)
power up reset.
GPIO2
C2
I/O
VDD1V8
When a pull-up resistor is used to set high input, ensure VIH is
met accounting for internal pull down as small as 500 kΩ
GPIO2 is an open-drain output after reset and can be left
floating when not used.
Defaults to an input mode at power up reset. RESETB assertion
and de-assertion or soft reset will revert GPIO0 to input mode
•
In I2C mode GPIO0 will default to control Carkit UART mode:
active low to enable Carkit UART mode. Default Carkit UART
direction is DP →eDP (RX) and eDN →DN (TX). GPIO0 must
be pulled up to be in USB repeater mode.
Internal
pulldown 1
MΩtypical
(disabled
GPIO0
B1
I/O
VDD1V8
•
•
In non I2C mode GPIO0 defaults to USB configuration input at
after reset)(1)
power up reset.
When a pull-up resistor is used to set high input, ensure VIH is
met accounting for internal pull down as small as 500 kΩ
Defaults to an input mode at power up reset. RESETB assertion
and de-assertion or soft reset will revert GPIO1 to input mode
Internal
•
•
In I2C mode GPIO1 defaults to debug input
In non I2C mode GPIO1 defaults to USB Configuration input at
pulldown 1
MΩtypical
(disabled
GPIO1
C1
I/O
VDD1V8
power up reset.
after reset)(1)
•
When a pull-up resistor is used to set high input, ensure VIH is
met accounting for internal pull down as small as 500 kΩ
eDN
eDP
DN
A2
A1
E2
E1
I/O
I/O
I/O
I/O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VDD1V8
VDD1V8
VDD3V3
VDD3V3
eUSB2 port D-
eUSB2 port D+
USB port D-
DP
USB port D+
(1) When configured as an input but not actively driven, use 1 MΩexternal pull-down to strap low.
(2) I = input, I/O = input or output, PWR= power, GND = ground
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GPIO2 (C2)
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
表6-2. Pin Configuration for Device Mode
Device Mode
SCL (C3)
SDA (B3)
GPIO0 (B1)
GPIO1 (C1)
Default to Input
Low = UART
Mode
•
•
Default to Open drain
output (can be left
floating when not
used)
Function can be
reconfigured through
register
Default to Input
Function can be
reconfigured through
register
Pull-up
Input sampled at
reset
Pull-up
Input sampled at
reset
High = USB
repeater mode
I2C Mode
Function can be
reconfigured through
register
Default to Input
•
Low = UART
Pull-up
Input sampled at
reset
Pull-down
Input sampled at
reset
transfer enabled
High-Z (can be left
floating)
High-Z (can be left
floating)
Non I2C UART mode
•
High = UART
transfer disabled
Pull-down
Input sampled at
reset
Non I2C USB
repeater mode
Default input sampled at reset.
See 表6-4
See 表6-3
See 表6-4
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表6-3. Pin Configuration for USB PHY Tuning without I2C
Equivalent
series
resistance
(ESR)
between
repeater
and USB
connector
U_HS_TX_ U_HS_TX_ U_SQUELC U_DISCON
U_EQ_P1 AMPLITUD PRE_EMPH H_THRESH NECT_THR
HS Term
setting
E_P1
setting
ASIS_P1
setting
OLD_P1
setting
ESHOLD_P
1 setting
GPIO2
GPIO1
GPIO0
dB
0.06
mV
840
dB
0.5
mV
104
mV
625
Ω
Ω
Float
Float
Float
Float
Float
Pull-Up
Float
2.5
45
(3’b000)
0.06
(4’b0101)
880
(3’b000)
0.9
(3’b100)
98
(4’b0101)
645
5
45
45
(3’b000)
0.58
(4’b0111)
900
(3’b001)
0.9
(3’b101)
98
(4’b0110)
645
Float
Pull-Up
Pull-Up
Float
7.5
10
(3’b001)
1.09
(4’b1000)
920
(3’b001)
0.9
(3’b101)
98
(4’b0110)
685
Float
Pull-Up
Float
45
(3’b010)
1.56
(4’b1001)
940
(3’b001)
1.2
(3’b101)
91
(4’b1000)
685
Pull-Up
Pull-Up
Pull-Up
Pull-Up
12.5
15
45
(3’b011)
2.26
(4’b1010)
980
(3’b010)
1.2
(3’b110)
91
(4’b1000)
685
Float
Pull-Up
Float
45
(3’b100)
2.67
(4’b1100)
1000
(3’b010)
1.7
(3’b110)
91
(4’b1000)
685
Pull-Up
Pull-Up
17.5
20
45
(3’b101)
2.67
(4’b1101)
1020
(3’b011)
1.7
(3’b110)
85
(4’b1000)
705
Pull-Up
42.75
(3’b101)
(4’b1110)
(3’b011)
(3’b111)
(4’b1001)
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表6-4. Pin Configuration for Battery Charging in non I2C Mode
Charger
Detection
Status
VBUS Control
Output
Repeater State
Device Mode
Peripheral
Repeater
{GPIO2,
GPIO1}
SCL (C3)
SDA (B3)
Un-configured Host Repeater
GPIO0
Input
•
•
2’b00: No
charger
detected
2’b01:
CDP or
DCP
Pull-down
resistor to
ground
•
•
Low = BC When BC 1.2 is
Non I2C USB
repeater mode
enabled,
charger
detection
1.2 disabled
N/A
N/A
High = BC
0 to 160 Ω
1.2 enabled
charger
detected
2’b10:
DCP (1.5A)
or Divider
Mode
•
Input
VBUS_Valid
input: use a
voltage divider VBUS_valid is
to reduce VBUS
voltage to
appropriate VIH
for 1.8 V or 1.2
V I/O mode.
N/A
When
Pull-down
resistor to
ground
(2.1A)
Charger
detection is
enabled
Non I2C USB
repeater mode
high enable
charger
detection
N/A
charger
detected
2’b11:
Divider
1.5 kΩto 2 kΩ
•
Mode
(2.4A)
charger
detected
Input
Pull-down
resistor to
ground
3.4 kΩto 3.96
kΩ
When BC 1.2 is
enabled,
advertise
charging BC 1.2
DCP
•
•
Low = BC
1.2 disabled
High = BC
1.2 enabled
Non I2C USB
repeater mode
Active High
Push-Pull
output for VBUS
switch Control
Advertise CDP
Advertise CDP
N/A
N/A
N/A
N/A
•
High =
VBUS ON
Low =
When BC 1.2 is
enabled,
Input
Pull-down
resistor to
ground
7.5 kΩto 11
kΩ
•
•
Low = BC
1.2 disabled
High = BC
1.2 enabled
advertise
•
Non I2C USB
repeater mode
charging (auto
cycle between
BC 1.2 DCP
and Divider
mode)
VBUS OFF
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
VDD3V3
4.32
V
–0.3
range
Analog Supply
VDD1V8
2.1
6
V
V
–0.3
–0.3
voltage range
DP, DN, (with OVP enabled), 1000 total number of short events
Voltage range
and cummulative duration of 1000 hrs.
Voltage range
Voltage range
eDP, eDN
1.6
2.1
V
V
–0.3
–0.3
RESETB, GPIO0, GPIO1, GPIO2, SCL, SDA
Junction
temperature
TJ(max)
Tstg
125
150
°C
°C
Storage
temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
3.3
MAX
3.6
UNIT
VDD3V3
VDD1V8
Supply voltage (VDD3V3)
V
V
V
V
Analog Supply voltage (VDD1V8)
1.62
1.08
1.62
1.8
1.98
1.32
1.98
V_I2C_Pullup I2C and GPIO open drain Bus Voltage (1.2 V Variant)
V_I2C_Pullup I2C and GPIO open drain Bus Voltage (1.8 V Variant)
1.2
1.8
USB
DP, DN
Voltage
0
0
0
0
3.6
1.32
1.98
1.32
V
V
V
V
eUSB2
eDP, eDN
voltage
Digital
RESETB, GPIO0, GPIO1, GPIO2, SCL, SDA (1.8 V Variant)
voltage
Digital
RESETB, GPIO0, GPIO1, GPIO2, SCL, SDA (1.2 V Variant)
voltage
TA
Operating free-air temperature
Junction temperature
85
105
105
92
°C
°C
°C
°C
−20
−20
−20
−20
TJ
TCASE
TPCB
Case temperature
PCB temperature (1 mm away from the device)
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ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.4 Thermal Information
TUSB2E11
YCG (DSBGA)
15 PINS
90.5
THERMAL METRIC(1)
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.6
22.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
22.9
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER
I2C interface active, GPIOs in output
mode, repeater in HS mode with USB
transmitting, maximum RX EQ, max TX
VOD and PE settings, maximum
Absolute worst case peak power
consumption (VDD1V8 only) for power
supply budgeting
PWC_1V8
280
mW
transition density. TA = −20°C to 85°C.
I2C interface active, GPIOs in output
mode, repeater in HS mode with USB
transmitting, maximum RX EQ, max TX
VOD and PE settings, maximum
Absolute worst case peak power
consumption (VDD3V3 only) for power
supply budgeting
PWC_3V3
30
75
mW
mW
transition density. TA = –20°C to 85°C.
I2C interface active, GPIOs in output
mode, repeater in FS mode with USB
Asynchronous traffic. TA = –20°C to
85°C.
Absolute worst case peak power
consumption (VDD3V3 only) for power
supply budgeting
PWCFS_3V3
Maximum TX Vod/Maximum TX PE for
both USB and eUSB2. Averaged over 8
ms and only 1 uFrame with data packet.
Toff threshold = 1/32. Host Peripheral
Mode.
PHS_IOC
USB Audio ISOC High-speed
Powered down
35
mW
µW
µW
Device powered, RESETB=Low,
TA=25°C, (DP/DN Voltage ≤VDD3V3).
PPD
9
Device powered, I2C/GPIO interfaces
functional but idle, repeater is disabled
and put into the lowest power state and
non-functional. TA=25°C, (DP/DN
Voltage ≤VDD3V3).
PDisabled
Disabled
43
43
95
I2C/GPIO interfaces idle, repeater is
connected to a eUSB2 PHY and waiting
for a USB attach event. TA = 25°C,
(DP/DN Voltage ≤VDD3V3)
PDetach
USB unconnected
85
85
µW
µW
I2C/GPIO interfaces idle, USB link is in
L2, repeater is monitoring for a resume/
remote wake event. TA = 25°C, (DP/DN
Voltage ≤VDD3V3). In peripheral mode
additional current is present due the DP
pull up.
PSuspend
L2 Suspend (host mode)
45
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I2C/GPIO interfaces idle, repeater is
supporting a USB connection, USB link
is in L1 (host exists L1 every 1 ms) and
repeater is monitoring for a L1 exit
event. TA = 25°C, (DP/DN Voltage ≤
VDD3V3)
PSleep
L1 Sleep
2.3
5
mW
I2C/GPIO interfaces idle, repeater in LS
PLS_Active
PFS1_Active
PFS2_Active
Low Speed Active
mode, maximum transition density. TA
85°C.
=
7.2
45
9
24
80
24
mW
mW
mW
I2C/GPIO interfaces idle, repeater in FS
mode, maximum transition density. TA
85°C.
Full Speed Active (ASYNC Traffic)
Full Speed Active (ISO Traffic)
=
I2C/GPIO interfaces idle, repeater in FS
mode, maximum transition density. TA
85°C.
=
PHS_Idle_Host High Speed Idle (Host mode)
L0.Idle. TA = 85°C. (Typical at 25°C).
L0.Idle. TA = 85°C. (Typical at 25°C).
26
70
mW
mW
PHS_Idle_Periph
High Speed Idle (Peripheral mode)
108
200
eral
DIGITAL INPUTS
VIH
VIH
VIL
VIL
VIL
VIH
High level input voltage
High level input voltage
Low-level input voltage
Low-level input voltage
Low-level input voltage
High level input voltage
GPIO0, GPIO1, GPIO2 (1.2 V Variant)
GPIO0, GPIO1, GPIO2 (1.8 V Variant)
GPIO0, GPIO1, GPIO2 (1.2 V Variant
GPIO0, GPIO1, GPIO2 (1.8 V Variant
RESETB
0.702
1.053
V
V
V
V
V
V
0.462
0.693
0.35
RESETB
0.75
VIH = 1.98 V, VDD3V3=3.0 V or 0 V,
VDD1V8=1.62 V or 0 V
RESETB, GPIO0, GPIO1
IIH
High level input current
Low level input current
0.5
0.5
µA
µA
VIL = 0 V, VDD3V3=3.0 V or 0 V,
VDD1V8=1.62 V or 0 V
IIL
RESETB, GPIO0, GPIO1
DIGITAL OUTPUTS
VOH High level output voltage
GPIO0, GPIO1, GPIO2, push-pull I/O
mode (IOH = 20 µA and maximum 3 pF
Cload) (1.2 V Variant)
0.81
1.21
V
V
GPIO0, GPIO1, GPIO2, push-pull I/O
mode (IOH = 20 µA and maximum 3 pF
Cload)(1.8 V Variant)
VOH
High level output voltage
GPIO0, GPIO1, GPIO2, push-pull I/O
mode (IOL = 1 mA) (1.2 V Variant)
VOL
Low level output voltage
Low level output voltage
0.25
0.35
5.6
8
V
GPIO0, GPIO1, GPIO2, push-pull I/O
mode (IOL = 1 mA) (1.8 V Variant)
VOL
V
Low level output current in push-pull
mode
GPIO0, GPIO1, GPIO2 (1.2 V Variant),
VOL=0.4 V
IOL_PP
IOL_PP
IOH_PP
IOH_PP
2.5
4
4
6
mA
mA
µA
µA
Low level output current in push-pull
mode
GPIO0, GPIO1, GPIO2 (1.8 V Variant),
VOL=0.4 V
High level output current in push-pull
mode
GPIO0, GPIO1, GPIO2, push-pull I/O
mode, VOH=0.9 V (1.2 V Variant)
22
50
High level output current in push-pull
mode
GPIO0, GPIO1, GPIO2, push-pull I/O
mode, VOH=0.9 V (1.8 V Variant)
I2C (SDA, SCL)
VIL
Low level input voltage, 1.2 V variant
SDA, SCL, V_I2C_Pullup = 1.08 V
0.387
V
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MAX UNIT
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VIL
Low level input voltage, 1.8 V variant
SDA, SCL, V_I2C_Pullup = 1.96 V
0.588
V
V
VIH
VIH
VHYS
VHYS
IIH
High level output voltage, 1.2 V variant SDA, SCL, V_I2C_Pullup = 1.08 V
High level output voltage, 1.8 V variant SDA, SCL, V_I2C_Pullup = 1.96 V
0.833
1.372
0.020
0.098
V
Input hysteresis, 1.2 V variant
Input hysteresis, 1.8 V variant
High level input leakage current
Low level input leakage current
V_I2C_Pullup = 1.08 V
V_I2C_Pullup = 1.96 V
VIH = 1.98 V
V
V
0.5
0.5
µA
µA
IIL
VIL = 0 V
Low level output voltage (1 kΩ pull up),
VOL
VOL
IOL = 2.5 mA, V_I2C_Pullup = 1.08 V
IOL = 2.5 mA, V_I2C_Pullup = 1.96 V
0.2
0.3
V
V
1.2 V variant
Low level output voltage (1 kΩ pull up),
1.8V variant
IOL
Open drain drive strength, 1.2 V Variant VOL = 0.4 V
Open drain drive strength, 1.8 V Variant VOL = 0.4 V
1.6
8
2.4
10
3.0
mA
mA
IOL
12.6
UART I/O
Internal UART output (eDP/eDN) 1.2 V
signalling
VOLI
VOHI
VILI
Internal output low
Internal output high
Internal input low
Internal input high
External output low
External output high
External input low
External input high
0.1
1.32
0.399
1.386
0.3
V
V
V
V
V
V
V
V
Internal UART output (eDP/eDN) 1.2 V
signalling
0.918
–0.1
0.819
0
Internal UART input (eDP/eDN) 1.2 V
signalling
Internal UART input (eDP/eDN) 1.2 V
signalling
VIHI
External UART output (DP/DN) 3.3 V
signalling
VOLE
VOHE
VILE
External UART output (DP/DN) 3.3 V
signalling
2.8
3.6
External UART input (DP/DN) 3.3 V
signalling
0.8
External UART input (DP/DN) 3.3 V
signalling
VIHE
2
USB (DP, DN)
Zinp_Dx
Impedance to GND, no pull up or pull
down
Vin=3.6 V, VDD3V3=3.0 V, Input
390
Characteristics(1)
kΩ
pF
Measured with VNA at 240 MHz, Driver
Hi-Z
CIO_Dx
RPUI
RPUR
RPD
Capacitance to GND
10
1.475
2.99
Bus pull-up resistor on upstream facing High-speed Device Speed
port (idle)
Identification(1)
0.92
1.525
14.35
1.1
2.2
19
kΩ
kΩ
kΩ
Bus pull-up resistor on upstream facing High-speed Device Speed
port (receiving)
Identification(1)
Bus pull-down resistor on downstream
facing port
High-speed Device Speed
Identification(1)
24.6
The output voltage in the high-speed
idle state, High-speed Input
Characteristics(1)
VHSTERM
Termination voltage in highspeed
10
mV
–10
USB TERMINATION
Driver Output Resistance (which also
(VOH= 0 to 600 mV) Full-speed (12
Mb/s) Driver Characteristics(1), Default,
U_HS_TERM_Px setting 01
ZHSTERM_P
40.6
40.6
45
45
49.4
49.4
Ω
Ω
serves as high speed termination)
(VOH= 0 to 600 mV) Full-speed (12
Mb/s) Driver Characteristics(1), Default,
U_HS_TERM_Px setting 01
Driver Output Resistance (which also
serves as high speed termination)
ZHSTERM_N
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ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX UNIT
USB INPUT LEVELS LS/FS
Receiver Characteristics(1) (measured at
the connector)
VIH
High (driven)
V
Receiver Characteristics(1) (HOST
downstream port pull-down resistor
enabled and external device pull up 1.5
kΩ± 5% to 3.0-3.6 V)
VIHZ
High (floating)
Low
2.7
3.6
V
VIL
VDI
Receiver Characteristics(1)
0.8
0.2
V
V
|(D+)-(D-)|; Differential Input Sensitivity
Range for Low-/full-speed(1); (measured
at connector) VCM=0.8 V to 2.0 V
Differential Input Sensitivity (hysteresis
is off)
USB OUTPUT LEVELS LS/FS
USB Driver Characteristics(1), (measured
at connector with RL of 1.425 kΩ to 3.6
V. )
VOL
Low
0
0.3
V
USB Driver Characteristics(1), (measured
at the connector with RL of 14.25 kΩ to
GND. )
USB Driver Characteristics(1), measured
VOH
High (Driven)
2.8
28
3.6
44
V
ZFSTERM
Driver Series Output Resistance
Ω
it during VOL or VOH
Measured as in Data Signal Rise and
Fall Time(1), excluding the first transition
from the Idle state. With external 1.5
kΩ pull up on DP to 3.0 V
VCRS2
Output Signal Crossover Voltage
1.3
1.3
2
2
V
V
Measured as in Data Signal Rise and
Fall Time(1), excluding the first transition
from the Idle state
VCRS
Output Signal Crossover Voltage
USB INPUT LEVELS HS
Full-/High-speed Signaling
Level(1), specification refers to peak
differential signal amplitude), measured
at 240 MHz with increasing amplitude,
U_SQUELCH_THRESHOLD_Px setting
011, VCM= -50 mV to 500 mV
High-speed squelch/no-squelch
detection threshold
VHSSQ
VHSSQ
VHSDSC
111
104
525
128
125
575
161
150
625
mV
mV
mV
Full-/High-speed Signaling
Levels(1), (specification refers to peak
differential signal amplitude), measured
at 240 MHz with increasing amplitude,
U_SQUELCH_THRESHOLD_Px setting
100, VCM= -50 mV to 500 mV
High-speed squelch/no-squelch
detection threshold
Full-/High-speed Signaling
Levels(1), (specification refers to
differential signal amplitude). (HW
Default),
High-speed disconnect detection
threshold
U_DISCONNECT_THRESHOLD_Px
setting 0000, VCM=200 mV to 600 mV
Full-/High-speed Signaling
Levels(1) (specification refers to
differential signal amplitude). (+25.6%),
U_DISCONNECT_THRESHOLD_Px
setting 1000, VCM=280 mV to 680 mV
High-speed disconnect detection
threshold
VHSDSC
685
757
846
mV
dB
USB high-speed data receiver
equalization, (measured indirectly
through jitter)
EQ_UHS
240 MHz, U_EQ_Px setting 000
0.06
0.57
−0.37
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MAX UNIT
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
USB High-speed data receiver
equalization, (measured indirectly
through jitter)
EQ_UHS
240 MHz, U_EQ_Px setting 010
0.62
1.09
1.57
dB
USB OUTPUT LEVELS HS
Full-/High-speed Signaling Levels(1),
measured single-ended peak voltage
per USB 2.0 test measurement spec,
U_HS_TX_AMPLITUDE_Px setting
0011, PE disabled, Test load is an ideal
45 Ω to GND on DP and DN
VHSOH
High-speed data signaling high
360
400
490
440
mV
Full-/High-speed Signaling
Levels(1), measured single ended peak
voltage per USB 2.0 test measurement
spec, U_HS_TX_AMPLITUDE_Px
setting 1100, PE disabled, Test load is
an ideal 45 Ω to GND on DP and DN
VHSOH
High-speed data signaling high
441
720
539
880
mV
mV
Measured p-p, 0%,
U_HS_TX_AMPLITUDE_Px setting
0011, PE disabled, Test load is an ideal
45 Ω to GND on DP and DN.
VHSOD
High-speed data signaling swing
High-speed data signaling swing
800
980
Measured p-p, 22.5%,
U_HS_TX_AMPLITUDE_Px setting
1100, PE disabled,Test load is an ideal
45 Ω to GND on DP and DN.
Full-/High-speed Signaling Levels(1), PE
disabled, test load is an ideal 45 Ω to
GND on DP and DN.
Full-/High-speed Signaling Levels(1), (PE
is disabled. swing setting has no impact
but slew rate control has impact), Test
load is an ideal 1.5 kΩ pull up on DP.
Full-/High-speed Signaling Levels(1), (PE
is disabled. swing setting has no impact
but slew rate control has impact), Test
load is an ideal 45 Ω to GND on DP and
DN.
VHSOD
VHSOL
VCHIRPJ
882
–10
700
1078
10
mV
mV
mV
High-speed data signaling low, driver is
off termination is on (measured single
ended)
Host or hub chirp J level (differential
voltage)
900
-760
-700
1100
VCHIRPK
Device chirp K level (differential voltage)
-900
-900
-500
-500
mV
mV
Full-/High-speed Signaling Levels(1), (PE
is disabled. swing setting has no impact
but slew rate control has impact), Test
load is an ideal 1.5 kΩ pull up on DP.
Host or hub Chirp K level (differential
voltage)
VCHIRPK
U_HS_TX_PRE_EMPHASIS_Px setting
000, test load is an ideal 45 Ω to GND
on DP and DN.
U2_TXPE
U2_TXPE
High-speed TX pre-emphasis
High-speed TX pre-emphasis
0.25
1.7
0.5
2.1
0.75
2.5
dB
dB
U_HS_TX_PRE_EMPHASIS_Px setting
100, test load is an ideal 45 Ω to GND
on DP and DN.
U_HS_TX_PE_WIDTH_Px setting
11 (measured with PE=2.5 dB setting of
101), Test load is an ideal 45 Ω to GND
on DP and DN.
U2_TXPE_UI High-speed TX pre-emphasis width
0.54
33
0.65
40
0.77
UI
eUSB2 TERMINATION
High-speed transmit source termination
impedance
RSRC_HS
High-Speed Tx Electrical Specification (2)
High-Speed Tx Electrical Specification (2)
47
4
Ω
Ω
High-speed source impedance
mismatch
ΔRSRC_HS
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ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-speed differential receiver
termination (repeater)
RRCV_DIF
RPD
High-Speed Rx Electrical Specification (2)
74
80
86
Ω
Pull-down (2), active during LS, FS and
HS
Pull-down resistors on eDP/eDN
Transmit output impedance
6
8
10
59
kΩ
Low-Speed /Full-Speed DC
Specifications for 1.2 V ± 10% (2) , TX
output impedance
RSRC_LSFS
28
44
Ω
Measured with VNA at 240 MHz, Driver
Hi-Z (VCM = 120 mV to 450 mV),
measured differentially.
CIO_eDx
Differential Capacitance
3.9
5.2
pF
eUSB2 FS/LS INPUT LEVELS
Low-Speed /Full-Speed DC
VIL
Single-ended input low
0.399
0.332
1.386
1.1
V
V
Specifications for 1.2 V ± 10% (2)
–0.1
−0.1
0.819
0.682
43.2
38
Low-Speed /Full-Speed DC
VIL
Single-ended input low
Specifications for 1.0 V ± 10% (2)
Low-Speed /Full-Speed DC
VIH
Single-ended input high
V
Specifications for 1.2 V ± 10% (2)
Low-Speed /Full-Speed DC
VIH
Single-ended input high
V
Specifications for 1.0 V ± 10% (2)
Low-Speed /Full-Speed DC
VHYS
VHYS
Receive single-ended hysteresis voltage
Receive single-ended hysteresis voltage
mV
mV
Specifications for 1.2 V ± 10% (2)
Low-Speed /Full-Speed DC
Specifications for 1.0 V ± 10% (2)
eUSB2 FS/LS OUTPUT LEVELS
Low-Speed /Full-Speed DC
VOL
VOL
VOH
VOH
Single-ended output low
Single-ended output low
Single-ended output high
Single-ended output high
0.1
0.1
V
V
V
V
Specifications for 1.2 V ± 10% (2)
Low-Speed /Full-Speed DC
Specifications for 1.0 V ± 10% (2)
Low-Speed /Full-Speed DC
0.918
0.765
1.32
1.1
Specifications for 1.2 V ± 10% (2)
Low-Speed /Full-Speed DC
Specifications for 1.0 V ± 10% (2)
eUSB2 HS INPUT LEVELS
High-Speed Rx Electrical Specification
VRX_CM
Receive DC common mode range (low) (2) (normative), low DC common mode
RX must tolerate
120
mV
mV
High-Speed Rx Electrical Specification
Receive DC common mode range (high) (2) (normative), high DC common mode
RX must tolerate
VRX_CM
280
High-Speed Rx Electrical Specification (2)
(informative), across the DC common-
mode range of 120 mV to 280 mV. (RX
capability tested with intentional TX rise/
fall time mismatch and prop delay
mismatch)
Receiver AC common mode (50 MHz–
480 MHz)
VCM_RX_AC
-60
15
60
60
50
97
mV
pF
High-Speed Rx Electrical Specification
CRX_CM
Receive center-tapped capacitance
Squelch/No-squelch detect threshold
(2) (informative)
High-Speed Rx Electrical Specification
(2), (measured as differential peak
voltage at 240 MHz with increasing
amplitude)
VEHSSQ
81
mV
E_SQUELCH_THRESHOLD_Px setting
100, VCM = 120 mV to 450 mV
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MAX UNIT
ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
High-Speed Rx Electrical Specification
(2), (measured as differential peak
voltage at 240 MHz with increasing
amplitude)
E_SQUELCH_THRESHOLD_Px setting
110, VCM = 120 mV to 450 mV
VEHSSQ
Squelch/No-squelch detect threshold
47
67
83
mV
dB
eUSB2 high-speed data receiver
equalization, (measured indirectly
through jitter)
EQ_EHS
240 MHz E_EQ_P1x setting 0000
0.34
420
0.73
−0.2
eUSB2 HS OUTPUT LEVELS
Measured p2p, RL = 80 Ω,
E_HS_TX_AMPLITUDE_ Px setting
011, ideal 80 ΩRx differential
termination load
VEHSOD
Transmit differential (terminated)
378
462
0.2
mV
dB
E_HS_TX_PRE_EMPHASIS_Px setting
000
E_TXPE
High-speed TX Pre-emphasis
0
−0.2
E_TXPE_UI
VE_TX_CM
High-speed TX Pre-emphasis width
Transmit DC common mode
E_HS_TX_PE_WIDTH_Px setting 00
High-Speed Tx Electrical Specification (2)
0.29
170
0.40
0.59
230
UI
mV
(1) USB 2.0 Promoter Group 2000, USB 2.0 Specification USB 2.0 Promoter Group
(2) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev.
1.2 USB Implementers Forum
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ZHCSQH7A –NOVEMBER 2021 –REVISED JUNE 2022
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
530
530
TYP
625
625
MAX
740
UNIT
ps
USB (DP, DN), HS Driver Switching Characteristics
Data Signal Rise and Fall, Eye Patterns
(1), U_HS_TX_SLEW_RATE_Px setting
11, ideal 45 Ω to GND loads on DP and
DN, pre-emphasis disabled.
THSR
Rise time (10% –90%)
Fall time (10% –90%)
Data Signal Rise and Fall, Eye Patterns,
U_HS_TX_SLEW_RATE_Px setting 11,
ideal 45 Ω to GND loads on DP and DN,
pre-emphasis disabled.
THSF
740
ps
USB (DP, DN), FS Driver Switching Characteristics
Data Signal Rise and Fall Time and Full-
speed Load (1)
TFR
TFF
4
4
20
20
ns
ns
Rise time (10% –90%)
Fall time (10% –90%)
Data Signal Rise and Fall Time and Full-
speed Load (1)
Data Signal Rise and Fall, Eye Patterns
(1), excluding the first transition from the
Idle state
TFRFM
(TFR/TFM
)
90
111.1
%
USB (DP, DN), LS Driver Switching Characteristics
Data Signal Rise and Fall Time and Full-
speed Load (1)
TLR
TLF
75
75
300
300
ns
ns
Rise time (10% –90%)
Fall time (10% –90%)
Data Signal Rise and Fall Time and Full-
speed Load (1)
eUSB2 (eDP, eDN), HS Driver Switching Characteristics
Full-Speed/Low-Speed Electrical
Specification (2) , ideal 80 ΩRx differential
termination E_HS_TX_SLEW_RATE_Px
setting = 01
TEHSRF
355
440
525
25
ps
%
Rise/fall time (20% –80%)
Full-Speed/Low-Speed Electrical
Specification (2)
,
TEHSRF_M
rise/fall mismatch = absolute delta of (rise
–fall time) / (average of rise and fall
time).
Transmit rise/fall mismatch
M
eUSB2 (eDP, eDN), LS/FS Driver Switching Characteristics
Low-Speed /Full-Speed DC Specifications
TERF
2
6
ns
%
for 1.2 V ± 10% (2)
Rise/fall time (10% –90%)
Low-Speed /Full-Speed DC Specifications
for 1.2 V ± 10% (2)
TERF_MM Transmit rise/fall mismatch
25
I2C (SDA)
Bus Speed = 100 kHz, CL= 200 pF, RPU
4 kΩ, IOL ≅ 1 mA
=
=
Tr
Tr
Tr
Tr
Tr
Tr
Tf
Rise time (STD)
Rise time (FM)
Rise time (FM+)
Rise time (STD)
Rise time (FM)
Rise time (FM+)
Fall time (STD)
600
180
72
ns
ns
ns
ns
ns
ns
ns
Bus Speed = 400 kHz, CL= 200 pF, RPU
2.2 kΩ, IOL ≅ 2 mA
Bus Speed = 1 MHz, CL= 10 pF, RPU = 1
kΩ, IOL ≅ 4 mA
Bus Speed = 100 kHz, CL= 200 pF, RPU
4 kΩ, IOL ≅ 2 mA
=
1000
300
Bus Speed = 400 kHz, CL= 200 pF, RPU
1 kΩ, IOL ≅ 8 mA
=
Bus Speed = 1 MHz, CL= 50 pF, RPU = 1
kΩ, IOL ≅ 4 mA
120
Bus Speed = 100 kHz, CL= 200 pF, RPU
2.2 kΩ, IOL ≅ 4 mA
=
106.5
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bus Speed = 400 kHz, CL= 200 pF, RPU
1 kΩ, IOL ≅ 8 mA
=
Tf
Tf
Tf
Tf
Tf
Fall time (FM)
106.5
81.5
ns
Bus Speed = 1 MHz, CL= 90 pF, RPU = 1
kΩ, IOL ≅ 8 mA
Fall time (FM+)
Fall time (STD)
Fall time (FM)
Fall time (FM+)
ns
ns
ns
ns
Bus Speed = 100 kHz, CL= 10 pF, RPU
4 kΩ, , IOL ≅ 2 mA
=
=
6.5
6.5
6.5
Bus Speed = 400 kHz, CL= 10 pF, RPU
2.2 kΩ, IOL ≅ 4 mA
Bus Speed = 1 MHz, CL= 10 pF, RPU = 1
kΩ, IOL ≅ 8 mA
(1) USB 2.0 Promoter Group 2000, USB 2.0 Specification USB 2.0 Promoter Group
(2) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev.
1.2 USB Implementers Forum
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7.7 Timing Requirements
MIN
NOM
MAX
UNIT
I/O TIMING
t_GPIO_PW Minimum GPIO pulse width for interrupt event
8
µs
RESET TIMING
t_VDD1V8_RA
Ramp time for VDD1V8 to reach minimum 1.62 V
2
2
ms
MP
t_VDD3V3_RA
Ramp time for VDD3V3 to reach minimum 3.0 V
ms
us
MP
t_aRESETB
Duration for RESETB to be asserted low to complete reset while powered
Time for the device to be ready to accept RAP and I2C requests and
10
t_RH_READY eUSB2 interface to be ready after RESETB is de-asserted or (VDD1V8 and
VDD3V3) reach the minimum recommended voltages, whichever is later.
3
ms
µs
Time for the device to be ready to accept RAP and I2C requests and
t_RS_READY
350
eUSB2 interface to be ready after a soft reset through I2C.
REPEATER TIMING
Total additive jitter for eUSB2 to USB 2.0 (output jitter − input jitter) of the
TJ1E
20
17
42
42
ps
ps
repeater.
Total additive jitter for USB 2.0 to eUSB2 (output jitter − input jitter) of the
repeater.
TJ1I
eUSB2 to USB 2.0 repeater FS jitter to next transition (Per Low-Speed /
Te_to_U_DJ1 Full-Speed DC Specifications for 1.2 V ± 10% (1) condition for supply and
GND delta).
+6.0
+3.0
+1.5
+1.5
ns
ns
ns
ns
−6.0
−3.0
−1.5
−1.5
USB 2.0 to eUSB2 repeater FS jitter to next transition (Per Low-Speed /
TU_to_e_DJ1 Full-Speed DC Specifications for 1.2 V ± 10% (1) condition for supply and
GND delta).
repeater FS paired transition jitter in eUSB2 to USB 2.0 direction (relaxed
TDJ2_e2U
relative to THDJ2 defined by USB 2.0 ± 1 ns). eUSB2 in 1.2 V signaling
mode.
repeater FS paired transition jitter in USB 2.0 to eUSB2 direction (relaxed
relative to THDJ2 defined by USB 2.0 ± 1 ns). eUSB2 in 1.2 V signaling
mode.
TDJ2_U2e
MODE TIMING
TMODE_SWI Time needed to change mode from UART bypass mode to and from USB
1
2
µs
mode
TCH
TUART_STAR Time needed to start transmitting UART data, post toggling GPIO0 to '0'
ms
when in UART strap mode (SCL=1, SDA=0 at power-up)
T
I2C (FM+)
Start setup time, SCL (Tr=72 ns –120 ns), SDA (Tf=6.5 ns –81.5 ns), 1
MHz FM+
tSU_STA
260
260
260
50
ns
ns
ns
ns
ns
ns
Stop setup time, SCL (Tr=72 ns –120 ns), SDA (Tf=6.5 ns –81.5 ns), 1
MHz FM+
tSU_STO
Start hold time, SCL (Tr=72 ns –120 ns), SDA (Tf=6.5 ns –81.5 ns), 1
MHz FM+
tHD_STA
Data input or false start/stop, setup time, SCL (Tr=72 ns –120 ns), SDA
(Tf=6.5 ns –81.5 ns), 1 MHz FM+
tSU_DAT
Data input or False start/stop, hold time, SCL (Tr=72 ns –120 ns), SDA
(Tf=6.5 ns –81.5 ns), 1 MHz FM+
tHD_DAT
0
tVD_DAT,
tVD_ACK
SDA output delay, SCL (Tr=72 ns –120 ns), SDA (Tf=6.5 ns –81.5 ns), 1
MHz FM+
20
450
91
tHD_DAT_SL Data hold time when device is transmitting
6.67
50
ns
ns
tSP
Glitch width suppressed
Bus free time between a STOP and START condition (Master minimum
spec that device must tolerate)
tBUF
0.5
µs
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MIN
0.5
NOM
MAX
UNIT
µs
tLOW
Low period for SCL clock (minimum spec that device must tolerate)
tHIGH
HIgh period for SCL clock (minimum spec that device must tolerate)
0.26
µs
I2C (FM)
Stop setup time, SCL (Tr=180 ns –300 ns), SDA (Tf=6.5 ns –106.5 ns),
400 kHz FM
tSU_STO
tHD_STA
tSU_STA
tSU_DAT
tHD_DAT
600
600
600
100
0
ns
ns
ns
ns
ns
ns
Start hold time, SCL (Tr=180 ns –300 ns), SDA (Tf=6.5 ns –106.5 ns),
400 kHz FM
Start setup time, SCL (Tr=180 ns –300 ns), SDA (Tf=6.5 ns –106.5 ns),
400 kHz FM
Data input or false start/stop, setup time, SCL (Tr=180 ns –300 ns), SDA
(Tf=6.5 ns –106.5 ns), 400 kHz FM
Data input or false start/stop, hold time, SCL (Tr=180 ns –300 ns), SDA
(Tf=6.5 ns –106.5 ns), 400 kHz FM
tVD_DAT,
tVD_ACK
SDA output delay, SCL (Tr=180 ns –300 ns), SDA (Tf=6.5 ns –106.5
ns), 400 kHz FM
20
900
91
tHD_DAT_SL Data hold time when device is transmitting
13.5
50
ns
ns
tSP
Glitch width suppressed
Bus free time between a STOP and START condition (minimum spec that
device must tolerate)
tBUF
1.3
µs
tLOW
Low period for SCL clock (minimum spec that device must tolerate)
1.3
0.6
µs
µs
tHIGH
HIgh period for SCL clock (Master minimum spec that device must tolerate)
I2C (STD)
Stop setup time, SCL (Tr=600 ns –1000 ns), SDA (Tf=6.5 ns –106.5 ns),
100 kHz STD
tSU_STO
tHD_STA
tSU_STA
tSU_DAT
tHD_DAT
4
4
µs
µs
µs
ns
µs
µs
Start hold time, SCL (Tr=600 ns –1000 ns), SDA (Tf=6.5 ns –106.5 ns),
100 kHz STD
Start setup time, SCL (Tr=600 ns –1000 ns), SDA (Tf=6.5 ns –106.5 ns),
100 kHz STD
4.7
250
5
Data input or false start/stop, setup time, SCL (Tr=600 ns –1000 ns), SDA
(Tf=6.5 ns –106.5 ns), 100 kHz STD
Data input or false start/stop, hold time, SCL (Tr=600 ns –1000 ns), SDA
(Tf=6.5 ns –106.5 ns), 100 kHz STD
tVD_DAT,
tVD_ACK
SDA output delay, SCL (Tr=600 ns –1000 ns), SDA (Tf=6.5 ns –106.5
ns), 100 kHz STD
3.45
91
tHD_DAT_SL Data hold time when device is transmitting
13.5
50
ns
ns
tSP
Glitch width suppressed
Bus free time between a STOP and START condition (minimum spec that
device must tolerate)
tBUF
4.7
µs
tLOW
tHIGH
Low period for SCL clock (minimum spec that device must tolerate)
HIgh period for SCL clock (minimum spec that device must tolerate)
4.7
4.0
µs
µs
(1) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev.
1.2 USB Implementers Forum
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7.8 Typical Characteristics
TJ1E is for egress direction from eUSB2 to USB and TJ1I is for ingress direction from USB to eUSB2
图7-1. Total Additive Jitter (Typical)
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7.9 Parameter Measurement Information
eUSB2
USB 2.0
22.1
15.8
15.8
86100
Scope
or
81130A
Pattern Generator
or
Repeater
Test Channel
BERT
Test Channel
BERT
22.1
50
50
40
45
Vin * 0.76
Vin scaled for impedance conversion
Impedance
conversion
Impedance
conversion
图7-2. USB 2.0 TX Output (Egress) Jitter, Eye Mask Test Setup
eUSB2 USB 2.0
22.1
22.1
15.8
15.8
81130A
Pattern Generator
or
86100
Scope
or
Repeater
Test Channel
Test Channel
BERT
BERT
50
50
40
45
USB 2.0 High speed test packets
Impedance
conversion
Impedance
conversion
Vin * 0.693
Vin scaled for impedance conversion
USB 2.0 TX Vpp * 0.68
Vout scaled for impedance conversion
图7-3. eUSB2 TX Output (Ingress) Jitter, Eye Mask Test Setup
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8 Detailed Description
8.1 Overview
The TUSB2E11 is an eUSB2 to USB 2.0 repeater that resides between the SoC with an eUSB2 port and an
external connector that supports USB 2.0. It can be configured by the register access protocol (RAP) or through
the I2C. The repeater is configurable as either a host or device repeater (DRD repeater).
I2C port supports up to 1 MHz (fast mode plus) for internal register access. A subset of internal registers can be
accessed through the register access protocol. Simultaneous register access using RAP and through the I2C is
supported with RAP having priority over I2C.
To power up in I2C mode, both SDA and SCL should have pull-up resistors to appropriate I2C bus voltage.
GPIO2 output pin can be configured to provide an active low open drain or selectable active low or active high
push-pull level sensitive interrupt output to the SoC.
8.2 Functional Block Diagram
VDD3V3 VDD1V8
Common Module
Power System
LDOs
Clock & Reset
Reference System
Internal
Oscillator
Bandgap
IREF
PoR
USB/eUSB2 Translator &
State Machine
eDN
eDP
DN
DP
eUSB
USB
Battery Charging Advertising
and Detection Controller
Carkit Debug mode support
control
OTP
Con g & Control
Registers (I2C)
GPIO
RESETB
GND
GPIO2
SCL
SDA
GPIO0
GPIO1
图8-1. Functional Block Diagram
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8.3 Feature Description
TUSB2E11 is an USB compliant eUSB2 to USB 2.0 repeater supporting both device and host modes. Both USB
and eUSB2 offer fully tunable TX and RX through I2C. Additionally, USB TX and RX can be tuned when I2C is
not used.
8.4 Device Functional Modes
8.4.1 Repeater Mode
Upon de-assertion of RESETB or software reset and after t_RH_READY or t_RS_READY, TUSB2E11 will enable and
enter the default state and be ready to accept eUSB2 packets, RAP, and I2C requests. The repeater will either
be in host repeater mode or peripheral repeater mode depending on the receipt of either host mode enable or
peripheral mode enable.
When TUSB2E11 is repeating high-speed packets, either from eUSB2 to USB 2.0 or from USB 2.0 to eUSB2, up
to 4UI (may include partial UI) of HS SOP could be truncated. This is the same as a standard USB 2.0 HUB
operating in high speed mode which could truncate up to 4UI.
When TUSB2E11 is repeating high-speed packets from eUSB2 to USB 2.0, up to 1.6UI of random dribble bits
(may include partial UI) could be introduced after HS EOP. This is the less than a standard USB 2.0 HUB
operating in high speed mode which could have up to 4UI of random dribble bits.
When TUSB2E11 is repeating high-speed packets from USB 2.0 to eUSB2, up to 5UI of random dribble bits
(may include partial UI) could be introduced after HS EOP. This is more than a standard USB 2.0 HUB operating
in high speed mode which could have up to 4UI of random dribble bits. eDSPr/eUSPr receiving eUSB2 high-
speed packets should ignore 5UI of dribble bits after detecting no stuffed bit insertion indicating HS EOP.
表8-1. Number of Hubs Supported with Host and Peripheral Repeater
Number of eUSB2
Repeaters
Number of Hubs
Operating at HS
Number of Hubs
Operating at FS
1
2
0
4
3
5
2
1
5
Number of hubs operating at FS is reduced due to
Te_to_U_DJ1 and TRJR1
Number of hubs operating at HS is reduced due to 2 3
1 SOP truncation and EOP dribble
.
non-eUSB2 system for reference
8.4.2 Power Down Mode
RESETB could be used as a power down pin when asserted low. Power down mode will put TUSB2E11 in
lowest power mode.
8.4.3 Disabled Mode
The repeater could be disabled by setting DISABLE bit through the I2C.
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8.4.4 UART Mode
In I2C mode GPIO0 will default to being an enable control for Carkit UART mode. GPIO0 is an active low signal
to enable Carkit UART mode. GPIO0 is intended to be controlled through APU or SoC. When APU or SoC is not
powered on or the firmware has not been loaded, the GPIO0 will be low, enabling the UART mode to allow APU
or SoC debug interface to be accessed through the USB port.
Default Carkit UART direction is DP →eDP (RX) and eDN →DN (TX).
On the rising edge of GPIO0, followed by TMODE_SWITCH, TUSB2E11 will enable and enter default state and be
ready to accept eUSB2 port reset, configuration or RAP. The repeater mode will be configured as host or
peripheral depending on the eUSB2-defined configuration received from eUSBr and acknowledged by the
repeater.
UART mode enable is controlled through GPIO0 after power up. This can be changed through
UART_use_bit1_P1 bit in UART-PORT1 register, so UART mode enable could be controlled through a register
instead of GPIO0.
8.4.5 Auto-Resume ECR
Optional host repeater auto-resume is supported by TUSB2E11 in L1/L2 by driving Resume K at D+/D- until
SOResume is received from eDSPr. In addition, TUSB2E11 eUSPh will hold Remote Wake line state until
SORresume is received from eDSPr.
This auto-resume feature provides host controller extra time to exit low power state and issue SOResume while
TUSB2E11 UDSP drives resume within 1 ms (TURSM) hub resume timing requirement. To take advantage of
this low power feature, host controller shall implement low power mechanism to detect wake on eDSPr lines
while host controller is in low power state.
This auto-resume is not needed if host controller is capable of initiating SOResume within 1 ms of detecting
Remote Wake on eDSPr.
This auto-resume is enabled by default but can be disabled via bit 6 of register 0x78. This auto-resume ECR
mode is disabled when L2 interrupt mode is enabled. When L2 interrupt mode is enabled, resume K at D+/D- is
still driven when Remote wake is detected on UDSP but eUSPh will be held at SE0 instead of in Remote Wake
state. See the L2 State Interrupt Modes section for more details.
图8-2. Timing Diagram for Auto-Resume for HS/FS
8.4.6 L2 State Interrupt Modes
To prevent signaling on eUSB2 while the eDSP is powered off, both L2 remote wake interrupt and disconnect
event interrupt modes should be enabled. The special remote wake sequence when L2 remote wake interrupt
mode is enabled.
• System enables interrupt USB_REMOTE_WAKE_P1.
• Repeater is in host mode and has received a CM.L2.
• Repeater detects wake on USB 2.0
• Repeater asserts interrupt.
• Repeater reflects resume on USB 2.0, but does not signal wake on eUSB2.
• Repeater waits for eDSPr to signal start of resume with no intervening configuration, connect, or reset
sequence.
• Repeater and eDSP follow normal eUSB2 protocol to signal resume starting and ending in L0.
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图8-3. Timing Diagram for Wake Interrupt for HS/FS
The special wake on disconnect sequence when disconnect event interrupt mode is enabled
• System enables interrupt USB_DISCONNECT_P1.
• Repeater is in host mode and has received a CM.L2.
• Repeater detects SE0 for disconnect on USB 2.0.
• Repeater asserts interrupt.
• Interrupt must be cleared prior to eDSPr reinitializing TUSB2E11 as a host.
• Repeater does not signal or report USB 2.0 SE0 on eUSB2.
• Repeater waits for eDSPr to power up, which starts with port reset announcement.
• Repeater and eDSP follow normal eUSB2 protocol, ending in unconnected state of host mode.
图8-4. Timing Diagram for Disconnect Interrupt for HS/FS
8.4.7 Attach Detect Interrupt Mode
When attach event detect is enabled TUSB2E11 will issue an interrupt event instead of signaling attach on
eUSB2.
• System enables interrupt USB_DETECT_ATTACH_P1. Interrupt has to be enabled prior to any connect
event.
• Repeater is in host mode.
• Repeater detects attach on USB 2.0.
• Repeater debounces attach for 60 µs and asserts interrupt instead of signaling attach on eUSB2.
• Interrupt must be disbled prior to eDSPr reinitializing as a host to process attach through normal mechanism.
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图8-5. Timing Diagram for Attach Detect Interrupt for HS/FS
8.4.8 GPIO Mode
GPIO0
GPIO0 pin will be in input mode at power up, will be sampled during reset.
GPIO0 defaults to active low UART mode (bypass mode) enable control after power up. This can be changed
through the UART_use_bit1_P1 bit in UART-PORT1 register, so GPIO0 can be repurposed. Refer to UART
Mode.
GPIO0 pin can be configured to be input or output mode through the I2C register write. Output event is selected
through the I2C register. Refer to GPIO0_CONFIG register for more information.
GPIO0 input status change can be reported through the GPIO2 as an interrupt if enabled through the I2C. Status
change trigger can be programmed to be edge trigger or level trigger through the I2C.
GPIO0 pin in output mode will default to open drain output but can be configured to be push-pull output. GPIO0
pin can drive up to 3 pF loads when in push-pull mode.
GPIO0 pin will revert back to input upon RESETB assert, de-assert, or soft reset.
In non I2C mode, GPIO0 is used for USB PHY tuning.
GPIO1
GPIO1 pin will be in input mode at power up, will be sampled during reset.
GPIO1 will be configured as an enable control for battery charger detection in repeater default state if
DEFAULT_STATE_BC_P1 is set to 0x01 through the BC_CONTROL register.
GPIO1 pin can be configured to be input or output mode through the I2C register write. Output event is selected
through the I2C register. Refer to GPIO1_CONFIG register.
GPIO1 input status change can be reported through the GPIO2 as an interrupt if enabled through the I2C. Status
change trigger can be programmed to be edge trigger or level trigger through the I2C.
GPIO1 pin in output mode will default to open drain output but can be configured to be push-pull output. GPIO1
pin can drive up to 3 pF loads when in push-pull mode.
GPIO1 pin will revert back to input upon RESETB assert, de-assert, or soft reset.
In non I2C mode, GPIO1 is used for USB PHY tuning.
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GPIO2
GPIO2 pin will default to open drain interrupt (INT) active low output at power up but can be programmed
through the I2C to be a push-pull output. In push-pull mode, it can be programmed to be either active high or
active low. Interrupt output will be level sensitive interrupt. Trigger events can be selected through the I2C.
Connect GPIO2 to APU to use interrupt functions and a pull-up resistor (open drain mode).
GPIO2 interrupt output can be configured through the INT_ENABLE and INT_STATUS registers.
GPIO2 can be configured as battery charger detect indicator instead of the interrupt output through the
BC_CONTROL register.
In non I2C mode, GPIO2 is used for USB PHY tuning.
8.4.9 USB 2.0 High-Speed HOST Disconnect Detection
USB 2.0 specification does not specify high-speed output differential swing VOD during disconnect without
external load. Only chirp level and HS host disconnect threshold are specified. Specification implicitly assumes
high-speed output differential swing VOD will double during disconnect. However, the high-speed output
differential swing during disconnect depends on the USB 2.0 TX output swing and pre-emphasis setting as the
common mode voltage increase will saturate the output swing level and might not double.
HS host disconnect threshold shall be adjusted to provide the most margin to avoid false disconnect as well as
failure to detect a disconnect. See 表8-2.
表8-2. Recommended USB 2.0 High-speed HOST Disconnect Thresholds per USB HSTX Amplitude and
Pre-Emphasis
USB HS TX Pre-Emphasis
USB HS TX
0.5 dB (0h)
0.9 dB (1h)
1.2 dB (2h)
1.7 dB (3h)
2.1 dB (4h)
2.5 dB (5h)
Amplitude (Vp-p)
740 mV (0h )
760 mV (1h )
780 mV (2h )
800 mV (3h )
820 mV (4h )
840 mV (5h )
860 mV (6h )
880 mV (7h )
900 mV (8h )
920 mV (9h )
940 mV (Ah )
960 mV (Bh )
980 mV (Ch )
1000 mV (Dh )
1020 mV (Eh )
1040 mV (Fh )
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
645 mV (6h)
645 mV (6h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
705 mV (9h)
725 mV (Ah)
725 mV (Ah)
725 mV (Ah)
745 mV (Bh)
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
645 mV (6h)
645 mV (6h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
705 mV (9h)
705 mV (9h)
725 mV (Ah)
725 mV (Ah)
725 mV (Ah)
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
645 mV (6h)
645 mV (6h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
705 mV (9h)
705 mV (9h)
705 mV (9h)
725 mV (Ah)
725 mV (Ah)
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
645 mV (6h)
645 mV (6h)
665 mV (7h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
705 mV (9h)
705 mV (9h)
705 mV (9h)
705 mV (9h)
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
625 mV (5h)
645 mV (6h)
665 mV (7h)
665 mV (7h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
685 mV (8h)
705 mV (9h)
705 mV (9h)
545 mV (1h)
565 mV (2h)
585 mV (3h)
585 mV (3h)
605 mV (4h)
625 mV (5h)
625 mV (5h)
645 mV (6h)
645 mV (6h)
665 mV (7h)
665 mV (7h)
665 mV (7h)
685 mV (8h)
685 mV (8h)
685 mV (8h)
685 mV (8h)
8.5 Manufacturing Test Modes
Below test procedures show how to use I2C to enter test modes to perform continuity test of DP/DM during
manufacturing or debug. During this mode the TUSB2E11 will not operate as a repeater.
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8.5.1 USB DP Test Procedure
I2C Commands to use DP pull-up to test DP/DM continuity:
Enable GPIOs and DP Pull-up:
h00, hA0 <-set gpio0 to push-pull output mode
h40, hA0 <-set gpio1 to push-pull output mode
hD5, h28
hD6, h04
hD7, h10 <-DP pull-up is now on
hCE, h18
hDC, h15 <-muxes DP / DM status onto GPIO lines
Status Readback Check:
h00 = hA0 <-DM status on bit 4 (normal, DM low)
h40 = hB0 <-DP status on bit 4 (normal, DP high)
h00 = hB0 <-DM status on bit 4 (DP + DM shorted together)
h40 = hA0 <-DP status on bit 4 (DP shorted to ground)
Exit Test Mode:
hB2, h80 <-soft reset (end test)
8.5.2 USB DM Test Procedure
I2C Commands to use DM pull-up to test DP/DM continuity:
Enable GPIOs and DM Pull-up:
h00, hA0 <-set gpio0 to push-pull output mode
h40, hA0 <-set gpio1 to push-pull output mode
hD5, h28
hD6, h04
hD7, h08 <-DM pull-up is now on
hCE, h18
hDC, h15 <-mux DP / DM status onto GPIO lines
Status Readback Check:
h00 = hB0 <-DM status on bit 4 (normal, DM high)
h40 = hA0 <-DP status on bit 4 (normal, DP low)
h40 = hB0 <-DP status on bit 4 (DP + DM shorted together)
h00 = hA0 <-DM status on bit 4 (DM shorted to ground)
Exit Test Mode:
hB2, h80 <-soft reset (end test)
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8.6 I2C Target Interface
I2C target interface enables access to internal registers by the system application processor. The primary
function of the interface is to enable configuring various PHY parameters, controlling the GPIO pins, and
enabling USB-BC functions. TUSB2E11 repeater functions will operate upon power up without requiring I2C
configuration.
TUSB2E11 has I2C 7-bit target address of 0x3E. 8-bit address of Write: 0x7C and Read: 0x7D.
I2C default target address could be changed at the factory through one time programming.
I2C drive strength could be changed through the I2C.
表8-3. Recommended I2C Drive Strength for I2C Bus Speed, Bus Pull Up and Bus Capacitance
I2C FM+ (1 MHz Max)
I2C drive strength (IOL) selection
I2C bus pull up RPU
C(bus) pF
10-50
1 kΩ
≅8 mA
≅8 mA
N/A
2.2 kΩ
≅4 mA
N/A
4 kΩ
N/A
N/A
N/A
N/A
7 kΩ
N/A
N/A
N/A
N/A
10-90
10-150
10-200
N/A
N/A
N/A
I2C FM (400kHz Max)
I2C drive strength (IOL) selection
I2C bus pull up RPU
C(bus) pF
10-50
1 kΩ
≅8 mA
≅8 mA
≅8 mA
≅8 mA
2.2 kΩ
≅4 mA
≅4 mA
≅8 mA
N/A
4 kΩ
≅2 mA
N/A
7 kΩ
N/A
N/A
N/A
N/A
10-90
10-150
10-200
N/A
N/A
I2C STD (100 kHz Max)
I2C drive strength (IOL) selection
I2C bus pull up RPU
C(bus) pF
10-50
1 kΩ
≅8 mA
≅8 mA
≅8 mA
≅8 mA
2.2 kΩ
≅4 mA
≅4 mA
≅4 mA
≅4 mA
4 kΩ
≅2 mA
≅2 mA
≅2 mA
≅2 mA
7 kΩ
≅1 mA
≅1 mA
≅2 mA
≅2 mA
10-90
10-150
10-200
图8-6. I2C Write with Data
The following procedure should be followed to write data to TUSB2E11 I2C registers (refer to 图8-6):
1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the address cycle.
3. The host presents the register offset within TUSB2E11 to be written, consisting of one byte of data, MSB-
first.
4. The TUSB2E11 acknowledges the sub-address cycle.
5. The host presents the first byte of data to be written to the I2C register.
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6. The TUSB2E11 acknowledges the byte transfer.
7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB2E11.
8. The host terminates the write operation by generating a stop condition (P).
图8-7. I2C Read Without Repeated Start
The following procedure should be followed to read the TUSB2E11 I2C registers without a repeated Start (refer
图8-7).
1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit
address and a zero-value “W/R”bit to indicate a read cycle.
2. The TUSB2E11 acknowledges the 7-bit address cycle.
3. Following the acknowledge the host continues sending clock.
4. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at register 00h or last read
register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB2E11 shall start at the
register offset specified in the write.
5. The TUSB2E11 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after
each byte transfer; the I2C host acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a
NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
7. The host terminates the write operation by generating a stop condition (P).
图8-8. I2C Read with Repeated Start
The following procedure should be followed to read the TUSB2E11 I2C registers with a repeated Start (refer 图
8-8).
1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the 7-bit address cycle.
3. The host presents the register offset within TUSB2E11 to be written, consisting of one byte of data, MSB-
first.
4. The TUSB2E11 acknowledges the register offset cycle.
5. The host presents a repeated start condition (Sr).
6. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit
address and a one-value “W/R”bit to indicate a read cycle.
7. The TUSB2E11 acknowledges the 7-bit address cycle.
8. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at the register offset.
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9. The TUSB2E11 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after
each byte transfer; the I2C host acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a
NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
11. The host terminates the read operation by generating a stop condition (P).
图8-9. I2C Write Without Data
The following procedure should be followed for setting a starting sub-address for I2C reads (refer to 图8-9).
1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the address cycle.
3. The host presents the register offset within TUSB2E11 to be written, consisting of one byte of data, MSB-
first.
4. The TUSB2E11 acknowledges the register offset cycle.
5. The host terminates the write operation by generating a stop condition (P).
备注
After initial power-up, if no register offset is included for the read procedure (refer to 图 8-7), then
reads start at register offset 00h and continue byte by byte through the registers until the I2C host
terminates the read operation. During a read operation, the TUSB2E11 auto-increments the I2C
internal register address of the last byte transferred independent of whether or not an ACK was
received from the I2C host.
70%
SDA
30%
t
t
R
t
F
HDSTA
tHIGH
t
t
LOW
BUF
70%
30%
SCL
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
图8-10. I2C Timing Diagram
9 Register Access Protocol (RAP)
The repeater in TUSB2E11 supports the register access protocol (RAP) over eUSB2 to allow access to its
related registers.
RAP accessible registers are indicated with corresponding RAP addresses in the register map. Default value of
a subset of the registers are factory programmable and are indicated in register map.
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10 Register Map
10.1 TUSB2E11 Registers
表 10-1 lists the TUSB2E11 registers. All register offset addresses not listed in 表 10-1 should be considered as
reserved locations and the register contents should not be modified.
表10-1. TUSB2E11 Registers
Offset
70h
71h
72h
73h
77h
78h
79h
0h
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
U_TX_ADJUST_PORT1
U_HS_TX_PRE_EMPHASIS_P1
U_RX_ADJUST_PORT1
U_DISCONNECT_SQUELCH_PORT1
E_HS_TX_PRE_EMPHASIS_P1
E_TX_ADJUST_PORT1
E_RX_ADJUST_PORT1
GPIO0_CONFIG
RAP Register for Port 1 (0h), Default through OTP
RAP Register for Port 1 (1h), Default through OTP
RAP Register for Port 1 (2h), Default through OTP
RAP Register for Port 1 (3h), Default through OTP
RAP Register for Port 1 (7h), Default through OTP
RAP Register for Port 1 (8h), Default through OTP
RAP Register for Port 1 (9h), Default through OTP
40h
50h
B0h
B2h
B3h
B4h
B6h
B7h
A3h
A4h
60h
F5h
GPIO1_CONFIG
UART_PORT1
RAP Register for Port 1 (20h)
REV_ID
GLOBAL_CONFIG
INT_ENABLE_1
INT_ENABLE_2
BC_CONTROL
BC_STATUS_1
INT_STATUS_1
INT_STATUS_2
CONFIG_PORT1
TEST_MODE1
Complex bit access types are encoded to fit into small table cells. 表 10-2 shows the codes that are used for
access types in this section.
表10-2. TUSB2E11 Access Type Codes
Access Type
Code
Description
Read Type
H
H
R
Set or cleared by hardware
Read
R
RH
R
H
Read
Set or cleared by hardware
Write Type
W
W
Write
W1C
W
Write
1C
1 to clear
WtoP
W
Write
Reset or Default Value
- n
Value after reset or the default value
10.1.1 GPIO0_CONFIG Register (Offset = 00h) [Reset = 00h]
GPIO0_CONFIG is shown in GPIO0_CONFIG Register Field Descriptions.
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Return to the Summary Table.
表10-3. GPIO0_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO0_OD_PP
R/W
0h
GPIO0 output type
0h = open drain output
1h = push pull ouput
6
5
Reserved
R
0h
0h
Reserved
GPIO0_DIRECTION
R/W
GPIO0 direction
0h = input
1h = output
4
GPIO0_INPUT_STATUS RH
0h
0h
Logical value of GPIO0 pin input
(0=Low, 1=High)
0h = input is low
1h = input is high
3-0
GPIO0_OUTPUT_SELEC R/W
T
Dh = HIGH_OUTPUT –output is forced static high
Eh = LOW_OUTPUT –output is forced static low
10.1.2 GPIO1_CONFIG Register (Offset = 40h) [Reset = 00h]
GPIO1_CONFIG is shown in GPIO1_CONFIG Register Field Descriptions.
Return to the Summary Table.
表10-4. GPIO1_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_OD_PP
R/W
0h
GPIO1 output type selection
0h = open drain output
1h = push pull ouput
6
5
4
GPIO1_IN_TRIGGER_TY R/W
PE
0h
0h
0h
GPIO1 input trigger type selection for interrupt
0h = edge trigger input
1h = level trigger input (GPIO2 output will reflect the input level state)
GPIO1_DIRECTION
R/W
GPIO1 direction selection
0h = input
1h = output
GPIO1_INPUT_STATUS RH
Logical value of GPIO1 pin input status
(0=Low, 1=High)
0h = input is low
1h = input is high
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表10-4. GPIO1_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
GPIO1_OUTPUT_SELEC R/W
T
0h
GPIO1 output selection
0h = Remote wakeup –host repeater is receiving remote wake but
has not seen start of resume
1h = USB disconnect –host repeater is actively forwarding LS/FS
disconnect.
2h = USB_HS_Unsquelched –host repeater in L0 seeing USB HS
or in reset seeing Chirp
3h = PVTB –HOST repeater is actively transmitting ESE1 due to
HS disconnect.
4h = DEFAULT –waiting to be configured host/peripheral
5h = HOST –in host repeater mode
6h = PERIPHERAL –in peripheral repeater mode
7h = CONNECTED –repeater is connected, connection seen
acknowledged by start of reset
8h = RESET –reset in progress, reset is detected is high, L0 is low
9h = L0 –fully configured and repeating data, keep-alive and reset/
disconnect
Ah = L1 –device has received CM.FS/CM.L1,has stopped
repeating and is waiting for wake or resume
Bh = L2 –device has received CM.L2, has stopped repeating and is
waiting for wake or resume.
Ch = GPIO1_HS_TEST –in host repeater in L0 mode, received
CM.TEST
Dh = HIGH_OUTPUT –output is forced static high
Eh = LOW_OUTPUT –output is forced static low
Fh = OVP –over voltage (DP/DN voltage > VOVP_TH) detected on
the USB DP/DN
10.1.3 U_TX_ADJUST_PORT1 Register (Offset = 70h) [Reset = 7Ch]
U_TX_ADJUST_PORT1 is shown in 表10-5.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
表10-5. U_TX_ADJUST_PORT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
U_HS_TERM_P1
RH/W
1h
0h = 42.75 Ω(typical)
1h = 45 Ω(typical) (default)
2h = 47.25 Ω(typical)
3h = 49.5 Ω(typical)
5-4
U_HS_TX_SLEW_RATE_ RH/W
P1
3h
0h = 425 ps (typical)
1h = 465 ps (typical)
2h = 510 ps (typical)
3h = 625 ps (typical) (OTP default)
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表10-5. U_TX_ADJUST_PORT1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
U_HS_TX_AMPLITUDE_ RH/W
P1
Ch
0h = 800 mV –7.5%, 740 mV (typical)
1h = 800 mV –5.0%, 760 mV (typical)
2h = 800 mV –2.5%, 780 mV (typical)
3h = 800 mV (USB 2.0 spec nominal), 800 mV (typical) (B0 OTP
default)
4h = 800 mV + 2.5%, 820 mV (typical)
5h = 800 mV + 5.0%, 840 mV (typical)
6h = 800 mV + 7.5%, 860 mV (typical)
7h = 800 mV + 10%, 880 mV (typical)
8h = 800 mV + 12.5%, 900 mV (typical)
9h = 800 mV + 15%, 920 mV (typical)
Ah = 800 mV + 17.5%, 940 mV (typical)
Bh = 800 mV + 20%, 960 mV (typical)
Ch = 800 mV + 22.5%, 980 mV (typical) (B1 OTP default)
Dh = 800 mV + 25%, 1000 mV (typical)
Eh = 800 mV + 27.5%, 1020 mV (typical)
Fh = 800 mV + 30%, 1040 mV (typical)
10.1.4 U_HS_TX_PRE_EMPHASIS_P1 Register (Offset = 71h) [Reset =3Ch]
U_HS_TX_PRE_EMPHASIS_P1 is shown in 表10-6.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
表10-6. U_HS_TX_PRE_EMPHASIS_P1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CDP_2_EN_P1
RH/W
0h
0h = CDP advertising disabled
1h = CDP advertising enabled
6
Reserved
RH/W
0h
3h
Reserved
5-4
U_HS_TX_PE_WIDTH_P RH/W
1
0h = 0.35 UI (typical)
1h = 0.45 UI (typical)
2h = 0.55 UI (typical)
3h = 0.65 UI (typical) (OTP default)
3
U_HS_TX_PE_ENABLE_ RH/W
P1
1h
4h
USB HS TX pre-emphasis enable
Default through OTP
PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK)
0h = Disabled
1h = Enabled (OTP default)
2-0
U_HS_TX_PRE_EMPHAS RH/W
IS_P1
0h = 0.5 dB (typical) (B0 OTP default)
1h = 0.9 dB (typical)
2h = 1.2 dB (typical)
3h = 1.7 dB (typical)
4h = 2.1 dB (typical) (B1 OTP default)
5h = 2.5 dB (typical)
6h = not recommended
7h = not recommended
10.1.5 U_RX_ADJUST_PORT1 Register (Offset = 72h) [Reset = 92h]
U_RX_ADJUST_PORT1 is shown in 表10-7.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
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表10-7. U_RX_ADJUST_PORT1 Register Field Descriptions
Bit
7-4
3
Field
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
U_EQ_P1
RH/W
RH/W
RH/W
9h
0h
2-0
2h
0h = 0.06 dB (typical) (B0 OTP default)
1h = 0.58 dB (typical)
2h = 1.09 dB (typical) (B1 OTP default)
3h = 1.56 dB (typical)
4h = 2.26 dB (typical)
5h = 2.67 dB (typical)
6h = 3.03 dB (typical)
7h = 3.35 dB (typical)
10.1.6 U_DISCONNECT_SQUELCH_PORT1 Register (Offset = 73h) [Reset = 83h]
U_DISCONNECT_SQUELCH_PORT1 is shown in 表10-8.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
表10-8. U_DISCONNECT_SQUELCH_PORT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
U_DISCONNECT_THRES RH/W
HOLD_P1
8h
0h = 525 mV (minimum), 0% (B0 OTP default)
1h = 545 mV (minimum), +4%
2h = 565 mV (minimum), +8%
3h = 585 mV (minimum), +11%
4h = 605 mV (minimum), +15%
5h = 625 mV (minimum), +19%
6h = 645 mV (minimum), +23%
7h = 665 mV (minimum), +27%
8h = 685 mV (minimum) (B1 OTP default), +31%
9h = 705 mV (minimum), +34%
Ah = 725 mV (minimum), +38%
Bh = 745 mV (minimum), +42%
Ch = 765 mV (minimum), +46%
Dh = 785 mV (minimum), +50%
Eh = 805 mV (minimum), +53%
Fh = 825 mV (minimum), +57%
3
Reserved
RH/W
0h
3h
Reserved
2-0
U_SQUELCH_THRESHO RH/W
LD_P1
0h = 130 mV (minimum), +30%
1h = 124 mV (minimum), +24%
2h = 117 mV (minimum), +17%
3h = 111 mV (minimum), +11% (B1 OTP default)
4h = 104 mV (minimum), +4% (B0 OTP default)
5h = 98 mV (minimum), −2%
6h = 91 mV (minimum), −9%
7h = 85 mV (minimum), −15%
10.1.7 E_HS_TX_PRE_EMPHASIS_P1 Register (Offset = 77h) [Reset = 0h]
E_HS_TX_PRE_EMPHASIS_P1 is shown in 表10-9.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
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表10-9. E_HS_TX_PRE_EMPHASIS_P1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
E_HS_TX_PRE_EMPHAS RH/W
IS_P1
0h
0h = 0 dB (typical) (default)
1h = 0.67 dB (typical)
2h = 1.29 dB (typical)
3h = 1.87 dB (typical)
4h = 2.41 dB (typical)
5h = 2.92 dB (typical)
6h = 3.41 dB (typical)
7h = 3.86 dB (typical)
4-3
E_HS_TX_PE_WIDTH_P RH/W
1
0h
0h = 0.40 UI (typical) (default)
1h = 0.5 UI (typical)
2h = 0.55 UI (typical)
3h = 0.65 UI (typical)
2-1
0
Reserved
RH/W
0h
0h
Reserved
BC_DETECTION_ENABL RH/W
E_P1
Enables battery charger (BC) detection during peripheral repeater
mode. BC detection is disabled if the corresponding register is
written low.
Detection enable is further gated with connect announcement by
SoC. After detection attempt completes, repeater will enable the pull
up.
0h = detection disabled.
1h = detection enabled
10.1.8 E_TX_ADJUST_PORT1 Register (Offset = 78h) [Reset = 0Bh]
E_TX_ADJUST_PORT1 is shown in 表10-10.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
表10-10. E_TX_ADJUST_PORT1 Register Field Descriptions
Bit
7
Field
Type
Reset
0h
Description
Reserved
RH/W
RH/W
Reserved
6
Autoresume Disable
0h
Added in B1
0h = autoresume enabled
1h = autoresume disabled
5
Reserved
RH/W
0h
1h
Reserved
4-3
E_HS_TX_SLEW_RATE_ RH/W
P1
0h = 390 ps (typical)
1h = 440 ps (typical) (default)
2h = 460 ps (typical)
3h = 490 ps (typical)
2-0
E_HS_TX_AMPLITUDE_ RH/W
P1
3h
0h = 360 mV (typical)
1h = 380 mV (typical)
2h = 400 mV (typical)
3h = 420 mV (typical) (default)
4h = 440 mV (typical)
5h = 460 mV (typical)
6h = 480 mV (typical)
7h = 500 mV (typical)
10.1.9 E_RX_ADJUST_PORT1 Register (Offset = 79h) [Reset = 60h]
E_RX_ADJUST_PORT1 is shown in 表10-11.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
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表10-11. E_RX_ADJUST_PORT1 Register Field Descriptions
Bit
7
Field
Reserved
Type
Reset
Description
RH/W
0h
Reserved
6-4
E_SQUELCH_THRESHO RH/W
LD_P1
6h
0h = 104 mV (typical)
1h = 101 mV (typical)
2h = 98 mV (typical)
3h = 90 mV (typical)
4h = 81 mV (typical) (B0 OTP default)
5h = 73 mV (typical)
6h = 67 mV (typical) (B1 OTP default)
7h = 60 mV (typical)
3-0
E_EQ_P1
RH/W
0h
0h = 0.34 dB (typical) (default)
1h = 0.71 dB (typical)
2h = 1.02 dB (typical)
3h = 1.36 dB (typical)
4h = 1.64 dB (typical)
5h = 1.94 dB (typical)
6h = 2.19 dB (typical)
7h = 2.45 dB (typical)
8h = 2.69 dB (typical)
9h = 2.93 dB (typical)
Ah = 3.13 dB (typical)
Bh = 3.35 dB (typical)
Ch = 3.53 dB (typical)
Dh = 3.72 dB (typical)
Eh = 3.89 dB (typical)
Fh = 4.07 dB (typical)
10.1.10 UART_PORT1 Register (Offset = 50h) [Reset = 02h]
UART_PORT1 is shown in 表10-12.
Return to the Summary Table.
表10-12. UART_PORT1 Register Field Descriptions
Bit
7-6
4
Field
Type
R/W
R/W
Reset
Description
Reserved
uart_cross_P1
0h
Reserved
0h
Select whether plus and minus pins are crossed between USB 2.0
and eUSB2 during UART mode
0h = if UART mode is enabled, pair eD+ with D+ and eD- with D-
1h = if UART mode is enabled, pair eD+ with D- and eD- with D+
3
2
UART_use_bit1_P1
R/W
0h
0h
Select whether UART enable select is set by register bit 1 or not
0h = bit 1 ignored. UART mode enabled by GPIO0
1h = bit 1 (UART_en_by_reg_not_pin_P1) enabled
UART_dir_not_Carkit_P1 R/W
Set UART mode, direction, low for Carkit and high for opposite
0h = UART mode uses Carkit directions, D+ to eUSB2 and eD- to
USB 2.0
1h = UART mode directions are opposite of Carkit, D- to eUSB2 and
eD+ to USB 2.0
1
0
UART_en_by_reg_not_pin R/W
_P1
1h
0h
Select whether Carkit UART mode is enabled by register or by
GPIO0 pin
0h = select GPIO0 pin to enable UART mode
1h = select UART_mode_en_P1 register to enable UART mode
UART_mode_en_P1
R/W
If GPIO0 is not selected to enable Carkit UART mode, this register
will enable it.
0h = disable UART mode between eUSB2 and USB 2.0 pins
1h = enable UART mode between eUSB2 and USB 2.0 pins
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10.1.11 REV_ID Register (Offset = B0h) [Reset = 02h]
REV_ID is shown in 表10-13.
Return to the Summary Table.
表10-13. REV_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
REV_ID
RH
02h
Device revision.
01h = A0
02h = B0
03h = B1
10.1.12 GLOBAL_CONFIG Register (Offset = B2h) [Reset = 0h]
GLOBAL_CONFIG is shown in 表10-14.
Return to the Summary Table.
表10-14. GLOBAL_CONFIG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
SOFT_RST
DISABLE_P1
HWtoP
0h
Writing a 1 to this field is equivalent to pulsing RESETB low
6
R/W
0h
Disabled Mode Repeater 1 (I2C will remain Active)
(If port is not disconnected, wait until disconnect event to disable the
repeater)
0h = repeater enabled
1h = repeater disabled
5
4
Reserved
R
0h
0h
Reserved
GPIO2_OUT_TYPE
R/W
GPIO2 output type
0h = open drain
1h = push-pull
3
GPIO2_POLARITY
Reserved
R/W
R
0h
0h
GPIO2 pin polarity in push-pull mode only (open drain mode will
always be active low)
0h = active high
1h = active low
2-0
Reserved
10.1.13 INT_ENABLE_1 Register (Offset = B3h) [Reset = 00h]
INT_ENABLE_1 is shown in INT_ENABLE_1 Register Field Descriptions.
Return to the Summary Table.
表10-15. INT_ENABLE_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_RISING_EDGE
R/W
0h
INT_GPIO1_RISING_EDGE enable.
When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt
on Rising Edge of GPIO1.
When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables
interrupt when GPIO1 = High.
0h = not enabled
1h = enabled
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表10-15. INT_ENABLE_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
GPIO1_FALLING_EDGE R/W
0h
INT_GPIO1_FALLING_EDGE enable.
When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt
on Falling Edge of GPIO1.
When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables
interrupt when GPIO1 = Low.
0h = not enabled
1h = enabled
5
4
3
Reserved
Reserved
R
R
0h
0h
0h
Reserved
Reserved
USB_REMOTE_WAKE_P R/W
1
INT_USB_REMOTE_WAKE_P1 enable.
See L2 State Interrupt Modes
0h = not enabled
1h = enabled
2
USB_DISCONNECT_P1 R/W
0h
INT_USB_DISCONNECT_P1 enable.
See L2 State Interrupt Modes
0h = not enabled
1h = enabled
1
0
Reserved
Reserved
R
R
0h
0h
Reserved
Reserved
10.1.14 INT_ENABLE_2 Register (Offset = B4h) [Reset = 00h]
INT_ENABLE_2 is shown in INT_ENABLE_2 Register Field Descriptions.
Return to the Summary Table.
表10-16. INT_ENABLE_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_OVERRIDE_EN
R/W
0h
Override GPIO2 INT output
0h = not enabled
1h = enabled
See INT_VALUE
6
INT_VALUE
R/W
0h
Value to drive on GPIO2 when INT_OVERRIDE_EN=1
GPIO2 output pin will indicate the interrupt assertion. It will follow the
GPIO2 pin configuration.
In open drain mode it will be active low to indicate interrupt assertion
and in push-pull mode it will follow active low/high configuration to
indicate GPIO2 assertion.
0h = output: interrupt not asserted
1h = output: interrupt asserted
5
BC_CHG_DET_P1
Reserved
R/W
R
0h
INT_BC_CHG_DET_P1 enable.
0h = not enabled
1h = enabled
4
3
0h
0h
Reserved
USB_DETECT_ATTACH_ R/W
P1
INT_USB_DET_ATTACH_P1 enable.
Enable device attach detection while eDSP is powered down
See Attach Detect Interrupt Mode
0h = not enabled
1h = enabled
2
1
Reserved
R
0h
0h
Reserved
USB_OVP_P1
R/W
Over Voltage Port 1 interrupt enable
0h = not enabled
1h = enabled
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表10-16. INT_ENABLE_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
Reserved
R
0h
Reserved
10.1.15 BC_CONTROL Register (Offset = B6h) [Reset = C0]
BC_CONTROL is shown in BC_CONTROL Register Field Descriptions.
Return to the Summary Table.
表10-17. BC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
i2c_ds_config
RH/W
3h
I2C open drain output drive strength selection
This is intended to be set through I2C.
0h ≅1 mA (typical)
1h ≅2 mA (typical)
2h ≅4 mA (typical)
3h ≅8 mA (typical) (default)
5-4
DEFAULT_STATE_BC_P1 RH/W
0h
Battery charger advertisement or detection selected for default state
of eUSB2 repeater
0h = neither detect nor advertise charger
1h = detect charger starting when GPIO1 goes high.
2h = advertise short mode DCP. DCP is 1.2 V if 1P2V_MODE is '1'
else pure BC 1.2 DCP
3h = auto-cycle ACP3 to short mode DCP. Short mode will pass
through 1.2V DCP for 12 seconds prior to pure BC 1.2 DCP if
1P2V_MODE is '1'
3
2
VBUS_CONTROL_POLA RH/W
RITY
0h
0h
Select polarity of VBUS control output pin
0h = active high
1h = active low
1P2V_MODE_DIS
RH/W
Disable advertising 1.2 V mode in default state whether enabled to
auto-cycle or not
0h = 1.2 V mode enabled
1h = 1.2 V mode disabled
1
0
INT_PIN_FUNCTION
CHG_DET_POLARITY
RH/W
RH/W
0h
0h
Select function of GPIO2 pin in I2C mode
0h = INT (interrupt)
1h = CHG_DET (Charger Detected)
Select polarity of CHG_DET I2C mode status output pin
0h = active low
1h = active high
10.1.16 BC_STATUS_1 Register (Offset = B7h) [Reset = 00h]
BC_STATUS_1 is shown in BC_STATUS_1 Register Field Descriptions.
Return to the Summary Table.
表10-18. BC_STATUS_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserverd
RH
0h
Reserved
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表10-18. BC_STATUS_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-4
CHARGER_TYPE_DET_ RH
0h
Type of battery charger detected on Port 1
P1
0h = SDP –500 mA
1h = divider 0 –500 mA
2h = divider 1 –1 A
3h = CDP –1.5 A
4h = BC 1.2 DCP –1.5 A
5h = 1.2 V pullup and short –2 A
6h = divider 2 –2.1 A
7h = divider 3 –2.4 A
3
Reserverd
RH
RH
0h
0h
Reserved
2-0
Auto_DCP_STATE_P1
State of auto-DCP sequence on Port 1
0h = no advertisement
5h = divider 3 (2.4 A)
6h = 1.2 V pullup and short
7h = BC 1.2 DCP
10.1.17 INT_STATUS_1 Register (Offset = A3h) [Reset = 00h]
INT_STATUS_1 is shown in INT_STATUS_1 Register Field Descriptions.
Return to the Summary Table.
表10-19. INT_STATUS_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_GPIO1_RISING_ED R/W1C
GE
0h
GPIO1 Rising Edge enable
0h = no interrupt
1h = interrupt
6
INT_GPIO1_FALLING_ED R/W1C
GE
0h
GPIO1 Falling Edge enable
0h = no interrupt
1h = interrupt
5
4
3
Reserved
Reserved
R
R
0h
0h
0h
Reserved
Reserved
INT_USB_REMOTE_WAK R/W1C
E_P1
Remote Wake Event Detect on USB Port 1
See L2 State Interrupt Modes
0h = no interrupt
1h = interrupt
2
INT_USB_DISCONNECT R/W1C
_P1
0h
0h
Disconnect event has occurred on Port 1
See L2 State Interrupt Modes
0h = no interrupt
1h = interrupt
1-0
Reserved
R
Reserved
10.1.18 INT_STATUS_2 Register (Offset = A4h) [Reset = 00h]
INT_STATUS_2 is shown in INT_STATUS_2 Register Field Descriptions.
Return to the Summary Table.
表10-20. INT_STATUS_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
Reserved
R
0h
Reserved
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表10-20. INT_STATUS_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
INT_BC_CHG_DET_P1
R/W1C
0h
Detected battery charger on Port 1
0h = no interrupt
1h = interrupt
4
3
Reserved
R
0h
0h
Reserved
INT_USB_DET_ATTACH_ R/W1C
P1
Device Attach event has occurred on Port 1 See Attach Detect
Interrupt Mode
0h = no interrupt
1h = interrupt
2
1
Reserved
R
0h
0h
Reserved
INT_USB_OVP_P1
R/W1C
Over voltage condition has occurred (DP/DN)
0h = no interrupt
1h = interrupt
0
Reserved
R
0h
Reserved
10.1.19 CONFIG_PORT1 Register (Offset = 60h) [Reset = 00h]
CONFIG_PORT1 is shown in CONFIG_PORT1 Register Field Descriptions.
Return to the Summary Table.
表10-21. CONFIG_PORT1 Register Field Descriptions
Bit
7-5
4-3
Field
Type
Reset
Description
Reserved
R
0h
Reserved
HOST_DEVICE_P1
RH
0h
Port1 is configured as a Host repeater or a Device repeater
0h = not configured
1h = host repeater
2h = device repeater
3h = reserved
2-1
0
Reserved
R
0h
0h
Reserved
CDP_2_STATUS_P1
RH
Primary detection detected on port1 if CDP_2_EN_P1=1
0h = CDP primary detection detected
1h = CDP primary detection not detected
10.1.20 TEST_MODE1 Register (Offset = F5h) [Reset = 32h]
TEST_MODE1 is shown in TEST_MODE1 Register Field Descriptions.
Return to the Summary Table.
表10-22. TEST_MODE1 Register Field Descriptions
Bit
7-4
3
Field
Type
R/W
R/W
Reset
Description
Reserved
FORCE_HS_L0
0h
Reserved, make sure to rewrite what was read
0h
Force repeater into high-speed L0 state for test purposes only.
0h = normal repeater mode (setting this bit to 0 will not return the
device to normal repeater mode, the device needs to be hard reset,
soft reset or power cycled)
1h = forced high-speed L0 mode
2-0
Reserved
R/W
2h
Reserved, make sure to rewrite what was read
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11 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
11.1 Application Information
TUSB2E11 can be used in either HOST or Peripheral implementation. The mode is configured by the eUSB2
SoC.
11.2 Typical Application
VDD18
VDD12
0.1
F
VDD18
VDD33
1 k
1 kΩ
0.1
F
APU
SCL
SDA
VDD1V8
VDD1V8
VDD3V3
SCL
SDA
Connector
DP
DN
eDP
eDN
DP
DN
Repeater
VBUS
VDD18
VSS GPIO0 GPIO1 RESETB
GPIO2
*
*
20 k
20 k
GND
GPIO2
GPIO0
GPIO1
RESETB
1 M
GND
图11-1. Typical System Implementation Using 1.8 V I2C Variant
The 0.1 µF recommendation per supply pin is based on capacitor placement of 2 mm or less trace length away.
If the placement of capacitor is further away, the value of the capacitor needs to be redetermined to account for
the additional trace inductance and maintain resonance around 12 MHz. Additionally, system power design
should have adequate bulk capacitance to account for maximum transient current expected by the device when
transitioning from low power mode to active mode. GPIO2 can be optionally used as interrupt output. Note that
the pull-up resistor on GPIO[0:2] should be adjusted based on leakage of the APU I/O to ensure VIH and VIL of
GPIO0 are met.
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VDD18
VDD12
0.1
F
VBUS_5V
324 kΩ
SDA
VDD33
100 kΩ
GND
0.1
F
APU
SCL
VDD1V8
VDD1V8
VDD3V3
1.65 k
SCL
SDA
Connector
GND
DP
DN
eDP
eDN
DP
DN
Repeater
VBUS_5V
VDD18
VDD18
VSS GPIO0 GPIO1 RESETB
GPIO2
*
*
20 k
20 k
GND
*
GPIO0
GPIO2
20 k
20 k
100 k
RESETB
GPIO1
*
*
*
20 k
20 k
GND
GND
Charger Detection Status
图11-2. Typical System Implementation Using 1.8 V Variant without I2C (Configured for Charger
Detection)
The 0.1 µF recommendation per supply pin is based on capacitor placement of 2 mm or less trace length away.
If the placement of the capacitor is further away, then the value of the capacitor needs to be redetermined to
account for the additional trace inductance and maintain resonance around 12 MHz. Additionally, system power
design should have adequate bulk capacitance to account for maximum transient current expected by the device
when transitioning from low power mode to active mode. GPIO2 can be optionally used as interrupt output. Note
that the pull-up and pull-down resistors on GPIO[0:2] should be selected based on USB PHY tuning needs. SDA
should be used for Vbus_valid detection with a voltage divider. GPIO1 and GPIO2 can be routed as needed for
charger detection status. Pull-down resistor value on SCL determines the battery charging mode.
11.2.1 Design Requirements
TUSB2E11 requires a valid reset signal as described in the Power Supply Recommendations section.
For design examples, use the parameters shown in 表11-1, 表11-2, and 表11-3.
表11-1. Design Parameters for High Loss USB 2.0 System Using I2C
PARAMETER
VALUE(1)
3.3 V ±10%
1.8 V ±5%
Yes
VDD3V3
VDD1V8
I2C support required in system (Yes or No)
Parameter
Register
Setting
Value
U_TX_ADJUST_PORT1
(Offset = 70h)
USB 2.0 TX Swing (peak to peak)
7Ch
980 mVp-p
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表11-1. Design Parameters for High Loss USB 2.0 System Using I2C (continued)
PARAMETER
VALUE(1)
U_HS_TX_PRE_EMPHASIS_P1
(Offset = 71h)
USB 2.0 TX Pre-emphasis
USB 2.0 RX Equalization
3Ch
92h
83h
83h
2.1 dB
U_RX_ADJUST_PORT1
(Offset = 72h)
1.09 dB
685 mV
111 mV
U_DISCONNECT_SQUELCH_PORT1
(Offset = 73h)
USB 2.0 HS host disconnect threshold (peak differential)
U_DISCONNECT_SQUELCH_PORT1
(Offset = 73h)
USB 2.0 HS squelch/RX sensitivity threshold (peak differential)
表11-2. Design Parameters for Medium Loss USB 2.0 System Using I2C
PARAMETER
VALUE(1)
3.3 V ±10%
1.8 V ±5%
Yes
VDD3V3
VDD1V8
I2C support required in system (Yes or No)
Parameter
Register
Setting
Value
U_TX_ADJUST_PORT1
(Offset = 70h)
USB 2.0 TX Swing (peak to peak)
79h
920 mVp-p
0.9 dB
U_HS_TX_PRE_EMPHASIS_P1
(Offset = 71h)
USB 2.0 TX Pre-emphasis
39h
92h
83h
83h
U_RX_ADJUST_PORT1
(Offset = 72h)
USB 2.0 RX Equalization
1.09 dB
685 mV
111 mV
U_DISCONNECT_SQUELCH_PORT1
(Offset = 73h)
USB 2.0 HS host disconnect threshold (peak differential)
USB 2.0 HS squelch/RX sensitivity threshold (peak differential)
U_DISCONNECT_SQUELCH_PORT1
(Offset = 73h)
(1) These parameters are starting values for a high loss system. Further tuning might be required based on specific loss profile and
measurements.
表11-3. Design Parameters for Medium Loss USB 2.0 System without I2C and Configured for Charger
Detection
PARAMETER
VALUE(1)
3.3 V ±10%
1.8 V ±5%
No
VDD3V3
VDD1V8
I2C support required in system (Yes or No)
SCL (pull-down resistor to ground)
SDA (pull-down resistor to ground)
SDA (pull-up resistor to VBUS5V)
Parameter
1.65 kΩ
100 kΩ
324 kΩ
Value
GPIO0 GPIO1 GPIO2
USB 2.0 TX Swing (peak to peak)
USB 2.0 TX Pre-emphasis
USB 2.0 RX Equalization
Float
Float
Float
Float
Float
Pull-up Pull-up 920 mVp-p
Pull-up Pull-up
Pull-up Pull-up
Pull-up Pull-up
Pull-up Pull-up
0.9 dB
1.09 dB
685 mV
98 mV
USB 2.0 HS host disconnect threshold (peak differential)
USB 2.0 HS squelch/RX sensitivity threshold (peak differential)
(1) These parameters are starting values for a medium loss system. Further tuning might be required based on specific loss profile and
measurements.
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11.2.2 Detailed Design Procedure
The ideal PHY setting is dependent upon the signal chain loss characteristics of the target platform. The
recommendation is to start with lowest level of compensation for TX swing and pre-emphasis, and then
increment until optimal eye diagram margin is achieved. Same applies to the RX sensitivity or squelch threshold
setting where it is recommended to adjust from low threshold until optimum RX sensitivity and squelch margins
are achieved.
To optimize the TUSB2E11 RX equalization, monitor the corresponding TX eye digram to achieve best RX EQ
setting. In other words, to optimize eUSB2 RX equlization, monitor USB 2.0 TX eye and monitor eUSB2.0 TX
eye to optimize USB RX equalization.
HS host disconnect threshold shall be adjusted to provide the most margin to avoid false disconnect as well as
failure to detect a disconnect. See 表8-2.
备注
The TUSB2E11 compensates for extra attenuation in the signal path according to the configuration of
the TX and RX settings. General recommendation is to use just enough pre-emphasis and
equalization to achieve eye margin and not over-equalize to avoid excessive jitter. Maximum PE width
and slew rates are recommended.
11.2.3 Application Curves
U_HS_TX_AMPLITUDE_P1 = 3h
E_HS_TX_AMPLITUDE_P1 = 3h
图11-3. USB 2.0 TX Eye Diagram with Near-End
图11-4. eUSB2 TX Eye Diagram with eTP1
Mask
(Terminated) Mask
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12 Power Supply Recommendations
12.1 Power Up Reset
RESETB pin is active low reset pin and can also be used as a power down pin.
TUSB2E11 does not have power supply sequence requirements between VDD3V3 and VDD1V8.
Maximum VDD3V3 and VDD1V8 ramp time to reach minimum supply voltages should be 2 ms.
Digital and analog inputs may be applied when VDD3V3 and VDD1V8 are in unpowered state.
Internal power on reset circuit along with the external RESETB input pin ensures proper initialization when
RESETB is de-asserted high prior to the power rails being valid. If RESETB de-assert high before the power
supplies are stable, internal power on reset circuit will hold off internal reset until the supplies are stable.
I2C/RAP and eUSB2 interfaces will be ready after t_RH_READY upon de-assertion of RESETB or power up.
I2C/RAP and eUSB2 interfaces will be ready after t_RH_READY upon soft reset through the I2C.
Upon de-assertion of RESETB (after t_RH_READY) or software reset (after t_RH_READY), TUSB2E11 will enable and
enter default state and be ready to accept eUSB2 packets, RAP and I2C requests. The repeater will either be in
host repeater mode or device repeater mode depending on the receipt of either host mode enable or peripheral
mode enable.
13 Layout
13.1 Layout Guidelines
1. Place supply bypass capacitors as close to VDD1V8 and VDD3V3 pins as possible and avoid placing the
bypass caps near the eDP/eDN and DP/DN traces.
2. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections
and impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance
of picking up interference from the other layers of the board. Be careful when designing test points on
twisted pair lines; through-hole pins are not recommended.
3. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
4. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
5. Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub
must be less than 200 mil.
6. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
7. Avoid crossing over anti-etch, commonly found with plane splits.
8. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in 图13-1.
Signal 1
GND Plane
Power Plane
Signal 2
图13-1. Four-Layer Board Stack-Up
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13.2 Example Layout for Application with 1.8 V I2C Variant
图 13-2 shows how GPIO2 can be optionally used as an open drain interrupt output with a pull-up resistor to
VDD18.
VDD18
VDD18
Via to
VDD33
Plane
Via to
VDD18
Plane
Via to
GND
Plane
1k
1k
VDD33
VDD18
GND
GND
GND
GND
SDA
SCL
VDD18
GND
0.1
F
VDD18
VDD33
GPIO2
eDN
DN
eDN
eDP
DN
DP
SoC
eUSB2
USB 2.0
connector
eDP
GPIO0
GPIO1
RESETB
DP
VDD18
20 k
Reset
control
from
1 M
SoC
GND
图13-2. Example Layout for Application with 1.8 V I2C Variant
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14 Device and Documentation Support
14.1 Device Support
14.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
14.2 Documentation Support
14.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, High-Speed Interface Layout Guidelines application note
• USB 2.0 Promoter Group (2000). USB 2.0 Specification USB 2.0 Promoter Group
• USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB
Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum
14.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
14.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
14.5 Trademarks
USB Type-C™ is a trademark of USB Implementers Forum.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
14.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB2E111YCGR
ACTIVE
DSBGA
YCG
15
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-20 to 85
T2E111A
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
YCG0015
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
0.7 TYP
SYMM
E
D
C
1.4
TYP
SYMM
D: Max = 2.034 mm, Min =1.973 mm
E: Max = 1.333 mm, Min =1.273 mm
B
A
0.35
TYP
2
3
0.225
0.185
C A B
15X
0.015
0.35 TYP
4224261/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
15X ( 0.2)
3
1
2
A
(0.35) TYP
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224261/C 12/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YCG0015
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
15X ( 0.21)
1
2
3
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224261/C 12/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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