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TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

TUSB320LI、TUSB320HI USB Type-C 配置通道逻辑和端口控制

1 特性

3 说明

1

•

USB Type-C™规范 1.1

向后兼容 USB Type-C 规范 1.0

支持高达 3A 的电流通告和检测

模式配置

TUSB320LI 和 TUSB320HI 器件（除非另外注明，否

则本文档后续部分将统称为 TUSB320）可在 USB

Type-C 端口上实现 Type-C 生态系统所需的配置通道

(CC) 逻辑。TUSB320 器件使用 CC 引脚来确定端口

的连接状态和电缆方向，以及进行角色检测和 Type-C

电流模式控制。TUSB320 器件可配置为下行端口

(DFP)、上行端口 (UFP) 或双角色端口 (DRP)，因此

成为任何应用的理想选择。

•

–

仅主机 - 下行端口 (DFP)（供电设备）

仅设备 – 上行端口 (UFP)（受电设备）

双角色端口 – DRP

支持 Try.SRC 和 Try.SNK

•

通道配置 (CC)

根据 Type-C 规范，TUSB320 会交替配置为 DFP 或

UFP。CC 逻辑块通过监视 CC1 和 CC2 引脚上的上拉

或下拉电阻，以确定何时连接了 USB 端口、电缆的方

向以及检测到的角色。CC 逻辑根据检测到的角色来确

定 Type-C 电流模式为默认、中等还是高。该逻辑通过

实施 V_BUS检测来确定端口在 UFP 和 DRP 模式下是

否连接成功。

–

V

USB 端口连接检测

电缆方向检测

角色检测

Type-C 电流模式（默认、中等和高）

_BUS检测

I²C 或 GPIO 控制

•

通过 I²C 实现角色配置控制

电源电压：2.7V 至 5V

低电流消耗

该系列器件能够在宽电源范围内工作，并且具有较低功

耗。TUSB320 提供两种使能版本：低电平有效使能，

称为 TUSB320LI；高电平有效使能，称为

TUSB320HI。TUSB320 系列器件适用于工业级温度范

围。

工业温度范围：–40°C 至 85°C

2 应用

器件信息⁽¹⁾

•

主机、设备、双角色端口应用

移动电话

器件型号

TUSB320HI

TUSB320LI

封装

X2QFN (12)

封装尺寸（标称值）

1.60mm x 1.60mm

平板电脑和笔记本电脑

USB 外设

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

简化电路原理图

示例应用

VBUS

Detection

VBUS

CC Logic

For Mode

Configuration and

Detection

CC1

CC2

I2C

GPIO

Controller

GPIOs

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEP2

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

7.5 Register Maps......................................................... 16

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Application .................................................. 21

8.3 Initialization Set Up ................................................ 28

Power Supply Recommendations...................... 28

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Switching Characteristics.......................................... 6

Detailed Description .............................................. 8

7.1 Overview ................................................................... 8

7.2 Feature Description................................................... 9

7.3 Device Functional Modes........................................ 13

7.4 Programming........................................................... 15

8

9

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 29

11 器件和文档支持 ..................................................... 30

11.1 相关链接................................................................ 30

11.2 接收文档更新通知 ................................................. 30

11.3 社区资源................................................................ 30

11.4 商标....................................................................... 30

11.5 静电放电警告......................................................... 30

11.6 Glossary................................................................ 30

12 机械、封装和可订购信息....................................... 30

7

4 修订历史记录

Changes from Revision C (October 2016) to Revision D

Page

•

Changed R_VBUSvalues From: MIN = 891, TYP = 900, MAX = 909 KΩ To: MIN = 855, TYP = 887, MAX = 920 KΩ ........... 6

Changes from Revision B (September 2016) to Revision C

Page

•

Changed text for Pin 7 in the Pin Functions table From: "default current mode detected (H); medium or high current

mode detected (L)." To: "Refer to Table 3 for more details." ................................................................................................. 3

Changed text for Pin 8 in the Pin Functions table From: "default or medium current mode detected (H); high current

mode detected (L)." To: "Refer to Table 3 for more details." ................................................................................................. 3

Changes from Revision A (February 2016) to Revision B

Page

•

Changed pins CC1 and CC2 values From: MIN = –0.3 MAX = V_DD+ 0.3 To: MIN –0.3 MAX = 6 in the Absolute

Maximum Ratings................................................................................................................................................................... 4

Changes from Original (August 2015) to Revision A

Page

•

Added Note 1 and 2 to the Pin Functions table...................................................................................................................... 3

Changed the DESCRIPTION of pin EN_N pin in the Pin Functions table ............................................................................. 4

Changed the DESCRIPTION of pin EN pin in the Pin Functions table.................................................................................. 4

Changed the DESCRIPTION of pin V_DDin the Pin Functions table ....................................................................................... 4

Added Note 2 to the Electrical Characteristics table ............................................................................................................. 5

Added Test Condition "See Figure 1" to VBUS_THR in the Electrical Characteristics ......................................................... 6

Replaced the Timing Requirements table ............................................................................................................................. 6

Added Note: "SW must make sure..." to the Description of INTERRUPT_STATUS in Table 9 ......................................... 18

Added text to list item 2 in the TUSB320L Initialization Procedure section ......................................................................... 28

Added text to list item 2 in the TUSB320H Initialization Procedure section......................................................................... 28

2

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

5 Pin Configuration and Functions

RWB Package

12-Pin X2QFN

TUSB320L Top View

RWB Package

12-Pin X2QFN

TUSB320H Top View

2

1

2

1

PORT

VBUS_DET

ADDR

3

4

5

6

12

11

10

9

VDD

PORT

VBUS_DET

ADDR

3

4

5

6

12

11

10

9

VDD

EN_N

EN

GND

ID

GND

INT_N/OUT3

ID

7

8

7

8

Pin Functions

NO.

TYPE

DESCRIPTION

NAME

TUSB320L

TUSB320H

CC1

CC2

1

2

1

2

I/O

Type-C configuration channel signal 1

Type-C configuration channel signal 2

Tri-level input pin to indicate port mode. The state of this pin is sampled when TUSB320L's

EN_N is asserted low, TUSB320H's EN is asserted high, and VDD is active. This pin is also

sampled following a I2C_SOFT_RESET.

PORT⁽¹⁾

3

I

H - DFP (Pull-up to V_DDif DFP mode is desired)

NC - DRP (Leave unconnected if DRP mode is desired)

L - UFP (Pull-down or tie to GND if UFP mode is desired)

5- to 28-V V_BUSinput voltage. V_BUSdetection determines UFP attachment. One 900-kΩ

external resistor required between system V_BUSand VBUS_DET pin.

VBUS_DET⁽¹⁾

ADDR⁽¹⁾

4

5

4

5

I

Tri-level input pin to indicate I²C address or GPIO mode:

H - I²C is enabled and I²C 7-bit address is 0x67.

NC - GPIO mode (I²C is disabled)

L - I²C is enabled and I²C 7-bit address is 0x47.

ADDR pin should be pulled up to V_DDif high configuration is desired

The INT_N/OUT3 is a dual-function pin. When used as the INT_N, the pin is an open drain

output in I²C control mode and is an active low interrupt signal for indicating changes in I²C

registers. When used as OUT3, the pin is in audio accessory detect in GPIO mode: no

detection (H), audio accessory connection detected (L).

INT_N/OUT3⁽¹⁾

SDA/OUT1⁽¹⁾⁽²⁾

SCL/OUT2⁽¹⁾⁽²⁾

6

7

8

6

7

8

O

The SDA/OUT1 is a dual-function pin. When I²C is enabled (ADDR pin is high or low), this pin

is the I²C communication data signal. When in GPIO mode (ADDR pin is NC), this pin is an

open drain output for communicating Type-C current mode detect when the device is in UFP

mode: Refer to Table 3 for more details.

I/O

The SCL/OUT2 is a dual function pin. When I²C is enabled (ADDR pin is high or low), this pin

is the I²C communication clock signal. When in GPIO mode (ADDR pin is NC), this pin is an

open drain output for communicating Type-C current mode detect when the device is in UFP

mode: Refer to Table 3 for more details.

Open drain output; asserted low when the CC pins detect device attachment when port is a

source (DFP), or dual-role (DRP) acting as source (DFP).

ID⁽¹⁾

9

O

G

GND

10

Ground

(1) When V_DDis off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, ID, OUT[3:1] pins) could back-drive the TUSB320 device if

not handled properly. When necessary to pull these pins up, it is recommended to pullup PORT, ADDR, INT_N/OUT3, and ID to the

device V_DDsupply. The VBUS_DET must be pulled up to VBUS through a 900-kΩ resistor.

(2) When using the 3.3 V supply for I²C, the end user must ensure that the V_DDis 3 V and above. Otherwise the I²C may back power the

device.

3

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

Pin Functions (continued)

NO.

TYPE

DESCRIPTION

NAME

TUSB320L

TUSB320H

Enable signal; active low. Pulled up to V_DDinternally to disable the TUSB320L device. If

controlled externally, must be held low at least for 50 ms after VDD has reached its valid

voltage level.

EN_N

11

—

I

Enable signal; active high. Pulled down to GND internally to disable the TUSB320H device. If

controlled externally, must be held low at least for 50 ms after VDD has reached its valid

voltage level.

EN

—

11

12

I

V_DD

12

P

Positive supply voltage. V_DDmust ramp within 25 ms or less

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–65

MAX

UNIT

Supply voltage

Control pins

V_DD

6.0

V

CC1, CC2, PORT, ADDR, ID, EN_N, INT_N/OUT3

CC1, CC2

V_DD+ 0.3

6

V_DD+ 0.3

4

V

SDA/OUT1, SCL/OUT2

VBUS_DET , EN

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±5000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

4

NOM

MAX

5

UNIT

V

V_DD

V_BUS

T_A

Supply voltage range

System V_BUSvoltage

5

28

V

TUSB320HI and TUSB320LI Operating free air temperature range

–40

25

85

°C

6.4 Thermal Information

TUSB320

THERMAL METRIC⁽¹⁾

RWB (X2QFN)

12 PINS

169.3

68.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

83.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.2

ψ_JB

83.4

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application

report, SPRA953.

4

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Power Consumption

Current consumption in unattached mode when port is

unconnected and waiting for connection. [V_DD= 4.5 V,

EN_N (TUSB320L) = L, EN (TUSB320H) = H, ADDR = NC,

I_{UNATTACHED_UFP}

100

µA

PORT = L]

Current consumption in active mode. (V_DD= 4.5 V, EN_N

I_{ACTIVE_UFP}

(TUSB320L) = L, EN (TUSB320H) = H, ADDR = NC,

PORT = L)

100

µA

Leakage current when V_DDis supplied, but the TUSB320

device is not enabled. (V_DD= 4.5 V, EN_N (TUSB320L) =

H, EN (TUSB320H) = L)

I_SHUTDOWN

0.040

CC1 and CC2 Pins

R_{CC_DB}

Pulldown resistor when in dead-battery mode.

Pulldown resistor when in UFP or DRP mode.

4.1

4.6

5.1

6.1

5.6

kΩ

R_{CC_D}

Voltage threshold for detecting a DFP attach when

configured as a UFP and DFP is advertising default current

source capability.

V_{TH_UFP_CC_USB}

V_{TH_UFP_CC_MED}

V_{TH_UFP_CC_HIGH}

V_{TH_DFP_CC_USB}

V_{TH_DFP_CC_MED}

V_{TH_DFP_CC_HIGH}

0.15

0.61

1.169

1.51

2.46

0.2

0.66

1.23

1.6

0.25

0.7

V

Voltage threshold for detecting a DFP attach when

configured as a UFP and DFP is advertising medium (1.5

A) current source capability.

Voltage threshold for detecting a DFP attach when

configured as a UFP and DFP is advertising high (3 A)

current source capability.

1.29

1.64

2.74

Voltage threshold for detecting a UFP attach when

configured as a DFP and advertising default current source

capability.

Voltage threshold for detecting a UFP attach when

configured as a DFP and advertising medium current (1.5

A) source capability.

1.6

Voltage threshold for detecting a UFP attach when

configured as a DFP and advertising high current (3.0 A)

source capability.

2.6

Default mode pullup current source when operating in DFP

or DRP mode.

I_{CC_DEFAULT_P}

I_{CC_MED_P}

64

166

304

80

180

330

96

194

356

µA

Medium (1.5 A) mode pullup current source when

operating in DFP or DRP mode.

High (3 A) mode pullup current source when operating in

DFP or DRP mode.⁽¹⁾

I_{CC_HIGH_P}

Control Pins: PORT, ADDR, INT/OUT3, EN_N, EN, ID

Low-level control signal input voltage (PORT, ADDR,

EN_N, EN)

V_IL

V_IM

V_IH

0.4

0.56 × V_DD

V_DD

V

Mid-level control signal input voltage (PORT, ADDR)

0.28 × V_DD

V_DD- 0.3

High-level control signal input voltage (PORT, ADDR,

EN_N)

High-Level control signal input voltage for EN for

TUSB320H

V_{IH_EN}

1.05

3.65

V

I_IH

High-level input current

–20

–10

20

10

µA

I_IL

Low-level input current

R_{EN_N}

Internal pullup resistance for EN_N for TUSB320L

Internal pulldown resistance for EN for TUSB320H

Internal pullup resistance (PORT, ADDR)

Internal pulldown resistance (PORT, ADDR)

1.1

500

588

1.1

MΩ

kΩ

R_EN

(2)

R_pu

kΩ

(2)

R_pd

MΩ

Low-level signal output voltage (open-drain) (INT_N/OUT3,

ID)

V_OL

I_OL= –1.6 mA

0.4

V

External pullup resistor on open drain IOs (INT_N/OUT3,

ID)

R_{p_ODext}

R_{p_TLext}

200

4.7

kΩ

Tri-level input external pullup resistor (PORT, ADDR)

(1) V_DDmust be 3.5 V or greater to advertise 3 A current.

(2) Internal pullup and pulldown for PORT and ADDR are removed after the device has sampled EN = high or EN_N = low.

5

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

I²C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%)⁽³⁾

Supply range for I²C (SDA/OUT1, SCL/OUT2)

V_{DD_I2C}

1.65

1.05

1.8

3.6

0.4

V

V_IH

V_IL

High-level signal voltage

Low-level signal voltage

V_OL

Low-level signal output voltage (open drain)

I_OL= –1.6 mA

See Figure 1

VBUS_DET IO Pins (Connected to System V_BUSsignal)

V_{BUS_THR}

R_VBUS

V_BUSthreshold range

2.95

855

3.30

887

95

3.80

920

V

External resistor between V_BUSand VBUS_DET pin

Internal pulldown resistance for VBUS_DET

KΩ

R_{VBUS_PD}

(3) When using 3.3 V for I²C, customer must ensure V_DDis above 3 V at all times.

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

I²C (SDA, SCL)

t_SU:DAT

t_HD;DAT

t_SU:STA

t_HD:STA

t_SU:STO

t_BUF

Data setup time

100

10

ns

µs

kHz

ns

pF

Data hold time

Set-up time, SCL to start condition

Hold time (repeated), start condition to SCL

Set up time for stop condition

0.6

1.3

Bus free time between a stop and start condition

Data valid time

t_VD;DAT

t_VD;ACK

f_SCL

0.9

Data valid acknowledge time

SCL clock frequency; I²C mode for local I²C control

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

400

300

400

100

t_r

t_f

C_{BUS_100KHZ}Total capacitive load for each bus line when operating at ≤ 100 kHz

C_{BUS_400KHz}Total capacitive load for each bus line when operating at 400 kHz

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

ms

Power on default of CC1 and CC2 voltage debounce

time

t_{CCCB_DEFAULT}

t_{VBUS_DB}

DEBOUCE register = 2'b00

168

2

Debounce of VBUS_DET pin after valid V_{BUS_THR}

ms

t_{DRP_DUTY_CY}Power-on default of percentage of time DRP advertises DRP_DUTY_CYCLE register

30%

DFP during a T_DRP

= 2'b00

CLE

The period during which the TUSB320 in DFP mode

completes a DFP to UFP and back advertisement.

t_DRP

50

26

75

100

ms

Time from TUSB320L's EN_N low or TUSB320H's EN

high and V_DDactive to I²C access available

t_{I2C_EN}

100

95

ms

t_{SOFT_RESET}

Soft reset duration

49

6

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

VBUS

V_{BUS_THR}

T_{VBUS_DB}

0 V

Figure 1. VBUS Detect and Debounce

7

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The USB Type-C ecosystem operates around a small form factor connector and cable that is flippable and

reversible. Because of the nature of the connector, a scheme is needed to determine the connector orientation.

Additional schemes are needed to determine when a USB port is attached and the acting role of the USB port

(DFP, UFP, DRP), as well as to communicate Type-C current capabilities. These schemes are implemented over

the CC pins according to the USB Type-C specifications. The TUSB320 devices provide Configuration Channel

(CC) logic for determining USB port attach and detach, role detection, cable orientation, and Type-C current

mode. The TUSB320 devices also contains several features such as mode configuration and low standby current

which make these devices ideal for source or sinks in USB2.0 applications.

ADDR

3-State Buffer

PORT

CC±

Connection and

cable detection

Digital Controller

CC2

SDA/OUT±

I2C

CSR

SCL/OUT2

Open Drain

Output

CTRL_EN

VBUS Detection

EN_N

EN_N Logic

SYS_VBUS

900 K ±±1

Figure 2. Functional Block Diagram of TUSB320

7.1.1 Cables, Adapters, and Direct Connect Devices

Type-C Specification 1.1 defines several cables, plugs and receptacles to be used to attach ports. The TUSB320

device supports all cables, receptacles, and plugs. The TUSB320 device does not support e-marking.

7.1.1.1 USB Type-C Receptacles and Plugs

Below is list of Type-C receptacles and plugs supported by the TUSB320 device:

•

USB Type-C receptacle for USB2.0 platforms and devices

USB full-featured Type-C plug

USB2.0 Type-C plug

8

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

Overview (continued)

7.1.1.2 USB Type-C Cables

Below is a list of Type-C cables types supported by the TUSB320 device:

•

USB full-featured Type-C cable

USB2.0 Type-C cable with USB2.0 plug

Captive cable on remote device with either a USB full-featured plug or USB2.0 plug

7.1.1.3 Legacy Cables and Adapters

The TUSB320 device supports legacy cable adapters as defined by the Type-C Specification. The cable adapter

must correspond to the mode configuration of the TUSB320 device.

To System VBUS detection

VBUS

900 kΩ 1%

Rp (56k 5%)

VBUS_DET

TUSB320

CC

Rd (5.1k 10%)

Legacy Host Adapter

Figure 3. Legacy Adapter Implementation Circuit

7.1.1.4 Direct Connect Devices

The TUSB320 device supports the attaching and detaching of a direct-connect device.

7.1.1.5 Audio Adapters

Additionally, the TUSB320 device supports audio adapters for audio accessory mode, including:

•

Passive Audio Adapter

Charge Through Audio Adapter

7.2 Feature Description

7.2.1 Port Role Configuration

The TUSB320 device can be configured as a downstream facing port (DFP), upstream facing port (UFP), or

dualrole port (DRP) using the tri-level PORT pin. The PORT pin should be pulled high to V_DDusing a pullup

resistance, low to GND or left as floated on the PCB to achieve the desired mode. This flexibility allows the

TUSB320 device to be used in a variety of applications. The TUSB320 device samples the PORT pin after reset

and maintains the desired mode until the TUSB320 device is reset again. The port role can also be selected

through I²C registers. Table 1 lists the supported features in each mode:

9

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

Feature Description (continued)

Table 1. Supported Features for the TUSB320 Device by Mode

PORT PIN

HIGH

(DFP ONLY)

LOW

(UFP ONLY)

NC

(DRP)

SUPPORTED

FEATURES

Port attach and

detach

Yes

Cable orientation

(through I²C)

Current advertisement

Current detection

Yes

-

Yes (DFP)

Yes (UFP)

Yes

Accessory modes

(audio and debug)

Yes

Try.SRC

Try.SNK

-

Yes

-

Active cable detection

I²C / GPIO

Yes

-

Yes (DFP)

Yes

Legacy cables

V_BUSdetection

Yes

Yes (UFP)

7.2.1.1 Downstream Facing Port (DFP) - Source

The TUSB320 device can be configured as a DFP only by pulling the PORT pin high through a resistance to

V_DD. In DFP mode, the TUSB320 device constantly presents Rps on both CC. In DFP mode, the TUSB320

device initially advertises default USB Type-C current. The Type-C current can be adjusted through I²C if the

system needs to increase the amount advertised. The TUSB320 device adjusts the Rps to match the desired

Type-C current advertisement. In GPIO mode, the TUSB320 device only advertises default Type-C current.

When configured as a DFP, the TUSB320 can operate with older USB Type-C 1.0 devices except for a USB

Type-C 1.0 DRP device. A USB Type-C 1.1 compliant DFP can not connect to a Type-C 1.0 DRP. Because the

TUSB320 is compliant to Type-C 1.1, the TUSB320 can not operate with a USB Type-C 1.0 DRP device. This

limitation is a result of a backwards compatibility problem between USB Type-C 1.1 DFP and a USB Type-C 1.0

DRP.

7.2.1.2 Upstream Facing Port (UFP) - Sink

The TUSB320 device can be configured as a UFP only by pulling the PORT pin low to GND. In UFP mode, the

TUSB320 device constantly presents pulldown resistors (Rd) on both CC pins. The TUSB320 device monitors

the CC pins for the voltage level corresponding to the Type-C mode current advertisement by the connected

DFP. The TUSB320 device debounces the CC pins and wait for V_BUSdetection before successfully attaching. As

a UFP, the TUSB320 device detects and communicates the advertised current level of the DFP to the system

through the OUT1 and OUT2 GPIOs (if in GPIO mode) or through the I²C CURRENT_MODE_DETECT register

one time in the Attached.SNK state.

7.2.1.3 Dual Role Port (DRP)

The TUSB320 device can be configured to operate as a DRP when the PORT pin is left floated on the PCB. In

DRP mode, the TUSB320 device toggles between operating as a DFP and a UFP. When functioning as a DFP in

DRP mode, the TUSB320 device complies with all operations as defined for a DFP according to the Type-C

Specification. When presenting as a UFP in DRP mode, the TUSB320 device operates as defined for a UFP

according to the Type-C Specification.

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The TUSB320 supports two optional Type-C DRP features called Try.SRC and Try.SNK. Products supporting

dual-role functionality may have a need to be a source (DFP) or a sink (UFP) when connected to another dual-

role capable product. For example, a dual-role capable notebook may desire to be a source when connected to a

tablet, or a cell phone would prefer to be a sink when connected to a notebook or tablet. When standard DRP

products (products which don’t support either Try.SRC or Try.SNK) are connected together, the role (UFP or

DFP) outcome is not predetermined. These two optional DRP features provide a means for dual-role capable

products to connect to another dual-role capable product in the role desired. Try.SRC and Try.SNK are only

available when TUSB320 is configured in I2C mode. When operating in GPIO mode, the TUSB320 will always

operate as a standard DRP.

The TUSB320’s Try.SRC feature provides a means for a DRP product to connect as a DFP when connected to

another DRP product that doesn’t implement Try.SRC. When two products which implement Try.SRC are

connected together, the role outcome of either UFP or DFP is the same as a standard DRP. Try.SRC is enabled

by changing I2C register SOURCE_PREF to 2’b11. Once this register is changed to 2’b11, the TUSB320 will

always attempt to connect as a DFP when attached to another DRP capable device.

The TUSB320’s Try.SNK feature provides a method for a DRP product to connect as a UFP when connected to

another DRP product that doesn’t implement Try.SNK. When two products which implement Try.SNK are

connected together, the role outcome of either UFP or DFP is the same as a standard DRP. Try.SNK is enabled

by changing I2C register SOURCE_PREF to 2’b01. Once this register is changed to 2’b01, the TUSB320 will

always attempt to connect as a UFP when attached to another DRP capable device.

7.2.2 Type-C Current Mode

When a valid cable detection and attach have been completed, the DFP has the option to advertise the level of

Type-C current a UFP can sink. The default current advertisement for the TUSB320 device is max of 500 mA (for

USB2.0) or max of 900 mA (for USB3.1). If a higher level of current is available, the I²C registers can be written

to provide medium current at 1.5 A or high current at 3 A. When the CURRENT_MODE_ADVERTISE register

has been written to advertise higher than default current, the DFP adjusts the Rps for the specified current level.

If a DFP advertises 3 A, system designer must ensure that the V_DDof the TUSB320 device is 3.5 V or greater.

Table 2 lists the Type-C current advertisements in GPIO an I²C modes.

Table 2. Type-C Current Advertisement for GPIO and I²C Modes

GPIO MODE (ADDR PIN IN NC)

I²C MODE (ADDR PIN H, L)

TYPE-C CURRENT

UFP (PORT PIN L)

DFP (PORT PIN H)

UFP

DFP

max of 500

mA (USB2.0)

max of 900

mA (USB3.1)

I²C register default is 500

or 900 mA (max)

Default

Only advertisement

N/A

Current mode detected

and output through OUT1

/ OUT2

Current mode detected

and read through I²C

register

Medium - 1.5 A (max)

Advertisement selected

through writing I²C

register

High - 3 A (max)

7.2.3 Accessory Support

The TUSB320 device supports audio and debug accessories in UFP, DFP mode and DRP mode. Audio and

debug accessory support is provided through reading of I²C registers. Audio accessory is also supported through

GPIO mode with INT_N/OUT3 pin (audio accessory is detected when INT_N/OUT3 pin is low).

7.2.3.1 Audio Accessory

Audio accessory mode is supported through two types of adapters. First, the passive audio adapter can be used

to convert the Type-C connector into an audio port. In order to effectively detect the passive audio adapter, the

TUSB320 device must detect a resistance < Ra on both of the CC pins.

Secondly, a charge through audio adapter may be used. The primary difference between a passive and charge

through adapter is that the charge through adapter supplies 500 mA of current over VBUS. The charge through

adapter contains a receptacle and a plug. The plug acts as a DFP and supply V_BUSwhen the plug detects a

connection.

When the TUSB320 device is configured in GPIO mode, OUT3 pin determines if an audio accessory is

connected. When an audio accessory is detected, the OUT3 pin is pulled low.

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7.2.3.2 Debug Accessory

Debug is an additional state supported by USB Type-C. The specification does not define a specific user

scenario for this state, but it is important because the end user could use debug accessory mode to enter a test

state for production specific to the application. Charge through debug accessory is not supported by TUSB320

when in DRP or UFP mode.

7.2.4 I²C and GPIO Control

The TUSB320 device can be configured for I²C communication or GPIO outputs using the ADDR pin. The ADDR

pin is a tri-level control pin. When the ADDR pin is left floating (NC), the TUSB320 device is in GPIO output

mode. When the ADDR pin is pulled high or pulled low, the TUSB320 device is in I²C mode.

All outputs for the TUSB320 device are open drain configuration.

The OUT1 and OUT2 pins are used to output the Type-C current mode when in GPIO mode. Additionally, the

OUT3 pin is used to communicate the audio accessory mode in GPIO mode. Table 3 lists the output pin settings.

See for more information.

Table 3. Simplified Operation for OUT1 and OUT2

OUT1

OUT2

H

L

H

L

Default Current in Unattached State

Default Current in Attached State

Medium Current (1.5 A) in Attached State

High Current (3.0 A) in Attached State

H

L

When operating in I²C mode, the TUSB320 device uses the SCL and SDA lines for clock and data and the

INT_N pin to communicate a change in I²C registers, or an interrupt, to the system. The INT_N pin is pulled low

when the TUSB320 device updates the registers with new information. The INT_N pin is open drain. The

INTERRUPT_STATUS register will be set when the INT_N pin is pulled low. To clear the INTERRUPT_STATUS

register, the end user writes to I²C.

When operating in GPIO mode, the OUT3 pin is used in place of the INT_N pin to determine if an audio

accessory is detected and attached. The OUT3 pin is pulled low when an audio accessory is detected.

NOTE

When using the 3.3 V supply for I²C, the end user must ensure that the V_DDis 3 V and

above. Otherwise the I²C may back power the device.

7.2.5 V_BUSDetection

The TUSB320 device supports V_BUSdetection according to the Type-C Specification. V_BUSdetection is used to

determine the attachment and detachment of a UFP and to determine the entering and exiting of accessary

modes. V_BUSdetection is also used to successfully resolve the role in DRP mode.

The system V_BUSvoltage must be routed through a 900-kΩ resistor to the VBUS_DET pin on the TUSB320

device if the PORT pin is configured as a DRP or a UFP. If the TUSB320 device is configured as a DFP and only

ever used in DFP mode, the VBUS_DET pin can be left unconnected.

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7.3 Device Functional Modes

The TUSB320 device has four functional modes. Table 4 lists these modes:

Table 4. USB Type-C States According to TUSB320 Functional Modes

MODES

GENERAL BEHAVIOR

PORT PIN

STATES⁽¹⁾

Unattached.SNK

UFP

AttachWait.SNK

USB port unattached. ID, PORT

operational. I²C on. CC pins

configure according to PORT pin.

Toggle Unattached.SNK → Unattached.SRC

AttachedWait.SRC or AttachedWait.SNK

Unattached.SRC

Unattached

DRP

DFP

AttachWait.SRC

Attached.SNK

UFP

DRP

DFP

Audio accessory

Debug accessory

Attached.SNK

Attached.SRC

USB port attached. All GPIOs

operational. I²C on.

Active

Audio accessory

Debug accessory

Attached.SRC

Audio accessory

Debug accessory

No operation.

V_DDnot available.

Dead battery

Shutdown

UFP/DRP/DFP

Default device state to UFP/SNK with Rd.

V_DDavailable.

TUSB320L's EN_N pin high.

TUSB320H's EN pin low.

Default device state to UFP/SNK with Rd.

(1) Required; not in sequential order.

7.3.1 Unattached Mode

Unattached mode is the primary mode of operation for the TUSB320 device, because a USB port can be

unattached for a lengthy period of time. In unattached mode, V_DDis available, and all IOs and I²C are

operational. After the TUSB320 device is powered up, the part enters unattached mode until a successful attach

has been determined. Initially, right after power up, the TUSB320 device comes up as an Unattached.SNK. The

TUSB320 device checks the PORT pin and operates according to the mode configuration. The TUSB320 device

toggles between the UFP and the DFP if configured as a DRP. In unattached mode, I²C can be used to change

the mode configuration or port role if the board configuration of the PORT pin is not the desired mode. Writing to

the I²C MODE_SELECT register can override the PORT pin in unattached mode. The PORT pin is only sampled

at reset (TUSB320L's EN_N high to low transition or TUSB320H's EN low to high transition), after

I2C_SOFT_RESET, or power up. I²C must be used after reset to change the device mode configuration.

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7.3.2 Active Mode

Active mode is defined as the port being attached. In active mode, all GPIOs are operational, and I²C is read /

write (R/W). When in active mode, the TUSB320 device communicates to the AP that the USB port is attached.

This happens through the ID pin if TUSB320 is configured as a DFP or DRP connect as source. If TUSB320 is

configured as a UFP or a DRP connected as a sink, the OUT1/OUT2 and INT_N/OUT3 pins are used. The

TUSB320 device exits active mode under the following conditions:

•

Cable unplug

V_BUSremoval if attached as a UFP

Dead battery; system battery or supply is removed

TUSB320L EN_N pin floated or pulled high

TUSB320H EN pin floated or pulled low.

During active mode, I²C be used to change the mode configuration. This can be done by following the sequence

below. This same sequence is valid when TUSB320 is in unattached mode.

•

Set DISABLE_TERM register (address 0x0A bit 0) to a 1'b1.

Change MODE_SELECT register (address 0x0A bits 5:4) to desired mode of operation.

Wait 5 ms.

Clear DISABLE_TERM register (address 0x0A bit 0) to 1'b0.

7.3.3 Dead Battery Mode

During dead battery mode, V_DDis not available. CC pins always default to pulldown resistors in dead battery

mode. Dead battery mode means:

•

TUSB320 in UFP with 5.1-kΩ ± 20% Rd; cable connected and providing charge

TUSB320 in UFP with 5.1-kΩ ± 20% Rd; nothing connected (application could be off or have a discharged

battery)

NOTE

When V_DDis off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, ID, OUT[3:1]

pins) could back-drive the TUSB320 device if not handled properly. When necessary to

pull these pins up, it is recommended to pullup PORT, ADDR, INT_N/OUT3, and ID to the

device’s V_DDsupply. The VBUS_DET must be pulled up to V_BUSthrough a 900-kΩ

resistor.

7.3.4 Shutdown Mode

Shutdown mode for TUSB320L device is defined as follows:

•

Supply voltage available and EN_N pin is pulled high or floating.

EN_N pin has internal pullup resistor.

The TUSB320L device is off, but still maintains the Rd on the CC pins

Shutdown mode for TUSB320H device is defined as follows:

•

Supply voltage available and EN pin is pulled low or floating.

EN pin has internal pulldown resistor.

The TUSB320H device is off, but still maintains the Rd on the CC pins

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7.4 Programming

For further programmability, the TUSB320 device can be controlled using I²C. The TUSB320 device local I²C

interface is available for reading/writing after T_{I2C_EN}when the device is powered up. The SCL and SDA terminals

are used for I²C clock and I²C data respectively. If I²C is the preferred method of control, the ADDR pin must be

set accordingly.

Table 5. TUSB320 I²C Addresses

TUSB320 I²C Target Address

ADDR pin

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

H

L

1

0

1

0/1

The following procedure should be followed to write to TUSB320 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB320 7-bit

address and a zero-value R/W bit to indicate a write cycle

2. The TUSB320 device acknowledges the address cycle

3. The master presents the sub-address (I²C register within the TUSB320 device) to be written, consisting of

one byte of data, MSB-first

4. The TUSB320 device acknowledges the sub-address cycle

5. The master presents the first byte of data to be written to the I²C register

6. The TUSB320 device acknowledges the byte transfer

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TUSB320 device

8. The master terminates the write operation by generating a stop condition (P)

The following procedure should be followed to read the TUSB320 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB320 7-bit

address and a one-value R/W bit to indicate a read cycle

2. The TUSB320 device acknowledges the address cycle

3. The TUSB320 device transmits the contents of the memory registers MSB-first starting at register 00h or last

read sub-address+1. If a write to the T I²C register occurred prior to the read, then the TUSB320 device

starts at the sub-address specified in the write.

4. The TUSB320 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I²C master acknowledges reception of each data byte transfer

5. If an ACK is received, the TUSB320 device transmits the next byte of data

6. The master terminates the read operation by generating a stop condition (P)

The following procedure should be followed for setting a starting sub-address for I²C reads:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB320 7-bit

address and a zero-value R/W bit to indicate a read cycle

2. The TUSB320 device acknowledges the address cycle

3. The master presents the sub-address (I²C register within the TUSB320 device) to be read, consisting of one

byte of data, MSB-first

4. The TUSB320 device acknowledges the sub-address cycle

5. The master terminates the read operation by generating a stop condition (P)

NOTE

If no sub-addressing is included for the read procedure, then the reads start at register

offset 00h and continue byte-by-byte through the registers until the I²C master terminates

the read operation. If a I²C address write occurred prior to the read, then the reads start at

the sub-address specified by the address write.

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7.5 Register Maps

Table 6. CSR Registers

ACCESS

NAME

TAG

MEANING

R

W

S

Read

Write

The field may be read by software.

The field may be written by software.

Set

The field may be set by a write of one. Writes of zeros to the field have no effect.

C

Clear

The field may be cleared by a write of one. Writes of zeros to the field have no effect.

Hardware may autonomously update this field.

U

Update

No Access

NA

Not accessible or not applicable.

7.5.1 CSR Registers (address = 0x00 – 0x07)

Figure 4. CSR Registers (address = 0x00 – 0x07)

7

6

5

4

3

2

1

0

DEVICE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. CSR Registers (address = 0x00 – 0x07)

Bit

Field

Type

Reset

Description

For the TUSB320 device these fields return a string of ASCII

characters returning TUSB320

Addresses 0x07 - 0x00 = {0x00 0x54 0x55 0x53 0x42 0x33 0x32

0x30}

7:0

DEVICE_ID

R

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7.5.2 CSR Registers (address = 0x08)

Figure 5. CSR Registers (address = 0x08)

7

6

5

4

3

2

1

0

ACTIVE_CABLE_

DETECTION

CURRENT_MODE_ADVERTISE

RW

CURRENT_MODE_DETECT

RU

ACCESSORY_CONNECTED

RU

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. CSR Registers (address = 0x08)

Bit

Field

Type

Reset

Description

These bits are programmed by the application to raise the

current advertisement from default.

00 – Default (500 mA / 900 mA) initial value at startup

7:6

CURRENT_MODE_ADVERTISE

00

RW

01 – Mid (1.5 A)

10 – High (3 A)

11 – Reserved

These bits are set when a UFP determines the Type-C Current

mode.

00 – Default (value at start up)

01 – Medium

5:4

CURRENT_MODE_DETECT

00

RU

10 – Charge through accessory – 500 mA

11 – High

These bits are read by the application to determine if an

accessory was attached.

000 – No accessory attached (default)

001 – Reserved

010 – Reserved

3:1

ACCESSORY_CONNECTED

ACTIVE_CABLE_DETECTION

000

RU

011 – Reserved

100 – Audio accessory

101 – Audio charged thru accessory

110 – Debug accessory when TUSB320 is connected as a DFP.

111 – Debug accessory when TUSB320 is connected as a UFP.

This flag indicates that an active cable has been plugged into

the Type-C connector. When this field is set, an active cable is

detected.

0

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7.5.3 CSR Registers (address = 0x09)

Figure 6. CSR Registers (address = 0x09)

7

6

5

4

3

—

R

2

1

0

DISABLE_UFP_

ACCESSORY

ATTACHED_STATE

RU

CABLE_DIR INTERRUPT_STATUS

RU RCU

DRP_DUTY_CYCLE

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. CSR Registers (address = 0x09)

Bit

Field

Type

Reset

Description

This is an additional method to communicate attach other than

the ID pin. These bits can be read by the application to

determine what was attached.

00 – Not attached (default)

01 – Attached.SRC (DFP)

10 – Attached.SNK (UFP)

11 – Attached to an accessory

7:6

ATTACHED_STATE

00

RU

Cable orientation. The application can read these bits for cable

orientation information.

5

4

CABLE_DIR

1

0

RU

0 – CC1

1 – CC2 (default)

The INT pin is pulled low whenever a CSR with RU in Access

field changes. When a CSR change has occurred this bit should

be held at 1 until the application clears it. A write of 1'b1 is

required to clear this field.

0 – Clear

INTERRUPT_STATUS

RCU

1 – Interrupt (When INT_N is pulled low, this bit will be 1. )

Note: SW must make sure the INTERRUPT_STATUS has been

cleared to zero. Rewrites to this register are needed for the

INT_N to be correctly asserted for all interrupt events.

3

Reserved

R

0

Reserved

Percentage of time that a DRP advertises DFP during tDRP

00 – 30% (default)

2:1

DRP_DUTY_CYCLE

00

01 – 40%

RW

10 – 50%

11 – 60%

Settings this field will disable UFP accessory support.

0 – UFP accessory support enabled (Default)

1 – UFP accessory support disabled

0

DISABLE_UFP_ACCESSORY

RW

0

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7.5.4 CSR Registers (address = 0x0A)

Figure 7. CSR Registers (address = 0x0A)

7

6

5

4

3

2

1

0

DISABLE_TERM

RW

DEBOUNCE

RW

MODE_SELECT

RW

I²C_SOFT_RESET

SOURCE_PREF

RW

RSU

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. CSR Registers (address = 0x0A)

Bit

Field

Type

Reset

Description

The nominal amount of time the TUSB320 device debounces

the voltages on the CC pins.

00 – 168ms (default)

01 – 118ms

7:6

DEBOUNCE

00

RW

10 – 134ms

11 – 152ms

This register can be written to set the TUSB320 device mode

operation. The ADDR pin must be set to I²C mode. If the default

is maintained, the TUSB320 device operates according to the

PORT pin levels and modes.

5:4

MODE_SELECT

00

RW

00 – Maintain mode according to PORT pin selection (default)

01 – UFP mode (unattached.SNK)

10 – DFP mode(unattached.SRC)

11 – DRP mode(start from unattached.SNK)

This resets the digital logic. The bit is self-clearing. A write of 1

starts the reset. The following registers maybe affected after

setting this bit:

CURRENT_MODE_DETECT

ACTIVE_CABLE_DETECTION

ACCESSORY_CONNECTED

ATTACHED_STATE

3

I²C_SOFT_RESET

RSU

0

CABLE_DIR

This field controls the TUSB320 behavior when configured as a

DRP.

00 – Standard DRP (default)

01 – DRP will perform Try.SNK.

10 – Reserved.

2:1

SOURCE_PREF

DISABLE_TERM

RW

00

11 – DRP will perform Try.SRC.

This field will disable the termination on the CC pins and

transition the TUSB320's CC state machine to the Disable State.

0

0 – Termination enabled according to Port (Default)

1 – Termination disabled and state machine held in Disabled

state.

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7.5.5 CSR Registers (address = 0x45)

Figure 8. CSR Registers (address = 0x45)

7

6

5

—

R

4

3

2

DISABLE_RD_RP

RW

1

0

—

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. CSR Registers (address = 0x45)

Bit

Field

Type

Reset

Description

7:3

Reserved

R

00000

Reserved

When this field is set, Rd and Rp are disabled.

0 – Normal operation (default)

2

DISABLE_RD_RP

Reserved

RW

0

1 – Disable Rd and Rp

1:0

00

For TI internal use only. Do not change default value.

7.5.6 CSR Registers (address = 0xA0)

Figure 9. CSR Registers (address = 0xA0)

7

6

5

4

3

2

1

0

REVISION

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. CSR Registers (address = 0xA0)

Bit

Field

Type

Reset

Description

Revision of TUSB320. Defaults to 0x01.

7:0

REVISION

R

0x01

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TUSB320 device is a Type-C configuration channel logic and port controller. The TUSB320 device can

detect when a Type-C device is attached, what type of device is attached, the orientation of the cable, and power

capabilities (both detection and broadcast). The TUSB320 device can be used in a source application (DFP), in a

sink application (UFP), or a combination source/sink application (DRP).

8.2 Typical Application

8.2.1 DRP in I²C Mode

Figure 10 and Figure 11 show a Type-C configuration for the DRP mode.

5 V

Legacy TypeA

Switch

VBUS

PMIC

VPH

PORT

ID

VBUS

2.7 - 5 V VDD

PORT

CC1

CC2

VDD

ID

CC1

CC2

CC/Mode

Controller

CC/Mode

Controller

DP

DM

DP

DM

GPIOs

I2C

GPIOs

I2C

Processor

TUSB320

Figure 10. TUSB320 in DRP Mode Supporting Default

Implementation

Figure 11. TUSB320 in DRP Mode Supporting Advanced

Power Delivery

Figure 12 shows the TUSB320 device configured as a DRP in I²C mode.

21

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

Typical Application (continued)

USB VBUS Switch

(optional BC 1.2 support for legacy)

SCL

SDA

DM

DP

DM_OUT

DP_OUT

DM_IN

DP_IN

VOUT

System VBUS

VIN

PS_EN

EN

FAULT#

PS_FAULT#

VBUS

I2C I/O

1.8V or 3.3V

VBAT

USB2

OTG

and

DM

DP

150uF

100nF

VBUS

PMIC

A1

A2

A3

A4

B12

900K

4.7K 4.7K

200K 200K

VBUS_DET

B11

B10

B9

PORT

INT_N/OUT3

CC1

CC2

INT#

CC1

CC2

A5

A6

B8

B7

B6

TUSB320L

ID

SCL

SDA

ID

A7

A8

B5

B4

B3

SCL/OUT2

SDA/OUT1

A9

A10

A11

B2

B1

1uF

A12

Figure 12. DRP in I²C Mode Schematic

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 13:

Table 13. Design Requirements for DRP in I²C Mode

DESIGN PARAMETER

VALUE

V_DD(2.75 V to 5 V)

VBAT (less than 5 V)

Mode (I²C or GPIO)

I²C: ADDR pin must be pulled down or pulled up

0x47: ADDR pin must be pulled low or tied to GND

DRP: PORT pin is NC

I²C address (0x67 or 0x47)

Type-C port type (UFP, DFP, or DRP)

Shutdown support

No

8.2.1.2 Detailed Design Procedure

The TUSB320 device supports a V_DDin the range of 2.75 V to 5 V. In this particular use case, VBAT which must

be in the required V_DDrange is connected to the V_DDpin. A 100-nF capacitor is placed near V_DD

.

The TUSB320 device is placed into I²C mode by either pulling the ADDR pin high or low. In this case, the ADDR

pin is tied to GND which results in a I²C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or

3.3 V. When pulled up to 3.3 V, the V_DDsupply must be at least 3 V to keep from back-driving the I²C interface.

The TUSB320L device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320L device

into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N

pin is tied to GND. The TUSB320H device can enter shutdown mode by pulling the EN pin low, which puts the

TUSB320H device into a low power state. In this case, external control of the EN pin is not implemented and

therefore the EN pin is tied to 1.8V or 3.3V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I²C registers occurs. This pin is

an open drain output and requires an external pullup resistor. The pin should be pulled up to V_DDusing a 200-kΩ

resistor.

22

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

The ID pin is used to indicate when a connection has occurred if the TUSB320 device is a DFP while configured

for DRP. An OTG USB controller can use this pin to determine when to operate as a USB Host or USB Device.

When this pin is driven low, the OTG USB controller functions as a host and then enables V_BUS. The Type-C

standard requires that a DFP not enable V_BUSuntil it is in the Attached.SRC state. If the ID pin is not low but

V_BUSis detected, then OTG USB controller functions as a device. The ID pin is open drain output and requires

an external pullup resistor. It should be pulled up to V_DDusing a 200-kΩ resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is not connected, the

TUSB320 device is in DRP mode. The Type-C port mode can also be controlled by the MODE_SELECT register

through the I²C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to V_BUSon the Type-C that is connected. This

large resistor is required to protect the TUSB320 device from large V_BUSvoltage that is possible in present day

systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the

recommended range.

The USB2 specification requires the bulk capacitance on V_BUSbased on UFP or DFP. When operating the

TUSB320 device in a DRP mode, it alternates between UFP and DFP. If the TUSB320 device connects as a

UFP, the large bulk capacitance must be removed.

Table 14. USB2 Bulk Capacitance Requirements

PORT CONFIGURATION

Downstream facing port (DFP)

Upstream facing port (UFP)

MIN

120

1

MAX

UNIT

µF

10

µF

8.2.1.3 Application Curves

Figure 13. Application Curve for DRP in I²C Mode

23

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

8.2.2 DFP in I²C Mode

Figure 14 and Figure 15 show a Type-C configuration for the DFP mode.

Legacy TypeA

Switch

5 V

VBUS

PMIC

VDD

PORT

VPH

ID

VBUS

VDD

VBUS

2.7 - 5 V VDD

PORT

CC1

CC2

VDD

ID

CC1

CC2

CC/Mode

Controller

CC/Mode

Controller

DP

DM

GPIOs

I2C

DP

DM

GPIOs

I2C

Processor

TUSB320

Figure 14. TUSB320 in DFP Mode Supporting Default

Implementation

Figure 15. TUSB320 in DFP Mode Supporting Advanced

Power Delivery

Figure 16 shows the TUSB320 device configured as a DFP in I²C mode.

USB VBUS Switch

(optional BC 1.2 support for legacy)

SCL

SDA

DM

DP

DM_OUT

DP_OUT

DM_IN

DP_IN

VOUT

System VBUS

VIN

PS_EN

EN

FAULT#

PS_FAULT#

VBUS

I2C I/O

1.8V or

3.3V

VDD_5V

USB2

OTG

and

DM

DP

150uF

100nF

VBUS

PMIC

B12

A1

A2

A3

A4

900K

200K

4.7K 4.7K

200K

VBUS_DET

B11

B10

B9

PORT

INT_N/OUT3

CC1

CC2

INT#

A5

A6

B8

B7

B6

CC1

CC2

TUSB320L

ID

SCL

SDA

ID

A7

A8

B5

B4

B3

SCL/OUT2

SDA/OUT1

A9

A10

A11

B2

B1

A12

Figure 16. DFP in I²C Mode Schematic

24

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 15:

Table 15. Design Requirements for DFP in I²C Mode

DESIGN PARAMETER

V_DD(2.75 V to 5 V)

VALUE

5 V

Mode (I²C or GPIO)

I²C: ADDR pin must be pulled down or pulled up

0x47: ADDR pin must be pulled low or tied to GND

DFP: PORT pin is pulled up

I²C address (0x67 or 0x47)

Type-C port type (UFP, DFP, or DRP)

Shutdown support

No

8.2.2.2 Detailed Design Procedure

The TUSB320 device supports a V_DDin the range of 2.75 V to 5 V. In this particular case, V_DDis set to 5 V. A

100-nF capacitor is placed near V_DD

.

The TUSB320 device is placed into I²C mode by either pulling the ADDR pin high or low. In this particular case,

the ADDR pin is tied to GND which results in a I²C address of 0x47. The SDA and SCL must be pulled up to

either 1.8 V or 3.3 V. When pulled up to 3.3 V, the V_DDsupply must be at least 3 V to keep from back-driving the

I²C interface.

The TUSB320L device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320L device

into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N

pin is tied to GND. The TUSB320H device can enter shutdown mode by pulling the EN pin low, which puts the

TUSB320H device into a low power state. In this case, external control of the EN pin is not implemented and

therefore the EN pin is tied to 1.8V or 3.3V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I²C registers occurs. This pin is

an open drain output and requires an external pullup resistor. The pin should be pulled up to V_DDusing a 200-kΩ

resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled high, the

TUSB320 device is in DFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register

through the I²C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to V_BUSon the Type-C that is connected. This

large resistor is required to protect the TUSB320 device from large V_BUSvoltage that is possible in present day

systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the

recommended range.

The USB2 specification requires the bulk capacitance on V_BUSbased on UFP or DFP. When operating the

TUSB320 device in a DFP mode, a bulk capacitance of at least 120µF is required. In this particular case, a 150-

µF capacitor was chosen.

8.2.2.3 Application Curves

Figure 17. Application Curve for DFP in I²C Mode

25

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

8.2.3 UFP in I²C Mode

Figure 18 and Figure 19 show a Type-C configuration for the UFP mode.

5 V

VBUS

PMIC

VPH

PORT

ID

VBUS

2.7 - 5 V

VDD

CC1

CC2

VDD

ID

CC1

CC2

PORT

CC/Mode

Controller

CC/Mode

Controller

DP

DM

GPIOs

I2C

DP

DM

Processor

GPIOs

I2C

Processor

TUSB320

GND

TUSB320

Figure 18. TUSB320 in UFP Mode Supporting Default

Implementation

Figure 19. TUSB320 in UFP Mode Supporting Advanced

Power Delivery

Figure 20 shows the TUSB320 device configured as a UFP in I²C mode.

Optional power

TUSB320 with VBUS

less than 5.5V

DM

DP

VBUS

D1

I2C I/O

1.8V or 3.3V

VDD_5V

USB2

Device

DM

DP

and

100nF

VBUS

PMIC

B12

A1

A2

A3

A4

900K

4.7K 4.7K

200K 200K

VBUS_DET

B11

B10

B9

PORT

CC1

CC2

INT#

INT_N/OUT3

A5

A6

B8

B7

B6

CC1

CC2

TUSB320L

ID

A7

A8

B5

B4

B3

SCL

SDA

SCL/OUT2

SDA/OUT1

A9

A10

A11

1uF

B2

B1

A12

4.7K

Figure 20. UFP in I²C Mode Schematic

26

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

8.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 16:

Table 16. Design Requirements for UFP in I²C Mode

DESIGN PARAMETER

V_DD(2.75 V to 5 V)

VALUE

5 V

Mode (I²C or GPIO)

I²C: ADDR pin must be pulled down or pulled up

0x47: ADDR pin must be pulled low or tied to GND

UFP: PORT pin is pulled down

No

I²C address (0x67 or 0x47)

Type-C port type (UFP, DFP, or DRP)

Shutdown support

8.2.3.2 Detailed Design Procedure

The TUSB320 device supports a V_DDin the range of 2.75 V to 5 V. In this particular case, V_DDis set to 5 V. A

100-nF capacitor is placed near V_DD. If V_BUSis guaranteed to be less than 5.5 V, powering the TUSB320 device

through a diode can be implemented.

The TUSB320 device is placed into I²C mode by either pulling the ADDR pin high or low. In this case, the ADDR

pin is tied to GND which results in a I²C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or

3.3 V. When pulled up to 3.3 V, the V_DDsupply must be at least 3 V to keep from back-driving the I²C interface.

The TUSB320L device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320L device

into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N

pin is tied to GND. The TUSB320H device can enter shutdown mode by pulling the EN pin low, which puts the

TUSB320H device into a low power state. In this case, external control of the EN pin is not implemented and

therefore the EN pin is tied to 1.8V or 3.3V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I²C registers occurs. This pin is

an open drain output and requires an external pullup resistor. The pin should be pulled up to V_DDusing a 200-kΩ

resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled low, the

TUSB320 device is in UFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register

through the I²C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to V_BUSon the Type-C that is connected. This

large resistor is required to protect the TUSB320 device from large V_BUSvoltage that is possible in present day

systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the

recommended range.

The USB2 specification requires the bulk capacitance on V_BUSbased on UFP or DFP. When operating the

TUSB320 device in a UFP mode, a bulk capacitance between 1 to 10µF is required. In this particular case, a 1-

µF capacitor was chosen.

8.2.3.3 Application Curves

Figure 21. Application Curve for UFP in I²C Mode

27

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

8.3 Initialization Set Up

8.3.1 TUSB320L Initialization Procedure

The general power-up sequence for the TUSB320L device (EN_N tied to ground) is as follows:

1. System is powered off (device has no V_DD). The TUSB320L device is configured internally in UFP mode with

Rds on CC pins (dead battery).

2. V_DDramps – POR circuit. V_DDmust ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT,

SCL, SDA, ADDR, PORT) must ramp with V_DDor lag after V_DD

3. I²C supply ramps up.

.

4. The TUSB320L device enters unattached mode and determines the voltage level from the PORT pin. This

determines the mode in which the TUSB320L device operates (DFP, UFP, DRP).

5. The TUSB320L device monitors the CC pins as a DFP and V_BUSfor attach as a UFP.

6. The TUSB320L device enters active mode when attach has been successfully detected.

8.3.2 TUSB320H Initialization Procedure

The general power-up sequence for the TUSB320H device (EN tied to 1.8V or 3.3V) is as follows:

1. System is powered off (device has no V_DD). The TUSB320H device is configured internally in UFP mode with

Rds on CC pins (dead battery).

2. V_DDramps – POR circuit. V_DDmust ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT,

SCL, SDA, ADDR, PORT) must ramp with V_DDor lag after V_DD

3. I²C supply ramps up.

.

4. The TUSB320H device enters unattached mode and determines the voltage level from the PORT pin. This

determines the mode in which the TUSB320H device operates (DFP, UFP, DRP).

5. The TUSB320H device monitors the CC pins as a DFP and V_BUSfor attach as a UFP.

6. The TUSB320H device enters active mode when attach has been successfully detected.

9 Power Supply Recommendations

The TUSB320 device has a wide power supply range from 2.7 to 5 V. The TUSB320 device can be run off of a

system power such as a battery.

28

TUSB320HI, TUSB320LI

www.ti.com.cn

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

10 Layout

10.1 Layout Guidelines

1. An extra trace (or stub) is created when connecting between more than two points. A trace connecting pin A6

to pin B6 will create a stub because the trace also has to go to the USB Host. Ensure that:

–

A stub created by short on pin A6 (DP) and pin B6 (DP) at Type-C receptacle does not exceed 3.5 mm.

A stub created by short on pin A7 (DM) and pin B7 (DM) at Type-C receptacle does not exceed 3.5 mm.

2. A 100-nF capacitor should be placed as close as possible to the TUSB320 V_DDpin.

10.2 Layout Example

SCL/OUT2

Figure 22. TUSB320 Layout

29

TUSB320HI, TUSB320LI

ZHCSE04D –AUGUST 2015–REVISED MAY 2017

www.ti.com.cn

11 器件和文档支持

11.1 相关链接

下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的

快速链接。

表 17. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

TUSB320HI

TUSB320LI

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产

品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

USB Type-C is a trademark of USB Implementers Forum.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不

会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

30

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB320HIRWBR

TUSB320LIRWBR

X2QFN

RWB

12

3000

180.0

8.4

1.8

0.61

4.0

8.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB320HIRWBR

TUSB320LIRWBR

X2QFN

RWB

12

3000

213.0

191.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RWB0012A

X2QFN - 0.4 mm max height

SCALE 6.500

PLASTIC QUAD FLATPACK - NO LEAD

1.65

1.55

B

A

PIN 1 INDEX AREA

1.65

1.55

C

0.4 MAX

SEATING PLANE

0.05 C

2X 1.2

SYMM

(0.13)

TYP

0.05

0.00

6X 0.4

3

6

2

1

7

8

SYMM

2X

0.4

8X

0.2

12

9

0.25

0.15

12X

0.6

4X

0.4

0.07

0.05

C B A

C

4221631/B 07/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RWB0012A

X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.3)

6X (0.4)

9

12

4X (0.7)

2X (0.4)

1

8

SYMM

(1.5)

7

2

8X (0.5)

3

6

SYMM

(R0.05) TYP

12X (0.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:30X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221631/B 07/2017

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RWB0012A

X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.3)

6X (0.4)

12

9

4X (0.67)

2X (0.4)

1

2

8

SYMM

(1.5)

7

8X

METAL

8X (0.5)

3

6

(R0.05) TYP

SYMM

12X (0.2)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PADS 1,2,7 & 8

96% PRINTED SOLDER COVERAGE BY AREA

SCALE:50X

4221631/B 07/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TUSB320LI
厂家：	TEXAS INSTRUMENTS
描述：	USB Type-C 配置通道逻辑和端口控制
文件：	总38页 (文件大小：1889K)
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TUSB320LI [TI]

相关型号：

TUSB320LIRWBR

TUSB320RWBR

TUSB321

TUSB3210

TUSB3210PM

TUSB3210PMG4

TUSB3210_1

TUSB3210_15

TUSB321AI

TUSB321AIRWBR

TUSB321RWBR

TUSB322I