TXS02326MRGER [TI]
DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR WITH AUTOMATIC DETECTION AND SLOT DEDICATED DUAL LDO; 双电源2 : 1 SIM卡多路复用器/翻译器具有自动检测和插槽专线双路LDO型号: | TXS02326MRGER |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR WITH AUTOMATIC DETECTION AND SLOT DEDICATED DUAL LDO |
文件: | 总35页 (文件大小:693K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TXS02326
www.ti.com
SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR
WITH AUTOMATIC DETECTION AND SLOT DEDICATED DUAL LDO
Check for Samples: TXS02326
1
FEATURES
RGE PACKAGE
(TOP VIEW)
•
Level Translator
V_I/O Range of 1.7 V to 3.3 V
Low-Dropout (LDO) Regulator
–
•
–
–
–
–
50-mA LDO Regulator With Enable
24 23 22 21 20 19
1.8-V or 2.95-V Selectable Output Voltage
2.3-V to 5.5-V Input Voltage Range
1
2
3
4
5
6
18
IRQ
RSTX
SDN
SIMI/O
SIMCLK
SIMRST
NC
SIM1CLK
SIM1I/O
17
16
15
14
13
Exposed
Thermal Pad
Very Low Dropout: 100 mV (Max) at 50 mA
BSI
SIM2CLK
SIM2I/O
•
•
Control and Communication Through I2C
Interface With Baseband Processor
7
8 9 10 11 12
ESD Protection Exceeds JESD 22
–
–
2000-V Human-Body Model (A114-B)
1000-V Charged-Device Model (C101)
•
Package
24-Pin QFN (4 mm x 4 mm)
Note: The Exposed Thermal Pad must be
connect to Ground.
–
DESCRIPTION/ORDERING INFORMATION
The TXS02326 is a complete dual-supply standby Smart Identity Module (SIM) card solution for interfacing
wireless baseband processors with two individual SIM subscriber cards to store data for mobile handset
applications. It is a custom device which is used to extend a single SIM/UICC interface to be able to support two
SIMs/UICCs.
The device complies with ISO/IEC Smart-Card Interface requirements as well as GSM and 3G mobile standards.
It includes a high-speed level translator capable of supporting Class-B (2.95 V) and Class-C (1.8 V) interfaces,
two low-dropout (LDO) voltage regulators that have output voltages that are selectable between 2.95-V Class-B
and 1.8-V Class-C interfaces, an integrated "fast-mode" 400 kb/s "slave" I2C control register interface for
configuration purposes, a 32-kHz clock input for internal timing generation, a shutdown input and a comparator
input detecting battery pack removal to safely power-down the two SIM cards, each equipped with two
programmable debounce counter (i.e. BSI input and SDN input) circuit realized by an 8 bit counter.
The voltage-level translator has two supply voltage pins. V_I/O sets the reference for the baseband interface and
can be operated from 1.7 V to 3.3 V. VSIM1 and VSIM2 are programmed to either 1.8 V or 2.95 V, each supplied
by an independent internal LDO regulator. The integrated LDO accepts input battery voltages from 2.3 V to 5.5 V
and outputs up to 50 mA to the B-side circuitry and external Class-B or Class-C SIM card.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
QFN – RGE (Pin 1, Quadrant 2)
QFN – RGE (Pin 1, Quadrant 1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
YJ326
YJ326
TXS02326RGER
–40°C to 85°C
Tape and reel
TXS02326MRGER
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TXS02326
SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
VBAT
3-V or 1.8-V
SIM Card
I2C
Control
Logic
SCK
VSIM1
SDA
LDO
V
GND
VPP
I/O
CC
SIM1_RST
SIM1_CLK
Reset
CLK
NC
SIM_RST
SIM_CLK
NC
Translator
SIM1_I/O
SIM_I/O
V_I/O
Baseband
V
CC
3-V or 1.8-V
SIM Card
RSTX
IRQ
VSIM2
LDO
V
GND
VPP
I/O
CC
SIM2_RST
SIM2_CLK
Reset
CLK
NC
CLK
BSI
OE
NC
Translator
SIM2_I/O
GND
TXS02326
SDN
Figure 1. Interfacing With SIM Card
2
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NO.
SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
TERMINAL FUNCTIONS
POWER
DOMAIN
NAME
TYPE(1)
DESCRIPTION
1
IRQ
RSTX
SDN
I/O
I
VDDIO
VDDIO
VDDIO
VDDIO
VSIM2
VSIM2
VSIM2
VSIM2
VBAT
Interrupt to baseband. This signal is used to set the I2C address.
2
Active-low reset input from baseband
3
I
Power down SIM2; for example, from switch
4
BSI
I
Analog signal from battery. This input accepts input voltages up to 3 V.
5
SIM2CLK
SIM2I/O
SIM2RST
VSIM2
VBAT
O
I/O
O
O
P
SIM2 clock
6
SIM2 data
7
SIM2 reset
8
1.8 V/2.95 V supply voltage to SIM2
Battery power supply
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
G
O
O
I/O
O
VSIM1
SIM1RST
SIM1I/O
SIM1CLK
NC
VSIM1
VSIM1
VSIM1
VSIM1
1.8 V/2.95 V supply voltage to SIM1
SIM1 reset
SIM1 data
SIM1 clock
No connect
SIMRST
SIMCLK
SIMI/O
OE
I
I
VDDIO
VDDIO
VDDIO
VDDIO
UICC/SIM reset from baseband
UICC/SIM clock
I/O
I
UICC/SIM data
UICC/SIM data direction from baseband
GND
G
P
I
VDDI/O
CLK
VDDIO
VDDIO
VDDIO
VDDIO
1.8-V power supply for device operation and I/O buffers toward baseband
32-kHz clock
I2C clock
I2C data
SCK
I
SDA
I/O
(1) G = Ground, I = Input, O = Output, P = Power
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
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Table 1. Register Overview
REGISTER BITS
COMMAND
BYTE
READ
OR
WRITE
POWER-UP
DEFAULT
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
(HEX)
Device
hardware
revision
00h
01h
04h
R
R
R
xxxx xxxx
xxxx xxxx
0000 0000
information
Software
revision
information
Battery
Removal Battery
Interrupt
Status
SDN
Interrupt
Status
SIM2 Interface
Status
SIM1 Interface
Status
SDN
Status
Status
Register
Status
SIM2
SIM2
SIM1
LDO
Enable/
Disable
SIM
SIM1
Voltage
Select
SIM2 Interface
Status
LDO
SIM1 Interface
Status
Interface
Control
Register
Voltage
Enable/
Select
08h
0Ah
R/W
R/W
0000 0000
0000 0100
Disable
BSI Input
Debounce
Counter
BSI Debounce Counter Value
SDN Input
Debounce
Counter
SDN Debounce Counter Value
Reserved / Not Supported
Clock Control (Reserved)
0Bh
0Ch
0Dh
R/W
R/W
R/W
0000 0100
0000 0000
0000 0000
Reserved
Clock
Source
Select
External
Clock
Control
Battery
Removal
Interrupt Direction Control
Enable/
Disable
SDN
Detection
SDN
Level
SDN
BSI
BSI
Level
OE
OE
Device
Control
Register
Interrupt Detection
0Eh
10h-14h
15h
R/W
R/W
R/W
0000 0000
xxxx xxxx
0000 0000
Behavior Detection Enable/ Behavior Detection
control Select Disable Control Select
Control
Select
Device-
specific
testing
SDN
Pull-
down
Enable/
Disable
SDN
Pull-up
Enable/
Disable
General
purpose
Reserved
4
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
Table 2. Device Hardware Revision Register (00h)
Device HW Driver Register
HW identification
Bits(s)
Type (R/W)
Description
This register contains the manufacturer and
device ID(1) (value to be specified by the
manufacturer)
7:0
R
(1) The manufacturer ID part of this data shall remain unchanged when the HW revision ID is updated. The manufacturer ID shall uniquely
identify the manufacturer. The manufacturer ID is encoded on the MSB nibble.
Table 3. Device Hardware Revision Register (01h)
Device SW Driver Register
Bits(s)
Type (R/W)
Description
This register contains information about the
SW driver required for this device. This
information shall only be updated when
changes to the device requires SW
SW Driver Version
7:0
R
modifications. Initial register value is 00h
Table 4. Status Register (04h)
Status Register
Bits(s)
Type (R/W)
Description
SDN signal state captured after debounce
counter has expired '0' SDN signal at GND
'1' SDN signal at V_I/O level
SDN Status(1)
0
R
SDN interrupt status
'0' No interrupt
'1' Interrupt occurred, (the read operation will
automatically clear this bit)
SDN Interrupt(1)
1
2
3
R
R
R
'0' Battery present
'1' Battery not present, i.e. debounce counter
expired
Battery Status
Battery removal interrupt status
'0' No interrupt
'1' Interrupt occurred, (the read operation will
automatically clear this bit)
Battery Removal Interrupt
Status of SIM1 interface
'00' Powered down with pull-downs activated
'01' Isolated with pull-downs deactivated
'10' Powered with pull downs activated
'11' Active with pull downs deactivated
SIM1 Interface Status [1:0]
SIM2 Interface Status [1:0]
5:4(2)
R
R
Status of SIM2 interface
'00' Powered down with pull-downs activated
'01' Isolated with pull-downs deactivated
'10' Powered with pull downs activated
'11' Active with pull downs deactivated
7:6(2)
(1) The SDN status bit indicates the state of the SDN signal at the input when the debounce counter expired, i.e. when the SDN interrupt bit
is set.
(2) The content of bits 5:4 and 7:6 reflects the value written to the state bits in the SIM Interface control register 3:2 and 7:6 respectively
and the setting of the regulator bits in the SIM interface control register 0 and 4 respectively.
Table 5. State and Status Bit Mapping
SIM interface control register
state bits 3:2 and 7:6
SIM interface control register
regulator control bits 0 and 4
SIM status register bits 5:4 and
7:6
Comment
'00' Powered down state with
pull-downs activated
'0' Regulator is off, regulator
output is pulled down
'00' Powered down with
pulldowns activated
'1' Regulator is powered on,
regulator output pull-down is
released
'00' Powered down state with
pull-downs activated
'10' Powered with pull-downs
activated
The interface can only be in
isolated state when the interface
is powered
01' Isolated state with pulldowns '0' Regulator is off, regulator
deactivated output is pulled down
'00' Powered down with
pulldowns activated
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Table 5. State and Status Bit Mapping (continued)
SIM interface control register
state bits 3:2 and 7:6
SIM interface control register
regulator control bits 0 and 4
SIM status register bits 5:4 and
7:6
Comment
'1' Regulator is powered on,
regulator output pull-down is
released
'01' Isolated state with pulldowns
deactivated
'01' Isolated with pull-downs
deactivated
This combination shall not be
used. If used the status bit
coding is as specified
'0' Regulator is off, regulator
output is pulled down
'00' Powered down with
pulldowns activated
'10' Not allowed
10' Not allowed
'1' Regulator is powered on,
regulator output pull-down is
released
This combination shall not be
used. If used the status bit
coding is as specified
'10' Powered with pull downs
activated
'11' Active state with pull-downs
deactivated
'0' Regulator is off, regulator
output is pulled down
'00' Powered down with
pulldowns activated
The interface can only be active
if it is powered
'1' Regulator is powered on,
regulator output pull-down is
released
11' Active state with pull-downs
deactivated
'11' Active with pull-downs
deactivated
Table 6. SIM Interface Control Register (08h)(1)(2)
Status Register
Bit(s)
Type (R/W)
Description
'0' Regulator is off, regulator output is pulled
down
'1' Regulator is powered on, regulator output
pull-down is released
SIM1 Regulator Control
0
R/W
'0' 1.8 V
'1' 2.95 V
SIM1 Regulator Voltage Selection
SIM1 Interface State [1:0]
1
R/W
R/W
Status of SIM1 interface
'00' Powered down state with pull-downs
activated
'01' Isolated state with pull-downs
deactivated
3:2
'10' Not allowed
'11' Active state with pull downs deactivated
'0' Regulator is off, regulator output is pulled
down
'1' Regulator is powered on, regulator output
pull-down is released
SIM2 Regulator Control
4
5
R/W
R/W
'0' 1.8 V
'1' 2.95 V
SIM2 Regulator Voltage Selection
Status of SIM2 interface
'00' Powered down state with pull-downs
activated
SIM2 Interface State [1:0]
(1) Reset value: 00h
7:6
R/W
'01' Isolated state with pull-downs
deactivated
'10' Not allowed
'11' Active state with pull downs deactivated
(2) The state '10', on bits 3:2 and 7:6, is not prevented by HW but shall never be set by SW. State '10' means that the interface is powered
with the pull-downs active, this state correspond to state '00' with the regulator being switched on. Setting the state to '10' does not have
any impact on the corresponding regulator bit setting. The regulator control bits do not impact the state bits in this register. The regulator
control bits however do impact the status bits in the status register.
Table 7. Battery Presence Detection Debounce Counter (0Ah)(1)(2)
BSI Debounce Counter
Bits(s)
Type (R/W)
Description
This register contains the BSI input
debounce counter value. The value 00h
means that the counter is not used, i.e. no
debounce.
Debounce Counter Value [7:0]
7:0
R/W
(1) Reset value: 04h
(2) Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new
value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.
6
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
Table 8. SDN Input Debounce Counter (0Bh)(1)(2)
SDN Debounce Counter
Bits(s)
Type (R/W)
Description
This register contains the SDN input
debounce counter value. The value 00h
means that the counter is not used, i.e. no
debounce.
Debounce Counter Value [7:0]
7:0
R/W
(1) Reset value: 04h
(2) Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new
value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.
Table 9. External Clock Control (0Dh)(1)
Clock Control Register
Clock Control
Bits(s)
Type (R/W)
Description
6:0
R/W
Reserved
'0' Internal clock source used
'1' External clock source CLK (supplied on
pin 22 used)
Clock Source Select
(1) Reset value: 00h
7
R/W
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Table 10. Device Control Register (0Eh)(1)
Clock Control Register
Bits(s)
Type (R/W)
Description
‘0’ OE is not used to control the data
direction on the selected SIM I/O and the
base band I/O
OE Control
0
R/W
‘1’ OE controls the data direction, see below
‘0’ OE input = ‘0’ data direction Base band
-> SIM
OE input = ‘1’ data direction SIM -> base
band
OE Direction Control
1
R/W
‘1’ OE input = ‘0’ data direction SIM -> base
band
OE input = ‘1’ data direction Base band ->
SIM
‘0’ Battery removal interrupt disabled
‘1’ Battery removal detected causes interrupt
on IRQ (interrupt sets b3 in the status
register)
Battery Removal Interrupt
BSI Level Detection
2
3
R/W
R/W
BSI detection level
‘0’ 1.2V
‘1’ 1.65V
BSI detection behavior
‘0’ Battery not present causes automatic
power down of both SIM interfaces
‘1’ Battery not present doesn’t cause
automatic power down
BSI Detection Control
4
5
R/W
R/W
‘0’ SDN detection interrupt disabled
‘1’ SDN detected causes interrupt on IRQ
(interrupt sets b1 in the status register)
SDN Detection Interrupt
SDN input active level
‘0’ SDN is active low
i.e. automatic shutdown occurs when
debounced SDN is low.
‘1’ SDN is active high
i.e. automatic shutdown occurs when
debounced SDN is high
SDN Detection Level
6
7
R/W
R/W
Disable automatic power down upon SDN
detection
‘0’ SDN detection causes automatic power
down of SIM2 interface
‘1’ SDN detection doesn’t cause automatic
power down of SIM2 interface
SDN Detection Control
(1) Reset value: 00h
Table 11. General Purpose Register (15h)(1)
Function
Bit(s)
Type (R/W)
Description
'0' SDN input pull-up enabled
'1' SDN input pull-up disabled
SDN pull-up control
0
R/W
'0' SDN pull-down disabled
'1' SDN pull-down enabled
SDN pull-down control
RFU
1
R/W
R/W
7:2
(1) The RFU bits shall allow for the write operation to complete but shall read as '0'. The SW should write '0' into these locations, reset
value.
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
BASIC DEVICE OPERATION
The TXS02326 is controlled through a standard I2C interface reference to VDDIO. It is connected between the
two SIM card slots and the SIM/UICC interface of the baseband. The device uses VBAT and VDDI/O as supply
voltages. The supply voltage for each SIM card is generated by an on-chip low drop out regulator. The interface
between the baseband and the TXS02326 is reference to VDDIO while the interface between the TXS02326 and
the SIM card is referenced to the LDO output of either VSIM1 or VSIM2 depending on which slot is being
selected. The VDDIO on the baseband side normally does not exceed 1.8V, thus voltage level shifting is needed
to support a 3V SIM/UICC interface (Class B).
The TXS02326 has two basic states, the reset and operation state. The baseband utilizes information in the
status registers to determine how to manipulate the control registers to properly switch between two SIM cards.
These fundamental sequences are outlined below and are to help the user to successfully incorporate this device
into the system.
DEVICE ADDRESS
The address of the device is shown below:
Slave Address
IRQ
0
1
1
1
1
0
R/W
Address Reference
IRQ@ Reset
R/W
0 (W)
1 (R)
0 (W)
1 (R)
Slave Address
0
0
1
1
120 (decimal), 78(h)
121 (decimal), 79(h)
122 (decimal), 7A(h)
123 (decimal), 7B(h)
RESET STATE
In the reset state the device settings are brought back to their default values and any SIM card that has been
active is deactivated. After reset, neither of the UICC/SIM interfaces is selected. The active pull-downs at the
UICC/SIM interface are automatically activated. To ensure the system powers up in an operational state, device
uses an internal 32 KHz clock for internal timing generation. After power up, the system has the option to
continue to utilize the internal clock or select an external clock source. This clock source is selectable by the
Clock Source Select I2C register bit.
•
•
Power up the TXS02326 by asserting VBAT to enter the operation state
I2C Interface becomes active with the VDD_I/O supply
RESET summary:
•
•
•
•
•
Any pending interrupts are cleared
I2C registers are in the default state
BSI and SDN counter value in the registers are set to four clock cycles or “0000 0100”
Both on chip regulators are set to 1.8V and disabled
All SIM1 and SIM2 signals are pulled to GND
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SETTING UP THE SIM INTERFACE
The TXS02326 supports both Class C (1.8V) or Class B (2.95V) SIM cards. In order to support these cards
types, the interface on the SIM side needs to be properly setup. After power up, the system should default to
SIM1 card. The following sequence outlines a rudimentary sequence of preparing the SIM1 card interface:
•
Configure the SIM1 regulator to 1.8V by asserting B1 = 0 in the SIM Interface Control Register (08h). The
system by default should start in 1.8V mode.
•
Configure the OE signal by asserting B0 = 0 in the Device Control Register (0Eh). The default value
essentially disables the OE pin and the device is configured as an auto direction translator.
•
•
•
•
•
•
The baseband SIM interface is set to a LOW state.
Disable the SIM1 interface by asserting B2 = 0 and B3 = 0 in the SIM Interface Control Register.
Disable the SIM2 interface by asserting B6 = 0 and B7 = 0 in the SIM Interface Control Register.
VSIM1 voltage regulator should now be activated by asserting B0 = 1 in the SIM Interface Control Register.
Enable the SIM1 interface by asserting B2 = 1 and B3 = 1 in the SIM Interface Control Register.
The SIM1 interface (VSIM1, SIM1CLK, SIM1I/O) is now active. The TXS02326 relies on the baseband to
perform the power up sequencing of the SIM card. If there is lack of communication between the baseband
and the SIM card, the SIM1 interface must be powered-down and then powered up again through the
regulator by configuring it to 2.95V by asserting B1 = 1 in the SIM Interface Control Register.
SWITCHING BETWEEN SIM CARDS
The following sequence outlines a rudimentary sequence of switching between the SIM1 card and SIM2 card:
•
Put the SIM1 card interface into “clock stop” mode then assert B2 = 1 and B3 = 0 in the SIM Interface Control
Register (08h). This will latch the state of the SIM1 interface (SIM1CLK, SIM1I/O, SIM1RST).
•
There can be two scenarios when switching to SIM2 card:
–
SIM2 may be in the power off mode, B6 = 0 and B7 = 0 in the Status Register (04h). If SIM2 is in power
off mode, the SIM/UICC interface will need to be set to the power off state. In this case the baseband will
most likely need to go through a power up sequence iteration
–
SIM2 may already be in the “clock stop” mode, B6 = 1 and B7 = 0 in the Status Register (04h). If SIM2 is
in “clock stop” mode, the interface between the baseband and the device is set to the clock stop mode
levels that correspond to the SIM2 card interface.
•
•
After determining whether the SIM2 card is either in power off mode or clock stop mode, the SIM2 card
interface is then activated by asserting B6 = 1 and B7 = 1 in the SIM Interface Control Register (08h) and the
negotiation between the baseband and card can continue.
Switching from SIM2 to SIM1 done in the same manner.
AUTOMATIC SHUTDOWN
Both SIM card interfaces can be configured to automatically shut down upon disconnecting the battery. The
shutdown threshold BSIThreshold is configured in B3 of the Device Control Register (0Eh). Two threshold levels are
available for this configuration. When the BSI input level exceeds the BSIThreshold level that caused this
power-down, both SIM card interfaces will automatically be shut down. If the battery removal interrupt is enabled
through B2 of the Device Control Register, then an interrupt will be issued to the baseband on IRQ. This case
may happen if the user decides to remove the battery.
There are two scenarios for shutting down each SIM: SIMx is “active”, or in “clock stop” mode. In clock stop
mode, when the debounce timer expires, the SIMx signals all go low immediately, then the regulator is disabled
one 32KHz cycle later. If SIMx is active, the signals go low and the regulator is disabled in a particular sequence
to be described in the next section.
The SIM2 interface can also be configured to automatically shut down via the SDN pin.
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
BSI / SDN DEBOUNCE AND AUTOMATIC SHUTDOWN SEQUENCE TIMING
There are two debounce counters: one each for the BSI and SDN inputs. For each counter, when the device is
reset or the related input is “false”, the counter is loaded with the value in the associated Debounce Counter
register and the debounced signal (i.e. BSI_DEB or SDN_DEB) is subsequently set to a “false” state. When the
related input becomes “true”, the counter begins counting down on subsequent CLK rising-edges. (CLK is either
the internal or external 32 kHz clock as selected by Clock Source Select)
If the input changes state during the count, the counter is again loaded with the register value. The debounce
counter propagates the input signal to the output when the counter expires.
For BSI and BSI_DEB, the “true” state is high. For SDN and SDN_DEB, the “true” state is the state stored in the
SDN Detection Level register. Once either count reaches zero, the debounced signal switches to the “true” state
on the next CLK rising edge.
If BSI_DEB goes high and Battery Removal Interrupt (bit 2 of the Device Control Register) is 1, an interrupt is
generated and appears on IRQ. Also, if BSI_DEB goes high and BSI Detection Control (bit 4 of the Device
Control Register) is 0, the Automatic Shutdown sequence begins for both SIM’s.
If SDN_DEB goes “true” and SDN Detection Interrupt (bit 5 of the Device Control Register) is 1, an interrupt is
generated and appears on IRQ. Also, if SDN_DEB goes “true” and SDN Detection Control (bit 7 of the Device
Control Register) is 0, the Automatic Shutdown sequence begins for SIM2 only, leaving SIM1 unaffected.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
BSI
4
3
2
4
3
2
1
4
0
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Active Data
Latched RST
Latched Clock
Latched Data
Figure 2. BSI Debounce Timing – SIM1 Active and SIM2 Isolated
Notes:
BSI debounce count value set to 4
SIM1 Active, SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM1 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM2 is powered up
but inactive, it follows the instant shutdown sequence.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
BSI
4
3
2
4
3
2
1
4
0
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Clock stopped
Active Data
Latched RST
Latched Clock
Latched Data
Figure 3. BSI Debounce Timing – SIM1 Clock Stop and SIM2 Isolated
Notes:
BSI debounce counter set to 4
SIM1 Active in Clock Stop Mode
SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM1 is active with SIMCLK stopped, it follows the instant shutdown sequence. Since SIM2 is powered up
but inactive, it follows the instant shutdown sequence.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
BSI
4
3
2
4
3
2
1
4
0
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Latched RST
Latched Clock
Latched Data
Active Data
Figure 4. BSI Debounce Timing – SIM1 Isolated, SIM2 Active
Notes:
BSI debounce counter set to 4
SIM2 Active
SIM1 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM2 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM1 is powered up
but inactive, it follows the instant shutdown sequence.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
Wt. 0Ah
BSI
4
3
2
1
7
6
5
4
3
2
1
4
0
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Active Data
Latched RST
Latched Clock
Latched Data
Figure 5. BSI Debounce Timing – Debounce Count Value Write During Debounce
Notes:
BSI debounce count value set to 4, but written to 7 during debounce
SIM1 Active
SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to
BSI_DEB goes high causing automatic shutdown sequence on both SIM’s. Since SIM1 follows the staged
shutdown sequence. SIM2 follows the instant shutdown sequence. BSI returning low does not interrupt shutdown
sequence.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
SDN
4
3
2
4
3
2
1
4
0
SDN_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Active Data
Latched RST
Latched Clock
Latched Data
Figure 6. SDN Debounce Timing – SDN Detection Level High
Notes:
SDN debounce count value set to 4
SIM1 Active
SIM2 powered but Isolated
SDN Detection Control set to 0
SDN Detection level set to 1
SDN Detection Interrupt set to 1
Once SDN is high for four cycles, SDN_DEB goes high causing automatic shutdown sequence on SIM2. SIM1 is
unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
SDN
4
3
2
4
3
2
1
4
0
SDN_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Active Data
Latched RST
Latched Clock
Latched Data
Figure 7. SDN Debounce Timing – SDN Detection Level Low
Notes:
SDN debounce count value set to 4
SIM1 Active
SIM2 powered but Isolated
SDN Detection Control set to 0
SDN Detection level set to 0
SDN Detection Interrupt set to 1
Once SDN is low for four cycles, SDN_DEB goes low causing automatic shutdown sequence on SIM2. SIM1 is
unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
DEB CNT
SDN
4
3
2
4
3
2
1
4
0
SDN_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
SIM1 VCC
SIM2 RST
SIM2 CLK
SIM2 I/O
SIM2 VCC
Latched RST
Latched Clock
Latched Data
Active Data
Figure 8. SDN Debounce Timing – SIM1 Isolated and SIM 2 Active
Notes:
SDN debounce count value set to 4
SIM1 powered but Isolated
SIM2 Active
SDN Detection Control set to 0
SDN Detection level set to 1
SDN Detection Interrupt set to 1
SDN_DEB goes high causing automatic shutdown sequence on SIM2. Since SIM2 is active with SIMCLK
running, it follows the staged shutdown sequence, SIM1 is unaffected.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Level Translator(1)
MIN
–0.3
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V_I/O
VI
Supply voltage range
Input voltage range
V
V_I/O-port
VSIMx-port
Control inputs
V_I/O-port
VSIMx-port
V_I/O-port
VSIMx-port
VI < 0
4.6
4.6
V
4.6
4.6
Voltage range applied to any output in the high-impedance or
power-off state
VO
VO
V
V
4.6
4.6
Voltage range applied to any output in the high or low state
4.6
IIK
IOK
IO
Input clamp current
–50
–50
±50
±100
150
mA
mA
mA
mA
°C
Output clamp current
VO < 0
Continuous output current
Continuous current through VCCA or GND
Storage temperature range
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
LDO(1)
MIN
–0.3
–0.3
–55
–55
MAX
6
UNIT
V
VIN
Input voltage range
VOUT
TJ
Output voltage range
6
V
Junction temperature range
Storage temperature range
150
150
2
°C
°C
kV
V
Tstg
Human-Body Model (HBM)
ESD rating
Charged-Device Model (CDM)
1000
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
THERMAL IMPEDANCE RATINGS
UNIT
qJA
Package thermal impedance(1)
RGE package
45
°C/W
(1) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
Level Translator
Description
MIN
MAX
3.3
UNIT
V
V_I/O
VIH
Supply voltage
1.7
High-level input voltage
Applies to pins: RESET, SDN,
SCL, SDA, IRQ, OE, 32kHz,
SIM_RST, SIM_CLK, SIM_I/O
V_I/O × 0.7
0
1.9
V
VIL
Low-level input voltage
V_I/O × 0.3
V
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
5
ns/V
°C
TA
–40
85
(1) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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ELECTRICAL CHARACTERISTICS
Level Translator
over recommended operating free-air temperature range (unless otherwise noted)
TYP(
PARAMETER
TEST CONDITIONS
V_I/O
VSIM1
VSIM2
MIN
MAX
UNIT
1)
SIM1_RST
SIM1_CLK
VSIM1 × 0.8
VSIM1 × 0.8
IOH = –100 µA
Push-Pull
IOH = –10 µA
Open-Drain
SIM1_I/O
VSIM1 × 0.8
IOH = –100 µA
Push-Pull
SIM2_RST
SIM2_CLK
VSIM2 × 0.8
VSIM2 × 0.8
IOH = –100 µA
Push-Pull
1.8 V / 2.95 1.8 V / 2.95
1.7 V to
3.3 V
V
V
VOH
V
(Supplied
by LDO)
(Supplied by
LDO)
IOH = –10 µA
Open-Drain
SIM2_I/O
SIM_I/O
VSIM2 × 0.8
V_I/O × 0.8
IOH = –100 µA
Push-Pull
IOH = –10 µA
Open-Drain
IOH = –100 µA
Push-Pull
IOL = 1 mA
Push-Pull
SIM1_RST
SIM1_CLK
VSIM1 × 0.2
VSIM1 × 0.2
IOL = 1 mA
Push-Pull
IOL = 1 mA
Open-Drain
SIM1_I/O
0.3
IOL = 1 mA
Push-Pull
IOL = 1 mA
Push-Pull
1.8 V / 2.95 1.8 V / 2.95
SIM2_RST
SIM2_CLK
VSIM2 × 0.2
VSIM2 × 0.2
1.7 V to
3.3 V
V
V
VOL
V
(Supplied
by LDO)
(Supplied by
LDO)
IOL = 1 mA
Push-Pull
IOL = 1 mA
Open-Drain
SIM2_I/O
SIM_I/O
0.3
0.3
IOL = 1 mA
Push-Pull
IOL = 1 mA
Open-Drain
IOL = 1 mA
Push-Pull
1.8 V / 2.95 1.8 V / 2.95
Control
inputs
1.7 V to
3.3 V
V
V
II
VI = OE
±1
±5
µA
µA
(Supplied
by LDO)
(Supplied by
LDO)
1.8 V / 2.95 1.8 V / 2.95
VI = VCCI
IO = 0
1.7 V to
3.3 V
V
V
ICC I/O
(Supplied
by LDO)
(Supplied by
LDO)
SIM_I/O
port
7
4
Cio
Ci
pF
pF
SIMx port
Control
inputs
VI = V_I/O or GND
3
Clock input
(1) All typical values are at TA = 25°C.
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ELECTRICAL CHARACTERISTICS
LDO (Control Input Logic = High)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.3
TYP(1)
MAX
5.5
UNIT
VBAT
VOUT
VDO
Input voltage
V
Class-B Mode
Class-C Mode
IOUT = 50 mA
IOUT = 0 mA
2.85
1.7
2.95
1.8
3.05
1.9
Output voltage
V
Dropout voltage
Ground-pin current
100
35
mV
µA
IGND
IOUT = 50 mA
150
VENx ≤ 0.4 V, (VSIMx + VDO) ≤ VBAT ≤ 5.5
ISHDN
Shutdown current (IGND
)
V,
3
µA
TJ = 85°C
IOUT(SC)
COUT
Short-circuit current
Output Capacitor
RL = 0 Ω
400
mA
µF
1
VBAT = 3.25 V,
VSIMx = 1.8 V or 3 V,
COUT = 1 µF, IOUT = 50 mA
f = 1 kHz
50
40
PSRR
Power-supply rejection ratio
dB
f = 10 kHz
VSIMx = 1.8 V or 3 V, IOUT = 10 mA,
COUT = 1 µF
TSTR
TJ
Start-up time
50
85
µS
°C
Operating junction
temperature
–40
(1) All typical values are at TA = 25°C.
GENERAL ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.7
UNIT
BSI detection level “1”
BSI detection level “0”
1.6
1.1
BSIThreshold Comparator Threshold
V
1.3
Hyst
Internal hysteresis of comparator
±50
32
mV
KHz
kΩ
CLKInt
RSIMPU
Internal System Clock
SIM I/O pull-up
–20%
18
+20%
22.6
9
20
Class B
Class C
6
7.5
4.5
RSIMxPU
RSIMPD
SIMx I/O pull-up
kΩ
3.8
5.2
Active pull-downs are connected to
the VSIM1/2 regulator output to the
SIM1/2 CLK, SIM1/2 RST, SIM1/2
I/O when the respective regulator is
disabled
SIMx I/O pull-down
2
kΩ
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SWITCHING CHARACTERISTICS
VSIMx = 1.8 V or 2.95 V Supplied by Internal LDO, VBAT = 2.3V to 5.5V
over recommended operating free-air temperature range (unless otherwise noted)
V_I/O = 1.7 V to 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
210
8.6
4.3
4
SIM_I/O
SIM_I/O
Open Drain
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Push Pull
Push Pull
Push Pull
Open Drain
Push Pull
Push Pull
Push Pull
Open Drain
Push Pull
Open Drain
Push Pull
Push Pull
Push Pull
Push Pull
Open Drain
Push Pull
Open Drain
Push Pull
Push Pull
Push Pull
Open Drain
Push Pull
Open Drain
Push Pull
trA
Baseband side to SIM side
SIM_RST
SIM_CLK
SIMx_I/O
16
6.5
4
SIMx_I/O
trA
Baseband side to SIM side
SIM_RST
SIMx_CLK
5
SIMx_I/O
210
10
6
trB
SIM side to Baseband side
SIMx_I/O
SIMx_I/O
trB
SIM side to Baseband side
SIMx_I/O
8
fmax
SIMx_CLK
5
SIMCLK to SIMx_CLK
SIMRST to SIMx_RST
SIMIO to SIMx_IO
SIMIO to SIMx_IO
SIMx_IO to SIMIO
SIMx_IO to SIMIO
SIMCLK to SIMx_CLK
SIMRST to SIMx_RST
SIMIO to SIMx_IO
SIMIO to SIMx_IO
SIMx_IO to SIMIO
SIMx_IO to SIMIO
8
8
260
10
260
10.5
7
tPLH
7
23
8
tPLH
23
10
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OPERATING CHARACTERISTICS
TA = 25°C, VSIMx = 1.8 V for Class C, VSIMx = 2.95 V for Class B
TEST
CONDITIONS
PARAMETER
TYP
UNIT
Class B
Class C
CL = 0,
f = 5 MHz,
tr = tf = 1 ns
11
(1)
Cpd
pF
9.5
(1) Power dissipation capacitance per transceiver
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APPLICATION INFORMATION
The LDO’s included on the TXS02326 achieve ultra-wide bandwidth and high loop gain, resulting in extremely
high PSRR at very low headroom (VBAT – VSIM1/2). The TXS02326 provides fixed regulation at 1.8V or 2.95V.
Low noise, enable (through I2C control), low ground pin current make it ideal for portable applications. The device
offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from –40°C to
+85°C.
VSIM1
VDDIO
VBAT
TXS02326
1μF
VSIM2
GND
1μF
1μF
0.1μF
Figure 9. Typical Application circuit for TXS02326
Input and Output Capacitor Requirements
It is good analog design practice to connect a 1.0 mF low equivalent series resistance (ESR) capacitor across the
input supply (VBAT) near the regulator. Also, a 0.1uF is required for the logic core supply (VDDIO).
This capacitor will counteract reactive input sources and improve transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if
the device is located several inches from the power source. The LDO’s are designed to be stable with standard
ceramic capacitors of values 1.0 mF or larger. X5R- and X7R-type capacitors are best because they have
minimal variation in value and ESR over temperature. Maximum ESR should be < 1.0 Ω.
Output Noise
In most LDO’s, the bandgap is the dominant noise source. To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN
and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect directly to the GND pin of the device.
Internal Current Limit
The TXS02326 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the
device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TXS02326 has a built-in body diode that conducts current when the voltage at
VSIM1/2 exceeds the voltage at VBAT. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
Dropout Voltage
The TXS02326 uses a PMOS pass transistor to achieve low dropout. When (VBAT – VSIM1/2) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO will approximately scale with output current because
the PMOS device behaves like a resistor in dropout.
Startup
The TXS02326 uses a quick-start circuit which allows the combination of very low output noise and fast start-up
times. Note that for fastest startup, VBATT should be applied first, and then enabled by asserting the I2C register.
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
Transient Response
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases duration of the transient response.
Minimum Load
The TXS02326 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The TXS02326 employs an innovative low-current mode circuit to
increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation
performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage
because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature should be limited to +85°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +85°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TXS02326 has been designed to protect against overload conditions. It
was not intended to replace proper heat sinking. Continuously running the TXS02326 into thermal shutdown will
degrade device reliability.
TYPICAL CHARACTERISTICS
110
100
90
80
70
60
50
40
30
20
10
0
-90
-80
-70
-60
-50
-40
-30
-20
1.8 V Vsim
85°C Vsim
2.95 V Vsim
-40°C Vsim
25°C Vsim
-10
0
100
1000
10000
100000
1000000
0
5
10 15 20 25 30 35 40 45 50
- Output Current - mA
f - Frequency - Hz
I
OUT
Figure 10. PSRR
Figure 11. Dropout Voltage vs Output Current
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
1
0.8
0.6
0.4
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1
I
= 50 mA
O
-100 mA, Vsim
-40°C Vsim
-0.2
-0.4
-0.6
-0.8
-1
85°C Vsim
-1.2
-1.4
-1.6
-1.2
-1.4
-50 mA, Vsim
25°C Vsim
-1.6
-1.8
-2
-2.2
-2.4
-1.8
-2
0
5
10 15 20 25 30 35 40 45 50
- Output Current - mA
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
- Temperature - °C
I
OUT
T
A
Figure 12. Output Voltage vs Temperature, Class-B/C
Figure 13. Load Regulation, Iout = 50 mA, Class-C
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1
I = 50 mA
O
-40°C Vsim
-0.2
-0.4
-0.6
-40°C Vsim
25°C Vsim
25°C Vsim
-0.8
-1.2
-1.4
-1.6
-1.8
-2
85°C Vsim
-1
-1.2
85°C Vsim
-1.4
-1.6
I
= 50 mA
-1.8
-2
-2.2
-2.4
O
0
5
10 15 20 25 30 35 40 45 50
- Output Current - mA
2.7
3.1
3.5
3.9
V
4.3
- V
4.7
5.1
5.5
I
BAT
OUT
Figure 14. Load Regulation, Iout = 50 mA, Class-B
Figure 15. Line Regulation, Iout = 50 mA, Class-C
26
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TXS02326
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
TYPICAL CHARACTERISTICS (continued)
330
300
270
240
210
180
150
120
90
0
-0.2
-0.4
-0.6
-0.8
-1
I
= 50 mA
O
-40°C Vsim
25°C Vsim
-40°C Vsim
25°C Vsim
85°C Vsim
85°C Vsim
-1.2
-1.4
-1.6
-1.8
-2
60
30
-2.2
-2.4
0
2.7
3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
3.5
3.1
3.9
V
4.3
- V
4.7
5.1
5.5
V
- V
BAT
BAT
Figure 16. Line Regulation, Iout = 50 mA, Class-B
Figure 17. Current Limit vs Input Voltage, Class-B/C
150
-50 mA, Vsim
120
90
60
30
-100 mA, Vsim
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
- ºC
T
A
Figure 18. Ground Current vs Temperature, Class-C
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SCES795B –SEPTEMBER 2010–REVISED NOVEMBER 2010
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REVISION HISTORY
Changes from Revision A (November 2010) to Revision B
Page
•
Added TYPICAL CHARACTERISTICS Section ................................................................................................................. 25
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Nov-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TXS02326MRGER
TXS02326RGER
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
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information and additional product content details.
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the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TXS02326MRGER
TXS02326RGER
VQFN
VQFN
RGE
RGE
24
24
3000
3000
330.0
330.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q1
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TXS02326MRGER
TXS02326RGER
VQFN
VQFN
RGE
RGE
24
24
3000
3000
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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