UC1903_16 [TI]
Quad Supply and Line Monitor;
| 型号： | UC1903_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad Supply and Line Monitor |
| 文件： | 总16页 (文件大小：808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1903
UC2903
UC3903
www.ti.com ........................................................................................................................................ SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008
Quad Supply and Line Monitor
1
FEATURES
DESCRIPTION
•
•
•
•
Inputs for Monitoring up to Four Separate
Supply Voltage Levels
The UC1903 family of quad supply and line monitor
integrated circuits will respond to under- and
over-voltage conditions on up to four continuously
monitored voltage levels. An internal op-amp inverter
allows at least one of these levels to be negative. A
separate line/switcher sense input is available to
provide early warning of line or other power source
failures.
Internal Inverter for Sensing a Negative Supply
Voltage
Line/Switch Sense Input for Early Power
Source Failure Warning
Programmable Under- and Over-Voltage Fault
Thresholds with Proportional Hysteresis
The fault window adjustment circuit on these devices
provides easy programming of under- and
over-voltage thresholds. The thresholds, centered
around a precision 2.5-V reference, have an input
hysteresis that scales with the window width for
precise, glitch-free operation. A reference output pin
allows the sense input fault windows to be scaled
independently using simple resistive dividers.
•
•
•
A Precision 2.5-V Reference
General Purpose Op-Amp for Auxiliary Use
Three High Current, >3 0mA, Open-Collector
Outputs Indicate Over-Voltage, Under-Voltage
and Power OK Conditions
•
8-V to 40-V Supply Operation with 7-mA
Stand-By Current
The three open collector outputs on these devices
sink in excess of 30 mA of load current when active.
The under- and over-voltage outputs respond after
separate, user defined, delays to respective fault
conditions. The third output is active during any fault
condition including under- and over-voltage,
line/switcher faults, and input supply under-voltage.
The off state of this output indicates a "power OK"
situation.
BLOCK DIAGRAM
Note: Pin numbers refer to J, N and DW packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2008, Texas Instruments Incorporated
UC1903
UC2903
UC3903
SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
DESCRIPTION (CONT.)
An additional, uncommitted, general purpose op-amp is also included. This op-amp, capable of sourcing 20 mA
of output current, can be used for a number of auxiliary functions including the sensing and amplification of a
feedback error signal when the 2.5-V output is used as a system reference.
These parts operate over an 8-V to 40-V input supply range and require a typical stand-by current of only 7 mA.
CONNECTION DIAGRAMS
DIL-18, SOIC-18
J or N, DW PACKAGE
(TOP VIEW)
PLCC-20, LCC-20
Q, L PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
18
17 G.P. OP-AMP N.I.
+VIN
VREF (2.5 V)
GND
G.P. OP-AMP INV.
16
15
14
13
12
11
10
G.P. OP-AMP OUT
LINE/SWITCHER SENSE
POWER OK
WINDOW ADJUST
SENSE 4
INVERT INPUT
SENSE 4
3
2
1 20 19
UV DELAY
4
5
G.P. OP-AMP OUT
18
17
GND
SENSE 3
SENSE 2
SENSE 1
UV FAULT
LINE/SWITCHER
SENSE
POWER OK
OV FAULT
WINDOW ADJUST
OV DELAY
6
7
8
NC
SENSE 4 INVERT
INPUT
16
15
14
UV DELAY
UV FAULT
SENSE 4
9
10 11 12 13
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
+40
UNIT
V
+VIN
Supply Voltage
Open Collector Output Voltages.
Open Collector Output Currents.
Sense 1-4 Input Voltages
+40
V
50
mA
V
–0.3 to +20
–0.3 to +40
–0.3 to +40
–40
Line/Switcher Sense Input Voltage
Op-Amp and Inverter Input Voltages
Op-Amp and Inverter Output Currents .
Window Adjust Voltage.
V
V
mA
V
0.0 to +10
0.0 to +5
–40
Delay Pin Voltages
V
Reference Output Current
mA
mW
mW
°C
C
Power Dissipation at TA = 25°C(1)
Power Dissipation at TC = 25°C(1)
Operating Junction Temperature
Storage Temperature
1000
2000
–55 to +150
–65 to +150
300
Lead Temperature (Soldering, 10 Seconds)
°C
(1) Voltages are referenced to ground (Pin 3). Currents are positive into, negative out of, the specified terminals. Consult Packaging Section
of Databook for thermal limitations and considerations of package.
2
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Product Folder Link(s): UC1903 UC2903 UC3903
UC1903
UC2903
UC3903
www.ti.com ........................................................................................................................................ SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1903; –40°C to +85°C for the
UC2903; and 0°C to +70°C for the UC3903; +VIN = 15V; Sense Inputs (Pins 6–9 and Pin 15) = 2.5V; VPIN 4 = 1.0V, TA = TJ.
UC1903 / UC2903
UC3903
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
SUPPLY
Input Supply Current
No Faults
7
10
9
15
7
10
11
18
mA
mA
V
UV, OV and Line Fault
Fault Outputs Enabled
Supply Under Voltage Threshold
6.0
7.0
7.5
5.5
7.0
8.0
(VSUV
)
Minimum Supply to Enable Power
OK Output
3.0
2.5
4.0
3.0
2.5
4.0
V
REFERENCE
Output Voltage (VREF
)
TJ = 25°C
2.485
2.465
2.515
2.535
10
2.470
2.465
2.530
2.535
15
V
Over Temperature
IL = 0 to 10mA
+VIN = 8 to 40V
TJ = 25°C
V
Load Regulation
Line Regulation
1
1
1
1
mV
mV
mA
4
8
Short Circuit Current
FAULT THRESHOLDS(1)
OV Threshold Adj.
40
40
Offset from VREF as a function of VPIN
4 Input = Low to High, 0.5V ≤ VPIN 4 ≤ 2.5V
0.230
–0.270
10
0.25
0.270
0.230
0.25
0.270
V/V
V/V
UV Threshold Adj.
Offset from VREF as a function of VPIN
4 Input = High to Low, 0.5V ≤ VPIN 4 ≤ 2.5V
–0.25 –0.230 –0.270 –0.25 –0.270
OV & UV Threshold Hyst.
0.5V ≤ VPIN 4 ≤ 2.5V
20
30
10
20
30
mV/V
%/V
OV & UV Threshold Supply
Sensitivity
+VIN = 8V to 40V
0.002
0.01
0.002
0.02
Adjust Pin (Pin 4) Input Bias Current 0.5V ≤ VPIN 4 ≤ 2.5V
±1
2.0
±10
2.06
225
±1
2.0
±12
2.1
µA/V
V
Line Sense Threshold
Input = High to Low
1.94
125
1.9
Line Sense Threshold Hyst.
175
100
175
250
mV
SENSE INPUTS
Input = 2.8V(2)
Input = 2.2(2)
Input = 2.3V(2)
1
–1
1
3
–3
3
1
–1
1
6
-6
6
µA
µA
µA
Sense 1-4 Input Bias Current
Line Sense Input Bias Current
OV AND UV FAULT DELAY
Charging Current
60
1.8
250
30
60
1.8
250
30
µA
V
Threshold Voltage
Delay Pin = Low to High
TJ = 25°C
Threshold Hysteresis
Delay
mV
Ratio of Threshold Voltage to Charging
Current
20
50
20
50
ms/µF
(1) Reference to pin numbers in this specification pertain to 18 pin DIL N and J packages and 18 pin SOIC DW package.
(2) These currents represent maximum input bias currents required as the sense inputs cross appropriate thresholds.
Copyright © 1999–2008, Texas Instruments Incorporated
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UC1903
UC2903
UC3903
SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1903; –40°C to +85°C for the
UC2903; and 0°C to +70°C for the UC3903; +VIN = 15V; Sense Inputs (Pins 6–9 and Pin 15) = 2.5V; VPIN 4 = 1.0V, TA = TJ.
UC1903 / UC2903
UC3903
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
FAULT OUTPUTS (OV, UV, AND POWER 0K)
Maximum Current
Saturation Voltage
Leakage Current
SENSE 4 INVERTER(3)
Input Offset Voltage
Input Bias Current
Open Loop Gain
PSRR
VOUT = 2V
30
70
0.25
3
30
70
0.25
3
mA
V
IOUT = 12mA
VOUT = 40 V
0.40
25
0.40
25
µA
2
0.1
80
8
2
2
0.1
80
10
4
mV
µA
65
65
65
65
dB
+VIN = 8 to 40 V
TJ = 2°C
100
1
100
1
dB
Unity Gain Frequency
Slew Rate
MHz
V/µs
mA
0.4
40
0.4
40
Short Circuit Current
G.P. OP-AMP(3)
Input Offset Voltage
Input Bias Voltage
Input Offset Current
Open Loop Gain
CMRR
1
0.1
0.01
120
100
100
1
5
2
1
0.1
0.01
120
100
100
1
8
4
mV
µA
.5
1.0
µA
65
65
65
65
65
65
dB
VCM = 0 to +VIN = 2.0V
+VIN = 8 to 40V
dB
PSRR
dB
Unity Gain Frequency
Slew Rate
MHz
V/µs
mA
0.4
40
0.4
40
Short Circuit Current
TJ = 25°C
(3) When either the G.P. OP-Amp, or the Sense 4 Inverter, are configured for sensing a negative supply voltage, the divider resistance at
the inverting input should be chosen such that the nominal divider current is ≤1.4mA. With the divider current at or below this level
possible latching of the circuit is avoided. Proper operation for currents at or below 1.4mA is 100% tested in production.
4
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Product Folder Link(s): UC1903 UC2903 UC3903
UC1903
UC2903
UC3903
www.ti.com ........................................................................................................................................ SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008
Block Diagram
UC1903
TO
OV HYSTERESIS
CONTROL
+VIN
REFERENCE
CIRCUIT
I
OA
I
OB
Q4
1.25 V
Q2
Q1
OV THRESHOLD
1.84 kW
Q3
R5
2.5 V
OUTPUT
R1
15 W
R6
R7
R8
0.16 kW
0.16 kW
FAULT WINDOW
THREAHOLD and HYSTERESIS
CIRCUITS
R2
R3
2.5 kW
2.5 kW
1.84 kW
R
A
VADJ
R4
I
=
UV THRESHOLD
O
R4
8 kW
TO
UV HYSTERESIS
CONTROL
R
S
V
I
ADJ
BIAS
I
OC
OD
Q5
CANCELLATION
AND MIRROR
CIRCUITS
A. The UC1903 fault window circuitry generates OV and UV thresholds centered around the 2.5-V reference. Window
magnitude and threshold hysteresis are proportional to the window adjust input voltage at Pin 4.
Figure 1. Operation and Application Information
Typical Characteristics
Typical 2.5 V Reference
vs
Temperature Characteristic
Typical Fault Delay
vs
Temperature Characteristic (CDELAY ≥270 pF)
0.2
0.1
40
35
0
- 0.1
- 0.2
- 0.3
- 0.4
- 0.5
30
25
20
- 0.6
- 0.7
- 55 - 35 - 15
T
5
25
45
- Junction Temperature - °C
65
85 105 125
- 55 - 35 - 15
T
5
25
45
- Junction Temperature - °C
65
85 105 125
J
J
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UC1903
UC2903
UC3903
SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
OPERATION AND APPLICATION INFORMATION
Setting a Fault Window
The fault thresholds on the UC1903 are generated by creating positive and negative offsets, equal in magnitude,
that are referenced to the chip’s 2.5-V reference. The resulting fault window is centered around 2.5 V and has a
magnitude equal to that of the applied offsets. Simplified schematics of the fault window and reference circuits
are shown in Figure 1 along with the Typical Characteristics diagrams. The magnitude of the offsets is
determined by the voltage applied at the window adjust pin, Pin 4. A bias cancellation circuit keeps the input
current required at Pin 4 low, allowing the use of a simple resistive divider off the reference to set the adjust pin
voltage.
The adjust voltage at Pin 4 is internally applied across R4, and an 8-kΩ resistor. The resulting current is mirrored
four times to generate current sources IOA, IOB, IOC, and IOD, all equal in magnitude. When all four of the sense
inputs are inside the fault window, a no-fault condition, Q4 and Q5 are turned on. In combination with D1 and D2
this prevents LOB and LOD from affecting the fault thresholds. In this case, the OV and UV thresholds are equal to
VREF + IOA(R5 + R6) and VREF – IOC(R7 + R8) respectively. The fault window can be expressed as:
VADJ
2.5 V
4
(1)
In terms of a sensed nominal voltage level, VS, the window as a percent variation is:
VS
10 × V
%
)
ADJ
(
(2)
When a sense input moves outside the fault window given in Equation 1, the appropriate hysteresis control signal
turns off Q4 or Q5. For the under-voltage case, Q5 is disabled and current source IOB flows through D2. The net
current through R7 becomes zero as IOB cancels IOC, giving an 8% reduction in the UV threshold offset. The
overvoltage case is the same, with Q4 turning off, allowing IOD to cancel the current flow, IOA, through R6. The
result is a hysteresis at the sense inputs which is always 8% of the window magnitude. This is shown graphically
in Figure 2.
25
20
3.125
3
2.875
2.750
2.625
2.5
15
10
5
Hysteresis
Fault
Window
0
-5
2.375
2.25
-10
-15
-20
-25
No Fault
Fault
2.125
2
Fault
Window
1.875
2.5
0
1.5
2
) at Pin 4
0.5
1
Window Adjust Voltage (V
ADJ
Figure 2. Fault Window and Threshold Hysteresis Scale as a Function of the Voltage Applied at Pin 4
6
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UC1903
UC2903
UC3903
www.ti.com ........................................................................................................................................ SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008
Fault Windows Scaled Independently
In many applications, it may be desirable to monitor various supply voltages, or voltage levels, with varying fault
windows. Using the reference output and external resistive dividers this is easily accomplished with the UC1903.
Figure 3 and Figure 4 illustrate how the fault window at any sense input can be scaled independently of the
remaining inputs.
Monitored
Supply Voltage
V
S
UC1903
R1
SENSE 1-4 INPUT
R3
R2
2.5 V
REF.
Fault window for the Sense Input,
in percent, is:
R3 + R1R2/(R1 + R2)
–10 (VADJ)•
,
R3
for:
R2
R1 + R2
VS (NOM)•
= 2.5V
A. Using the reference output and a resistive divider, a sense input with an independently wider fault window can be
generated.
Figure 3. UC1903 Sense Input with an Independently Wider Fault Window
UC1903
G.P. OP-AMP
R1
SENSE
INPUT
R2
2.5 V
REF.
SENSE 1-4 INPUT
Fault window for the sense input, in percent, is:
R2
ADJ
10 (V
)
•
R1 + R2
A. The general purpose op-amp on the UC1903 can be used to create a sense input with an independently tighter fault
window.
Figure 4. UC1903 Sense Input with an Independently Tighter Fault Window
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UC2903
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Figure 4 demonstrates one of many auxiliary functions that the uncommitted op-amp on the UC1903 can be used
for. Alternatively, this op-amp can be used to buffer high impedance points, perform logic functions, or for
sensing and amplification. For example, the G.P. op-amp, combined with the 2.5-V reference, can be used to
produce and buffer an optically coupled feedback signal in isolated supplies with primary side control. The output
stage of this op-amp is detailed in Figure 5. The NPN emitter follower provides high source current capability.
≥20 mA while the substrate device, Q3, provides good transient sinking capability.
+V
IN
75 mA
Q1
Q2
R1
10 kW
UC1903
G.P. OP-AMP
OUTPUT STAGE
Q6
D1
R2
15 W
16
R3
150 W
OUTPUT
Q3
TO OP-AMP
INPUT STAGE
Q5
Q4
R4
500 W
150 mA
A. The G.P. op-amp on the UC1903 has a high source current (20 mA) capability and enhanced transient sinking
capability through substrate device Q3.
Figure 5. The G.P. Op-Amp on the UC1903
Sensing a Negative Voltage Level
The UC1903 has a dedicated inverter coupled to the sense 4 input. With this inverter, a negative voltage level
can be sensed as shown in Figure 6. The output of the inverter is an unbiased emitter follower. By tying the
inverting input, Pin 5, high the output emitter follower will be reverse biased, leaving the sense 4 input in a high
impedance state. In this manner, the sense 4 input can be used, as the remaining sense inputs would be, for
sensing positive voltage levels.
UC1903
SENSE 4 INPUT
R1
2.5 V
SENSE 4
INVERTER
R2
V
S
GROUND
(NOM) = 2.5 V
NEGATIVE
SUPPLY (-V )
V
S
S
Note: A similar scheme w/the G.P. op-amp will allow a sec-
ond negative supply to be monitored.
Figure 6. Inverting the Sense 4 Input for Monitoring a Negative Supply, Accommodated with the
Dedicated Inverter
8
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UC1903
UC2903
UC3903
www.ti.com ........................................................................................................................................ SLUS233A–OCTOBER 1999–REVISED SEPTEMBER 2008
Using The Line/Switcher Sense Output
The line switcher sense input to the UC1903 can be used for early detection of line, switcher, or other power
source, failures. Internally referenced to 2.0 V, the line sense comparator will cause the POWER OK output to
indicate a fault (active low) condition when the LINE/SWITCHER SENSE input goes from above to below 2.0 V.
The line sense comparator has approximately 175 mV of hysteresis requiring the line/switcher input to reach
2.175 V before the POWER OK output device can be turned off, allowing a no-fault indication. In Figure 7 an
example showing the use of the LINE/SWITCHER SENSE input for early switcher-fault detection is detailed. A
sample signal is taken from the output of the power transformer, rectified and filtered, and used at the
line/switcher input. By adjusting the R2C time constant with respect to the switching frequency of the supply and
the hold up time of the output capacitor, switcher faults can be detected before supply outputs are significantly
affected.
POWER
LINE
INPUT
FILTER
TRANSFORMER
Figure 7. Line/Switcher Sense Input Used for Early Line or Switcher Fault Indication
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UC2903
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OV and UV Comparators Maintain Accurate Thresholds
The structure of the OV and UV comparators, shown in Figure 8 results in accurate fault thresholds even in the
case where multiple sense inputs cross a fault threshold simultaneously. Unused sense inputs can be tied either
to the 2.5-V reference, or to another, utilized, sense input. The four under- and over-voltage sense inputs on the
UC1903 are clamped as detailed on the Sense 1 input in Figure 8. The series 2-kΩ resistor, R1, and zener diode
Z1, prevent extreme under- and over-voltage conditions from inverting the outputs of the fault comparators. A
parasitic diode, D1, is present at the inputs as well. Under normal operation it is advisable to insure that voltage
levels at all of the sense inputs stay above –0.3 V. The same type of input protection exists at the line sense
input, Pin 15, except a 5-kΩ series resistor is used.
The fault delay circuitry on the UC1903 is also shown in Figure 8. In the case of an over-voltage condition at one
of the sense inputs Q20 is turned off, allowing the internal 60-mA current source to charge the user-selected
delay capacitor. When the capacitor voltage reaches 1.8 V, the OV and POWER OK outputs become active low.
When the fault condition goes away Q20 is turned back on, rapidly discharging the delay capacitor. Operation of
the under- voltage delay is, with appropriate substitutions, the same.
6.4 V
60 mA
EXT.
OV DELAY
CAPACITOR
6.4 V
Q7 Q8
Q9
OV FAULT
INDICATION
TO OUTPUT
LOGIC
Q6
Q20
1.8 V
OV COMPARATOR
Q3
Q2
Q4
Q5
Q1
OV
HYSTERESIS
CONTROL
TO OV
THRESHOLD
VOLTAGE
SENSE 1
2 kW
100 mA
R1
D1
Z1
5.7 V
6.4 V
SENSE 2
SENSE 3
SENSE 4
50 mA
TO UV
THRESHOLD
VOLTAGE
UV
V
6.4 V
60 mA
REF
EXT.
HYSTERESIS
CONTROL
Q11 Q12 Q13 Q14
Q10
UV DELAY
CAPACITOR
UV FAULT
INDICATION
TO OUTPUT
LOGIC
UV COMPARATOR
Q19
1.8 V
Q15 Q16
Q17 Q18
A. The OV and UV comparators on the UC1903 trigger respective fault delay circuits when one or more of the sense
inputs move outside the fault window. Input clamps insure proper operation under extreme fault conditions.
Terminating the UV delay capacitor to VREF assures correct logic at power up.
Figure 8. OV and UV Comparators on the UC1903
Start Latch and Supply Under-Voltage Sense Allow Predictable Power-Up
At power-Up, while the +VIN input supply is below 3 V, all open collector outputs are off. With +VIN greater than 3
V the POWER OK output will be driven low and the UV OV FAULT outputs are disabled. Once +VIN rises above
the VSUV threshold of 7 V the fault outputs will be enabled. As would be expected, the SENSE 1-4 voltages at
power up may be below the UVFAULT window and the UVFAULT output may be driven low.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
5962-88697012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
-55 to 125 5962-
88697012A
UC1903L/
883B
5962-8869701VA
ACTIVE
CDIP
J
18
1
TBD
Call TI
Call TI
-55 to 125 5962-8869701VA
UC1903J/883B
UC1903J
ACTIVE
ACTIVE
CDIP
CDIP
J
J
18
18
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125 UC1903J
UC1903J883B
-55 to 125 5962-8869701VA
UC1903J/883B
UC1903L
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125 UC1903L
UC1903L883B
-55 to 125 5962-
88697012A
UC1903L/
883B
UC2903DW
UC2903DWG4
UC2903DWTR
UC2903DWTRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
18
18
18
18
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
UC2903DW
UC2903DW
UC2903DW
UC2903DW
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2903J
UC2903N
ACTIVE
ACTIVE
CDIP
PDIP
J
18
18
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-40 to 85
-40 to 85
UC2903J
UC2903N
N
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
UC2903NG4
UC2903Q
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PLCC
PLCC
SOIC
N
18
20
20
18
20
46
46
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
N / A for Pkg Type
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
0 to 70
UC2903N
UC2903Q
UC2903Q
UC3903DW
FN
FN
DW
Green (RoHS
& no Sb/Br)
UC2903QG3
UC3903DW
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
UC3903DWG4
UC3903DWTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
18
18
18
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC3903DW
UC3903DW
UC3903DW
2000
2000
Green (RoHS
& no Sb/Br)
0 to 70
UC3903DWTRG4
Green (RoHS
& no Sb/Br)
0 to 70
UC3903J
UC3903N
ACTIVE
ACTIVE
CDIP
PDIP
J
18
18
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
UC3903J
UC3903N
N
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
UC3903NG4
UC3903Q
ACTIVE
ACTIVE
ACTIVE
PDIP
PLCC
PLCC
N
18
20
20
20
46
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
N / A for Pkg Type
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
0 to 70
UC3903N
UC3903Q
UC3903Q
FN
FN
Green (RoHS
& no Sb/Br)
UC3903QG3
Green (RoHS
& no Sb/Br)
CU SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1903, UC2903, UC2903M, UC3903, UC3903M :
Catalog: UC3903, UC2903, UC3903M, UC3903
•
Military: UC2903M, UC1903, UC1903
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC3903DWTR
SOIC
DW
18
2000
330.0
24.4
10.9
12.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 18
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
UC3903DWTR
2000
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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