UC2524ANG4 [TI]
Advanced Regulating Pulse Width Modulators; 高级稳压脉宽调制器
| 型号： | UC2524ANG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced Regulating Pulse Width Modulators |
| 文件： | 总8页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1524A
UC2524A
UC3524A
Advanced Regulating Pulse Width Modulators
FEATURES
DESCRIPTION
•
•
•
•
•
Fully Interchangeable with
Standard UC1524 Family
The UC1524A family of regulating PWM ICs has been designed to retain the
same highly versatile architecture of the industry standard UC1524 (SG1524)
while offering substantial improvements to many of its limitations. The UC1524A
is pin compatible with “non-A” models and in most existing applications can be
directly interchanged with no effect on power supply performance. Using the
UC1524A, however, frees the designer from many concerns which typically had
required additional circuitry to solve.
Precision Reference Internally
±
Trimmed to 1%
High-Performance Current Limit
Function
Under-Voltage Lockout with
Hysteretic Turn-on
±
The UC1524A includes a precise 5V reference trimmed to 1% accuracy, elimi-
nating the need for potentiometer adjustments; an error amplifier with an input
range which includes 5V, eliminating the need for a reference divider; a current
sense amplifier useful in either the ground or power supply output lines; and a
pair of 60V, 200mA uncommitted transistor switches which greatly enhance out-
put versatility.
Start-Up Supply Current Less
Than 4mA
•
•
•
Output Current to 200mA
60V Output Capability
An additional feature of the UC1524A is an under-voltage lockout circuit which
disables all the internal circuitry, except the reference, until the input voltage has
risen to 8V. This holds standby current low until turn-on, greatly simplifying the
design of low power, off-line supplies. The turn-on circuit has approximately
600mV of hysteresis for jitter-free activation.
Wide Common-Mode Input
Range for both Error and
Current Limit Amplifiers
•
•
•
•
•
PWM Latch Insures Single
Pulse per Period
Other product enhancements included in the UC1524A’s design include a PWM
latch which insures freedom from multiple pulsing within a period, even in noisy
environments, logic to eliminate double pulsing on a single output, a 200ns ex-
ternal shutdown capability, and automatic thermal protection from excessive
chip temperature. The oscillator circuit of the UC1524A is usable beyond 500kHz
and is now easier to synchronize with an external clock pulse.
Double Pulse Suppression
Logic
200ns Shutdown through PWM
Latch
The UC1524A is packaged in a hermetic 16-pin DIP and is rated for operation
from -55°C to +125°C. The UC2524A and 3524A are available in either ceramic
or plastic packages and are rated for operation from -40°C to +85°C and 0°C to
70°C, respectively. Surface mount devices are also available.
Guaranteed Frequency
Accuracy
Thermal Shutdown Protection
BLOCK DIAGRAM
+5V
15
3
REFERENCE
REGULATOR
16
12
V
V
REF
IN
POWER TO
INTERNAL
CIRCUITRY
U.V.
SENSE
C
A
OSC
FLIP
FLOP
6
7
T
R
T
11
13
E
A
OSC
CLOCK
C
T
COMP
RAMP
R
C
+
B
S
PWM
LATCH
–
COMP
9
1
S
V
IN
INV. INPUT
14
E
B
–
E/A
+
1k
10 SHUTDOWN
N.I. INPUT
2
4
V
200mV
IN
6V
10k
5.5V
CL (+) SENSE
8
GND
+
C/L
–
CL (–) SENSE
5
UDG-99178
SLUS181A - NOVEMBER 1999
UC1524A
UC2524A
UC3524A
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAMS
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . . 60V
Output Current (each Output). . . . . . . . . . . . . . . . . . . . . 200mA
Maximum Forced Voltage (Pin 9, 10) . . . . . . . . . . . . . -3 to +5V
Maximum Forced Current (Pin 9, 10) . . . . . . . . . . . . . . . ±10mA
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Power Dissipation at TA = +25°C. . . . . . . . . . . . . . . . . 1000mW
Power Dissipation at TC = +25°C . . . . . . . . . . . . . . . . 2000mW
Operating Temperature Range . . . . . . . . . . . . -55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature, (Soldering, 10 seconds) . . . . . . . . . +300°C
Note: Consult packaging section of Databook for thermal limita-
tions and considerations of package.
PLCC-20, LCC-20 (TOP VIEW)
Q or L Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
Inv. Input
Non-Inv. Input
OSC/SYNC
C.L. (+) sense
N/C
2
3
4
5
6
C.L. (-) sense
RT
7
8
CT
9
Ground
10
11
12
13
14
15
16
17
18
19
20
DIL-16, SOIC-16 (TOP VIEW)
J or N Package, DW Package
N/C
Compensation
Shutdown
Emitter A
Collector A
N/C
Collector B
Emitter B
+VIN
+5V VREF
Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN
= VC = 20V, TA = TJ.
ELECTRICAL CHARACTERISTICS:
UC1524A / UC2524A
UC3524A
TYP
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
Turn-on Characteristics
Input Voltage
Operating Range after Turn-on
8
40
8.5
4
8
40
8.5
4
V
V
Turn-on Threshold
Turn-on Current
6.5
7.5
2.5
5
6.5
7.5
2.5
5
VIN = 6V
mA
mA
V
Operating Current
Turn-on Hysteresis*
Reference Section
Output Voltage
VIN = 8 to 40V
10
10
0.5
0.5
TJ = 25°C
4.95
4.9
5.00
5.05
5.1
20
4.90
4.85
5.00
5.10
5.15
30
V
V
Over Operating Range
VIN = 10 to 40V
Line Regulation
10
20
20
80
40
20
10
20
20
80
40
20
mV
mV
mV
mA
µVrms
mV
Load Regulation
IL = 0 to 20 mA
25
35
Temperature Stability*
Short Circuit Current
Output Noise Voltage*
Long Term Stability*
Over Operating Range*
VREF = 0, 25°C ≤ TJ ≤ 125°C
10Hz ≤ f ≤ 10kHz, TJ =25°C
TJ =125°C, 1000 Hrs.
25
35
100
100
50
50
* These parameters are ensured by design but not 100% tested in production.
2
UC1524A
UC2524A
UC3524A
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN
= VC = 20V, TA = TJ.
UC1524A / UC2524A
UC3524A
TYP
UNITS
PARAMETER
TEST CONDITIONS
MIN
Oscillator Section (Unless otherwise specified, RT = 2700Ω, CT = 0.01 mfd)
TYP
43
1
MAX
MIN
MAX
Initial Accuracy
TJ = 25°C
41
45
45.9
2
39
43
1
47
47.9
2
kHz
kHz
%
Over Operating Range
Over Operating Temperature Range
RT = 150kΩ, CT = 0.1mfd
RT = 2.0kΩ, CT = 470pF
40.2
38.2
Temperature Stability*
Minimum Frequency
Maximum Frequency
Output Amplitude*
Output Pulse Width*
Ramp Peak
140
120
Hz
500
3
500
3
kHz
V
3.5
0.5
3.5
0.8
-1.0
3.5
0.5
3.5
0.8
-1.0
0.29
3.3
0.7
1.0
3.7
0.9
0.3
3.3
0.7
1.0
3.7
0.9
µs
V
Ramp Valley
TJ = 25°C
V
Ramp Valley T.C.
mV/°C
Error Amplifier Section (Unless otherwise specified, VCM = 2.5V)
Input Offset Voltage
0.5
1
5
5
1
2
1
10
10
1
mV
µA
µA
dB
Input Bias Current
Input Offset Current
.05
80
80
0.5
80
80
Common Mode Rejection Ratio VCM = 1.5 to 5.5V
Power Supply Rejection Ratio VIN = 10 to 40V
Output Swing (Note 1)
70
70
5.0
72
1
70
70
5.0
64
1
dB
0.5
0.5
V
Open Loop Voltage Gain
Gain-Bandwidth*
∆VO= 1 to 4V, RL ≥ 10MΩ
TJ = 25°C, AV = 0dB
80
3
80
3
dB
MHz
mS
DC Transconductance*§
TJ = 25°C, 30kΩ ≤ RL ≤ 1MΩ
1.7
2.3
1.7
2.3
P.W.M. Comparator (RT = 2kΩ, CT = 0.01mfd)
Minimum Duty Cycle
Maximum Duty Cycle
VCOMP = 0.5V
VCOMP = 3.8V
0
0
%
%
45
45
Current Limit Amplifier (Unless otherwise specified, Pin 5 = 0V)
Input Offset Voltage
TJ = 25°C, E/A Set for Maximum
Output
190
180
200
210
180
170
200
220
mV
Over Operating Temperature Range
220
-10
230
-10
mV
µA
dB
dB
V
Input Bias Current
-1
60
60
-1
60
60
Common Mode Rejection Ratio V(pin 5) = -0.3V to + 5.5V
Power Supply Rejection Ratio VIN = 10 to 40V
50
50
5.0
70
50
50
5.0
70
Output Swing (Note 1)
Open-Loop Voltage Gain
Delay Time*
Minimum Total Range
0.5
0.5
20
∆VO = 1 to 4V, RL ≥ 10MΩ
Pin 4 to Pin 9, ∆VIN = 300mV
80
80
dB
ns
300
300
Output Section (Each Output)
Collector Emitter Voltage
Collector Leakage Current
IC = 100µA
60
80
.1
60
80
.1
V
VCE = 50V
20
µA
* These parameters are ensured by design but not 100% tested in production.
§ DC transconductance (gM) relates to DC open-loop voltage gain according to the following equation: AV = gMRL
where RL is the resistance from pin 9 to the common mode voltage.
The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded.
Note 1: Min Limit applies to output high level, max limit applies to output low level.
3
UC1524A
UC2524A
UC3524A
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the
UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN
= VC = 20V. TA = TJ.
UC1524A / UC2524A
UC3524A
TYP
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
Output Section ( cont.) (Each Output)
Saturation Voltage
IC = 20mA
IC = 200mA
.2
1
.4
2.2
.2
1
.4
2.2
V
V
Emitter Output Voltage
Rise Time*
IE = 50mA
17
18
120
25
17
18
120
25
V
ns
ns
ns
ns
V
TJ = 25°C, R = 2kΩ
400
200
400
200
Fall Time*
TJ = 25°C, R = 2kΩ
Comparator Delay*
Shutdown Delay*
Shutdown Threshold
S/D Threshold Over Temp.
Thermal Shutdown*
TJ = 25°C, Pin 9 to output
TJ = 25°C, Pin 10 to output
TJ = 25°C, RC = 2kΩ
300
200
.7
300
200
.7
0.6
0.4
1.0
1.2
0.6
0.4
1.0
1.0
Over Operating Temperature Range
V
165
165
°C
* These parameters are ensured by design but not 100% tested in production.
OPEN-LOOP CIRCUIT
4
UC1524A
UC2524A
UC3524A
Supply Current vs Voltage
Error Amplifier Voltage Gain
and Phase vs Frequency
Pulse Width Modulator
Transfer Function
Oscillator Frequency
vs Timing Components
Output Dead Time vs Timing Capacitor Value
Output Saturation Voltage
5
UC1524A
UC2524A
UC3524A
Shutdown Delay From PWM Comparator - Pin 9
Current Limit Amplifier Delay
Turn-Off Delay From Shutdown - Pin 10
6
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
LCCC
LCCC
SOIC
SOIC
CDIP
PDIP
PDIP
Drawing
5962-8764502EA
UC1524AJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
20
20
16
16
16
16
16
1
1
None
None
None
None
None
None
None
None
None
None
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
UC1524AJ/80503
UC1524AJ883B
UC1524AL
J
1
J
1
FK
FK
DW
DW
J
1
POST-PLATE Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UC1524AL883B
UC2524ADW
UC2524ADWTR
UC2524AJ
1
40
2000
1
A42 SNPB
CU SNPB
Level-NC-NC-NC
Level-NA-NA-NA
UC2524AN
N
25
UC2524ANG4
N
1000 Green (RoHS & CU NIPDAU Level-NA-NA-NA
no Sb/Br)
UC3524ADW
UC3524ADWTR
UC3524AJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
CDIP
PDIP
DW
DW
J
16
16
16
16
40
2000
1
None
None
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
A42 SNPB
CU SNPB
Level-NC-NC-NC
Level-NA-NA-NA
UC3524AN
N
25
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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