UCC1806L883B_技术文档

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

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for applications ranging from off-line power

supplies to battery operated portable equipment.

Dual high-current, MOSFET driving outputs and a

fast current sense loop further enhance device

versatility.

FEATURES

D

BiCMOS Version of UC3846 Family

1.4-mA Maximum Operating Current

100-µA Maximum Startup Current

0.5-A Peak Output Current

125-ns Circuit Delay

All the benefits of current mode control including

simpler loop closing, voltage feed-forward,

parallelability with current sharing, pulse-by-pulse

current limiting, and push/pull symmetry

correction are readily achievable with the

UCC3806 series.

Easier Parallelability

Improved Benefits of Current Mode Control

DESCRIPTION

These devices are available in multiple package

options for both through-hole and surface mount

applications; and in commercial, industrial, and

military temperature ranges.

The UCC3806 family of BiCMOS PWM controllers

offers exceptionally improved performance with a

familiar architecture. With the same block diagram

and pinout of the popular UC3846 series, the

UCC3806 line features increased switching

frequency capability while greatly reducing the

bias current used within the device. With a typical

startup current of 50 µA and a well defined voltage

threshold for turn-on, these devices are favored

The UCC3806 is specified for operation from

−55°C to 125°C, the UCC2806 is specified for

operation from −40°C to 85°C, and the UCC3806

is specified for operation from 0°C to 70°C.

SIMPLIFIED APPLICATION DIAGRAM

+V

OUT

+V

IN

UC39431

15

13

VIN

VC

UCC3612

UCC3806

2

VREF

INV

6

7

COMP

8

5

1

CT

NI

AOUT 11

BOUT 14

CURLIM

SHUT

15

10 SYNC

DOWN

9

RT

CS− GND

12

CS+ 4

3

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Copyright  1999 − 2003, Texas Instruments Incorporated

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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ

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1

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

UCx806

UNIT

V

Supply voltage, V

IN

VIN, low impedance

VIN, high impedance

VC

15

Supply current, I

IN

25

mA

V

Output supply voltage

18

Continuous source or sink

Gate drive

200

500

30

Output current

mA

SYNC

COMP

10 to −(self-limiting)

Analog input voltage range

CS−, CS+, NI, INV, SHUTDOWN

−0.3 to (V + 0.3)

IN

V

Storage temperature, T

stg

−65 to 150

−55 to 150

300

°C

Operating temperature, T

J

Lead temperature, T

sol,

1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is

not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to

GND. Currents are positive into and negative out of, the specified terminal.

RECOMMENDED OPERATING CONDITIONS

MIN

8.0

−55

−40

0

NOM

MAX UNIT

Input voltage, V

IN

14.5

125

85

V

UCC1806

UCC2806

UCC3806

Operating junction temperature, T

°C

J

70

PACKAGE DESCRIPTION

Q OR L PACKAGE

(TOP VIEW)

D, DW, J, M, N OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CURLIM

VREF

CS−

CS+

NI

INV

COMP

CT

SHUTDOWN

VIN

BOUT

VC

3

2

1

20 19

18

BOUT

VC

CS−

CS+

N/C

NI

4

5

6

7

8

GND

17

16

15

14

AOUT

SYNC

RT

N/C

GND

AOUT

INV

9 10 11 12 13

N/C − No connection

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

ORDERING INFORMATION

PACKAGED DEVICES

T = T

A J

DESIGNATOR

TYPE

OPTION

QUANTITY

40

− 55°C to 125°C

− 40°C to 85°C

UCC2806D

0°C to 70°C

–

Tube

Reeled

Tube

–

D

SOIC−16

2,500

40

–

UCC2806DTR

UCC2806DW

UCC2806DWTR

UCC2806J

–

UCC3806DW

UCC3806DWTR

UCC3806J

–

DW

SOICW−16

Reeled

Tube

2,000

25

–

J

L

CDIP−16

CLCC−20

SSOP−16

PDIP−16

UCC1806J

Tube

55

UCC1806L

–

M

N

Reeled

Tube

2,500

25

–

UCC2806MTR

UCC2806N

–

UCC3806N

UCC3806PW

UCC3806PWTR

UCC3806Q

UCC3806QTR

Tube

90

UCC2806PW

UCC2806PWTR

UCC2806Q

PW

Q

TSSOP−16

PLCC−20

Reeled

Tube

2,000

46

Reeled

1,000

UCC2806QTR

ELECTRICAL CHARACTERISTICS

V

= 12 V, R = 33 kΩ, C = 330 pF, C

BYPASS

on V = 0.01 µF, −55°C < T < 125°C for the UCC1806, −40°C < T < 85°C for the

REF A A

IN

T

UCC2806, 0°C < T < 70°C for the UCC3806, and T = T (unless otherwise noted)

A

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE

UCC1806

UCC2806

5.02

5.00

5.10

5.17

V

Supply, UVLO, turn-on

Load regulation

V

REF

UCC3806

5.10

3

5.20

25

0.2 mA ≤ I

OUT

≤ 5 mA

mV

(1)(2)

Total output variation

Output noise voltage

Line, load, temperature

10 Hz ≤ f ≤ 10 kHz,

−150

150

(2)

T

J

= 25°C

70

5

µV

mV

mA

OSC

= 125°C,

(2)

Long term stability

T

A

1000 hours

25

Output short circuit

−10

42

−30

OSCILLATOR

Initial accuracy

Temperature stability

Amplitude

T

J

= 25°C

47

2%

52

kHz

V

(2)

T(min) ≤ T ≤ T(max)

A

2.35

UCC1806

UCC2806 0.8 V ≤ V

V

= 0 V,

V

= V

CT

RT

≤ 2.0 V

REF

50

125

100

SYNC

t

Delay-to-output time, SYNC

ns

DELAY

V

= 0 V,

V

CT

0.8 V ≤ V

RT

≤ 2.0 V

REF

UCC3806

SYNC

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

ELECTRICAL CHARACTERISTICS

V

= 12 V, R = 33 kΩ, C = 330 pF, C

on V = 0.01 µF, −55°C < T < 125°C for the UCC1806, −40°C < T < 85°C for the

REF A A

IN

T

BYPASS

UCC2806, 0°C < T < 70°C for the UCC3806, and T = T (unless otherwise noted)

A

J

PARAMETER

OSCILLATOR (continued)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

Discharge current

T

J

= 25°C,

V

CT

= 2.0 V

2

mA

DCHG

V

Low-level output voltage, SYNC

High-level output voltage, SYNC

Low-level input voltage, SYNC

High-level input voltage, SYNC

Input current, SYNC

I

= 1 mA

= −4 mA

= 0 V,

0.4

0.8

1

OL

OH

IL

OUT

2.4

OUT

V

= V

CT

RT

REF

= 0 V,

2.0

−1

IH

CT

RT

REF

I

µA

SYNC

ERROR AMPLIFIER

UCC1806

UCC2806

5

Input offset voltage

mV

UCC3806

10

−1

I

Input bias current

Input offset current

Common mode range

Open loop gain

µA

nA

BIAS

500

OFSET

(1)

CMR

0

80

1

V

−2

V

IN

A

VOL

GBW

1 V ≤ V

OUT

≤ 4 V

100

dB

bandwidth

MHz

mA

µA

I

Output sink current

Output source current

V

ID

V

ID

V

ID

V

ID

< −20 mV,

< 20 mV,

= −50 mV

V

= 1 V

= 3 V

1

COMP_SINK

COMP

I

−80

−120

COMP_SRC

COMP

V

Low-level output voltage

High-level output voltage

0.5

COMP_L

COMP_H

V

4.5

CURRENT SENSE AMPLIFIER

(3)(4)

Amplifier gain

A

V

= 0 V,

V

= V

REF

2.75

1.1

3.00

3.35

V/V

V

CS−

CURLIM

Maximum differential input signal (V

V

= V = V

NI REF,

CS+

CURLIM

= 0V

− V

)

CS−

INV

UCC1806

UCC2806

V

= 0.5 V,

V

= OPEN

10

30

50

µA

CURLIM

COMP

Input offset voltage

UCC3806

V

mV

dB

µA

CMRR

PSRR

Common mode rejection ratio

Power supply rejection ratio

0 V ≤ V

≤ (V − 3.5 V)

IN

60

56

CM

(3)

I

Input bias current

V

= 0.5 V,

V

= OPEN

−1

1

BIAS

CURLIM

COMP

(3)

Input offset current

CURLIM

COMP

V

(V

= V

REF,

= 0 V,

INV

NI

CURLIM

− V

(5)

Delay-to-output time

= 2.75 V,

125

0.5

175

ns

) = 0 V to 1.5 V step

CS−

CS+

CURRENT LIMIT ADJUST

Current limit offset

Input bias current

V

CS−

= V

= 0 V,V

COMP

= OPEN

0.4

0.6

1

V

CS+

I

BIAS

Minimum latching current

300

200

µA

Maximum non-latching current

80

(1)

(2)

Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA

Ensured by design. Not production tested.

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

ELECTRICAL CHARACTERISTICS

V

= 12 V, R = 33 kΩ, C = 330 pF, C

BYPASS

on V = 0.01 µF, −55°C to 125°C for the UCC1806, −40°C < T < 85°C for the UCC2806,

IN

T

REF A

0°C < T < 70°C for the UCC3806, and T = T (unless otherwise noted)

A

J

SHUTDOWN TERMINAL

UCC1806

UCC2806

0.94

1.00

1.0

1.06

1.1

Threshold voltage

Input voltage range

V

UCC3806

0.9

0

V

IN

t

Delay-to-output time

0 V ≤ V

SHUTDOWN

≤ 1.3 V

75

150

ns

DLY

OUTPUT

Output supply voltage

2.5

15.0

300

1.1

I

= 20 mA

= 100 mA

= 20 mA

100

0.4

UCC1806 SINK

UCC2806

I

SINK

SRC

Low-level output voltage

High-level output voltage

100

0.4

200

1.1

V

UCC3806

= 100 mA

= −20 mA

= −100 mA

11.6

11.0

11.9

11.6

35

t

Rise time

Fall time

T

= 25°C,

C

= 1000 pF

65

RISE

J

LOAD

ns

T

= 25°C,

C

35

FALL

UNDERVOLTAGE LOCKOUT (UVLO)

V

Startup threshold voltage

Threshold hysteresis

Startup current

6.5

7.5

0.75

50

8.0

V

START

I

V

IN

< V

START

100

1.4

µA

mA

START

Operating supply current

1.0

V

IN

shunt voltage

I

= 10 mA

15.0

17.5

VIN

(1)

(2)

(3)

(4)

(5)

Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA

Ensured by design. Not production tested.

Parameters measured at trip point of latch with V = VREF , V

= 0V.

NI INV

Amplifier gain defined as: G = delta change at COMP /delta change forced at CS+ delta voltage at CS+ = 0 to 1V

Current-sense amplifier output is slew rate limited to provide noise immunity.

THERMAL RESISTANCE TABLE

PACKAGE

θ

JA

JC

PACKAGE TYPE

DESIGNATOR

(°C/W)

35

(°C/W)

50 to 120

50 to 100

(1)

D

SOIC−16

SOICW−16

CDIP−16

DW

27

J

28

80 to 120

70 to 80

L

CLCC−20

SSOP−16

PDIP−16

20

(2)

144 to 172

M

38

(1)

90

N

PW

45

(2)

TSSOP−16

15

123 to 147

(1)

Q

PLCC−20

34

43 to 75

(1)

(2)

2

(junction to ambient) is for devices mounted to 5 in FR4 PC board

with one ounce copper where noted. When resistance range is given, lower values

are for 5 in aluminum PC board. Test PWB was 0.062 in thick and typically used

0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power

packages with a 100x100 mil probe land area at the end of each trace.

Specified θ

JA

2

Modeled data. If value range given for θ , the lower value is for 3x3 inch1 oz

JA

internal copper ground plane, and the higher value is for 1x1 inch ground plane. All

model data assumes only one trace for each non-fused lead.

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

TERMINAL FUNCTIONS

TERMINAL

PACKAGES

I/O

DESCRIPTION

NAME

D/DW/J/M

/N/PW

L,Q

AOUT

11

14

7

14

18

9

O

High-current gate drive for the external MOSFETs

BOUT

COMP

CS−

O

I

Output of the error amplifier

3

4

Inverting input of the 3×, differential current sense amplifier

Non-inverting input of the 3×, differential current sense amplifier

Oscillator timing capacitor connection point

CS+

4

5

I

CT

8

10

I

Programs the primary current limit threshold that determins latching or retry after an

overcurrent situation

CURLIM

1

2

I

GND

INV

NI

12

6

15

8

−

I

Reference ground and power ground for all functions of this device

Inverting input of the error amplifier.

5

7

I

Non-nverting input of the error amplifier.

RT

9

12

I

Connection point for the oscillator timing resistor

Provided for enhanced protection. When SHUTDOWN is driven above 1 V, AOUT and

BOUT are forced low.

SHUTDOWN

16

20

I

SYNC

VC

10

13

15

2

13

17

19

3

I/O

Allows providing external synchronization with TTL compatible thresholds.

Input supply connection for the FET drive outputs.

Input supply connection for this device.

I

VIN

VREF

O

Reference output.

DETAILED PIN DESCRIPTIONS

AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty

cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS

transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing

operation without the use of clamp diodes.

COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier is

a low output impedance, 2-MHz operational amplifier which allows sinking or sourcing of current at the COMP

pin. The error amplifier is internally current limited, so that zero duty cycle can be commanded by externally

forcing COMP to GND.

CS−: CS− is the inverting input of the 3× differential current sense amplifier.

CS+: CS+ is the non-inverting input of the 3× differential current sense amplifier.

CT: CT is the oscillator timing capacitor connection point, which is charged by the current set by RT. CT is

discharged to GND through a 2.6-mA current sink. This causes a linear discharge of CT to 0 V which then

initiates the next switching cycle. Dead time occurs during the discharge of CT, forcing AOUT and BOUT low.

Switching frequency (f ) and dead time (t ) are approximated by:

S

D

1

f +

and

t

+ 961 C

T

S

D

2 R C ) t

T

D

(1)

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

DETAILED PIN DESCRIPTIONS (continued)

CURLIM: CURLIM programs the primary current limit threshold and determines whether the device latches off

or retries after an overcurrent condition. When a shutdown signal is generated, a 200-µA current source to

ground pulls down on CURLIM. If the voltage on the pin remains above 350 mV the device remains latched and

the power must be cycled to restart. If the voltage on the pin falls below 350 mV, the device attempts a restart.

The voltage threshold is typically set by a resistor divider from V

adjust voltage threshold the following equations can be used.

to ground. To calculate the current limit

REF

Current limit adjust latching mode voltage is calculated in equation (2)

(

)

V

* R1 300 mA 3

REF

V +

u 350 mV

R1

ǒ Ǔ

1 )

R2

(2)

Current limit adjust non-latching mode voltage is calculated in equation (3)

(

)

V

* R1 80 mA 3

REF

V +

t 350 mV

R1

ǒ Ǔ

1 )

R2

(3)

where

D

R1 is the resistance from the VREF to CURLIM

R2 is the resistance from CURLIM to GND

D

GND: GND is the reference ground and power ground for all functions of this part. Bypass and timing capacitors

should be connected as close as possible to GND.

RT: RT is the connection point for the oscillator timing resistor. It has a low impedance input and is nominally

at 1.25 V. The current through RT is mirrored to the timing capacitor pin, CT. This causes a linear charging of

CT from 0 V to 2.35 V. Note that the current mirror is limited to a maximum of 100 µA so R must be greater

T

than 12.5 kΩ.

SYNC: SYNC is a bi-directional pin, allowing or providing external synchronization with TTL compatible

thresholds. In a typical application RT is connected through a timing resistor to GND which allows the internal

oscillator to free run. In this mode SYNC outputs a TTL compatible pulse during the oscillator dead time (when

CT is being discharged). If RT is forced above 4.4 V, SYNC acts as an input with TTL compatible thresholds

and the internal oscillator is disabled. When SYNC is high, greater than 2 V the outputs are held active low.

When SYNC returns low, the outputs may be high until the on−time is terminated by the normal peak current

signal, a fault seen at SHUTDOWN or the next high assertion of SYNC. Multiple UCC3806s can be

synchronized by a single master UCC3806 or external clock.

VC: VC is the input supply connection for the FET drive outputs and has an input range from 2.5 V to 15 V. VC

should be capacitively bypassed for proper operation.

VIN: VIN is the input supply connection for this device. The UCC1806 has a maximum startup threshold of 8 V

and internally limited by means of a 15 V shunt regulator. The shunted supply current must be limited to 2.5 mA.

For proper operation, VIN must be bypassed to GND with at least a 0.01-µF ceramic capacitor

VREF: VREF is a 5.1 V 1% trimmed reference output with a 5 mA maximum available current. VREF must be

bypassed to GND with at least a 0.1-µF ceramic capacitor for proper operation.

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SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

FUNCTIONAL BLOCK DIAGRAM

SYNC 10

13 VC

4.4V

1.5 V

−

+

−

+

RT

9

11 AOUT

OSC

LO

Q

CT

CS−

CS+

8

3

4

14 BOUT

12 GND

T

R

QB

Comparator

QB

−

S

3X

1

+

−

+

S

2

Shutdown

Lockout

−

+

120 µA

0.5 V

NI

5

1

CURLIM

+

EA

−

+

−

INV

6

7

R

S

0.35 V

S

1

COMP

Q

16 SHUT

DOWN

+

−

S

2

7.0 V

+

R

200 µA

1.0 V

S

−

VIN 15

200kΩ

Q

Current Limit

Restart

+

−

R

7.5 V

UVLO

15 V

4.25 V

+

−

2

VREF

5.1 V

Reference

Regulator

Reference Low

UDG−99035

8

www.ti.com

ꢀ

ꢁ

ꢂ

ꢆ

ꢇ

ꢃ

ꢄ

ꢅ

SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

TYPICAL APPLICATION DIAGRAM

UDG−99036

TYPICAL CHARACTERISTICS

Design equations for oscillator are described in the following equations.

1

f

+

OSC

t

) t

(4)

(5)

RAMP

FALL

t

+ 1.92 R C

RAMP

T

2.4 C

T

t

+

FALL

1.25

ǒ Ǔ

Ǔ

R

T

ǒ

0.002 *

(6)

(7)

t

+ t

DEAD

FALL

9

www.ti.com

ꢀ

ꢁ

ꢂ

ꢆ

ꢇ

ꢃ

ꢄ

ꢅ

SLUS272C − FEBRUARY 2000 − REVISED JUNE 2003

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY

vs

JUNCTION TEMPERATURE

ERROR AMPLIFIER GAIN AND PHASE

vs

60

58

FREQUENCY

80

60

40

180

135

90

56

54

52

50

48

Phase

20

0

45

0

46

44

Gain

42

40

−55

−20

−45

10 M

−25

0

25

50

75

100

125

1 k

10 k

100 k

1 M

f

− Oscillator Frequency − Hz

T

J

− Junction Temperature − °C

OSC

Figure 1.

Figure 2.

OSCILLATOR FREQUENCY

vs

TIMING RESISTANCE

1 M

100 k

10 k

C

= 220 pF

T

C

= 100 pF

T

C

= 47 pF

T

C

= 330 pF

T

C

= 470 pF

T

C

= 1.0 nF

T

C

= 2.2 nF

T

0

10 k

100 k

1 M

R

− Timing Resistance − Ω

T

Figure 3.

10

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

LCCC

CDIP

LCCC

SOIC

CDIP

Drawing

5962-9457501MEA

5962-9457501Q2A

5962-9457501V2A

5962-9457501VEA

UCC1806J

ACTIVE

J

FK

J

16

20

16

20

16

1

None

A42 SNPB

Level-NC-NC-NC

POST-PLATE Level-NC-NC-NC

Call TI

Level-NC-NC-NC

Call TI

J

A42 SNPB

Call TI

UCC1806J883B

UCC1806JQMLV

UCC1806L

J

FK

D

1

POST-PLATE Level-NC-NC-NC

UCC1806L883B

UCC1806LQMLV

UCC2806D

Call TI

40

2500

40

CU NIPDAU Level-1-220C-UNLIM

CU NIPDAU Level-2-220C-1 YEAR

UCC2806DTR

UCC2806DW

D

DW

J

UCC2806DWTR

UCC2806J

2000

1

A42 SNPB

Level-NC-NC-NC

UCC2806M

SSOP/

QSOP

DBQ

75

CU NIPDAU Level-2-220C-1 YEAR

UCC2806MTR

ACTIVE

SSOP/

QSOP

DBQ

16

2500

None

CU NIPDAU Level-2-220C-1 YEAR

UCC2806N

UCC2806PW

ACTIVE

PDIP

N

16

25

90

None

CU SNPB

Level-NA-NA-NA

TSSOP

PW

CU NIPDAU Level-2-220C-1 YEAR

UCC2806PWTR

UCC2806PWTRG4

2000

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2806Q

UCC2806QTR

UCC3806DW

UCC3806DWTR

UCC3806J

ACTIVE

PLCC

SOIC

FN

DW

J

20

16

20

46

1000

40

None

CU SNPB

Level-2-220C-1 YEAR

CU NIPDAU Level-2-220C-1 YEAR

SOIC

2000

1

CDIP

A42 SNPB

CU SNPB

Level-NC-NC-NC

Level-NA-NA-NA

UCC3806N

PDIP

N

25

UCC3806PW

UCC3806PWTR

UCC3806Q

TSSOP

PLCC

PW

FN

90

CU NIPDAU Level-2-220C-1 YEAR

2000

46

CU SNPB

Level-2-220C-1 YEAR

UCC3806QTR

1000

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

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solutions:

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Amplifiers

amplifier.ti.com

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microcontroller.ti.com

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	UCC1806L883B
厂家：	TEXAS INSTRUMENTS
描述：	LOW-POWER, DUAL-OUTPUT, CURRENT-MODE PWM CONTROLLER 低功耗，双路输出，电流模式PWM控制器稳压器开关式稳压器或控制器电源电路开关式控制器输出元件信息通信管理
文件：	总21页 (文件大小：722K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC1806L883B [TI]

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