UCC1895J [TI]
BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER; BiCMOS高级相移PWM控制器型号: | UCC1895J |
厂家: | TEXAS INSTRUMENTS |
描述: | BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER |
文件: | 总25页 (文件大小:668K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
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FEATURES
DESCRIPTION
D
D
D
D
Programmable Output Turn-on Delay
The UCC3895 is a phase-shift PWM controller
Adaptive Delay Set
that implements control of a full-bridge power
stage by phase shifting the switching of one
half-bridge with respect to the other. It allows
constant frequency pulse-width modulation in
conjunction with resonant zero-voltage switching
to provide high efficiency at high frequencies. The
part can be used either as a voltage-mode or
current-mode controller.
Bidirectional Oscillator Synchronization
Voltage-Mode, Peak Current-Mode, or
Average Current-Mode Control
D
Programmable Softstart/Softstop and Chip
Disable via a Single Pin
D
D
D
D
D
0% to 100% Duty-Cycle Control
7-MHz Error Amplifier
While the UCC3895 maintains the functionality of
the UC3875/6/7/8 family and UC3879, it improves
on that controller family with additional features
such as enhanced control logic, adaptive delay
set, and shutdown capability. Since it is built using
the BCDMOS process, it operates with
dramatically less supply current than it’s bipolar
counterparts. The UCC3895 can operate with a
maximum clock frequency of 1 MHz.
Operation to 1 MHz
Typical 5-mA Operating Current at 500 kHz
Very Low 150-µA Current During UVLO
APPLICATIONS
D
D
D
D
Phase-Shifted Full-Bridge Converters
Off-Line, Telecom, Datacom and Servers
Distributed Power Architecture
High-Density Power Modules
UCC3895
Q1
1
2
3
4
5
6
7
8
9
EAN
EAP 20
SS/DISB 19
OUTA 18
OUTB 17
PGND 16
VCC 15
V
OUT
EAOUT
RAMP
REF
A
C
GND
SYNC
CT
V
IN
V
BIAS
OUTC 14
OUTD 13
CS 12
B
D
RT
DELAB
10 DELCD
ADS 11
UDG−03123
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2008, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢉ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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1
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ORDERING INFORMATION
PACKAGED DEVICES
T
A
TSSOP−20(PW)
(1)
SOIC−20(DW)
(1)
PLCC−20(Q)
PDIP−20(N)
CLCC−20(L)
CDIP−20(J)
(1)
−55°C to 125°C
−40°C to 85°C
0°C to 70°C
UCC1895L
UCC1895J
UCC2895DW
UCC3895DW
UCC2895N
UCC3895N
UCC2895PW
UCC3895PW
UCC2895Q
UCC3895Q
(1)
The DW, PW and Q packages are available taped and reeled. Add TR suffix to device
type (e.g. UCC2895DWTR) to order quantities of 2000 devices per reel for DW.
N and J PACKAGE
(TOP VIEW)
PW and DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAN
EAOUT
RAMP
REF
EAP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
GND
SYNC
CT
OUTC
OUTD
CS
RT
DELAB
DELCD
ADS
ADS
Q and L PACKAGE
(TOP VIEW)
EAN
EAOUT
RAMP
EAP
SS/DISB
3
2
1
20 19
18
REF
GND
SYNC
CT
4
5
6
7
8
OUTA
OUTB
PGND
VDD
17
16
15
14
RT
OUTC
9
10 11 12 13
DELAB
DELCD
OUTD
CS
ADS
2
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ABSOLUTE MAXIMUM RATINGS
(2)
−40°C ≤ T ≤ 85°C, all voltage values are with respect to the network ground terminal unless otherwise noted.
A
UCC2895N
UNIT
Supply voltage
Supply current
Reference current
Output crrent
Analog inputs
(I
DD
< 10 mA)
17
V
30
15
mA
100
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB
OUTA, OUTB, OUTC, OUTD
DW−20 package
−0.3 V to REF+0.3 V
V
Drive outputs
−0.3 V to VCC + 0.3 V
650
1
mW
W
Power dissipation at T = 25°C
A
N−20 package
Storage temperature range, T
stg
−65 to 150
−55 to 150
300
Junction temperature range, T
°C
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS(3)
TYP
MAX
UNIT
MIN
Supply voltage, V
DD
9
16.5
V
(1)
Supply voltage bypass capacitor, V
10 x C
REF
DD
(2)
µF
pF
kΩ
Reference bypass capacitor, C
REF
0.1
1.0
Timing capacitor, C (for 500 kHz switching frequency)
220
82
T
Timing resistor, R (for 500 kHz switching frequency)
T
Delay resistor R
R
2.5
40
DEL_AB, DEL_CD
(4)
Operating junction temperature, T
−55
125
°C
J
(1)
The V
DD
capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor should
pins.
capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired
belocated as physically close as possible to the V
(2)
DD
The V
REF
for the V
V
DD
(3)
then it should be located near the V
cap and connected to the V pin with a resistor of 51 Ω or greater. The bulk capacitor on
REF
REF
REF
must be a factor of 10 greater than the total V
capacitance.
It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a seperate ground
REF
plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located over this ground plane. Any
connections associated with these pins to ground should be connected to this ground plane.
(4)
It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
3
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS V = 12 V, R = 82 kΩ, C = 220 pF, R = 10 kΩ, R
DELAB DELCD
= 10 kΩ, C = 0.1 µF,
REF
DD
T
T
C
= 0.1 µF and no load on the outputs, T = T . T = 0°C to 70°C for UCC3895x, T = −40°C to 85°C for UCC2895x and TA = −55°C to 125°C
VDD
A
J
A
A
for the UCC1895x. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO
UVLO
UVLO
Start-up voltage threshold
10.2
8.2
11
9
11.8
(on)
(off)
(hys)
Minimum operating voltage after
start-up
9.8
3.0
V
Hysteresis
1.0
2.0
SUPPLY
I
I
Start-up current
VDD = 8 V
150
5
250
6
µA
mA
V
START
Operating current
DD
V
V
DD
clamp voltage
IDD = 10 mA
16.5
17.5
18.5
DD_CLAMP
VOLTAGE REFERENCE
T = 25°C
4.94
4.85
10
5.00
5
5.06
5.15
J
10 V < VDD < V
0 mA < IREF < 5 mA,
temperature
,
DD_CLAMP
V
REF
Output voltage
V
I
Short circuit current
REF = 0 V,
T = 25°C
20
mA
SC
J
ERROR AMPLIFIER
Common-mode input voltage range
−0.1
−7
3.6
7
V
V
IO
Offset voltage
mV
µA
I
Input bias current (EAP, EAN)
High-level output voltage
Low-level output voltage
−1
1
BIAS
EAOUT_
VOH
EAP−EAN = 500 mV,
I
= −0.5 mA
= 0.5 mA
4.0
0
4.5
0.2
1.5
4.5
85
5.0
0.4
EAOUT
EAP−EAN = −500 mV, I
EAOUT
V
EAOUT_
VOL
I
Error amplifier output source current
Error amplifier output sink current
Open-loop dc gain
EAP−EAN = 500 mV, EAOUT = 2.5 V
EAP−EAN = −500 mV, EAOUT = 2.5 V
1.0
2.5
75
SOURCE
SINK
mA
I
A
dB
VOL
(1)
GBW
Unity gain bandwidth
5.0
1.5
7.0
2.2
MHz
1 V < EAN < 0 V,
0.5 V < EAOUT < 3.0 V
EAP = 500 mV
(1)
Slew rate
V/µs
No-load comparator turn-off
threshold
0.45
0.50
0.60
0.55
0.69
No-load comparator turn-on
threshold
V
0.55
No-load comparator hysteresis
0.035
0.10 0.165
OSCILLATOR
f
Frequency
T = 25°C
473
500
2.5%
2.10
4.5
527
5%
kHz
OSC
J
(1)
Frequency total variation
Over line, temperature
V
V
V
SYNC input threshold, SYNC
High-level output voltage, SYNC
Low-level output voltage, SYNC
Sync output pulse width
2.05
4.1
2.40
5.0
IH_SYNC
OH_SYNC
OL_SYNC
I
I
= −400 µA,
= 100 µA,
V
V
= 2.6 V
= 0.0 V
V
SYNC
CT
0.0
0.5
1.0
SYNC
CT
LOAD
SYNC
= 3.9 kΩ and 30 pF in parallel
85
135
3.1
ns
V
V
V
Timing resistor voltage
2.9
2.25
0.0
3
RT
Timing capacitor peak voltage
Timing capacitor valley voltage
2.35
0.2
2.55
0.4
V
CT(peak)
CT(valley)
(1)
Ensured by design. Not production tested.
4
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS V = 12 V, R = 82 kΩ, C = 220 pF, R = 10 kΩ, R
DELAB DELCD
= 10 kΩ, C = 0.1 µF,
REF
DD
T
T
C
= 0.1 µF and no load on the outputs, T = T . T = 0°C to 70°C for UCC3895x, T = −40°C to 85°C for UCC2895x and TA = −55°C to 125°C
VDD
A
J
A
A
for the UCC1895x. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
CURRENT SENSE
I
Current sense bias current
Peak current threshold
0 V < CS < 2.5 V,
0 V ADS < 2.5 V
−4.5
1.90
2.4
20
2.10
2.6
µA
V
CS(bias)
2.00
2.5
75
Overcurrent threshold
V
Current sense to output delay
0V ≤ CS ≤ 2.3 V,
DELAB=DELCD=REF
110
ns
SOFT-START/SHUTDOWN
I
Softstart source current
Softstart sink current
SS/DISB = 3.0 V,
SS/DISB = 3.0 V,
CS = 1.9 V
CS = 2.6 V
−40
325
−35
350
−30
375
µA
µA
V
SOURCE
I
SINK
Softstart/disable comparator threshold
ADAPTIVE DELAY SET (ADS)
0.44
0.50
0.56
ADS = CS = 0 V
ADS = 0 V,
0.45
1.9
0.50
2.0
0.55
2.1
620
20
V
V
DELAB/DELCD output voltage
CS = 2.0 V
(1)(3)
Output delay
t
ADS = CS = 0 V
0 V < ADS < 2.5 V,
450
−20
560
ns
µA
DELAY
ADS bias current
0 V < CS < 2.5 V
VDD to output
OUTPUT
V
V
t
High−level output voltage (all outputs)
Low-level output voltage (all outputs)
I
I
= −10 mA,
= 10 mA
250
150
20
400
250
35
mV
mV
ns
OH
OUT
OL
OUT
(1)
Rise time
C
C
= 100 pF
= 100 pF
LOAD
LOAD
R
(1)
Fall time
t
20
35
ns
F
(1)
(2)
Ensured by design. Not production tested.
Minimum phase shift is defined as:
tf
) * tf
tf
) * tf
(
(
)
(
(
)
OUTC
OUTA
OUTC
OUTB
F + 180
or F + 180
where
tPERIOD
tPERIOD
t
t
t
= falling edge of OUTA signal,
t
= falling edge of OUTB signal
= falling edge of OUTD signal
f(OUTA)
f(OUTC)
PERIOD
f(OUTB)
= falling edge of OUTC signal, t
f(OUTD)
= period of OUTA or OUTB signal
(3)
Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is defined as shown below where:
t
= falling edge of OUTA signal, t
= rising edge of OUTB signal
f(OUTA)
r(OUTB)
tPERIOD
OUTA
OUTA
t
= t
− t
t
= t
− t
DELAY R(OUTB) f(OUTA)
DELAY f(OUTC) f(OUTA)
OUTB
OUTC
Same applies to OUTB and OUTD
Same applies to OUTC and OUTD
5
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS V = 12 V, R = 82 kΩ, C = 220 pF, R = 10 kΩ, R
DELAB DELCD
= 10 kΩ, C = 0.1 µF,
REF
DD
T
T
C
= 0.1 µF and no load on the outputs, T = T . T = 0°C to 70°C for UCC3895x, T = −40°C to 85°C for UCC2895x and TA = 55°C to 125°C
VDD
A
J
A
A
for the UCC1895x. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
PWM COMPARATOR
EAOUT to RAMP input offset voltage
RAMP = 0 V,
RAMP = 0 V
DELAB=DELCD=REF
EAOUT = 650 mV
0.72
0.85
1.05
V
(2)
Minimum phase shift
(OUTA to OUTC, OUTB to OUTD)
(3)
.0% .85% 1.4%
Delay
0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB=DELCD=REF
t
70
19
120
5
ns
DELAY
(RAMP to OUTC, RAMP to OUTD)
I
I
RAMP bias current
RAMP < 5 V,
RAMP = 5 V,
CT = 2.2 V
CT = 2.6 V
−5
12
µA
R(bias)
RAMP sink current
mA
R(sink)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
ADS
NO.
11
I
I
Adaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time.
Current sense input for cycle-by-cycle current limiting and for over-current comparator.
CS
12
Oscillator timing capacitor for programming the switching frequency. The UCC3895’s oscillator charges CT
via a programmed current.
CT
7
9
I
I
I
Delay programming between complementary outputs. DELAB programs the dead time between switching of
output A and output B.
DELAB
DELCD
Delay programming between complementary outputs. DELCD programs the dead time between switching of
output C and output D.
10
EAOUT
EAP
2
I/O Error amplifier output.
20
1
I
Non-inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
Inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
Chip ground for all circuits except the output stages.
EAN
I
GND
5
−
O
O
O
O
−
I
OUTA
OUTB
OUTC
OUTD
PGND
RAMP
18
17
14
13
16
3
The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits
such as UCC27424 or gate drive transformers.
Output stage ground.
Inverting input of the PWM comparator.
5 V, 1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-µF low ESR, low ESL capacitor
to ground. Do not use more than 1.0 µF of total capacitance on this pin.
REF
4
O
RT
8
19
6
I
I
Oscillator timing resistor for programming the switching frequency.
Soft-start/disable. This pin combines the two independent functions.
SS/DISB
SYNC
I/O Oscillator synchronization. This pin is bidirectional.
Power supply input pin. VDD must be bypassed with a minimum of a 1.0-µF low ESR, low ESL capacitor to
ground. The addition of a 10−µF low ESR, low ESL between VDD and PGND is recommended.
VDD
15
I
6
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
BLOCK DIAGRAM
I
RT
Q
RT
CT
VDD
8
7
15
S
R
D
Q
Q
8(I
RT
OSC
)
Q
OUTA
DELAB
OUTB
18
9
S
R
DELAY A
DELAY B
D
Q
SYNC
RAMP
6
3
Q
PWM
COMPARATOR
17
+
0.8 V
EAOUT
EAP
OUTC
2
20
1
14
DELAY C
DELAY D
D
Q
Q
S
R
ERROR
AMP
NO LOAD
COMPARATOR
10 DELCD
OUTD
+
+
13
EAN
CURRENT SENSE
COMPARATOR
+
0.5 V / 0.6 V
2 V
16 PGND
11 ADS
CS
12
OVER CURRENT
ADAPTIVE DELAY
SET AMPLIFIER
COMPARATOR
+
2.5 V
+
0.5V
Q
Q
S
R
UVLO COMPARATOR
+
REF
11 V / 9 V
DISABLE
I
RT
REF
4
COMPARATOR
REF
HI = ON
HI = ON
0.5 V
REFERENCE OK
COMPARATOR
SS
19
+
4 V
GND
5
+
10(I
RT
)
UDG−98140
REF
V
REF
8 x I
RT
RT
R
T
I
RT
CT
CLOCK
2.5 V
S
R
Q
+
+
C
T
CLOCK
0.2 V
SYNC
UDG−03135
Figure 1. Oscillator Block Diagram
7
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
REF
0.5 V
TO DELAY A
AND DELAY B
BLOCKS
75 kΩ
+
100 kΩ
CS
DELAB
+
100 kΩ
ADS
75 kΩ
REF
TO DELAY C
AND DELAY D
BLOCKS
DELCD
+
UDG−98141
Figure 2. Adaptive Delay Set Block Diagram
REF
BUSSED CURRENT
FROM ADS CIRCUIT
3.5 V
DELAB/CD
FROM PAD
DELAYED
CLOCK
SIGNAL
2.5 V
CLOCK
UDG−03132
Figure 3. Delay Block Diagram (One Delay Block Per Outlet)
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
DETAILED PIN DESCRIPTION
Adaptive Delay Set (ADS)
This function sets the ratio between the maximum and minimum programmed output-delay dead time. When
the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation
occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2.0 V
(the peak-current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the
following formula:
ǒ
Ǔ
+ ƪ0.75 V
ƫ) 0.5 V
V
* V
DEL
CS
ADS
(1)
where V and V
are in volts. ADS must be limited to between 0 V and 2.5 V and must be less than or equal
CS
ADS
to CS. DELAB and DELCD are clamped to a minimum of 0.5 V.
Current Sense (CS)
The inverting input of the current-sense comparator and the non-inverting input of the overcurrent comparator
and the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode
control, and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output
disable initiated by an overcurrent fault also results in a restart cycle, called soft stop, with full soft start.
Oscillator Timing Capacitor (CT)
The UCC3895’s oscillator charges CT via a programmed current. The waveform on C is a sawtooth, with a peak
T
voltage of 2.35 V. The approximate oscillator period is calculated by the following formula:
5 R C
T
48
T
t
+
) 120 ns
OSC
(2)
where C is in Farads, and R is in Ohms and t
is in seconds. C can range from 100 pF to 880 pF.
T
T
T
OSC
NOTE: A large C and a small R combination results in extended fall times on the C waveform.
T
T
T
The increased fall time increases the SYNC pulse width, hence limiting the maximum phase shift
between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum duty cycle of the
converter. (Refer to Figure 1)
Delay Programming Between Complementary Outputs (DELAB, DELCD)
DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time
between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the
external bridge. The UCC2895N allows the user to select the delay, in which the resonant switching of the external
power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in
resonant-capacitor charging currents. The delay in each stage is set according to the following formula:
*12
(
)
25 10
R
DEL
t
+
) 25 ns
DELAY
V
DEL
(3)
where V
(V), and R
is in (Ω) and t is in seconds. DELAB and DELCD can source about 1 mA
DELAY
DEL
DEL
maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay is
defeated by tying DELAB and/or DELCD to REF. For an optimum performance keep stray capacitance on these
pins at less than 10 pF.
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
DETAILED PIN DESCRIPTION (continued)
Error Amplifier (EAOUT), (EAP), (EAN)
EAOUT connected internally to the non-inverting input of the PWM comparator and the no-load comparator.
EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages
when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP is the non−inverting and the EAN is the inverting input to the error amplifier.
Output MOSFET Drivers (OUTA, OUTB, OUTC, OUTD)
The 4 outputs are 100-mA complementary MOS drivers, and are optimized to drive MOSFET driver circuits.
OUTA and OUTB are fully complementary, (assuming no programming delay). They operate near 50% duty
cycle and one-half the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an
external power stage. OUTC and OUTD drive the other half-bridge and have the same characteristics as OUTA
and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.
NOTE: Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB
requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients.
Power Ground (PGND)
To keep output switching noise from critical analog circuits, the UCC3895 has two different ground connections.
PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically
tied together. Also, since PGND carries high current, board traces must be low impedance.
Inverting Input of the PWM Comparator (RAMP)
This pin receives either the C waveform in voltage and average current-mode controls, or the current signal
T
(plus slope compensation) in peak current-mode control.
Voltage Reference (REF)
The 5 V, 1.2% reference supplies power to internal circuitry, and can also supply up to 5 mA to external loads.
The reference is shut down during undervoltage lockout but is operational during all other disable modes. For
best performance, bypass with a 0.1-µF, low-ESR, low-ESL capacitor to GND. Do not use more than 1.0 µF of
total capacitance on this pin. To ensure the stability of the internal reference.
Oscillator Timing Resistor (RT)
The oscillator in the UCC3895 operates by charging an external timing capacitor, C , with a fixed current
T
programmed by R . R current is calculated as follows:
T
T
3.0 V
I
(A) +
RT
R (W)
T
(4)
R can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging currents are also programmed by I
T
RT
(Refer to Figure 1).
Analog Ground (GND)
This pin is the chip ground for all internal circuits except the output stages.
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
DETAILED PIN DESCRIPTION (continued)
Soft-Start/Disable (SS/DISB)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF
being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal
MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft-stop is initiated. In this mode, SS/DISB sinks a constant
current of (10 × I ). The soft-stop continues until SS/DISB falls below 0.5 V. When any of these faults are
RT
detected, all outputs are forced to ground immediately.
NOTE:If SS/DISB is forced below 0.5 V, the pin starts to source current equal to I . The only time
RT
the part switches into low I
current mode, though, is when the part is in undervoltage lockout.
DD
Soft-start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and/or
SS/DISB falls below 0.5 V during a soft-stop, SS/DISB switches to a soft-start mode. The pin then sources
current, equal to I . A user-selected resistor/capacitor combination on SS/DISB determines the soft start time
RT
constant.
NOTE: SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin voltage
during both soft-start, soft-stop, and disable conditions.
Oscillator Synchronization (SYNC)
This pin is bidirectional (refer to Figure 1). When used as an output, SYNC can be used as a clock, which is the
same as the device’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator and
act as it’s clock signal. This bidirectional feature allows synchronization of multiple power supplies. Also, the
SYNC signal internally discharge the C capacitor and any filter capacitors that are present on the RAMP pin.
T
The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high threshold
of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the sync pulse width.
Chip Supply (VDD)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1.0 µF low ESR, low ESL capacitor
to ground. The addition of a 10−µF low ESR, low ESL between VDD and PGND is recommended.
11
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
APPLICATION INFORMATION
Programming DELAB, DELCD and the Adaptive Delay Set
The UCC2895N allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit according to equations:
*12
(
)
25 10
R
DEL
t
+
) 25 ns
DELAY
V
DEL
(5)
From this equation VDEL is determined in conjunction with the desire to use (or not) the adaptive delay set
feature from the following formula:
ǒ
Ǔ
+ ƪ0.75 V
ƫ) 0.5 V
V
* V
DEL
CS
ADS
(6)
The following diagram illustrates the resistors needed to program the delay periods and the adaptive delay set
function.
UCC3895
CS 12
9
DELAB
R
DELAB
10 DELCD
ADS 11
R
DELCD
Figure 4. Programming Adaptive Delay Set
The adaptive delay set feature (ADS) allows the user to vary the delay times between switch commands
within each of the converter’s two legs. The delay-time modulation is implemented by connecting ADS
(pin 11) to CS, GND, or a resistive divider from CS through ADS to GND to set V
as shown in Figure 4.
ADS
From equation (6) for V
, if ADS is tied to GND then V
rises in direct proportion to V , causing a
DEL
DEL CS
decrease in t
as the load increases. In this condition, the maximum value of V
is 2 V.
DEL
DELAY
If ADS is connected to a resistive divider between CS and GND, the term (V −V
) becomes smaller,
CS ADS
reducing the level of V
. This decreases the amount of delay modulation. In the limit of ADS tied to CS,
DEL
V
= 0.5 V and no delay modulation occurs. Figure 5 graphically shows the delay time vs. load for
DEL
varying adaptive delay set feature voltages (V
).
ADS
In the case of maximum delay modulation (ADS=GND), when the circuit goes from light load to heavy
load, the variation of V
load is changed.
is from 0.5 V to 2 V. This causes the delay times to vary by a 4:1 ratio as the
DEL
The ability to program an adaptive delay is a desirable feature because the optimum delay time is a
function of the current flowing in the primary winding of the transformer, and can change by a factor of
[5]
10:1 or more as circuit loading changes. Reference describes the many interrelated factors for choosing
the optimum delay times for the most efficient power conversion, and illustrates an external circuit to
enable adaptive delay set using the UC3879. Implementing this adaptive feature is simplified in the
UCC3895 controller, giving the user the ability to tailor the delay times to suit a particular application with a
minimum of external parts.
12
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
APPLICATION INFORMATION
DELAY TIME
vs
CURRENT SENSE VOLTAGE
A = V
/V
R
= 10 kΩ
ADS CS
DELAY
A = 1.0
500
400
300
200
A = 0.8
A = 0.6
A = 0.4
A = 0.2
A = 0.1
100
0
0.5
1.0
1.5
2.0
2.5
V
CS
− Current Sense Voltage − V
Figure 5. Delay Time Under Varying ADS Voltages
CLOCK
RAMP
&
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
UDG−99138
Figure 6. UCC3895 Timing Diagram (No Output Delay Shown, COMP to RAMP offset not included)
13
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
OUTPUT DELAY
vs
OSCILLATOR FREQUENCY
vs
DELAY RESISTANCE
TIMING CAPACITANCE
2000
1800
1600
1400
1200
1000
800
V
CS
= 0 V
R
= 62 kW
T
1600
1400
R
= 47 kW
T
1200
1000
800
600
600
V
CS
= 2 V
400
200
400
R
= 100 kW
T
200
0
R
= 82 kW
T
0
100
1000
0
10
20
30
40
C
T
− Timing Capacitance − pF
R
− Delay Resistor − kΩ
DEL
Figure 7
Figure 8
EAOUT to RAMP OFFSET
vs
AMPLIFIER GAIN AND PHASE MARGIN
vs
TEMPERATURE
FREQUENCY
1.00
100
200
GAIN
80
60
160
120
0.95
0.90
40
20
80
40
PHASE
MARGIN
0.85
0.80
0
0
−55 −35 −15
5
25
45 65
85 105 125
10
1k
1
100
10 k
100 k 1 MHz
10 MHz
T
A
− Temperature − °C
f
− Oscillator Frequency − kHz
OSC
Figure 9
Figure 10
14
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SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT CURRENT
vs
OSCILLATOR FREQUENCY
OSCILLATOR FREQUENCY
9
8
7
13
12
NO OUTPUT LOADING
0.1-nF OUTPUT LOADS
V
DD
= 15 V
V
= 15 V
DD
11
10
V
DD
= 17 V
9
V
DD
= 17 V
8
7
6
5
V
DD
= 12 V
6
5
V
DD
= 10 V
V
DD
= 10 V
V
DD
= 12 V
4
4
0
400
800
1200
1600
0
400
800
1200
1600
f
− Oscillator Frequency − kHz
f
− Oscillator Frequency − kHz
OSC
OSC
Figure 11
Figure 12
REFERENCES
1. M. Dennis, A Comparison Between the BiCMOS UCC3895 Phase Shift Controller and the UC3875
Application Note (SLUA246).
2. L. Balogh, The Current−Doubler Rectifier: An Alternative Rectification Technique for Push−Pull and Bridge
Converters Application Note (SLUA121).
3. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations, Application Note
(SLUA107).
4. L. Balogh, The New UC3879 Phase Shifted PWM Controller Simplifies the Design of Zero Voltage
Transition Full−Bridge Converters, Application Note (SLUA122).
5. L. Balogh, Design Review: 100 W, 400 kHz, dc-to-dc Converter with Current Doubler Synchronous
Rectification Achieves 92% Efficiency, Unitrode Power Supply Design Seminar Manual, SEM−1100, 1996,
Topic 2.
6. UC3875 Phase Shift Resonant Controller, Datasheet, (SLUS229).
7. UC3879 Phase Shift Resonant Controller, Datasheet, (SLUS230).
8. UCC3895EVM−1, “Configuring the UCC3895 for direct Control Driven Synchronous Rectification, (Texas
Instrument’s Literature Number SLUU109A)
9. UCC3895, CD Output Asymetrical Duty Cycle Operation, (Texas Instrument’s Literature Number SLUA275)
10. Texas Instrument’s Literature Number SLUA323
11. Synchronous Rectifiers of a Current Doubler, (Texas Instrument’s Literature Number SLUA287)
15
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
LCCC
SOIC
Drawing
UCC1895J
UCC1895L
ACTIVE
ACTIVE
ACTIVE
J
20
20
20
1
1
TBD
TBD
A42 SNPB
N / A for Pkg Type
FK
DW
POST-PLATE N / A for Pkg Type
UCC2895DW
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2895DWG4
UCC2895DWTR
UCC2895DWTRG4
UCC2895N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
20 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UCC2895NG4
UCC2895PW
PDIP
N
20 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PLCC
PLCC
SOIC
PW
PW
PW
PW
FN
FN
DW
DW
DW
DW
N
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2895PWG4
UCC2895PWTR
UCC2895PWTRG4
UCC2895Q
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
46 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
UCC2895QG3
UCC3895DW
46 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3895DWG4
UCC3895DWTR
UCC3895DWTRG4
UCC3895N
SOIC
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
20 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UCC3895NG4
UCC3895PW
PDIP
N
20 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PLCC
PLCC
PW
PW
PW
PW
FN
FN
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3895PWG4
UCC3895PWTR
UCC3895PWTRG4
UCC3895Q
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
46 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
UCC3895QG3
46 Green (RoHS &
CU SN
Level-2-260C-1 YEAR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
Orderable Device
Status (1)
Package Package
Type Drawing
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC1895, UCC2895, UCC3895 :
Automotive: UCC2895-Q1
Enhanced Product: UCC2895-EP
•
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UCC2895DWTR
UCC2895PWTR
UCC3895DWTR
UCC3895PWTR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
20
20
20
20
2000
2000
2000
2000
330.0
330.0
330.0
330.0
24.4
16.4
24.4
16.4
10.8
6.95
10.8
6.95
13.0
7.1
2.7
1.6
2.7
1.6
12.0
8.0
24.0
16.0
24.0
16.0
Q1
Q1
Q1
Q1
13.0
7.1
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC2895DWTR
UCC2895PWTR
UCC3895DWTR
UCC3895PWTR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
20
20
20
20
2000
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
41.0
33.0
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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