UCC21736QDWRQ1 [TI]
适用于 IGBT/SiC MOSFET 且具有主动短路的汽车类 5.7kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125;
| 型号： | UCC21736QDWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 IGBT/SiC MOSFET 且具有主动短路的汽车类 5.7kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125 栅极驱动 双极性晶体管 驱动器 |
| 文件： | 总59页 (文件大小：2395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
适用于 SiC/IGBT 并具有主动保护和高 CMTI 的 UCC21736-Q1 10A 拉电
流和灌电流增强型隔离式单通道栅极驱动器
1 特性
输入侧通过 SiO2 电容隔离技术与输出侧相隔离，支持
高达 1.5kVRMS 的工作电压、12.8kVPK 的浪涌抗扰
度，隔离层寿命超过 40 年，并提供较低的器件间偏
移、大于 150V/ns 的共模噪声抗扰度 (CMTI)。
1
•
•
•
•
•
•
•
•
•
•
5.7kV RMS 单通道隔离式栅极驱动器
符合面向汽车应用的 AEC-Q100 标准
高达 2121Vpk 的 SiC MOSFET 和 IGBT
33V 最大输出驱动电压 (VDD-VEE)
±10A 驱动强度和分离输出
UCC21736-Q1 具有高级保护功能 功能，如快速过流
和短路检测、分流电流检测支持、故障报告、有源米勒
钳位、输入和输出侧电源 UVLO（用于优化 SiC 和
IGBT 开关行为）和稳健性。可以利用 ASC 功能在系
统故障事件期间强制打开电源开关，从而进一步提高驱
动器的多功能性并消减系统设计工作量、尺寸和成本。
150V/ns 最小 CMTI
具有 200ns 快速响应时间的过流保护
外部有源米勒钳位
发生故障时的 900mA 软关断
隔离侧的 ASC 输入，用于在系统故障期间打开电
源开关
器件信息(1)
器件型号
封装
封装尺寸（标称值）
•
•
•
•
过流警报 FLT 和通过 RST/EN 重置
针对 RST/EN 的快速启用/禁用响应
抑制输入引脚上的 <40ns 噪声瞬态和脉冲
UCC21736-Q1
DW SOIC-16
10.3mm × 7.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
RDY 上的 12V VDD UVLO 和 3V VEE UVLO（具
有电源正常指示功能）
器件引脚配置
•
•
具有高达 5V 的过冲/欠冲瞬态电压抗扰度的输入/输
出
VCC 15
MOD
DEMOD
5
3
8
7
4
6
2
1
VDD
COM
VEE
VCC
Supply
130ns（最大）传播延迟和 30ns（最大）脉冲/器件
间偏移
VDD
Supply
GND
9
•
•
SOIC-16 DW 封装，爬电距离和间隙 > 8mm
工作结温范围：-40°C 至 +150°C
IN+ 10
INÅ 11
PWM
Inputs
CLMPE
OUTH
OUTL
OC
2 应用
Output
Stage
t
ON/OFF
Control
Second -
ary Logic
Primary
Logic
•
•
•
适用于 EV 的牵引逆变器
RDY 12
车载充电器和充电桩
FLT 13
用于 HEV/EV 的直流/直流转换器
RST/EN 14
APWM 16
OCP
3 说明
ASC
Control
UCC21736-Q1 是一款电隔离单通道栅极驱动器，用于
具有高达 2121V 直流工作电压的 SiC MOSFET 和
IGBT，具有高级保护功能 功能、出色的动态性能和稳
健性。UCC21736-Q1 具有高达 ±10A 的峰值拉电流和
灌电流。
ASC
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDM7
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
目录
7.5 OC (Over Current) Protection ................................. 23
7.6 ASC Protection........................................................ 23
Detailed Description ............................................ 27
8.1 Overview ................................................................. 27
8.2 Functional Block Diagram ....................................... 28
8.3 Feature Description................................................. 28
8.4 Device Functional Modes........................................ 34
Applications and Implementation ...................... 35
9.1 Application Information............................................ 35
9.2 Typical Application .................................................. 35
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 6
6.6 Electrical Characteristics........................................... 7
6.7 Switching Characteristics.......................................... 9
6.8 Insulation Specifications.......................................... 10
6.9 Safety-Related Certifications................................... 10
6.10 Safety Limiting Values .......................................... 11
6.11 Insulation Characteristics Curves ......................... 12
6.12 Typical Characteristics.......................................... 13
Parameter Measurement Information ................ 16
7.1 Propagation Delay................................................... 16
7.2 Input Deglitch Filter................................................. 18
7.3 Active Miller Clamp ................................................. 19
7.4 Under Voltage Lockout (UVLO) .............................. 20
8
9
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 48
12 器件和文档支持 ..................................................... 49
12.1 文档支持 ............................................................... 49
12.2 接收文档更新通知 ................................................. 49
12.3 社区资源................................................................ 49
12.4 商标....................................................................... 49
12.5 静电放电警告......................................................... 49
12.6 Glossary................................................................ 49
13 机械、封装和可订购信息....................................... 50
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2019 年 10 月
*
预告信息发布
2
Copyright © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
5 Pin Configuration and Functions
UCC21736-Q1
DW SOIC (16)
Top View
APWM
VCC
RST/EN
FLT
ASC
1
16
15
OC
2
14
13
12
11
10
9
COM
3
OUTH
4
RDY
INÅ
VDD
5
OUTL
6
CLMPE
IN+
7
GND
VEE
8
Not to scale
Copyright © 2019, Texas Instruments Incorporated
3
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
ASC
NO.
1
I
I
Active high to enable active short circuit function to force output high during system failure events
Over current detection pin, support lower threshold for SenseFET, DESAT, and Shunt resistor sensing
Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
Gate driver output pull up
OC
2
COM
OUTH
3
P
O
4
Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate
driver source peak current capability
VDD
5
P
OUTL
6
7
O
O
Gate driver output pull down
CLMPE
External Active miller clamp, connecting this pin to the gate of the external miller clamp MOSFET
Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate
driver sink peak current capability
VEE
8
P
GND
IN+
9
P
I
Input power supply and logic ground reference
Non-inverting gate driver control input
Inverting gate driver control input
10
11
IN–
I
Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other
RDY signals
RDY
FLT
12
13
O
O
Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be
paralleled with other faults
The RST/EN serves two purposes:
1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to
low;
RST/EN
14
I
2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A
reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The
FET is turned off by a general turn-off, if terminal EN is set to low.
VCC
15
16
P
Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND
Isolated PWM output monitoring ASC pin status
APWM
O
(1) P = Power, G = Ground, I = Input, O = Output
4
Copyright © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
–0.3
MAX
6
UNIT
V
VCC
VDD
VEE
VMAX
VCC – GND
VDD – COM
VEE – COM
VDD – VEE
–0.3
36
V
–17.5
0.3
V
–0.3
36
V
DC
GND–0.3
GND–5.0
–0.3
VCC
VCC+5.0
6
V
IN+, IN–, RST/EN
Transient, less than 100 ns(2)
V
ASC
OC
Reference to COM
Reference to COM
V
-0.3
6
DC
VEE–0.3
VEE–5.0
–0.3
VDD
VDD+5.0
5
V
V
OUTH, OUTL
Transient, less than 100 ns(2)
CLMPE
RDY, FLT
IFLT, IRDY
IAPWM
TJ
Reference to VEE
V
GND–0.3
VCC
20
V
FLT, and RDY pin input current
APWM pin output current
mA
mA
°C
°C
20
Junction temperature range
Storage temperature range
–40
–65
150
150
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Values are verified by characterization on bench.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
PARAMETER
MIN
MAX
UNIT
VCC
VCC–GND
VDD–COM
VDD–VEE
3.0
5.5
V
V
V
VDD
13
33
33
VMAX
–
0.7×VCC
0
High level input voltage
Low level input voltage
VCC
IN+, IN–, RST/EN
Reference to GND
V
0.3×VCC
5
ASC
tRST/EN
TA
Reference to COM
0
V
Minimum pulse width that reset the fault
Ambient Temperature
1000
–40
ns
°C
°C
125
150
TJ
Junction temperature
–40
6.4 Thermal Information
UCC21736-Q1
DW (SOIC)
16
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
68.3
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
5
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
Thermal Information (continued)
UCC21736-Q1
DW (SOIC)
16
THERMAL METRIC(1)
UNIT
RθJC(top)
RθJB
ψJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.5
°C/W
°C/W
°C/W
°C/W
32.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
14.1
ψJB
32.3
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
Value
UNIT
Maximum power dissipation (both
sides)
PD
985
20
mW
Maximum power dissipation by
transmitter side
VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,
50% Duty Cycle for 10nF load, Ta=25oC
PD1
PD2
mW
mW
Maximum power dissipation by
receiver side
965
6
Copyright © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
6.6 Electrical Characteristics
VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,
CL=100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2)
.
PARAMETER
VCC UVLO THRESHOLD AND DELAY
VVCC_ON
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.55
2.35
2.7
2.5
0.2
10
2.85
2.65
VVCC_OFF
VVCC_HYS
tVCCFIL
VCC–GND
V
VCC UVLO Deglitch time
tVCC+ to OUT
tVCC– to OUT
tVCC+ to RDY
tVCC– to RDY
VCC UVLO on delay to output high
VCC UVLO off delay to output low
VCC UVLO on delay to RDY high
VCC UVLO off delay to RDY low
37.8
10
IN+ = VCC, IN– = GND
µs
37.8
10
RST/EN = VCC
VDD UVLO THRESHOLD AND DELAY
VVDD_ON
11.2
9.9
12.0
10.7
0.8
5
12.8
11.5
VVDD_OFF
VVDD_HYS
tVDDFIL
VDD–COM
V
VDD UVLO Deglitch time
tVDD+ to OUT
tVDD– to OUT
tVDD+ to RDY
tVDD– to RDY
VDD UVLO on delay to output high
VDD UVLO off delay to output low
VDD UVLO on delay to RDY high
VDD UVLO off delay to RDY low
5
IN+ = VCC, IN– = GND
RST/EN = FLT=High
5
µs
10
10
VEE UVLO THRESHOLD AND DELAY
VVEE_ON
–3.3
–2.9
–3.0
–2.6
0.4
5
–2.7
–2.3
VVEE_OFF
VVEE_HYS
tVEEFIL
VEE–COM
V
VEE UVLO Deglitch time
tVEE+ to OUT
tVEE– to OUT
tVEE+ to RDY
tVEE– to RDY
VEE UVLO on delay to output high
VEE UVLO off delay to output low
VEE UVLO on delay to RDY high
VEE UVLO off delay to RDY low
5
IN+ = VCC, IN– = GND
RST/EN = FLT=High
5
µs
10
10
VCC, VDD QUIESCENT CURRENT
OUT(H) = High, fS = 0Hz, AIN=2V
OUT(L) = Low, fS = 0Hz, AIN=2V
OUT(H) = High, fS = 0Hz, AIN=2V
OUT(L) = Low, fS = 0Hz, AIN=2V
3
2
IVCCQ
VCC quiescent current
VDD quiescent current
mA
mA
4
IVDDQ
3.7
LOGIC INPUTS — IN+, IN–, and RST/EN
VINH
VINL
VINHYS
IIH
Input high threshold
VCC=3.3V
VCC=3.3V
VCC=3.3V
VIN = VCC
VIN = GND
1.85
1.52
0.33
90
2.31
V
V
Input low threshold
0.99
Input threshold hysteresis
Input high level input leakage current
Input low level input leakage
V
µA
µA
IIL
–90
see Detailed Description for more
information
RIND
RINU
Input pins pull down resistance
Input pins pull up resistance
55
55
kΩ
see Detailed Description for more
information
IN+, IN– and RST/EN deglitch (ON and
OFF) filter time
TINFIL
fS = 50kHz
28
40
ns
ns
TRSTFIL
Deglitch filter time to reset /FLT
500
650
800
GATE DRIVER STAGE
IOUT, IOUTH
IOUT, IOUTL
ROUTH
Peak source current
–10
10
A
A
Ω
CL=0.18µF, fS=1kHz
IOUT = –0.1A
Peak sink current
Output pull-up resistance
2.5
(1) Current are positive into and negative out of the specified terminal.
(2) All voltages are referenced to COM unless otherwise notified.
Copyright © 2019, Texas Instruments Incorporated
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UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,
CL=100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.3
MAX
UNIT
Ω
ROUTL
VOUTH
VOUTL
Output pull-down resistance
High level output voltage
Low level output voltage
IOUT = 0.1A
IOUT = –0.2A, VDD=15V
IOUT = 0.2A
14.5
60
V
mV
ACTIVE PULLDOWN
IOUTL or IOUT = 0.1×IOUT(L)(tpy)
VDD=OPEN, VEE=COM
,
VOUTPD
Output active pull down on OUT, OUTL
2.5
2.5
V
EXTERNAL MILLER CLAMP
VCLMPTH
VCLMPE
ICLMPEH
ICLMPEL
tCLMPER
tDCLMPE
Miller clamp threshold voltage
Reference to VEE
Reference to VEE
1.5
4.4
2.0
4.8
V
V
Output high voltage
Peak source current
Peak sink current
Rising time
0.12
0.12
0.25
0.25
20
A
CCLMPE = 10nF
CCLMPE = 330pF
A
40
ns
ns
Miller clamp ON delay time
40
SHORT CIRCUIT CLAMPING
VCLP-OUT(H)
VCLP-OUT(L)
VCLP-CLMPI
VOUT–VDD, VOUTH–VDD
OUT = Low, IOUT(H) = 500mA, tCLP=10us
OUT = High, IOUT(L) = 500mA, tCLP=10us
OUT = High, ICLMPI = -20mA, tCLP=10us
0.9
1.8
1.0
V
V
V
VOUT–VDD, VOUTL–VDD
VCLMPI–VDD
OC PROTECTION
IDCHG
OC pull down current when
VOC = 1V
40
mA
V
VOCTH
Detection Threshold
0.63
0.7
0.77
Voltage when OUT(L) = LOW, Reference
to COM
VOCL
IOC = 5mA
0.13
V
tOCFIL
tOCOFF
tOCFLT
OC fault deglitch filter
150
200
600
ns
ns
ns
OC propagation delay to OUT(L) 90%
OC to FLT low delay
INTERNAL SOFT TURN-OFF
ISTO
Soft turn-off current on fault conditions
900
mA
ASC - Active Short Circuit
VASCL
VASCH
tASC_r
tASC_f
ASC Input low threshold
1.7
3.2
V
V
ASC Input high threshold
ASC to output rising edge delay
ASC to output falling edge delay
660
227
ns
ns
ISOLATED ASC MONITOR (APWM)
fAPWM
APWM output frequency
APWM Dutycycle —
360
7
400
10
440
13
kHz
%
VASC = 0.5V
VASC = 2.5V
VASC = 4.5V
DAPWM
47
87
50
53
90
93
FLT AND RDY REPORTING
VDD UVLO RDY low minimum holding
time
tRDYHLD
0.55
0.55
1
1
ms
tFLTMUTE
RODON
VODL
Output mute time on fault
Open drain output on resistance
Open drain low output voltage
Reset fault through RST/EN
IODON = 5mA
ms
Ω
30
IODON = 5mA
0.3
V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode transient immunity
150
V/ns
8
Copyright © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
6.7 Switching Characteristics
VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, CL=100pF,
–40°C<TJ<150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tPDHL
tPDLH
PWD
tsk-pp
tr
Propagation delay time – High to Low
Propagation delay time – Low to High
90
90
Pulse width distortion |tPDHL – tPDLH
|
25
30
28
24
1
Part to Part skew
Rising or Falling Propagation Delay
Driver output rise time
CL=10nF
CL=10nF
tf
Driver output fall time
fMAX
Maximum switching frequency
MHz
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UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
UNIT
6.8 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
> 8
> 8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
CPG
Minimum internal gap (Internal clearance) of the
double insulation (2 × 0.0085 mm)
DTI
CTI
Distance through the insulation
> 17
µm
V
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664–1
> 600
I
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-III
Overvoltage Category per IEC 60664–1
DIN V VDE V 0884-11 (VDE V 0884-11):2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
2121
1500
VPK
VRMS
VDC
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
VIOWM
Maximum isolation working voltage
DC voltage
2121
8000
9600
VTEST=VIOTM, t = 60 s (qualification test)
VTEST=1.2 x VIOTM, t = 1 s (100% production test)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Method a: After I/O safety test subgroup 2/3, Vini
=
VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK
,
≤ 5
tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394
VPK, tm = 10 s
qpd
Apparent charge(4)
≤ 5
≤ 5
pC
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
VIO = 0.5 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~ 1
≥ 1012
≥ 1011
≥ 109
pF
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
5700
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device
6.9 Safety-Related Certifications
VDE
UL
Plan to certify according to DIN V VDE V 0884-11 (VDE V 0884-
11):2017-01;
DIN EN 61010-1 (VDE 0411-1):2011-07
Plan to certify according to UL 1577 Component Recognition
Program
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Safety-Related Certifications (continued)
VDE
UL
Reinforced insulation
Maximum transient isolation voltage, 8000 VPK
Maximum repetitive peak isolation voltage, 2121 VPK
Maximum surge isolation voltage, 8000 VPK
;
Single protection, 5700 VRMS
Certification Planned
;
Certification Planned
6.10 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
TBD
= 25°C
θJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
θJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
Safety input, output, or supply
current
IS
mA
R
TBD
Safety input, output, or total
power
R
PS
TS
TBD
150
mW
°C
Safety temperature
(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
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6.11 Insulation Characteristics Curves
1.E+12
1.E+11
1.E+10
54 Yrs
1.E+09
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
VDE Safety Margin Zone
1800VRMS
2200
200
1200
3200
4200
5200
6200
Applied Voltage (VRMS
)
图 1. Reinforced Isolation Capacitor Life Time Projection
100
2000
VDD=15V; VEE=-5V
VDD=20V; VEE=-5V
80
60
40
20
0
1500
1000
500
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Ambient Temperature (oC)
Ambient Temperature (oC)
Safe
Safe
图 2. Thermal Derating Curve for Limiting Current per VDE
图 3. Thermal Derating Curve for Limiting Power per VDE
12
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6.12 Typical Characteristics
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
6
6
4
4
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D016
D017
图 4. Output High Drive Current vs. Temperature
图 5. Output Low Driver Current vs. Temperature
6
5.5
5
4
3.5
3
VCC = 3.3V
VCC = 5V
VCC = 3.3V
VCC = 5V
4.5
4
2.5
2
3.5
3
1.5
1
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D015
D014
IN+ = High
IN- = Low
IN+ = Low
IN- = Low
图 6. IVCCQ Supply Current vs. Temperature
图 7. IVCCQ Supply Current vs. Temperature
5
4.5
4
6
5.5
5
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
3.5
3
4.5
4
2.5
2
3.5
3
30
70
110
150 190
Frequency (kHz)
230
270
310
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D018
D012
IN+ = High
IN- = Low
图 8. IVCCQ Supply Current vs. Input Frequency
图 9. IVDDQ Supply Current vs. Temperature
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Typical Characteristics (接下页)
6
10
9
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
5.5
5
8
7
4.5
4
6
5
4
3.5
3
3
2
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
30
70
110
150
190
Frequency (kHz)
230
270
310
D013
D019
IN+ = Low
IN- = Low
图 10. IVDDQ Supply Current vs. Temperature
图 11. IVDDQ Supply Current vs. Input Frequency
4
3.5
3
14
13.5
13
12.5
12
2.5
2
11.5
11
10.5
10
1.5
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D001
D002
图 12. VCC UVLO vs. Temperature
图 13. VDD UVLO vs. Temperature
100
90
80
70
60
50
100
90
80
70
60
50
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D021
D022
VCC = 3.3V
VDD=18V
CL = 100pF
VCC = 3.3V
VDD=18V
CL = 100pF
RON = 0Ω
ROFF = 0Ω
RON = 0Ω
ROFF = 0Ω
图 14. Propagation Delay tPDLH vs. Temperature
图 15. Propagation Delay tPDHL vs. Temperature
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Typical Characteristics (接下页)
60
60
50
40
30
20
10
50
40
30
20
10
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D023
D024
VCC = 3.3V
VDD=18V
CL = 10nF
VCC = 3.3V
VDD=18V
CL = 10nF
RON = 0Ω
ROFF = 0Ω
RON = 0Ω
ROFF = 0Ω
图 16. tr Rise Time vs. Temperature
图 17. tf Fall Time vs. Temperature
2.5
2.25
2
3
2.75
2.5
1.75
1.5
1.25
1
2.25
2
1.75
1.5
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D025
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
图 19. VCLP-OUT(H) Short Circuit Clamping Voltage vs. Temperature
D008
图 18. VOUTPD Output Active Pulldown Voltage vs.
Temperature
2
1.75
1.5
3
2.75
2.5
2.25
2
1.25
1
0.75
0.5
0.25
1.75
1.5
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D026
50
70
90
110
130
150 160
图 20. VCLP-OUT(L) Short Circuit Clamping Voltage vs. Temperature
Temperature (èC)
D009
图 21. VCLMPTH Miller Clamp Threshold Voltage vs.
Temperature
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Typical Characteristics (接下页)
400
70
60
50
40
30
350
300
250
200
150
100
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D010
D011
图 22. ICLMPEL Miller Clamp Sink Current vs. Temperature
图 23. tDCLMPE Miller Clamp ON Delay Time vs. Temperature
1
0.8
0.6
0.4
0.2
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D003
图 24. VOCTH OC Detection Threshold vs. Temperature
7 Parameter Measurement Information
7.1 Propagation Delay
7.1.1 Regular Turn-OFF
图 25 shows the propagation delay measurement for non-inverting configurations. 图 26 shows the propagation
delay measurement with the inverting configurations.
16
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Propagation Delay (接下页)
50%
50%
IN+
INÅ
tPDLH
tPDHL
90%
10%
OUT
图 25. Non-inverting Logic Propagation Delay Measurement
IN+
INÅ
50%
50%
tPDLH
tPDHL
90%
OUT
10%
图 26. Inverting Logic Propagation Delay Measurement
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7.2 Input Deglitch Filter
In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input
pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is no
faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the
input deglitch filter width, TINFIL, there will be no responses on OUT drive signal. 图 27 and 图 28 shows the IN+
pin ON and OFF pulse deglitch filter effect. 图 29 and 图 30 shows the IN– pin ON and OFF pulse deglitch filter
effect.
IN+
tPWM < TINFIL
tPWM < TINFIL
IN+
INÅ
INÅ
OUT
OUT
图 27. IN+ ON Deglitch Filter
图 28. IN+ OFF Deglitch Filter
IN+
IN+
INÅ
tPWM < TINFIL
tPWM < TINFIL
INÅ
OUT
OUT
图 29. IN– ON Deglitch Filter
图 30. IN– OFF Deglitch Filter
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7.3 Active Miller Clamp
7.3.1 External Active Miller Clamp
For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active
miller clamp can help add an additional low impedance path to bypass the miller current and prevent the high
dV/dt introduced unintentional turn-on through the miller capacitance. Different from the internal active miller
clamp, external active miller clamp function is used for applications where the gate driver may not be close to the
power device or power module due to system layout considerations. External active miller clamp function provide
a 5V gate drive signal to turn-on the external miller clamp FET when the gate driver voltage is less than miller
clamp threshold, VCLMPTH. 图 31 shows the timing diagram for external active miller clamp function.
(”IN+‘ Å ”INÅ‘)
IN
VDD
tDCLMPE
OUT
VCLMPTH
COM
VEE
HIGH
90%
tCLMPER
LOW
10%
CLMPE
图 31. Timing Diagram for External Active Miller Clamp Function
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7.4 Under Voltage Lockout (UVLO)
UVLO is one of the key protection features designed to protect the system in case of bias supply failures on
VCC — primary side power supply, and VDD — secondary side power supply.
7.4.1 VCC UVLO
The VCC UVLO protection details are discussed in this section. 图 32 shows the timing diagram illustrating the
definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(”IN+‘ Å ”INÅ‘)
tVCCFIL
tVCCÅ to OUT
VVCC_ON
VCC
VVCC_OFF
VDD
COM
VEE
tVCC+ to OUT
90%
VCLMPTH
OUT
10%
tVCC+ to RDY
tRDYHLD
tVCCÅ to RDY
Hi-Z
RDY
图 32. VCC UVLO Protection Timing Diagram
20
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Under Voltage Lockout (UVLO) (接下页)
7.4.2 VDD UVLO
The VDD UVLO protection details are discussed in this section. 图 33 shows the timing diagram illustrating the
definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(”IN+‘ Å ”INÅ‘)
tVDDFIL
VDD
tVDDÅ to OUT
VVDD_ON
VVDD_OFF
COM
VEE
VCC
tVDD+ to OUT
VCLMPTH
OUT
90%
tRDYHLD
10%
tVDD+ to RDY
tVDDÅ to RDY
RDY
Hi-Z
图 33. VDD UVLO Protection Timing Diagram
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Under Voltage Lockout (UVLO) (接下页)
7.4.3 VEE UVLO
The VEE UVLO protection details are discussed in this section. 图 34 shows the timing diagram illustrating the
definition of UVLO ON/OFF threshold, deglitch filter, response time, and RDY.
IN
(”IN+‘ Å ”INÅ‘)
tVEEÅ to OUT
VDD
tVEEFIL
COM
VVEE_OFF
VVEE_ON
VEE
VCC
90%
tVEE+ to OUT
OUT
VCLMPTH
10%
tVEEÅ to RDY
tVEE+ to RDY
tRDYHLD
RDY
Hi-Z
图 34. VEE UVLO Protection Timing Diagram
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7.5 OC (Over Current) Protection
7.5.1 OC Protection with Soft Turn-OFF
OC Protection is used to sense the current of SiC-MOSFETs and IGBTs under over current or shoot-through
condition. 图 35 shows the timing diagram of OC operation with soft turn-off.
IN
(”IN+‘ Å ”INÅ‘)
tOCFIL
VOCTH
OC
tOCOFF
90%
GATE
VCLMPTH
tOCFLT
tFLTMUTE
Hi-Z
FLT
tRSTFIL
tRSTFIL
RST/EN
HIGH
Hi-Z
OUTH
OUTL
LOW
Hi-Z
LOW
图 35. OC Protection with Soft Turn-OFF
7.6 ASC Protection
When ASC pin receives a logic high signal, the output will be forced high regardless of the input side pin
conditions. The ASC function has higher priority than the input signal and VCC UVLO. The priority of VDD and
VEE UVLO, and the overcurrent fault event are higher than ASC function.
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ASC Protection (接下页)
(”IN+‘ Å ”INÅ‘)
IN
VVCC_ON
VCC
VDD
VVCC_OFF
COM
VEE
tVCC- to RDY
tVCC+ to RDY
RDY
ASC
tASC_r
tASC_f
OUT
图 36. ASC Protection with VCC UVLO
24
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ASC Protection (接下页)
(”IN+‘ Å ”INÅ‘)
IN
VCC
VDD
VVDD_ON
VVDD_OFF
COM
VEE
tVDD- to RDY
tVDD+ to RDY
RDY
ASC
tVDD- to OUT
tASC_r
tVDD+ to OUT
tASC_f
OUT
图 37. ASC Protection with VDD UVLO
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ASC Protection (接下页)
(”IN+‘ Å ”INÅ‘)
IN
tOCFIL
VOCTH
OC
tOCFLT
FLT
RST/EN
ASC
tOCOFF
90%
GATE
图 38. ASC Protection with OC Fault
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8 Detailed Description
8.1 Overview
The UCC21736-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features
for SiC MOSFETs and IGBTs. The device can support up to 2121V DC operating voltage based on SiC
MOSFETs and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor
drive, on-board and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the
capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage
DSP/MCU and high voltage side.
The ±10A peak sink and source current of UCC21736-Q1 can drive the SiC MOSFET modules and IGBT
modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel
modules with external buffer stage. The input side is isolated with the output side with a reinforced isolation
barrier based on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8-
kVPK surge immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the
device fast and reduce the switching loss. While the 150V/ns minimum CMTI guarantees the reliability of the
system with fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime
setting, so the conduction loss can be reduced.
The device includes extensive protection and monitor features to increase the reliability and robustness of the
SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with
gate voltage ≥ 15V. The active miller clamp feature prevents the false turn on causing by miller capacitance
during fast switching. External miller clamp FET can be used, providing more versatility to the system design.
The device has the state-of-art overcurrent and short circuit detection time, and fault reporting function to the low
voltage side DSP/MCU. The soft turn off is triggered when the overcurrent or short circuit fault is detected,
minimizing the short circuit energy while reducing the overshoot voltage on the switches.
The active short circuit feature can create a phase to phase short circuit for a three-phase inverter, which is
useful for the motor drive applications to protect the battary if the microcontroller loses control.
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8.2 Functional Block Diagram
CLAMPE
OUTH
7
4
6
10
11
15
9
IN+
INt
PWM Inputs
MOD
DEMOD
Output Stage
t
ON/OFF Control
STO
VCC
OUTL
VDD
VCC
UVLO
VCC Supply
5
GND
RDY
UVLO
LDO[s for VEE,
COM and channel
3
8
COM
VEE
OC
12
13
14
16
Fault Decode
FLT
OCP
2
Fault Encode
RST/EN
ASC Circuit
PWM Driver
ASC
1
APWM
DEMOD
MOD
8.3 Feature Description
8.3.1 Power Supply
The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both
unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The
negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the
other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to
its fast switching speed.
28
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Feature Description (接下页)
8.3.2 Driver Stage
UCC21736-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength
can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.
UCC21736-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage.
Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an
important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW
state. The split output of the driver stage is depicted in . The driver has rail-to-rail output by implementing a
hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel
MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance RNMOS is the
same as ROL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed,
during the miller plateau region of the power semiconductor turn-on transient. The ROH in represents the on-
resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than
ROH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the
pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V
below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x ROL
.
Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up impedance results in
strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of
the power semiconductor and reduces the turn on switching loss.
The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. The on-
resistance of the N-Channel MOSFET ROL can be found in the . This MOSFET can ensure the OUTL voltage be
pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off
time, but also helps to increase the noise immunity considering the miller effect.
VDD
ROH
RNMOS
OUTH
Input
Signal
Anti Shoot-
through
Circuitry
OUTL
ROL
图 39. Gate Driver Output Stage
8.3.3 VCC, VDD and VEE Undervoltage Lockout (UVLO)
UCC21736-Q1 implements the internal UVLO protection feature for both input and output power supplies VCC
and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The
output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not
only reduces the power consumption of the driver itself during low power supply voltage condition, but also
increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the
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Feature Description (接下页)
gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD
value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the
power stage. UCC21736-Q1 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis; -3V
threshold voltage of VEE UVLO, with 400mV hysteresis. This threshold voltage is suitable for both SiC MOSFET
and IGBT.
The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity
of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak
transient current from the power supply, which can result in sudden voltage drop of the power supply. With
hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal
switching transients.
The timing diagrams of the UVLO feature of VCC, VDD and VEE are shown in 图 32, 图 33 and 图 34.The RDY
pin on the input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO
condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to
VCC to indicate the power good.
8.3.4 Active Pulldown
UCC21736-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the
VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature
can prevent the output be false turned on before the device is back to control.
VDD
OUTL
Ra
Control
Circuit
VEE
COM
图 40. Active Pulldown
8.3.5 Short Circuit Clamping
During short circuit condition, the miller capacitance can cause a current sinking to the OUTH/OUTL pin due to
the high dV/dt and boost the OUTH/OUTL voltage. The short circuit clamping feature of UCC21736-Q1 can
clamp the OUTH/OUTL pin voltage to be slightly higher than VDD, which can protect the power semiconductors
from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by an internal diode from
the OUTH/OUTL to VDD.
30
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Feature Description (接下页)
VDD
D1 D2 D3
OUTH
Control
Circuitry
OUTL
CLMPI
图 41. Short Circuit Clamping
8.3.6 External Active Miller Clamp
Active miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In
applications which the device can be in synchronous rectifier mode, the body diode conducts the current during
the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same and
the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-down
impedance of UCC21736-Q1 can provide a strong pulldown to hold the OUTL to VEE. However, external gate
resistance is usually adopted to limit the dV/dt. The miller effect during the turn on transient of the other power
semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or gate-
emitter voltage. If the voltage on VGS or VGE is higher than the threshold voltage of the power semiconductor, a
shoot through can happen and cause catastrophic damage. The active miller clamp feature of UCC21736-Q1
drives an external MOSFET, which connects to the device gate. The external MOSFET is triggered when the
gate voltage is lower than VCLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the false
turn on issue.
VCLMPTH
VCC
OUTH
+
3V to 5.5V
IN+
œ
CLMPI
OUTL
Control
Circuitry
µC
MOD
DEMOD
IN-
VEE
COM
VCC
图 42. Active Miller Clamp
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Feature Description (接下页)
8.3.7 Overcurrent and Short Circuit Protection
The UCC21736-Q1 implements a fast overcurrent and short circuit protection feature to protect the SiC MOSFET
or IGBT from catastrophic breakdown during fault. The OC pin of the device has a typical 0.7V threshold with
respect to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the
output is held in low state, the OC pin is pulled down by an internal MOSFET and held in LOW state, which
prevents the overcurrent and short circuit fault from false triggering. The OC pin is in high-impedance state when
the output is in high state, which means the overcurrent and short circuit protection feature only works when the
power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the voltage of OC pin
when the power semiconductor is turned off.
The overcurrent and short circuit protection feature can be used to SiC MOSFET module or IGBT module with
SenseFET, traditional desaturation circuit and shunt resistor in series with the power loop for lower power
applications. For SiC MOSFET module or IGBT module with SenseFET, the SenseFET integrated in the module
can scale down the drain current or collector current. With an external high precision sense resistor, the drain
current or collector current can be accurately measured. If the voltage of the sensed resistor higher than the
overcurrent threshold VOCTH is detected, the soft turn-off is initiated. A fault will be reported to the input side FLT
pin to DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin.
The state-of-art overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC
MOSFET and IGBT.
The overcurrent and short circuit protection feature can also be paired with desaturation circuit and shunt
resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device.
Detailed application diagrams of desaturation circuit and shunt resistor will be given in .
•
High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on shunt
resistor’s parasitic inductance and board layout parasitic, which results in false trigger of OC pin. High
precision, low ESL and small value resistor must be used in this approach.
•
Shunt resistor approach is not recommended for high power applications and short circuit protection of the
low power applications.
The detailed applications of the overcurrent and short circuit feature will be discussed in the Application and
Implementation section.
OUTL
ROFF
OC
RFLT
+
FLT
DEMOD
MOD
+
VOCTH
RS
CFLT
œ
Control
Logic
GND
COM
VEE
图 43. Overcurrent and Short Circuit Protection
32
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Feature Description (接下页)
8.3.8 Fault (FLT, Reset and Enable (RST/EN)
The FLT pin of UCC21736-Q1 is open drain and can report a fault signal to the DSP/MCU when the overcurrent
and short circuit fault is detected through OC pin. The FLT pin is pulled down to GND, and is held in low state
unless a reset signal is received from RST/EN. The device has a fault mute time tFLTMUTE, within which the device
ignores any reset signal.
The RST/EN is pulled down internally. The device is disabled by default if the RST/EN pin is floating. The pin has
two purposes:
•
Resets the overcurrent and short circuit fault signaled on FLT pin. The RST/EN pin is active low, if the pin is
set and held in low state for more than tRSTFIL, the fault signal is reset andFLT is reset back to the high
impedance status at the rising edge of RST/EN pin.
•
Enable and shutdown the device. If the RST/EN pin is pulled low, the driver is disabled and shut down by the
regular turn off. The pin must be pulled up externally to enable the part, otherwise the device is disabled by
default.
8.3.9 ASC Protection and APWM Monitor
When VCC loses power, or MCU is malfunctional, the motor can lose control and reversely charging the battery.
Overvoltage of the battery can cause battery break down, or even the fire hazard. In this case, the active short
circuit (ASC) function is used to protect the system by forcing the output signal high, turning on the switch and
creating an active short circuit loop between the phases to bypass the battery. The timing diagram of ASC
protection with VCC UVLO, VDD UVLO and OC fault are shown in 图 36, 图 37, and 图 38.
The UCC21736-Q1 encodes the voltage signal VASC to a PWM signal, passing through the reinforced isolation
barrier, and output to APWM pin on the input side. Thus the ASC pin status can be monitored. The PWM signal
can either be transferred directly to DSP/MCU to calculate the duty cycle, or filtered by a simple RC filter as an
analog signal. The ASC input voltage varies from 0V to 5V, and the corresponding duty cycle of the APWM
output ranges from 95% to 5% with 400kHz frequency.
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8.4 Device Functional Modes
lists the device function.
表 1. Function Table
Input
Output
OUTH/OUTL
VCC
X
VDD
PU
VEE
PU
PU
PD
X
IN+
X
IN-
X
RST/EN
X
ASC
High
X
RDY
X
FLT
X
CLMPE
Low
High
Low
Low
Low
Low
Low
HiZ
PU
PU
PU
PD
PU
PU
PU
PU
PU
PU
PD
X
X
High
High
X
Low
Low
Low
HiZ
HiZ
Low
Low
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
High
High
Low
PU
X
X
X
PD
X
X
Low
Low
Low
Low
Low
Low
Low
Low
PU
X
X
X
X
High
High
HiZ
PU
X
X
X
Low
X
Open
PU
X
X
X
Open
X
X
X
X
Low
Low
Low
HiZ
High
High
High
Low
PU
Low
X
X
High
High
High
PU
X
High
Low
PU
X
High
PU: Power Up (VCC ≥ 3V, VDD ≥ 12.8V; VEE ≤ -3.3V); PD: Power Down (VCC ≤ 2.2V, VDD ≤ 10.4V, VEE ≥
-2.3V); X: Irrelevant; P*: PWM Pulse; HiZ: High Impedance
34
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9 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21736-Q1 device is very versatile because of the strong drive strength, wide range of output power
supply, high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working
voltage and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus
voltage up to 2121V. The device can be used in both low power and high power applications such as the traction
inverter in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies
and etc. The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device
directly without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which
allows the driver to have more control to the power semiconductor and saves the cost and space of the board
design. UCC21736-Q1 can also be used to drive very high power modules or paralleled modules with external
buffer stage. The input side can support power supply and microcontroller signal from 3.3V to 5V, and the device
level shifts the signal to output side through reinforced isolation barrier. The device has wide output power supply
range from 13V to 33V and support wide range of negative power supply. This allows the driver to be used in
SiC MOSFET applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor
with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the
device can be used to drive either a low-side or high-side driver.
UCC21736-Q1 device features extensive protection and monitoring features, which can monitor, report and
protect the system from various fault conditions.
•
Fast detection and protection for the overcurrent and short circuit fault. The feature is preferable in a split
source SiC MOSFET module or a split emitter IGBT module. For the modules with no integrated current
mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement
short circuit protection. The semiconductor is shutdown when the fault is detected and FLTb pin is pulled
down to indicate the fault detection. The device is latched unless reset signal is received from the RST/EN
pin.
•
•
Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and
short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is
limited.
UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to
be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is
back to normal operation mode once the power supply is out of the UVLO status. The power good status can
be monitored from the RDY pin.
•
•
Active short circuit feature creates phase to phase short circuit in three-phase inverter to protect the battery
from overvoltage breakdown.
The active miller clamp feature protects the power semiconductor from false turn on by driving an external
MOSFET. This feature allows the flexibility of the board layout design and the pulldown strength of miller
clamp FET.
•
•
•
Enable and disable function through the RSTb/EN pin.
Short circuit clamping.
Active pulldown.
9.2 Typical Application
shows the typical application of a half bridge using two UCC21736-Q1 isolated gate drivers. The half bridge is a
basic element in various power electronics applications such as traction inverter in HEV/EV to convert the DC
current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion system. The
topology can also be used in motor drive applications to control the operating speed and torque of the AC
motors.
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Typical Application (接下页)
UCC
UCC
UCC
UCC
21736-Q1
21736-Q1
21736-Q1
21736-Q1
1
2
3
4
5
6
PWM
µC
3-Phase
Input
M
4
5
6
ASC
FLT
UCC
UCC
21736-Q1
21736-Q1
图 44. Typical Application Schematic
9.2.1 Design Requirements
The design of the power system for end equipment should consider some design requirements to ensure the
reliable operation of UCC1736-Q1 through the load range. The design considerations include the peak source
and sink current, power dissipation, overcurrent and short circuit protection and etc.
A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show
in .
表 2. Design Parameters
Parameter
Input Supply Voltage
IN-OUT Configuration
Positive Output Voltage VDD
Negative Output Voltage VEE
DC Bus Voltage
Value
5V
Non-inverting
15V
-5V
800V
Peak Drain Current
Switching Frequency
Switch Type
300A
50kHz
IGBT Module
36
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9.2.2 Detailed Design Procedure
9.2.2.1 Input filters for IN+, IN- and RST/EN
In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With
the strong drive strength of UCC21736-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise can not
only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal
PCB layout and coupled capacitance.
UCC21736-Q1 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can
be filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input
pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and
increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be
tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is
to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter
resistors and capacitors, both the noise immunity effect and delay time should be considered according to the
system requirements.
9.2.2.2 PWM Interlock of IN+ and IN-
UCC21736-Q1 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg
shoot through issue. As shown in , the output is logic low while both IN+ and IN- are logic high. When only IN+ is
used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the
phase leg can be sent to the IN- pin. As shown in , the PWM_T is the PWM signal to top side switch, the
PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to the
IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is
given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are
high, the outputs of both gate drivers are logic low to prevent the shoot through condition.
IN+
IN-
RON
OUTH
OUTL
ROFF
PWM_T
PWM_B
RON
IN+
IN-
OUTH
OUTL
ROFF
图 45. PWM Interlock for a Half Bridge
9.2.2.3 FLT, RDY and RST/EN Pin Circuitry
Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩ internal pulldown resistor, so the driver
is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for
the FLT, RDY and RST/EN pins.
To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be
added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to
300pF can be added.
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3.3V to 5V
0.1µF
VCC
15
9
1µF
GND
IN+
10
INt
11
5kQ
5kQ 5kQ
FLT
12
13
100pF
RDY
100pF
RST/EN
14
16
100pF
APWM
图 46. FLT, RDY and RST/EN Pins Circuitry
9.2.2.4 RST/EN Pin Control
RST/EN pin has two functions. It can be used to enable and shutdown the outputs of the driver, and reset the
fault signaled on the FLT pin. RST/EN pin needs to be pulled up to enable the device; when the pin is pulled
down, the device is in disabled status. With a 50kΩ pulldown resistor existing, the driver is disabled by default.
When the driver is latched after overcurrent or short circuit fault is detected, the FLT pin and output are latched
low and need to be reset byRST/EN pin. RST/EN pin is active low. The microcntroller needs to send a signal to
RST/EN pin after the fault mute time tFLTMUTE to reset the driver. This pin can also be used to automatically reset
the driver. The continuous input signal IN+ or IN- can be applied to RST/EN pin, so the microcontroller does not
need to generate another control signal to reset the driver. If non-inverting input IN+ is used, then IN+ can be tied
to RST/EN pin. If inverting input IN- is used, then a NOT logic is needed between the inverting PWM signal from
the microcontroller and the RST/EN pin. In this case, the driver can be reset in every switching cycle without an
extra control signal from microcontroller to RST/EN pin.
38
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3.3V to 5V
0.1µF
3.3V to 5V
0.1µF
VCC
VCC
15
15
1µF
1µF
GND
IN+
GND
IN+
9
9
10
10
INt
INt
5kQ
11
5kQ
5kQ
11
5kQ
FLT
FLT
12
13
12
13
100pF
100pF
100pF
100pF
RDY
RDY
RST/EN
APWM
RST/EN
APWM
14
16
14
16
图 47. Automatic Reset Control
9.2.2.5 Turn on and turn off gate resistors
UCC21736-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn on and
turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which
controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to
ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:
VDD - VEE
ROH_EFF +RON +RG _Int
Isource _ pk = min(10A,
Isink _ pk = min(10A,
)
VDD - VEE
ROL +ROFF +RG _Int
)
(1)
Where
•
ROH_EFF is the effective internal pull up resistance of the hybrid pull-up structure, which is approximately 2 x
ROL, about 0.7 Ω
•
•
•
•
ROL is the internal pulldown resistance, about 0.3 Ω
RON is the external turn on gate resistance
ROFF is the external turn off gate resistance
RG_Int is the internal resistance of the SiC MOSFET or IGBT module
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VDD
Cies=Cgc+Cge
+
VDD
Cgc
ROH_EFF
t
OUTH
OUTL
RON
RG_Int
ROFF
Cge
+
VEE
ROL
t
VEE
COM
图 48. Output Model for Calculating Peak Gate Current
For example, for an IGBT module based system with the following parameters:
•
•
•
Qg = 3300 nC
RG_Int = 1.7 Ω
RON=ROFF= 1 Ω
The peak source and sink current in this case are:
VDD - VEE
Isource _ pk = min(10A,
) ö 5.9A
ROH_EFF +RON +RG _Int
VDD - VEE
ROL +ROFF +RG _Int
Isink _ pk = min(10A,
) ö 6.7A
(2)
Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The
collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller
plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless
the turn on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the
turn on switching loss is. The dV/dt can be estimated as Qgc/Isource_pk. For the turn off switching transient, the
drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After Vce
reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled
by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If
using relatively large turn off gate resistance, the Vce overshoot can be limited. The overshoot can be estimated
by:
DV = Lstray ∂Iload / ((ROFF +ROL +RG_Int )∂Cies ∂ln(Vplat / V ))
ce
th
(3)
Where
•
•
•
•
•
Lstray is the stray inductance in power switching loop, as shown in 图 49
Iload is the load current, which is the turn off current of the power semiconductor
Cies is the input capacitance of the power semiconductor
Vplat is the plateau voltage of the power semiconductor
Vth is the threshold voltage of the power semiconductor
40
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LDC
Lc1
Lstray=LDC+Le1+Lc1+Le1+Lc1
RG
Lload
t
+
Le1
+
VDC
t
Lc2
VDD
Cgc
Cies=Cgc+Cge
RG
OUTH
OUTL
COM
Cge
Le2
图 49. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration
The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The
power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:
P = PQ +P
DR
SW
(4)
PQ is the quiescent power loss for the driver, which is Iq x (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent
power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic
circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the
charging and discharing current of the internal circuit when the driver is switching. The power dissipation when
the driver is switching can be calculated as:
ROH_EFF
ROL
1
P
=
∂(
+
)∂(VDD - VEE)∂ fsw ∂Qg
SW
2 ROH_EFF +RON +RG _Int ROL +ROFF +RG _Int
(5)
Where
•
•
Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
fsw is the switching frequency
In this example, the PSW can be calculated as:
ROH_EFF
ROL
1
P
=
∂(
+
)∂(VDD - VEE)∂ fsw ∂Qg = 0.505W
SW
2 ROH_EFF + RON + RG _Int ROL +ROFF +RG _Int
(6)
41
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Thus, the total power loss is:
P =P +P = 0.10W +0.505W = 0.605W
DR
Q
SW
(7)
(8)
When the board temperature is 125°C, the junction temperature can be estimated as:
Tj = T + yjb ∂P ö 150oC
b
DR
Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency
is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing
external gate resistance, the gate driver can be operated at a higher switching frequency.
9.2.2.6 External Active Miller Clamp
External active miller clamp feature allows the gate driver to stay at the low status when the gate voltage is
detected below VCLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through
the parasitic miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative
voltage drop on the turn off gate resistance, and bumps up the gate voltage to cause a false turn on. The
external active miller clamp features allows flexibility of board layout and active miller clamp pulldown strength.
Limited by the board layout, if the driver cannot be placed close enough to the switch, external active miller
clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak
current needed. Caution must be exercised when the driver is place far from the power semiconductor. Since the
device has high peak sink and source current, the high dI/dt in the gate loop can cause a ground bounce on the
board parasitics. The ground bounce can cause a positive voltage bump on CLMPE pin during the turn off
transient, and results in the external active miller clamp MOSFET to turn on shortly and add extra drive strength
to the sink current. To reduce the ground bounce, a 2Ω resistance is recommended to the gate of the external
active clamp MOSFET.
When the VOUTH is detected to be lower than VCLMPTH above VEE, the CLMPE pin outputs a 5V voltage with
respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak
drain current, unless the on-resistance of the external clamp FET is large.
VDS
ICLMPE _PK = min(ID _PK
,
)
RDS _ ON
(9)
Where
•
•
•
ID_PK is the peak drain current of the external clamp FET
VDS is the drain-to-source voltage of the clamp FET when the CLMPE is activated
RDS_ON is the on-resistance of the external clamp FET
The total delay time of the active miller clamp circuit from the gate voltage detection threshold VCLMPTH can be
calculated as tDCLMPE+tCLMPER. tCLMPER depends on the parameter of the external active miller clamp MOSFET.
As long as the total delay time is longer than the deadtime of high side and low side switches, the driver can
effectively protect the switch from false turn on issue caused by miller effect.
42
版权 © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
VCLMPTH
VCC
OUTH
+
3V to 5.5V
IN+
œ
CLMPE
OUTL
Control
Circuitry
µC
MOD
DEMOD
IN-
VEE
COM
VCC
图 50. External Active Miller Clamp Configuration
9.2.2.7 Overcurrent and Short Circuit Protection
Fast and reliable overcurrent and short circuit protection is important to protect the catastrophic break down of
the SiC MOSFET and IGBT modules, and improve the system reliability. The UCC21736-Q1 features a state-of-
art overcurrent and short circuit protection, which can be applied to both SiC MOSFET and IGBT modules with
various detection circuits.
9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
The overcurrent and short circuit protection function is suitable for the SiC MOSFET and IGBT modules with
integrated SenseFET. The SenseFET scales down the main power loop current and outputs the current with a
dedicated pin of the power module. With external high precision sensing resistor, the scaled down current can be
measured and the main power loop current can be calculated. The value of the sensing resistor RS sets the
protection threshold of the main current. For example, with a ratio of 1:N = 1:50000 of the integrated current
mirror, by using the RS as 20Ω, the threshold protection current is:
VOCTH
IOC _ TH
=
∂N = 1750A
RS
(10)
The overcurrent and short circuit protection based on integrated SenseFET has high precision, as it is sensing
the current directly. The accuracy of the method is related to two factors: the scaling down ratio of the main
power loop current and the SenseFET, and the precision of the sensing resistor. Since the current is sensed
from the SenseFET, which is isolated from the main power loop, and the current is scaled down significantly with
much less dI/dt, the sensing loop has good noise immunity. To further improve the noise immunity, a low pass
filter can be added. A 100pF to 10nF filter capacitor can be added. The delay time caused by the low pass filter
should also be considered for the protection circuitry design.
版权 © 2019, Texas Instruments Incorporated
43
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
OUTL
ROFF
SenseFET
Kelvin
Connection
OC
+
FLT
DEMOD
MOD
RFLT
+
VOCTH
œ
RS
CFLT
Control
Logic
GND
COM
VEE
图 51. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET
9.2.2.7.2 Protection Based on Desaturation Circuit
For SiC MOSFET and IGBT modules without SenseFET, desaturation (DESAT) circuit is the most popular circuit
which is adopted for overcurrent and short circuit protection. The circuit consists of a current source, a resistor, a
blanking capacitor and a diode. Normally the current source is provided from the gate driver, when the device
turns on, a current source charges the blanking capacitor and the diode forward biased. During normal operation,
the capacitor voltage is clamped by the switch VCE voltage. When short circuit happens, the capacitor voltage is
quickly charged to the threshold voltage which triggers the device shutdown. For the UCC21736-Q1, the OC pin
does not feature an internal current source. The current source should be generated externally from the output
power supply. When UCC21736-Q1 is in OFF state, the OC pin is pulled down by an internal MOSFET, which
creates an offset voltage on OC pin. By choosing R1 and R2 significantly higher than the pulldown resistance of
the internal MOSFET, the offset can be ignored. When UCC21736-Q1 is in ON state, the OC pin is high
impedance. The current source is generated by the output power supply VDD and the external resistor divider
R1, R2 and R3. The overcurrent detection threshold voltage of the IGBT is:
R2 + R3
R3
VDET =VOCTH
∂
-VF
(11)
(12)
The blanking time of the detection circuit is:
R1 + R2
R1 + R2 + R3
R1 + R2 + R3 VOCTH
tBLK = -
∂R3 ∂CBLK ∂ln(1-
∂
)
R3
VDD
Where:
•
•
•
•
VOCTH is the detection threshold voltage of the gate driver
R1, R2 and R3 are the resistance of the voltage divider
CBLK is the blanking capacitor
VF is the forward voltage of the high voltage diode DHV
The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has
negligible power loss, and is easy to implement. The detection threshold voltage of IGBT and blanking time can
be programmed by external components. Different with the conventional desaturation circuit, the overcurrent
detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the
detection threshold voltage of the driver. A parallel schottky diode can be connected between OC and COM pins
to prevent the negative voltage on the OC pin in noisy system. Since the desaturation circuit measures the VCE
of the IGBT or VDS of the SiC MOSFET, not directly the current, the accuracy of the protection is not as high as
the SenseFET based protection method. The current threshold cannot be accurately controlled in the protection.
44
版权 © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
ROFF
RDESAT
DHV
VDD
R1
OC
R2
+
FLT
DEMOD
MOD
+
VOCTH
R3
CBLK
œ
Control
Logic
GND
COM
VEE
图 52. Overcurrent and Short Circuit Protection Based on Desaturation Circuit
9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
In lower power applications, to simplify the circuit and reduce the cost, a shunt resistor can be used in series in
the power loop and measure the current directly. Since the resistor is in series in the power loop, it directly
measures the current and can have high accuracy by using a high precision resistor. The resistance needs to be
small to reduce the power loss, and should have large enough voltage resolution for the protection. Since the
sensing resistor is also in series in the gate driver loop, the voltage drop on the sensing resistor can cause the
voltage drop on the gate voltage of the IGBT or SiC MOSFET modules. The parasitic inductance of the sensing
resistor and the PCB trace of the sensing loop will also cause a noise voltage source during switching transient,
which makes the gate voltage oscillate. Thus, this method is not recommended for high power application, or
when dI/dt is high. To use it in low power application, the shunt resistor loop should be designed to have the
optimal voltage drop and minimum noise injection to the gate loop.
ROFF
OC
RFLT
+
FLT
DEMOD
MOD
+
VOCTH
RS
CFLT
œ
Control
Logic
GND
COM
VEE
图 53. Overcurrent and Short Circuit Protection Based on Shunt Resistor
版权 © 2019, Texas Instruments Incorporated
45
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
9.2.2.8 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in 图
54) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be
avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/ D45VH10
pair is up to 20 A peak.
In the case of a over-current detection, the soft turn off (STO) is activated. External components must be added
to implement STO instead of normal turn off speed when an external buffer is used. CSTO sets the timing for soft
turn off and RSTO limits the inrush current to below the current rating of the internal FET (10A). RSTO should be at
least (VDD-VEE)/10. The soft turn off timing is determined by the internal current source of 400mA and the
capacitor CSTO. CSTO is calculated using .
ISTO ∂ tSTO
VDD VEE
CSTO
=
(13)
•
•
ISTO is the the internal STO current source, 400mA
tSTO is the desired STO timing
VDD
VDD
ROH
Cies=Cgc+Cge
OUTH
OUTL
RNMOS
Cgc
Cgc
RG_2
RG_1
RG_Int
RG_Int
Cge
Cge
ROL
CSTO
COM
VEE
RSTO
图 54. Current Buffer for Increased Drive Strength
10 Power Supply Recommendations
During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and
VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a
voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of
decoupling capacitors are recommended at the power supplies. Considering UCC21736-Q1 has ±10A peak drive
strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE and
COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with output
side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out high
frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and
should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system
parasitics of PCB layout.
46
版权 © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
11 Layout
11.1 Layout Guidelines
Due to the strong drive strength of UCC21736-Q1, careful considerations must be taken in PCB design. Below
are some key points:
•
The driver should be placed as close as possible to the power semiconductor to reduce the parasitic
inductance of the gate loop on the PCB traces
•
The decoupling capacitors of the input and output power supplies should be placed as close as possible to
the power supply pins. The peak current generated at each switching transient can cause high dI/dt and
voltage spike on the parasitic inductance of PCB traces
•
The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If
the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close
as possible to the source or emitter terminal of the power device package to separate the gate loop from the
high power switching loop
•
•
Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the
high frequency noise generated by the output side switching transients. The ground plane provides a low-
inductance filter for the return current flow
If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the
ground plane on the output side to shield the output signals from the noise generated by the switch node; if
the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground
plane is not recommended
•
•
If ground plane is not used on the output side, separate the return path of the OC and AIN ground loop from
the gate loop ground which has large peak source and sink current
No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise
coupling between the input and output side which can contaminate the isolation barrier
版权 © 2019, Texas Instruments Incorporated
47
UCC21736-Q1
ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
11.2 Layout Example
图 55. Layout Example
48
版权 © 2019, Texas Instruments Incorporated
UCC21736-Q1
www.ti.com.cn
ZHCSKC0 –OCTOBER 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
《隔离相关术语》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2019, Texas Instruments Incorporated
49
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ZHCSKC0 –OCTOBER 2019
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
50
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版权 © 2019, Texas Instruments Incorporated
51
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC21736QDWQ1
UCC21736QDWRQ1
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
UCC21736Q
UCC21736Q
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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相关型号：
UCC21737-Q1
适用于 SiC/IGBT、具有主动短路保护功能的汽车类 10A 隔离式单通道栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21737QDWRQ1
适用于 SiC/IGBT、具有主动短路保护功能的汽车类 10A 隔离式单通道栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21739-Q1
适用于 IGBT/SiC MOSFET 且具有隔离式模拟检测的汽车类 3kVrms ±10A 单通道隔离式栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21739QDWQ1
适用于 IGBT/SiC MOSFET 且具有隔离式模拟检测的汽车类 3kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21739QDWRQ1
适用于 IGBT/SiC MOSFET 且具有隔离式模拟检测的汽车类 3kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750
适用于 IGBT/SiC FET 且具有 DESAT 和内部米勒钳位的 5.7kVrms ±10A 单通道隔离式栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750-Q1
适用于 IGBT/SiC MOSFET 且具有 DESAT 和内部钳位的汽车类 5.7kVrms、±10A 单通道隔离式栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750DW
适用于 IGBT/SiC FET 且具有 DESAT 和内部米勒钳位的 5.7kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750DWR
适用于 IGBT/SiC FET 且具有 DESAT 和内部米勒钳位的 5.7kVrms ±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750QDWQ1
适用于 IGBT/SiC MOSFET 且具有 DESAT 和内部钳位的汽车类 5.7kVrms、±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21750QDWRQ1
适用于 IGBT/SiC MOSFET 且具有 DESAT 和内部钳位的汽车类 5.7kVrms、±10A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC21755-Q1
具有主动保护和隔离式感应功能的汽车类 ±10A 隔离式单通道栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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