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UCC21739-Q1

SLUSDS3 –MARCH 2020

UCC21739-Q1 10-A Source/Sink Isolated Single Channel Gate Driver

for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI

The input side is isolated from the output side with

SiO₂capacitive isolation technology, supporting up to

700-kV_RMSworking voltage, 6-kV_PKsurge immunity

basic isolation with longer than 40 years isolation

barrier life, as well as providing low part-to-part skew,

and >150-V/ns common mode noise immunity

(CMTI).

1 Features

1

•

3-kV_RMSsingle channel isolated gate driver

AEC-Q100 qualified for automotive applications

SiC MOSFETs and IGBTs up to 990-V_pk

33-V maximum output drive voltage (VDD-VEE)

±10-A drive strength and split output

The UCC21739-Q1 includes the state-of-art

protection features, such as fast overcurrent and

short circuit detection, shunt current sensing support,

fault reporting, active miller clamp, and input and

output side power supply UVLO to optimize SiC and

IGBT switching behavior and robustness. The

isolated analog to PWM sensor can be utilized for

easier temperature or voltage sensing, further

increasing the drivers' versatility and simplifying the

system design effort, size and cost.

150-V/ns minimum CMTI

270-ns response time fast overcurrent protection

External active miller clamp

Internal 2-level turn-off when fault happens

Isolated analog sensor with PWM output for

–

Temperature sensing with NTC, PTC or

thermal diode

–

High voltage DC-Link or phase voltage

Device Information⁽¹⁾

•

Alarm FLT on over current and reset from

RST/EN

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Fast enable/disable response on RST/EN

UCC21739-Q1

DW SOIC-16

10.3 mm × 7.5 mm

Reject <40-ns noise transient and pulse on input

pins

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

12-V VDD UVLO with power good on RDY

Inputs/outputs with over/under-shoot transient

voltage Immunity up to 5 V

APWM

VCC

RST/EN

FLT

AIN

OC

1

2

3

4

5

6

7

8

16

15

•

130-ns (maximum) propagation delay and 30-ns

(maximum) pulse/part skew

COM

OUTH

VDD

14

13

12

11

10

9

SOIC-16 DW package with creepage and

clearance distance > 8 mm

Operating junction temperature –40°C to 150°C

RDY

INÅ

OUTL

CLMPE

VEE

2 Applications

IN+

•

Traction inverter for EVs

On-board charger and charging pile

DC/DC Converter for HEV/EVs

GND

Not to scale

3 Description

The UCC21739-Q1 is a galvanic isolated single

channel gate drivers designed for SiC MOSFETs and

IGBTs up to 990-V DC operating voltage with

advanced protection features, best-in-class dynamic

performance and robustness. UCC21739-Q1 has up

to ±10-A peak source and sink current.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC21739-Q1

SLUSDS3 –MARCH 2020

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Table of Contents

7.4 Under Voltage Lockout (UVLO) .............................. 21

7.5 OC (Over Current) Protection ................................. 23

Detailed Description ............................................ 24

8.1 Overview ................................................................. 24

8.2 Functional Block Diagram ....................................... 25

8.3 Feature Description................................................. 25

8.4 Device Functional Modes........................................ 32

Applications and Implementation ...................... 33

9.1 Application Information............................................ 33

9.2 Typical Application .................................................. 33

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Power Ratings........................................................... 6

6.6 Insulation Specifications............................................ 7

6.7 Safety-Related Certifications..................................... 7

6.8 Safety Limiting Values .............................................. 8

6.9 Electrical Characteristics........................................... 9

6.10 Switching Characteristics...................................... 11

6.11 Insulation Characteristics Curves ......................... 12

6.12 Typical Characteristics.......................................... 13

Parameter Measurement Information ................ 17

7.1 Propagation Delay................................................... 17

7.2 Input Deglitch Filter................................................. 19

7.3 Active Miller Clamp ................................................. 20

8

9

10 Power Supply Recommendations ..................... 49

11 Layout................................................................... 50

11.1 Layout Guidelines ................................................. 50

11.2 Layout Example .................................................... 51

12 Device and Documentation Support ................. 52

12.1 Documentation Support ....................................... 52

12.2 Receiving Notification of Documentation Updates 52

12.3 Community Resource............................................ 52

12.4 Trademarks........................................................... 52

12.5 Electrostatic Discharge Caution............................ 52

12.6 Glossary................................................................ 52

7

13 Mechanical, Packaging, and Orderable

Information ........................................................... 52

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

March 2020

*

Initial release

2

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5 Pin Configuration and Functions

UCC21739-Q1

DW SOIC (16)

Top View

APWM

VCC

RST/EN

FLT

AIN

OC

1

2

3

4

5

6

7

8

16

15

COM

OUTH

VDD

14

13

12

11

10

9

RDY

INÅ

OUTL

CLMPE

VEE

IN+

GND

Not to scale

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Table 1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

AIN

NO.

1

I

Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity

OC

2

Over current detection pin, support lower threshold for SenseFET, DESAT, and Shunt resistor sensing

Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET

Gate driver output pull up

COM

OUTH

3

P

O

4

Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate

driver source peak current capability

VDD

5

P

OUTL

6

7

O

Gate driver output pull down

CLMPE

External Active miller clamp, connecting this pin to the gate of the external miller clamp MOSFET

Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate

driver sink peak current capability

VEE

8

P

GND

IN+

9

P

I

Input power supply and logic ground reference

Non-inverting gate driver control input

Inverting gate driver control input

10

11

IN–

I

Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other

RDY signals

RDY

FLT

12

13

O

Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be

paralleled with other faults

The RST/EN serves two purposes:

1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to

low;

RST/EN

14

I

2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A

reset of signal FLT is asserted at the rising edge of terminal RST/EN.

For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The

FET is turned off by a general turn-off, if terminal EN is set to low.

VCC

15

16

P

Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND

Isolated Analog Sensing PWM output

APWM

O

(1) P = Power, G = Ground, I = Input, O = Output

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

MAX

6

UNIT

V

VCC

VDD

VEE

V_MAX

VCC – GND

VDD – COM

VEE – COM

VDD – VEE

–0.3

36

V

–17.5

0.3

V

–0.3

36

V

DC

GND–0.3

GND–5.0

–0.3

VCC

VCC+5.0

5

V

IN+, IN–, RST/EN

Transient, less than 100 ns⁽²⁾

V

AIN

OC

Reference to COM

V

-0.3

6

DC

VEE–0.3

VEE–5.0

–0.3

VDD

VDD+5.0

5

V

OUTH, OUTL

Transient, less than 100 ns⁽²⁾

CLMPE

Reference to VEE

V

RDY, FLT, APWM

GND–0.3

VCC

20

V

I_FLT, I_RDY

I_APWM

T_J

FLT, and RDY pin input current

APWM pin output current

mA

°C

20

Junction temperature range

Storage temperature range

–40

–65

150

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

PARAMETER

MIN

MAX

5.5

UNIT

VCC

VCC–GND

VDD–COM

VDD–VEE

3.0

V

VDD

13

33

V_MAX

–

0.7×VCC

0

33

High level input voltage

Low level input voltage

VCC

0.3×VCC

4.5

IN+, IN–, RST/EN

Reference to GND

V

AIN

t_RST/EN

T_A

Reference to COM

0.6

V

Minimum pulse width that reset the fault

Ambient Temperature

800

ns

°C

–40

125

150

T_J

Junction temperature

–40

6.4 Thermal Information

UCC21739-Q1

DW (SOIC)

16

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

68.3

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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Thermal Information (continued)

UCC21739-Q1

DW (SOIC)

16

THERMAL METRIC⁽¹⁾

UNIT

R_θJC(top)

R_θJB

ψ_JT

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

27.5

°C/W

32.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

14.1

ψ_JB

32.3

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

Value

UNIT

Maximum power dissipation (both

sides)

P_D

985

mW

Maximum power dissipation by

transmitter side

VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,

50% Duty Cycle for 10nF load, T_a=25^oC

P_D1

P_D2

20

mW

Maximum power dissipation by

receiver side

965

6

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6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

CPG

Minimum internal gap (Internal clearance) of the

double insulation (2 × 0.0085 mm)

DTI

CTI

Distance through the insulation

> 17

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664–1

> 600

I

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage Category per IEC 60664–1

DIN V VDE V 0884-11 (VDE V 0884-11):2017-01⁽²⁾

V_IORMMaximum repetitive peak isolation voltage AC voltage (bipolar)

990

700

990

V_PK

V_RMS

V_DC

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST=V_IOTM, t = 60 s (qualification test)

V_TEST=1.2 x V_IOTM, t = 1 s (100% production test)

V_IOTM

V_IOSM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

4242

V_PK

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 9600 V_PK(qualification)

6000

Method a: After I/O safety test subgroup 2/3, V_ini

V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM, t_m= 10 s

=

≤ 5

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 × V_IORM, t_m

10 s

=

≤ 5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1: At routine test (100% production) and

preconditioning (type test) V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.5 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

~ 1

≥ 10¹²

≥ 10¹¹

≥ 10⁹

pF

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 3000 V_RMS, t = 60 s (qualification);

V_TEST= 1.2 × V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

6.7 Safety-Related Certifications

VDE

UL

CSA

CQC

TUV

Plan to certify according Plan to certify

to DIN V VDE V 0884-11 according to

(VDE V 0884-11):2017- UL 1577

Plan to certify according to

EN 61010-1:2010 (3rd Ed)

and

Plan to certify according to

CSA Component Acceptance Plan to certify according to

01;

Component

Recognition

Program

Notice 5A, IEC 60950-1, and

IEC 60601-1

GB4943.1-2011

EN 60950-

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

DIN EN 61010-1 (VDE

0411-1):2011-07

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Safety-Related Certifications (continued)

VDE

UL

CSA

CQC

TUV

3000V_RMSBasic insulation per

EN 61010-1:2010 (3rd Ed) up

to working voltage of 700

V_RMS

3000 V_RMSBasic insulation

per

Basic insulation

Maximum transient

isolation voltage, 4242

Isolation Rating of 3000 V_RMS

Basic insulation per CSA

60950-1- 07+A1+A2 and IEC

60950-1 (2nd Ed.), 700V_RMS

max working voltage (pollution voltage

degree 2, material group I) ;

;

Basic Insulation, Altitude ≤

5000m, Tropical climate,

660V_RMSmaximum working

V_PK

;

Single

Maximum repetitive peak protection,

isolation voltage, 990

V_PK

3000 V_RMS

EN 60950-

;

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013 up to

working voltage of 700 V_RMS

Maximum surge isolation

voltage, 6000 V_PK

Certification

Planned

Certification Planned

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

_θJA=68.3°C/W, V_DD= 15V, V_EE=-5V, T_J= 150°C, T_A

61

= 25°C

_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A

= 25°C

_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A

= 25°C

Safety input, output, or supply

current

I_S

mA

R

49

Safety input, output, or total

power

R

P_S

T_S

1220

150

mW

°C

Safety temperature

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air

thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air

thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount

packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient

temperature plus the power times the junction-to-air thermal resistance.

8

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6.9 Electrical Characteristics

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,

C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾

.

PARAMETER

VCC UVLO THRESHOLD AND DELAY

V_{VCC_ON}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.55

2.35

2.7

2.5

0.2

10

2.85

2.65

V_{VCC_OFF}

V_{VCC_HYS}

t_VCCFIL

VCC–GND

V

VCC UVLO Deglitch time

t_{VCC+ to OUT}

t_{VCC– to OUT}

t_{VCC+ to RDY}

t_{VCC– to RDY}

VCC UVLO on delay to output high

VCC UVLO off delay to output low

VCC UVLO on delay to RDY high

VCC UVLO off delay to RDY low

29

5

37.8

10

50

15

50

15

IN+ = VCC, IN– = GND

µs

30

5

37.8

10

RST/EN = VCC

VDD UVLO THRESHOLD AND DELAY

V_{VDD_ON}

10.5

9.9

12.0

10.7

0.8

5

12.8

11.8

V_{VDD_OFF}

V_{VDD_HYS}

t_VDDFIL

VDD–COM

V

VDD UVLO Deglitch time

t_{VDD+ to OUT}

t_{VDD– to OUT}

t_{VDD+ to RDY}

t_{VDD– to RDY}

VDD UVLO on delay to output high

VDD UVLO off delay to output low

VDD UVLO on delay to RDY high

VDD UVLO off delay to RDY low

2

5

8

10

15

IN+ = VCC, IN– = GND

RST/EN = FLT=High

5

µs

10

VCC, VDD QUIESCENT CURRENT

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

2.5

1.45

3.6

3

2

4

2.75

5.9

I_VCCQVCC quiescent current

mA

4

I_VDDQ

VDD quiescent current

3.1

3.7

5.3

LOGIC INPUTS — IN+, IN– and RST/EN

V_INH

V_INL

V_INHYS

I_IH

Input high threshold

V_CC=3.3V

V_IN= VCC

V_IN= GND

1.85

1.52

0.33

90

2.31

V

Input low threshold

0.99

Input threshold hysteresis

Input high level input leakage current

Input low level input leakage

V

µA

I_IL

–90

see Detailed Description for more

information

R_IND

R_INU

Input pins pull down resistance

Input pins pull up resistance

55

kΩ

see Detailed Description for more

information

IN+, IN– and RST/EN deglitch (ON and

OFF) filter time

T_INFIL

f_S= 50kHz

28

40

60

ns

T_RSTFIL

Deglitch filter time to reset /FLT

500

650

800

GATE DRIVER STAGE

I_OUT, I_OUTHPeak source current

I_OUT, I_OUTL

–10

10

A

C_L=0.18µF, f_S=1kHz

Peak sink current

(3)

Output pull-up resistance

Output pull-down resistance

High level output voltage

Low level output voltage

I_OUT= –0.1A

2.5

0.3

17.5

60

Ω

R_OUTH

R_OUTL

V_OUTH

V_OUTL

I_OUT= 0.1A

Ω

I_OUT= –0.2A, V_DD=18V

I_OUT= 0.2A

V

mV

ACTIVE PULLDOWN

I_OUTLor I_OUT= 0.1×I_OUT(L)(tpy)

VDD=OPEN, VEE=COM

,

V_OUTPD

Output active pull down on OUT, OUTL

2.5

V

EXTERNAL MILLER CLAMP

V_CLMPTH

Miller clamp threshold voltage

Reference to VEE

1.5

2.0

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

(3) For internal PMOS only. Refer to Feature Description for effective pull-up resistance.

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Electrical Characteristics (continued)

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,

C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

5

MAX

UNIT

V

V_CLMPE

I_CLMPEH

I_CLMPEL

t_CLMPER

t_DCLMPE

Output high voltage

Peak source current

Peak sink current

Rising time

Reference to VEE

4.4

5.3

0.25

20

A

C_CLMPE= 10nF

0.12

0.37

40

A

ns

C_CLMPE= 330pF

Miller clamp ON delay time

40

70

SHORT CIRCUIT CLAMPING

V_CLP-OUT(H)

V_CLP-OUT(L)

OC PROTECTION

I_DCHG

V_OUT–VDD, V_OUTH–VDD

OUT = Low, I_OUT(H)= 500mA, t_CLP=10us

OUT = High, I_OUT(L)= 500mA, t_CLP=10us

0.9

1.8

0.99

1.98

V

V_OUT–VDD, V_OUTL–VDD

OC pull down current when

Detection Threshold

V_OC= 1V

40

mA

V

V_OCTH

0.63

0.7

0.77

Voltage when OUT(L) = LOW, Reference

to COM

V_OCL

I_OC= 5mA

0.13

V

t_OCFIL

t_OCOFF

t_OCFLT

OC fault deglitch filter

95

150

300

120

270

530

180

400

750

ns

OC propagation delay to OUT(L) 90%

OC to FLT low delay

2-LEVEL TURNOFF (Triggered by OC)

V_2LOFF

t_2LOFF

I_TL1

2LOFF voltage threshold

8.3

9.0

10.0

V

2LOFF voltage time

500

1000

ns

High to 2-Level transition sink current

Soft turn-off current on fault conditions

900

mA

I_TL3

500

1200

ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)

V_AIN

Analog sensing voltage range

Internal current source

0.5

196

380

4.5

209

420

V

I_AIN

V_AIN=2.5V, -40°C< T_J< 150°C

V_AIN=2.5V

200

400

10

µA

f_APWM

BW_AIN

APWM output frequency

AIN–APWM bandwidth

kHz

V_AIN= 0.6V

V_AIN= 2.5V

V_AIN= 4.5V

86.5

48.5

7.5

88

89.5

51.5

11.5

D_APWM

APWM Dutycycle

50

10

FLT AND RDY REPORTING

VDD UVLO RDY low minimum holding

time

t_RDYHLD

0.55

1

ms

t_FLTMUTE

R_ODON

V_ODL

Output mute time on fault

Open drain output on resistance

Open drain low output voltage

Reset fault through RST/EN

I_ODON= 5mA

ms

Ω

30

IODON = 5mA

0.3

V

COMMON MODE TRANSIENT IMMUNITY

CMTI Common-mode transient immunity

150

V/ns

10

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6.10 Switching Characteristics

VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, C_L=100pF,

–40°C<T_J<150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

130

30

UNIT

ns

t_PDHL

t_PDLH

PWD

t_sk-pp

t_r

Propagation delay time – High to Low

Propagation delay time – Low to High

60

90

60

90

Pulse width distortion |t_PDHL– t_PDLH

|

Part to Part skew

Rising or Falling Propagation Delay

30

Driver output rise time

C_L=10nF

33

27

t_f

Driver output fall time

f_MAX

Maximum switching frequency

1

MHz

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6.11 Insulation Characteristics Curves

Figure 1. Basic Isolation Capacitor Life Time Projection

80

60

40

20

0

1400

1200

1000

800

600

400

200

0

VDD=15V; VEE=-5V

VDD=20V; VEE=-5V

0

25

50

75

100

125

150

0

20

40

60

80

100

120

140

160

Ambient Temperature (^oC)

Safe

Figure 2. Thermal Derating Curve for Limiting Current per

VDE

Figure 3. Thermal Derating Curve for Limiting Power per

VDE

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6.12 Typical Characteristics

22

20

18

16

14

12

10

8

22

20

18

16

14

12

10

8

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

6

4

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D016

D017

Figure 4. Output High Drive Current vs. Temperature

Figure 5. Output Low Driver Current vs. Temperature

6

4

VCC = 3.3V

VCC = 5V

VCC = 3.3V

VCC = 5V

5.5

5

3.5

3

4.5

4

2.5

2

3.5

3

1.5

1

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D015

D014

IN+ = High

IN- = Low

IN+ = Low

IN- = Low

Figure 6. I_VCCQSupply Current vs. Temperature

Figure 7. I_VCCQSupply Current vs. Temperature

5

4.5

4

6

5.5

5

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

3.5

3

4.5

4

2.5

2

3.5

3

30

70

110

150 190

Frequency (kHz)

230

270

310

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D018

D012

IN+ = High

IN- = Low

Figure 8. I_VCCQSupply Current vs. Input Frequency

Figure 9. I_VDDQSupply Current vs. Temperature

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Typical Characteristics (continued)

6

10

9

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

5.5

5

8

7

4.5

4

6

5

4

3.5

3

2

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

30

70

110

150

190

Frequency (kHz)

230

270

310

D013

D019

IN+ = Low

IN- = Low

Figure 10. I_VDDQSupply Current vs. Temperature

Figure 11. I_VDDQSupply Current vs. Input Frequency

4

3.5

3

14

13.5

13

12.5

12

2.5

2

11.5

11

10.5

10

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D001

D002

Figure 12. VCC UVLO vs. Temperature

Figure 13. VDD UVLO vs. Temperature

100

90

80

70

60

50

100

90

80

70

60

50

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D021

D022

V_CC= 3.3V

V_DD=18V

C_L= 100pF

V_CC= 3.3V

V_DD=18V

C_L= 100pF

R_ON= 0Ω

R_OFF= 0Ω

R_ON= 0Ω

R_OFF= 0Ω

Figure 14. Propagation Delay t_PDLHvs. Temperature

Figure 15. Propagation Delay t_PDHLvs. Temperature

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Typical Characteristics (continued)

60

50

40

30

20

10

50

40

30

20

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D023

D024

V_CC= 3.3V

V_DD=18V

C_L= 10nF

V_CC= 3.3V

V_DD=18V

C_L= 10nF

R_ON= 0Ω

R_OFF= 0Ω

R_ON= 0Ω

R_OFF= 0Ω

Figure 16. t_rRise Time vs. Temperature

Figure 17. t_fFall Time vs. Temperature

2.5

2.25

2

3

2.75

2.5

1.75

1.5

1.25

1

2.25

2

1.75

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D025

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

Figure 19. V_{CLP-OUT(H) Short Circuit Clamping Voltage vs. Temperature}

D008

Figure 18. V_OUTPDOutput Active Pulldown Voltage vs.

Temperature

2

1.75

1.5

3

2.75

2.5

1.25

1

2.25

2

0.75

0.5

0.25

1.75

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D026

50

70

90

110

130

150 160

Figure 20. V_{CLP-OUT(L) Short Circuit Clamping Voltage vs. Temperature}

Temperature (èC)

D009

Figure 21. V_CLMPTHMiller Clamp Threshold Voltage vs.

Temperature

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Typical Characteristics (continued)

400

70

60

50

40

30

350

300

250

200

150

100

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D010

D011

Figure 22. I_CLMPELMiller Clamp Sink Current vs.

Temperature

Figure 23. t_DCLMPEMiller Clamp ON Delay Time vs.

Temperature

1

0.8

0.6

0.4

0.2

330

320

310

300

290

280

270

260

250

240

230

VCC = 3.3V

VCC = 5V

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D020

D003

Figure 24. t_OCOFFOC Propagation Delay vs. Temperature

Figure 25. V_OCTHOC Detection Threshold vs. Temperature

10

9.5

9

700

650

600

550

500

450

400

8.5

8

7.5

7

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D004

D005

Figure 26. t_OCFLTOC to FLT Low Delay Time vs.

Temperature

Figure 27. V_2LOFF2-Level Turn Off Voltage Threshold vs.

Temperature

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Typical Characteristics (continued)

900

800

700

600

500

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D006

Figure 28. t_2LOFF2-Level Turn Off Time vs. Temperature

7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Regular Turn-OFF

Figure 29 shows the propagation delay measurement for non-inverting configurations. Figure 30 shows the

propagation delay measurement with the inverting configurations.

50%

IN+

INÅ

t_PDLH

t_PDHL

90%

10%

OUT

Figure 29. Non-inverting Logic Propagation Delay Measurement

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Propagation Delay (continued)

IN+

INÅ

50%

t_PDLH

t_PDHL

90%

OUT

10%

Figure 30. Inverting Logic Propagation Delay Measurement

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7.2 Input Deglitch Filter

In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input

pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is no

faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the

input deglitch filter width, T_INFIL, there will be no responses on OUT drive signal. Figure 31 and Figure 32 shows

the IN+ pin ON and OFF pulse deglitch filter effect. Figure 33 and Figure 34 shows the IN– pin ON and OFF

pulse deglitch filter effect.

IN+

t_PWM< T_INFIL

IN+

INÅ

OUT

Figure 31. IN+ ON Deglitch Filter

Figure 32. IN+ OFF Deglitch Filter

IN+

INÅ

t_PWM< T_INFIL

INÅ

OUT

Figure 33. IN– ON Deglitch Filter

Figure 34. IN– OFF Deglitch Filter

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7.3 Active Miller Clamp

7.3.1 External Active Miller Clamp

For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active

miller clamp can help add an additional low impedance path to bypass the miller current and prevent the high

dV/dt introduced unintentional turn-on through the miller capacitance. Different from the internal active miller

clamp, external active miller clamp function is used for applications where the gate driver may not be close to the

power device or power module due to system layout considerations. External active miller clamp function provide

a 5V gate drive signal to turn-on the external miller clamp FET when the gate driver voltage is less than miller

clamp threshold, V_CLMPTH. Figure 35 shows the timing diagram for external active miller clamp function.

(”IN+‘ Å ”INÅ‘)

IN

VDD

t_DCLMPE

OUT

V_CLMPTH

COM

VEE

HIGH

90%

t_CLMPER

LOW

10%

CLMPE

Figure 35. Timing Diagram for External Active Miller Clamp Function

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7.4 Under Voltage Lockout (UVLO)

UVLO is one of the key protection features designed to protect the system in case of bias supply failures on

VCC — primary side power supply, and VDD — secondary side power supply.

7.4.1 VCC UVLO

The VCC UVLO protection details are discussed in this section. Figure 36 shows the timing diagram illustrating

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VCCFIL

t_{VCCÅ to OUT}

V_{VCC_ON}

VCC

V_{VCC_OFF}

VDD

COM

VEE

t_{VCC+ to OUT}

90%

V_CLMPTH

OUT

10%

t_{VCC+ to RDY}

t_RDYHLD

t_{VCCÅ to RDY}

Hi-Z

RDY

VCC

APWM

Figure 36. VCC UVLO Protection Timing Diagram

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Under Voltage Lockout (UVLO) (continued)

7.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. Figure 37 shows the timing diagram illustrating

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VDDFIL

VDD

t_{VDDÅ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

COM

VEE

VCC

t_{VDD+ to OUT}

V_CLMPTH

OUT

90%

t_RDYHLD

10%

t_{VDD+ to RDY}

t_{VDDÅ to RDY}

RDY

Hi-Z

VCC

APWM

Figure 37. VDD UVLO Protection Timing Diagram

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7.5 OC (Over Current) Protection

7.5.1 OC Protection with 2-Level Turn-OFF

OC Protection is used to sense the current of SiC-MOSFETs and IGBTs under over current or shoot-through

condition. Figure 38 shows the timing diagram of OC operation with 2-level turn-off.

IN

(”IN+‘ Å ”INÅ‘)

t_OCFIL

V_OCTH

OC

t_OCOFF

90%

V_2LOFF

t_2LOFF

GATE

V_CLMPTH

t_OCFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

A.

Figure 38. OC Protection with 2-Level Turn-OFF

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8 Detailed Description

8.1 Overview

The UCC21739-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features

for SiC MOSFETs and IGBTs. The device can support up 1700V SiC MOSFETs and IGBTs, targeting larger than

10kW applications such as HEV/EV traction inverter, motor drive, on-board and off-board battery charger, solar

inverter etc. The galvanic isolation is implemented by the capacitive isolation technology, which can realize

reliable isolation between the low voltage DSP/MCU and high voltage side.

The ±10A peak sink and source current of UCC21739-Q1 can drive the SiC MOSFET modules and IGBT

modules directly without an extra buffer. The input side is isolated with the output side with a basic isolation

barrier based on capacitive isolation technology. The minimum 150V/ns CMTI guarantees the reliability of the

strong drive strength. The small propagation delay and part-to-part skew can minimize the deadtime setting, so

the conduction loss can be reduced.

The device includes extensive protection and monitor features to increase the reliability and robustness of the

SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with

gate voltage ≥ 15V. The active miller clamp feature prevents the false turn on causing by miller capacitance

during fast switching. External miller clamp FET can be used, providing more versatility to the system design.

The device has the state-of-art overcurrent and short circuit detection time, and fault reporting function to the low

voltage side DSP/MCU. The 2-level turn-off with soft turn off is triggered when the overcurrent or short circuit

fault is detected, minimizing the short circuit energy while reducing the overshoot voltage on the switches.

The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,

auxiliary power supply sensing, etc. The PWM signal can be fed directly to DSP/MCU or through a low-pass-filter

as an analog signal.

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8.2 Functional Block Diagram

CLMPE

OUTH

7

4

6

10

11

15

9

IN+

INt

55kQ

PWM Inputs

MOD

DEMOD

Output Stage

t

ON/OFF Control

STO

VCC

OUTL

VDD

VCC

UVLO

VCC Supply

5

GND

RDY

UVLO

LDO[s for VEE,

COM and channel

3

8

COM

VEE

OC

12

13

14

16

Fault Decode

FLT

OCP

2

Fault Encode

RST/EN

50kQ

Analog 2 PWM

PWM Driver

AIN

1

APWM

DEMOD

MOD

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both

unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The

negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the

other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to

its fast switching speed.

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Feature Description (continued)

8.3.2 Driver Stage

UCC21739-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength

can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.

UCC21739-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage.

Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an

important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW

state. The split output of the driver stage is depicted in Figure 39. The driver has rail-to-rail output by

implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and

an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on

resistance R_NMOSis the same as R_OL. The hybrid pull-up structure delivers the highest peak-source current when

it is most needed, during the miller plateau region of the power semiconductor turn-on transient. The R_OHin

represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is

much smaller than R_OH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-

Channel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on

OUTH pin is about 3V below VDD voltage. The effective resistance of the hybrid pull-up structure during this

period is about 2 x R_OL. Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up

impedance results in strong drive strength during the turn-on transient, which shortens the charging time of the

input capacitance of the power semiconductor and reduces the turn on switching loss.

The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. The on-

resistance of the N-Channel MOSFET R_OLcan be found in the . This MOSFET can ensure the OUTL voltage be

pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off

time, but also helps to increase the noise immunity considering the miller effect.

VDD

R_OH

R_NMOS

OUTH

Input

Signal

Anti Shoot-

through

Circuitry

OUTL

R_OL

Figure 39. Gate Driver Output Stage

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Feature Description (continued)

8.3.3 VCC and VDD Undervoltage Lockout (UVLO)

UCC21739-Q1 implements the internal UVLO protection feature for both input and output power supplies VCC

and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The

output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not

only reduces the power consumption of the driver itself during low power supply voltage condition, but also

increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the

gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD

value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the

power stage. UCC21739-Q1 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis. This

threshold voltage is suitable for both SiC MOSFET and IGBT.

The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity

of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak

transient current from the power supply, which can result in sudden voltage drop of the power supply. With

hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal

switching transients.

The timing diagrams of the UVLO feature of VCC and VDD are shown in Figure 36, and Figure 37. The RDY pin

on the input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO

condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to

VCC to indicate the power good. The AIN-APWM function stops working during the UVLO status. The APWM pin

on the input side will be held LOW.

8.3.4 Active Pulldown

UCC21739-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the

VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature

can prevent the output be false turned on before the device is back to control.

VDD

OUTL

R_a

Control

Circuit

VEE

COM

Figure 40. Active Pulldown

8.3.5 Short Circuit Clamping

During short circuit condition, the miller capacitance can cause a current sinking to the OUTH/OUTL pin due to

the high dV/dt and boost the OUTH/OUTL voltage. The short circuit clamping feature of UCC21739-Q1 can

clamp the OUTH/OUTL pin voltage to be slightly higher than VDD, which can protect the power semiconductors

from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by an internal diode from

the OUTH/OUTL to VDD.

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Feature Description (continued)

VDD

D₁D₂

OUTH

OUTL

Control

Circuitry

Figure 41. Short Circuit Clamping

8.3.6 External Active Miller Clamp

Active miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In

applications which the device can be in synchronous rectifier mode, the body diode conducts the current during

the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same and

the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-down

impedance of UCC21739-Q1 can provide a strong pulldown to hold the OUTL to VEE. However, external gate

resistance is usually adopted to limit the dV/dt. The miller effect during the turn on transient of the other power

semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or gate-

emitter voltage. If the voltage on V_GSor V_GEis higher than the threshold voltage of the power semiconductor, a

shoot through can happen and cause catastrophic damage. The active miller clamp feature of UCC21739-Q1

drives an external MOSFET, which connects to the device gate. The external MOSFET is triggered when the

gate voltage is lower than V_CLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the false

turn on issue.

28

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Feature Description (continued)

V_CLMPTH

VCC

OUTH

+

3V to 5.5V

œ

CLMPE

OUTL

Control

Circuitry

IN+

µC

MOD

DEMOD

IN-

VEE

COM

VCC

Figure 42. Active Miller Clamp

8.3.7 Overcurrent and Short Circuit Protection

The UCC21739-Q1 implements a fast overcurrent and short circuit protection feature to protect the SiC MOSFET

or IGBT from catastrophic breakdown during fault. The OC pin of the device has a typical 0.7V threshold with

respect to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the

output is held in low state, the OC pin is pulled down by an internal MOSFET and held in LOW state, which

prevents the overcurrent and short circuit fault from false triggering. The OC pin is in high-impedance state when

the output is in high state, which means the overcurrent and short circuit protection feature only works when the

power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the voltage of OC pin

when the power semiconductor is turned off.

The overcurrent and short circuit protection feature can be used to SiC MOSFET module or IGBT module with

SenseFET, traditional desaturation circuit and shunt resistor in series with the power loop for lower power

applications. For SiC MOSFET module or IGBT module with SenseFET, the SenseFET integrated in the module

can scale down the drain current or collector current. With an external high precision sense resistor, the drain

current or collector current can be accurately measured. If the voltage of the sensed resistor higher than the

overcurrent threshold V_OCTHis detected, the 2-Level turn-off is initiated. A fault will be reported to the input side

FLT pin to DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN

pin. The state-of-art overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC

MOSFET and IGBT.

The overcurrent and short circuit protection feature can also be paired with desaturation circuit and shunt

resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device.

Detailed application diagrams of desaturation circuit and shunt resistor will be given in Overcurrent and Short

Circuit Protection.

•

High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on shunt

resistor’s parasitic inductance and board layout parasitic, which results in false trigger of OC pin. High

precision, low ESL and small value resistor must be used in this approach.

•

Shunt resistor approach is not recommended for high power applications and short circuit protection of the

low power applications.

The detailed applications of the overcurrent and short circuit feature will be discussed in the Application and

Implementation section.

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Feature Description (continued)

OUTL

R_OFF

OC

R_FLT

+

FLT

DEMOD

MOD

+

V_OCTH

R_S

C_FLT

œ

Control

Logic

GND

COM

VEE

Figure 43. Overcurrent and Short Circuit Protection

8.3.8 2-Level Turn-off

UCC21739-Q1 initiates a fast 2-level turn-off when the overcurrent and short circuit protection is triggered. When

the overcurrent and short circuit fault happens, the power power semiconductor transits from the linear region to

the saturation region very fast. The channel current is controlled by the gate voltage. By pulling down the gate

voltage to a mid-voltage level V2LOFF and stay for a fixed time t2LOFF, the channel current can be limited to a

much lower level, which significantly reduces the energy dissipation during the fault event. After t2LOFF, the

driver continues to pull down the gate voltage by the soft turn off current ITL3 until it reaches VEE. With dI/dt of

the channel current is controlled by the gate voltage and decreasing in a soft manner, thus the overshoot of the

power semiconductor is limited and prevents the overvoltage breakdown. The timing diagram of 2-level turn-off

shows in Figure 38.

OUTL

2-Level

Turn Off

R_OFF

OC

R_FLT

+

FLT

DEMOD

MOD

+

V_OCTH

R_S

C_FLT

œ

Control

Logic

GND

COM

VEE

Figure 44. 2-Level Turn-off

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Feature Description (continued)

8.3.9 Fault (FLT, Reset and Enable (RST/EN)

The FLT pin of UCC21739-Q1 is open drain and can report a fault signal to the DSP/MCU when the overcurrent

and short circuit fault is detected through OC pin. The FLT pin is pulled down to GND, and is held in low state

unless a reset signal is received from RST/EN. The device has a fault mute time t_FLTMUTE, within which the device

ignores any reset signal.

The RST/EN is pulled down internally. The device is disabled by default if the RST/EN pin is floating. The pin has

two purposes:

•

Resets the overcurrent and short circuit fault signaled on FLT pin. The RST/EN pin is active low, if the pin is

set and held in low state for more than t_RSTFIL, the fault signal is reset andFLT is reset back to the high

impedance status at the rising edge of RST/EN pin.

•

Enable and shutdown the device. If the RST/EN pin is pulled low, the driver is disabled and shut down by the

regular turn off. The pin must be pulled up externally to enable the part, otherwise the device is disabled by

default.

8.3.10 Isolated Analog to PWM Signal Function

The UCC21739-Q1 features an isolated analog to PWM signal function from AIN to APWM pin, which allows the

isolated temperature sensing, high voltage dc bus voltage sensing, etc. An internal current source I_AINin AIN pin

is implemented in the device to bias an external thermal diode or temperature sensing resistor. The UCC21739-

Q1 encodes the voltage signal V_AINto a PWM signal, passing through the isolation barrier, and output to APWM

pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate the duty cycle,

or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6V to 4.5V, and the

corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle increases linearly from

10% to 88% while the AIN voltage decreases from 4.5V to 0.6V. This corresponds to the temperature coefficient

of the negative temperature coefficient (NTC) resistor and thermal diode. When AIN is floating, the AIN voltage is

5V and the APWM operates at 400kHz with approximately 10% duty cycle. The accuracy of the duty cycle is

±5% across temperature without one time calibration. The accuracy can be improved to ±2% with calibration.

The accuracy of the internal current source I_AINis 3% across temperature.

The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high

voltage dc bus voltage, etc. The internal current source I_AINshould be taken into account when designing the

potential divider if sensing a high voltage.

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

Figure 45. Isolated Analog to PWM Signal

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8.4 Device Functional Modes

lists the device function.

Table 2. Function Table

Input

Output

OUTH/

OUTL

VCC

VDD

VEE

IN+

IN-

RST/EN

AIN

RDY

FLT

CLMPE

APWM

PU

PD

PU

PD

PU

X

Low

HiZ

Low

HiZ

Low

HiZ

Low

High

HiZ

Low

HiZ

Low

P^*

PU

X

Low

X

Open

PU

X

Open

PU

X

Low

High

PU

Low

X

High

PU

High

P^*

PU

High

PU: Power Up (VCC ≥ 2.85V, VDD ≥ 13.1V, VEE ≤ 0V); PD: Power Down (VCC ≤ 2.35V, VDD ≤ 9.9V); X:

Irrelevant; P^*: PWM Pulse; HiZ: High Impedance

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9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC21739-Q1 device is very versatile because of the strong drive strength, wide range of output power

supply, high isolation ratings, high CMTI and superior protection and sensing features. The device is suitable in

>10kW power applications such as the traction inverter in HEV/EV, on-board charger and charging pile, motor

driver, solar inverter, industrial power supplies and etc. The device can drive the high power SiC MOSFET

module, IGBT module or paralleled discrete device directly without traditional buffer drive circuit based on

NPN/PNP bipolar transistor in totem-pole structure, which allows the driver to have more control to the power

semiconductor and saves the cost and space of the board design. The input side can support 3V, 3.3V, 5V

power supply and microcontroller signal, and the device level shifts the signal to output side through isolation

barrier. The device has wide output power supply range from 13V to 33V and support wide range of negative

power supply. This allows the driver to be used in 20V and -5V SiC MOSFET applications, 15V and -15V IGBT

application and many others. The 12V UVLO benefits the power semiconductor with lower conduction loss and

improves the system efficiency. As a basic isolated single channel driver, the device can be used to drive either

as a low-side or high-side driver.

UCC21739-Q1 device features extensive protection and monitoring features, which can monitor, report and

protect the system from various fault conditions.

•

Fast detection and protection for the overcurrent and short circuit fault. The feature is preferable in a split

source SiC MOSFET module or a split emitter IGBT module. For the modules with no integrated current

mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement

short circuit protection. The semiconductor is shutdown when the fault is detected and FLTb pin is pulled

down to indicate the fault detection. The device is latched unless reset signal is received from the RST/EN

pin.

•

2-level turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent

and short circuit fault. The shutdown energy can be controlled while the overshoot of the power

semiconductor is limited.

UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to

be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is

back to normal operation mode once the power supply is out of the UVLO status. The power good status can

be monitored from the RDY pin.

•

Analog signal seensing with isolated analog to PWM signal feature. This feature allows the device to sense

the temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus

voltage with resistor divider. A PWM signal is generated on the low voltage side with isolated from the high

voltage side. The signal can be fed back to the microcontroller for the temperature monitoring, voltage

monitoring and etc.

The active miller clamp feature protects the power semiconductor from false turn on by driving an external

MOSFET. This feature allows the flexibility of the board layout design and the pulldown strength of miller

clamp FET.

•

Enable and disable function through the RSTb/EN pin.

Short circuit clamping.

Active pulldown.

9.2 Typical Application

shows the typical application of a half bridge using two UCC21739-Q1 isolated gate drivers. The half bridge is a

basic element in various power electronics applications such as traction inverter in HEV/EV to convert the DC

current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion system. The

topology can also be used in motor drive applications to control the operating speed and torque of the AC

motors.

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Typical Application (continued)

UCC

21739-Q1

1

2

3

4

5

6

PWM

3-Phase

Input

µC

1

2

3

4

5

6

M

APWM

FLT

UCC

21739-Q1

Figure 46. Typical Application Schematic

9.2.1 Design Requirements

The design of the power system for end equipment should consider some design requirements to ensure the

reliable operation of UCC1732-Q1 through the load range. The design considerations include the peak source

and sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog signal

sensing and etc.

A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show

in Table 3.

Table 3. Design Parameters

Parameter

Input Supply Voltage

IN-OUT Configuration

Positive Output Voltage VDD

Negative Output Voltage VEE

DC Bus Voltage

Value

5V

Non-inverting

15V

-5V

800V

Peak Drain Current

Switching Frequency

Switch Type

300A

50kHz

IGBT Module

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9.2.2 Detailed Design Procedure

9.2.2.1 Input filters for IN+, IN- and RST/EN

In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With

the strong drive strength of UCC21739-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise can not

only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal

PCB layout and coupled capacitance.

UCC21739-Q1 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can

be filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input

pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and

increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be

tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is

to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter

resistors and capacitors, both the noise immunity effect and delay time should be considered according to the

system requirements.

9.2.2.2 PWM Interlock of IN+ and IN-

UCC21739-Q1 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg

shoot through issue. As shown in , the output is logic low while both IN+ and IN- are logic high. When only IN+ is

used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the

phase leg can be sent to the IN- pin. As shown in , the PWM_T is the PWM signal to top side switch, the

PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to the

IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is

given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are

high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

IN+

IN-

R_ON

OUTH

OUTL

R_OFF

PWM_T

PWM_B

R_ON

IN+

IN-

OUTH

OUTL

R_OFF

Figure 47. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩ internal pulldown resistor, so the driver

is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for

the FLT, RDY and RST/EN pins.

To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be

added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to

300pF can be added.

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3.3V to 5V

0.1µF

VCC

15

9

1µF

GND

IN+

10

INt

11

5kQ

5kQ 5kQ

FLT

12

13

100pF

RDY

100pF

RST/EN

14

16

100pF

APWM

Figure 48. FLT, RDY and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

RST/EN pin has two functions. It can be used to enable and shutdown the outputs of the driver, and reset the

fault signaled on the FLT pin. RST/EN pin needs to be pulled up to enable the device; when the pin is pulled

down, the device is in disabled status. With a 50kΩ pulldown resistor existing, the driver is disabled by default.

When the driver is latched after overcurrent or short circuit fault is detected, the FLT pin and output are latched

low and need to be reset byRST/EN pin. RST/EN pin is active low. The microcntroller needs to send a signal to

RST/EN pin after the fault mute time t_FLTMUTEto reset the driver. This pin can also be used to automatically reset

the driver. The continuous input signal IN+ or IN- can be applied to RST/EN pin, so the microcontroller does not

need to generate another control signal to reset the driver. If non-inverting input IN+ is used, then IN+ can be tied

to RST/EN pin. If inverting input IN- is used, then a NOT logic is needed between the inverting PWM signal from

the microcontroller and the RST/EN pin. In this case, the driver can be reset in every switching cycle without an

extra control signal from microcontroller to RST/EN pin.

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3.3V to 5V

0.1µF

3.3V to 5V

0.1µF

VCC

15

1µF

GND

IN+

GND

9

IN+

10

INt

5kQ

11

5kQ

11

5kQ

FLT

12

13

12

13

100pF

RDY

RST/EN

APWM

RST/EN

14

16

APWM

16

Figure 49. Automatic Reset Control

9.2.2.5 Turn on and turn off gate resistors

UCC21739-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn on and

turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which

controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to

ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

I_{sink _ pk}= min(10A,

)

VDD - VEE

R_OL+R_OFF+R_{G _Int}

)

(1)

Where

•

R_{OH_EFF}is the effective internal pull up resistance of the hybrid pull-up structure, shown in Figure 39, which is

approximately 2 x R_OL, about 0.7 Ω. This is the dominant resistance during the switching transient of the pull

up structure.

•

R_OLis the internal pulldown resistance, about 0.3 Ω

R_ONis the external turn on gate resistance

R_OFFis the external turn off gate resistance

R_{G_Int}is the internal resistance of the SiC MOSFET or IGBT module

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VDD

C_ies=C_gc+C_ge

+

VDD

C_gc

R_{OH_EFF}

t

OUTH

OUTL

R_ON

R_{G_Int}

R_OFF

C_ge

+

VEE

R_OL

t

VEE

COM

Figure 50. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

•

Q_g= 3300 nC

R_{G_Int}= 1.7 Ω

R_ON=R_OFF= 1 Ω

The peak source and sink current in this case are:

VDD - VEE

I_{source _ pk}= min(10A,

) ö 5.9A

R_{OH_EFF}+R_ON+R_{G _Int}

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

) ö 6.7A

(2)

Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The

collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller

plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless

the turn on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the

turn on switching loss is. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn off switching transient, the

drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After V_ce

reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled

by V_ge. The peak sink current determines the dI/dt, which dominates the V_cevoltage overshoot accordingly. If

using relatively large turn off gate resistance, the V_ceovershoot can be limited. The overshoot can be estimated

by:

DV = L_stray∂I_load/ ((R_OFF+R_OL+R_{G_Int})∂C_ies∂ln(V_plat/ V ))

ce

th

(3)

Where

•

L_strayis the stray inductance in power switching loop, as shown in Figure 51

I_loadis the load current, which is the turn off current of the power semiconductor

C_iesis the input capacitance of the power semiconductor

V_platis the plateau voltage of the power semiconductor

V_this the threshold voltage of the power semiconductor

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L_DC

L_c1

L_stray=L_DC+L_e1+L_c1+L_e1+L_c1

R_G

L_load

t

+

L_e1

+

VDC

t

L_c2

VDD

C_gc

C_ies=C_gc+C_ge

R_G

OUTH

OUTL

COM

C_ge

L_e2

Figure 51. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The

power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

P = P_Q+P

DR

SW

(4)

P_Qis the quiescent power loss for the driver, which is I_qx (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent

power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic

circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the

charging and discharing current of the internal circuit when the driver is switching. The power dissipation when

the driver is switching can be calculated as:

R_{OH_EFF}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g

SW

2 R_{OH_EFF}+R_ON+R_{G _Int}R_OL+R_OFF+R_{G _Int}

(5)

Where

•

Q_gis the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD

f_swis the switching frequency

In this example, the P_SWcan be calculated as:

R_{OH_EFF}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g= 0.505W

SW

2 R_{OH_EFF}+ R_ON+ R_{G _Int}R_OL+R_OFF+R_{G _Int}

(6)

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Thus, the total power loss is:

P =P +P = 0.10W +0.505W = 0.605W

DR

Q

SW

(7)

(8)

When the board temperature is 125°C, the junction temperature can be estimated as:

T_j= T + y_jb∂P ö 150^oC

b

DR

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency

is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing

external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 External Active Miller Clamp

External active miller clamp feature allows the gate driver to stay at the low status when the gate voltage is

detected below V_CLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through

the parasitic miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative

voltage drop on the turn off gate resistance, and bumps up the gate voltage to cause a false turn on. The

external active miller clamp features allows flexibility of board layout and active miller clamp pulldown strength.

Limited by the board layout, if the driver cannot be placed close enough to the switch, external active miller

clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak

current needed. Caution must be exercised when the driver is place far from the power semiconductor. Since the

device has high peak sink and source current, the high dI/dt in the gate loop can cause a ground bounce on the

board parasitics. The ground bounce can cause a positive voltage bump on CLMPE pin during the turn off

transient, and results in the external active miller clamp MOSFET to turn on shortly and add extra drive strength

to the sink current. To reduce the ground bounce, a 2Ω resistance is recommended to the gate of the external

active clamp MOSFET.

When the V_OUTHis detected to be lower than V_CLMPTHabove VEE, the CLMPE pin outputs a 5V voltage with

respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak

drain current, unless the on-resistance of the external clamp FET is large.

V_DS

I_{CLMPE _PK}= min(I_{D _PK}

,

)

R_{DS _ ON}

(9)

Where

•

I_{D_PK}is the peak drain current of the external clamp FET

V_DSis the drain-to-source voltage of the clamp FET when the CLMPE is activated

R_{DS_ON}is the on-resistance of the external clamp FET

The total delay time of the active miller clamp circuit from the gate voltage detection threshold V_CLMPTHcan be

calculated as t_DCLMPE+t_CLMPER. t_CLMPERdepends on the parameter of the external active miller clamp MOSFET.

As long as the total delay time is longer than the deadtime of high side and low side switches, the driver can

effectively protect the switch from false turn on issue caused by miller effect.

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V_CLMPTH

VCC

OUTH

+

3V to 5.5V

IN+

œ

CLMPE

OUTL

Control

Circuitry

µC

MOD

DEMOD

IN-

VEE

COM

VCC

Figure 52. External Active Miller Clamp Configuration

9.2.2.7 Overcurrent and Short Circuit Protection

Fast and reliable overcurrent and short circuit protection is important to protect the catastrophic break down of

the SiC MOSFET and IGBT modules, and improve the system reliability. The UCC21739-Q1 features a state-of-

art overcurrent and short circuit protection, which can be applied to both SiC MOSFET and IGBT modules with

various detection circuits.

9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET

The overcurrent and short circuit protection function is suitable for the SiC MOSFET and IGBT modules with

integrated SenseFET. The SenseFET scales down the main power loop current and outputs the current with a

dedicated pin of the power module. With external high precision sensing resistor, the scaled down current can be

measured and the main power loop current can be calculated. The value of the sensing resistor R_Ssets the

protection threshold of the main current. For example, with a ratio of 1:N = 1:50000 of the integrated current

mirror, by using the R_Sas 20Ω, the threshold protection current is:

V_OCTH

I_{OC _ TH}

=

∂N = 1750A

R_S

(10)

The overcurrent and short circuit protection based on integrated SenseFET has high precision, as it is sensing

the current directly. The accuracy of the method is related to two factors: the scaling down ratio of the main

power loop current and the SenseFET, and the precision of the sensing resistor. Since the current is sensed

from the SenseFET, which is isolated from the main power loop, and the current is scaled down significantly with

much less dI/dt, the sensing loop has good noise immunity. To further improve the noise immunity, a low pass

filter can be added. A 100pF to 10nF filter capacitor can be added. The delay time caused by the low pass filter

should also be considered for the protection circuitry design.

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OUTL

R_OFF

SenseFET

Kelvin

Connection

OC

+

FLT

DEMOD

MOD

R_FLT

+

V_OCTH

œ

R_S

C_FLT

Control

Logic

GND

COM

VEE

Figure 53. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET

9.2.2.7.2 Protection Based on Desaturation Circuit

For SiC MOSFET and IGBT modules without SenseFET, desaturation (DESAT) circuit is the most popular circuit

which is adopted for overcurrent and short circuit protection. The circuit consists of a current source, a resistor, a

blanking capacitor and a diode. Normally the current source is provided from the gate driver, when the device

turns on, a current source charges the blanking capacitor and the diode forward biased. During normal operation,

the capacitor voltage is clamped by the switch V_CEvoltage. When short circuit happens, the capacitor voltage is

quickly charged to the threshold voltage which triggers the device shutdown. For the UCC21739-Q1, the OC pin

does not feature an internal current source. The current source should be generated externally from the output

power supply. When UCC21739-Q1 is in OFF state, the OC pin is pulled down by an internal MOSFET, which

creates an offset voltage on OC pin. By choosing R1 and R2 significantly higher than the pulldown resistance of

the internal MOSFET, the offset can be ignored. When UCC21739-Q1 is in ON state, the OC pin is high

impedance. The current source is generated by the output power supply VDD and the external resistor divider

R1, R2 and R3. The overcurrent detection threshold voltage of the IGBT is:

R₂+ R₃

R₃

V_DET=V_OCTH

∂

-V_F

(11)

(12)

The blanking time of the detection circuit is:

R₁+ R₂

R₁+ R₂+ R₃

R₁+ R₂+ R₃V_OCTH

t_BLK= -

∂R₃∂C_BLK∂ln(1-

∂

)

R₃

V_DD

Where:

•

V_OCTHis the detection threshold voltage of the gate driver

R₁, R₂and R₃are the resistance of the voltage divider

C_BLKis the blanking capacitor

V_Fis the forward voltage of the high voltage diode D_HV

The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has

negligible power loss, and is easy to implement. The detection threshold voltage of IGBT and blanking time can

be programmed by external components. Different with the conventional desaturation circuit, the overcurrent

detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the

detection threshold voltage of the driver. A parallel schottky diode can be connected between OC and COM pins

to prevent the negative voltage on the OC pin in noisy system. Since the desaturation circuit measures the V_CE

of the IGBT or V_DSof the SiC MOSFET, not directly the current, the accuracy of the protection is not as high as

the SenseFET based protection method. The current threshold cannot be accurately controlled in the protection.

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R_OFF

R_DESAT

D_HV

VDD

R₁

OC

R₂

+

FLT

DEMOD

MOD

+

V_OCTH

R₃

C_BLK

œ

Control

Logic

GND

COM

VEE

Figure 54. Overcurrent and Short Circuit Protection Based on Desaturation Circuit

9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop

In lower power applications, to simplify the circuit and reduce the cost, a shunt resistor can be used in series in

the power loop and measure the current directly. Since the resistor is in series in the power loop, it directly

measures the current and can have high accuracy by using a high precision resistor. The resistance needs to be

small to reduce the power loss, and should have large enough voltage resolution for the protection. Since the

sensing resistor is also in series in the gate driver loop, the voltage drop on the sensing resistor can cause the

voltage drop on the gate voltage of the IGBT or SiC MOSFET modules. The parasitic inductance of the sensing

resistor and the PCB trace of the sensing loop will also cause a noise voltage source during switching transient,

which makes the gate voltage oscillate. Thus, this method is not recommended for high power application, or

when dI/dt is high. To use it in low power application, the shunt resistor loop should be designed to have the

optimal voltage drop and minimum noise injection to the gate loop.

R_OFF

OC

R_FLT

+

FLT

DEMOD

MOD

+

V_OCTH

R_S

C_FLT

œ

Control

Logic

GND

COM

VEE

Figure 55. Overcurrent and Short Circuit Protection Based on Shunt Resistor

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9.2.2.8 Isolated Analog Signal Sensing

The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature

detection, voltage sensing and etc. One typical application of this function is the temperature monitor of the

power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or

IGBT module close to the dies to monitor the junction temperature. UCC21739-Q1 has an internal 200uA current

source with 3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage drop

on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation barrier

to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from 10% to

88% when the AIN voltage changes from 4.5V to 0.6V and can be represented using Equation 13.

D_APWM(%) = -20 * V_AIN+100

(13)

9.2.2.8.1 Isolated Temperature Sensing

A typical application circuit is shown in Figure 56. To sense temperature, the AIN pin is connected to the thermal

diode or thermistor which can be discrete or integrated within the power module. A low pass filter is

recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low pass filter

is mainly used for filtering the noise introduced by the switching of the power device, which does not require

stringent control for propagation delay. The filter capacitance for C_filtcan be chosen between 1nF to 100nF and

the filter resistance R_filtbetween 1Ω to 10Ω according to the noise level.

The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the

voltage input at AIN, using Equation 13.

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

Figure 56. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of UCC21739-Q1 the duty cycle

output of APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as

shown in Figure 57. The frequency of APWM is 400kHz, so the value for R_{filt_2}and C_{filt_2}should be such that the

cutoff frequency is below 400kHz. Temperature does not change rapidly, thus the rise time due to the RC

constant of the filter is not under a strict requirement.

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VDD

AIN

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

APWM

œ

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

Figure 57. APWM Channel with Filtered Output

The example below shows the results using a 4.7kΩ NTC, NTCS0805E3472FMT, in series with a 3kΩ resistor

and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4

MMBT3904 thermal diodes connected in series ranges from about 2.5V to 1.6V from 25°C to 135°C,

corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the

3kΩ resistor ranges from about 1.5V to 0.6V from 25°C to 135°C, corresponding to 70% to 88% duty cycle. The

voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in Figure 58.

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

90

84

78

72

66

60

54

Thermal Diode V_AIN

NTC V_AIN

Thermal Diode APWM

NTC APWM

48

20

40

60

80

Temperature (èC)

100

120

140

VAIN

Figure 58. Thermal diode and NTC V_AINand Corresponding Duty Cycle at APWM

The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in

Figure 59 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in

Figure 60.

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1.5

1.25

1

Thermal Diode APWM Duty Error

NTC APWM Duty Error

0.75

0.5

0.25

0

-0.25

20

40

60

80

Temperature (èC)

100

120

140

APWM

Figure 59. APWM Duty Error Without Calibration

0.8

0.6

0.4

0.2

0

Thermal Diode APWM Duty Error

NTC APWM Duty Error

-0.2

20

40

60

80

Temperature (èC)

100

120

140

APWM

Figure 60. APWM Duty Error with Single-Point Calibration

9.2.2.8.2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in

Figure 61. The same filtering requirements as given above may be used in this case, as well. The number of

attenuation resistors, R_{atten_1}through R_{atten_n}, is dependent on the voltage level and power rating of the resistor.

The voltage is finally measured across R_{LV_DC}to monitor the stepped-down voltage of the HV DC-link which must

fall within the voltage range of AIN from 0.6V to 4.5V. The driver should be referenced to the same point as the

measurement reference, thus in the case shown below the UCC21739-Q1 is driving the lower IGBT in the half-

bridge and the DC-link voltage measurement is referenced to COM. The internal current source I_AINshould be

taken into account when designing the resistor divider. The AIN pin voltage is:

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R_{LV _DC}

n

V_AIN

=

∂ V_DC+R_{LV _DC}∂I_AIN

R_{LV _DC}

+

R

atten _ i

ƒ

i=1

(14)

R_{atten_1}

R_{atten_2}

VDD

VCC

R_{atten_n}

13V to

33V

+

3V to 5.5V

APWM

œ

C_DC

+

AIN

DEMOD

MOD

µC

R_filt

C_filt

R_{filt_2}

C_{filt_2}

GND

R_{LV_DC}

OSC

COM

Figure 61. DC-link Voltage Sensing Configuration

9.2.2.9 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in

Figure 62) can be used. Inverting types are not compatible with the overcurrent and short circuit fault protection

circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the

D44VH10/ D45VH10 pair is up to 20 A peak.

In the case of a over-current detection, the 2-level turn-off is activated. External components must be added to

implement safe shutdown instead of normal turn off speed when an external buffer is used. C_STOsets the timing

for soft turn off and R_STOlimits the inrush current to below the current rating of the internal FET (10A). R_STO

should be at least (VDD-VEE)/10. The soft turn off timing is determined by the internal circuitry for 2-level turn-off

with soft turn-off current transitions and the capacitor C_STO. C_STOis calculated using Equation 15.

I_STO∂ t_STO

VDD

-

VEE

C_STO

=

(15)

•

I_STOis the the internal STO current source, 900mA

t_STOis the desired STO timing

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VDD

R_OH

C_ies=C_gc+C_ge

OUTH

OUTL

R_NMOS

C_gc

R_{G_2}

R_{G_1}

R_{G_Int}

C_ge

R_OL

C_STO

COM

VEE

R_STO

Figure 62. Current Buffer for Increased Drive Strength

9.2.3 Application Curves

Figure 63. PWM input (yellow) and driver output (blue)

Step Input (0.6 V to 4.5 V)

APWM Output

Figure 64. AIN step input (green) and APWM output (pink)

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10 Power Supply Recommendations

During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and

VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a

voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of

decoupling capacitors are recommended at the power supplies. Considering UCC21739-Q1 has ±10A peak drive

strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE and

COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with output

side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out high

frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and

should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system

parasitics of PCB layout.

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11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of UCC21739-Q1, careful considerations must be taken in PCB design. Below

are some key points:

•

The driver should be placed as close as possible to the power semiconductor to reduce the parasitic

inductance of the gate loop on the PCB traces

•

The decoupling capacitors of the input and output power supplies should be placed as close as possible to

the power supply pins. The peak current generated at each switching transient can cause high dI/dt and

voltage spike on the parasitic inductance of PCB traces

•

The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If

the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close

as possible to the source or emitter terminal of the power device package to separate the gate loop from the

high power switching loop

•

Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the

high frequency noise generated by the output side switching transients. The ground plane provides a low-

inductance filter for the return current flow

If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the

ground plane on the output side to shield the output signals from the noise generated by the switch node; if

the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground

plane is not recommended

•

If ground plane is not used on the output side, separate the return path of the OC and AIN ground loop from

the gate loop ground which has large peak source and sink current

No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise

coupling between the input and output side which can contaminate the isolation barrier

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11.2 Layout Example

Figure 65. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Isolation Glossary

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resource

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

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PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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IMPORTANT NOTICE AND DISCLAIMER

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21739QDWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 IGBT/SiC MOSFET 且具有隔离式模拟检测的汽车类 3kVrms ±10A 单通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 125 栅极驱动双极性晶体管驱动器
文件：	总59页 (文件大小：4230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21739QDWRQ1 [TI]

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