UCC21750-Q1_技术文档

UCC21750-Q1

ZHCSKA3C –SEPTEMBER 2019 –REVISED JANUARY 2023

UCC21750-Q1 适用于SiC/IGBT 并具有主动保护、隔离式模拟感应和高CMTI 的

10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

输入侧通过 SiO₂电容隔离技术与输出侧相隔离，支持

高达 1.5kV_RMS的工作电压、12.8kV_PK的浪涌抗扰

1 特性

• 5.7kV _RMS单通道隔离式栅极驱动器

• 符合面向汽车应用的AEC-Q100 标准

度，隔离层寿命超过 40 年，并提供较低的器件间偏

移，共模噪声抗扰度(CMTI) 大于150V/ns。

– 器件温度等级0：-40°C 至+150°C 环境工作温

度范围

UCC21750-Q1 包括先进的保护特性，如快速过流和短

路检测、分流电流检测支持、故障报告、有源米勒钳

位、输入和输出侧电源 UVLO（用于优化 SiC 和 IGBT

开关行为和稳健性）。可以利用隔离式模拟至PWM 传

感器更轻松地感测温度或电压，从而进一步提高驱动器

的多功能性并简化系统设计工作量、尺寸和成本。

– 器件HBM ESD 分类等级3A

– 器件CDM ESD 分类等级C6

• 高达2121V_pk的SiC MOSFET 和IGBT

• 33V 最大输出驱动电压(VDD –VEE)

• ±10A 驱动强度和分离输出

器件信息

封装⁽¹⁾

• 150V/ns 最小CMTI

• 具有200ns 快速响应时间的DESAT 保护

• 4A 内部有源米勒钳位

封装尺寸（标称值）

器件型号

UCC21750-Q1

DW SOIC-16

10.3mm × 7.5mm

• 发生故障时的400mA 软关断

• 具有PWM 输出的隔离式模拟传感器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 采用NTC、PTC 或热敏二极管的温度感应

– 高电压直流链路或相电压

器件引脚配置

• 过流警报FLT 和通过RST/EN 重置

• 针对RST/EN 的快速启用和禁用响应

• 抑制输入引脚上的<40ns 噪声瞬态和脉冲

• RDY 上的12V VDD UVLO（具有电源正常指示功

能）

• 具有高达5V 过冲/欠冲瞬态电压抗扰度的输入/输出

• 130 ns（最大）传播延迟和30 ns（最大）脉冲/器

件间偏移

APWM

VCC

RST/EN

FLT

AIN

DESAT

COM

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUTH

VDD

RDY

INÅ

• SOIC-16 DW 封装，爬电距离和间隙> 8mm

• 工作结温范围：-40°C 至+150°C

• 安全相关认证：

OUTL

CLMPI

VEE

IN+

GND

– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标

准的增强型绝缘

– UL 1577 组件认证计划

Not to scale

2 应用

• 适用于EV 的牵引逆变器

• 车载充电器和充电桩

• 用于HEV/EV 的直流/直流转换器

3 说明

UCC21750-Q1 是一款电隔离单通道栅极驱动器，设计

用于直流工作电压高达 2121V 的 SiC MOSFET 和

IGBT，具有先进的保护功能、出色的动态性能和稳健

性。UCC21750-Q1 具有高达 ±10A 的峰值拉电流和灌

电流。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDH9

UCC21750-Q1

ZHCSKA3C –SEPTEMBER 2019 –REVISED JANUARY 2023

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Table of Contents

7.5 Desaturation (DESAT) Protection............................. 21

8 Detailed Description......................................................23

8.1 Overview...................................................................23

8.2 Functional Block Diagram.........................................24

8.3 Feature Description...................................................24

8.4 Device Functional Modes..........................................30

9 Applications and Implementation................................31

9.1 Application Information............................................. 31

9.2 Typical Application.................................................... 31

10 Power Supply Recommendations..............................43

11 Layout...........................................................................44

11.1 Layout Guidelines................................................... 44

11.2 Layout Example...................................................... 45

12 Device and Documentation Support..........................46

12.1 Device Support....................................................... 46

12.2 Documentation Support.......................................... 46

12.3 接收文档更新通知................................................... 46

12.4 支持资源..................................................................46

12.5 Trademarks.............................................................46

12.6 静电放电警告.......................................................... 46

12.7 术语表..................................................................... 46

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 5

6.7 Safety Limiting Values.................................................6

6.8 Electrical Characteristics.............................................6

6.9 Safety-Related Certifications...................................... 8

6.10 Switching Characteristics..........................................9

6.11 Insulation Characteristics Curves............................10

6.12 Typical Characteristics............................................ 11

7 Parameter Measurement Information..........................16

7.1 Propagation Delay.................................................... 16

7.2 Input Deglitch Filter...................................................17

7.3 Active Miller Clamp................................................... 18

7.4 Undervoltage Lockout (UVLO)..................................19

Information.................................................................... 46

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (March 2020) to Revision C (January 2023)

Page

• 向特性中添加了AEC-Q100 子项目符号............................................................................................................. 1

• 向特性中添加了安全相关认证.............................................................................................................................1

• Added what to do with unused pins to pin functions table..................................................................................3

• Changed recommended value of decoupling capacitors. ..................................................................................3

• Added recommended decoupling capacitor layout placement. ......................................................................... 3

• Changed test conditions per DIN EN IEC 60747-17 (VDE 0884-17) .................................................................5

• Changed Ichg lower limit to 430uA.....................................................................................................................6

• Changed VAin lower limit to 0.6V........................................................................................................................6

• Changed direction of I_CLMPIin V_CLP-CLMPItest condition.....................................................................................6

• Added test condition for soft turn-off current.......................................................................................................6

• Deleted short circuit clamping max condition..................................................................................................... 6

• Changed VDE and UL to certified.......................................................................................................................8

• Changed DESAT figure.....................................................................................................................................28

• Changed DESAT soft turn-off figure................................................................................................................. 28

• Added function state showing gate driver turning on. Changed RDY condition when VCC is PD. ................. 30

Changes from Revision A (March 2020) to Revision B (March 2020)

Page

• Deleted test voltage, 9600V, from value column.................................................................................................5

Changes from Revision * (September 2019) to Revision A (March 2020)

Page

• 将销售状态从“预告信息”更改为“量产数据”。.............................................................................................1

2

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5 Pin Configuration and Functions

APWM

16

AIN

DESAT

COM

1

2

3

4

5

6

7

8

15

14

13

12

11

10

9

VCC

RST/EN

FLT

OUTH

VDD

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

Not to scale

图5-1. UCC21750-Q1 DW SOIC (16) Top View

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if

unused.

AIN

1

I

DESAT

COM

2

3

4

I

Desaturation current protection input. Tie to COM if unused.

Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET.

Gate driver output pull up.

P

O

OUTH

Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate

driver source peak current capability. Place decoupling capacitor close to the pin.

VDD

5

6

7

P

O

I

OUTL

CLMPI

Gate driver output pull down.

Internal Active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or

tie to VEE if unused.

Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified

gate driver sink peak current capability. Place decoupling capacitor close to the pin.

VEE

8

P

GND

IN+

9

P

I

Input power supply and logic ground reference.

10

11

Non-inverting gate driver control input. Tie to VCC if unused.

Inverting gate driver control input. Tie to GND if unused.

I

IN–

Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other

RDY signals.

RDY

FLT

12

13

O

Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be

paralleled with other faults.

The RST/EN serves two purposes:

1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to

low;

RST/EN

14

I

2) Resets the DESAT condition signaled on FLT pin if terminal RST/EN is set to low for more than 1000 ns.

A reset of signal FLT is asserted at the rising edge of terminal RST/EN.

For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The

FET is turned off by a regular turn-off, if terminal EN is set to low.

Input power supply from 3 V to 5.5 V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor

close to the pin.

VCC

15

16

P

APWM

O

Isolated Analog Sensing PWM output. Leave floating if unused.

(1) P = Power, G = Ground, I = Input, O = Output

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

MAX

6

UNIT

V

VCC

VDD

VEE

V_MAX

VCC –GND

VDD –COM

VEE –COM

VDD –VEE

36

V

–0.3

0.3

V

–17.5

36

V

–0.3

DC

VCC

VCC+5.0

VDD+0.3

5

V

GND–0.3

GND–5.0

COM–0.3

–0.3

IN+, IN–, RST/EN

Transient, less than 100 ns⁽²⁾

V

Reference to COM

DESAT

AIN

V

DC

VDD

VDD+5.0

VCC

20

V

VEE–0.3

VEE–5.0

GND–0.3

OUTH, OUTL , CLMPI

Transient, less than 100 ns⁽²⁾

V

RDY, FLT, APWM

V

I_FLT, I_RDY

I_APWM

T_J

FLT, and RDY pin input current

APWM pin output current

mA

°C

20

Junction temperature range

Storage temperature range

150

–40

–65

T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

PARAMETER

MIN

3.0

13

MAX

5.5

UNIT

VCC

VDD

V_MAX

V

VCC–GND

VDD–COM

VDD–VEE

33

–

0.7×VCC

0

High level input voltage

Low level input voltage

VCC

0.3×VCC

4.5

Reference to GND

V

IN+, IN–, RST/EN

AIN

t_RST/EN

T_A

Reference to COM

0.6

V

Minimum pulse width that reset the fault

Ambient temperature

800

ns

°C

125

150

–40

T_J

Junction temperature

4

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6.4 Thermal Information

UCC21750-Q1

THERMAL METRIC⁽¹⁾

DW (SOIC)

16 PINS

68.3

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

27.5

32.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

14.1

32.3

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

Value

UNIT

P_D

Maximum power dissipation (both sides)

985

mW

Maximum power dissipation by

transmitter side

P_D1

20

mW

VCC = 5 V, VDD–COM = 20 V, COM–VEE = 5 V, IN+/–= 5 V,

150 kHz, 50% Duty Cycle for a 10-nF load, T_a= 25^oC

Maximum power dissipation by receiver

side

P_D2

965

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

Minimum internal gap (Internal clearance) of the

double insulation (2 × 0.0085 mm)

DTI

CTI

Distance through the insulation

> 17

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664–1

> 600

I

I-IV

I-III

Rated mains voltage ≤300 V_RMS

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage Category per IEC 60664–1

DIN EN IEC 60747-17 (VDE 0884-17)⁽²⁾

V_IORMMaximum repetitive peak isolation voltage AC voltage (bipolar)

2121

1500

V_PK

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test

V_RMS

V_IOWM

Maximum isolation working voltage

DC voltage

2121

8000

V_DC

V_PK

V_IMP

Maximum impulse voltage

Tested in air, 1.2/50-μs waveform per IEC 62368-1

V_TEST=V_IOTM, t = 60 s (qualification test)

V_TEST=1.2 x V_IOTM, t = 1 s (100% production test)

Test method per IEC 62368-1, 1.2/50 µs waveform

V_IOTM

V_IOSM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

8000

V_PK

12800

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UNIT

6.6 Insulation Specifications (continued)

PARAMETER

TEST CONDITIONS

VALUE

Method a: After I/O safety test subgroup 2/3, V_ini

=

V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM= 2545 V_PK

t_m= 10 s

,

≤5

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 × V_IORM= 3394

V_PK, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

pC

≤5

Method b1: At routine test (100% production) and

preconditioning (type test) V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1 s

≤5

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

~ 1

pF

V_IO= 0.5 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

≥10¹²

≥10¹¹

≥10⁹

2

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Ω

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification);

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

R

_θJA= 68.3°C/W, V_DD= 15 V, V_EE= –5 V, T_J= 150°C,

61

T_A= 25°C

Safety input, output, or supply

current

I_S

mA

49

R

_θJA= 68.3°C/W, V_DD= 20 V, V_EE= –5 V, T_J= 150°C,

T_A= 25°C

R

_θJA= 68.3°C/W, V_DD= 20 V, V_EE= –5 V, T_J= 150°C,

P_S

T_S

Safety input, output, or total power

Safety temperature

1220

150

mW

°C

T_A= 25°C

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-

air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-

to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount

packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient

temperature plus the power times the junction-to-air thermal resistance.

6.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD –COM = 20 V, 18 V or 15 V, COM –VEE = 0 V, 5 V, 8 V or

15 V, C_L= 100 pF, –40°C < T_J< 150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VCC UVLO THRESHOLD AND DELAY

6

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6.8 Electrical Characteristics (continued)

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD –COM = 20 V, 18 V or 15 V, COM –VEE = 0 V, 5 V, 8 V or

15 V, C_L= 100 pF, –40°C < T_J< 150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

2.55

2.35

TYP

2.7

2.5

0.2

10

MAX UNIT

V_{VCC_ON}

2.85

V_{VCC_OFF}

V_{VCC_HYS}

t_VCCFIL

2.65

V

VCC–GND

VCC UVLO Deglitch time

t_{VCC+ to OUT}

t_{VCC–to OUT}

t_{VCC+ to RDY}

t_{VCC–to RDY}

VCC UVLO on delay to output high

VCC UVLO off delay to output low

VCC UVLO on delay to RDY high

VCC UVLO off delay to RDY low

28

5

37.8

10

50

15

50

15

IN+ = VCC, IN–= GND

µs

30

5

37.8

10

RST/EN = VCC

VDD UVLO THRESHOLD AND DELAY

V_{VDD_ON}

10.5

9.9

12.0

10.7

0.8

5

12.8

11.8

V_{VDD_OFF}

V_{VDD_HYS}

t_VDDFIL

V

VDD–COM

VDD UVLO Deglitch time

t_{VDD+ to OUT}

t_{VDD–to OUT}

t_{VDD+ to RDY}

t_{VDD–to RDY}

VDD UVLO on delay to output high

VDD UVLO off delay to output low

VDD UVLO on delay to RDY high

VDD UVLO off delay to RDY low

2

5

8

10

15

IN+ = VCC, IN–= GND

5

µs

10

RST/EN = FLT=High

VCC, VDD QUIESCENT CURRENT

OUT(H) = High, f_S= 0Hz, AIN = 2 V

OUT(L) = Low, f_S= 0Hz, AIN = 2 V

OUT(H) = High, f_S= 0Hz, AIN = 2 V

OUT(L) = Low, f_S= 0Hz, AIN = 2 V

2.5

1.45

3.6

3

2

4

2.75

5.9

I_VCCQVCC quiescent current

mA

4

I_VDDQ

VDD quiescent current

3.1

3.7

5.3

LOGIC INPUTS —IN+, IN–and RST/EN

V_INH

V_INL

V_INHYS

I_IH

Input high threshold

V_CC= 3.3 V

1.85

1.52

0.33

90

2.31

V

Input low threshold

V_CC= 3.3 V

0.99

Input threshold hysteresis

Input high level input leakage current

Input low level input leakage

Input pins pull down resistance

Input pins pull up resistance

V_CC= 3.3 V

V

V_IN= VCC

µA

I_IL

V_IN= GND

–90

55

R_IND

R_INU

see Detailed Description for more information

kΩ

55

IN+, IN–and RST/EN deglitch (ON and

OFF) filter time

T_INFIL

f_S= 50 kHz

28

40

60

ns

T_RSTFIL

Deglitch filter time to reset /FLT

400

650

800

GATE DRIVER STAGE

I_OUT, I_OUTHPeak source current

I_OUT, I_OUTL

10

A

C_L= 0.18 µF, f_S= 1 kHz

Peak sink current

(3)

R_OUTH

Output pull-up resistance

Output pull-down resistance

High level output voltage

Low level output voltage

2.5

0.3

17.5

60

I_OUT= –0.1 A

Ω

R_OUTL

V_OUTH

V_OUTL

I_OUT= 0.1 A

V

I_OUT= –0.2 A, V_DD= 18 V

I_OUT= 0.2 A

mV

ACTIVE PULLDOWN

I_OUTLor I_OUT= 0.1 × I_OUT(L)(tpy), VDD=OPEN,

VEE=COM

V_OUTPD

Output active pull down on OUT, OUTL

1.5

2

2.5

V

INTERNAL ACTIVE MILLER CLAMP

V_CLMPTH

V_CLMPI

I_CLMPI

Miller clamp threshold voltage

Reference to VEE

I_CLMPI= 1 A

2.0

V

A

Output low clamp voltage

Output low clamp current

VEE + 0.5

4

V_CLMPI= 0 V, VEE = –2.5 V

I_CLMPI= 0.2 A

R_CLMPI

Miller clamp pull down resistance

0.6

Ω

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6.8 Electrical Characteristics (continued)

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD –COM = 20 V, 18 V or 15 V, COM –VEE = 0 V, 5 V, 8 V or

15 V, C_L= 100 pF, –40°C < T_J< 150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_DCLMPI

Miller clamp ON delay time

C_L= 1.8 nF

15

50

ns

SHORT CIRCUIT CLAMPING

V_CLP-OUT(H)

V_CLP-OUT(L)

V_CLP-CLMPI

OUT = Low, I_OUT(H)= 500 mA, t_CLP=1 0 us

OUT = High, I_OUT(L)= 500 mA, t_CLP= 10 us

OUT = High, I_CLMPI= 20 mA, t_CLP= 10 us

0.9

1.8

1.0

V

V_OUT–VDD, V_OUTH–VDD

V_OUT–VDD, V_OUTL–VDD

V_CLMPI–VDD

DESAT PROTECTION

I_CHG

Blanking capacitor charge current

V_DESAT= 2.0 V

V_DESAT= 6.0 V

430

10

500

15

570

9.8

µA

mA

V

I_DCHG

Blanking capacitor discharge current

Detection Threshold

V_DESAT

t_DESATLEB

t_DESATFIL

t_DESATOFF

t_DESATFLT

8.5

9.15

200

140

200

580

Leading edge blank time

ns

DESAT deglitch filter

50

150

400

230

300

750

DESAT propagation delay to OUT(L) 90%

DESAT to FLT low delay

INTERNAL SOFT TURN-OFF

I_STOSoft turn-off current on fault conditions

V_DD-V_EE=20V, V_OUTL-COM=8V

250

400

570

mA

ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)

V_AIN

Analog sensing voltage range

Internal current source

0.6

196

380

4.5

209

420

V

I_AIN

V_AIN= 2.5 V, -40°C < T_J< 150°C

V_AIN= 2.5 V

200

400

10

µA

f_APWM

BW_AIN

APWM output frequency

AIN–APWM bandwidth

kHz

V_AIN= 0.6 V

V_AIN= 2.5 V

V_AIN= 4.5 V

86.5

48.5

7.5

88

89.5

51.5

11.5

D_APWM

APWM Dutycycle

50

%

10

FLT AND RDY REPORTING

t_RDYHLD

t_FLTMUTE

R_ODON

V_ODL

VDD UVLO RDY low minimum holding time

0.55

1

ms

Output mute time on fault

Reset fault through RST/EN

I_ODON= 5 mA

Open drain output on resistance

Open drain low output voltage

30

Ω

I_ODON= 5 mA

0.3

V

COMMON MODE TRANSIENT IMMUNITY

CMTI Common-mode transient immunity

150

V/ns

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

(3) For internal PMOS only. Refer to 节8.3.2 for effective pull-up resistance.

6.9 Safety-Related Certifications

VDE

UL

Recognized under UL 1577 Component

Certified according to DIN EN IEC 60747-17 (VDE 0884-17)

Reinforced insulation

Recognition Program, CSA Component Acceptance

Notice 5A

Maximum transient isolation voltage, 8000 V_PK

Maximum repetitive peak isolation voltage, 2121 V_PK

Maximum surge isolation voltage, 8000 V_PK

;

Single protection, 5700 V_RMS

File Number: E181974

;

Certificate number: 40040142

8

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6.10 Switching Characteristics

VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, C_L=100pF, –

40°C<T_J<150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time –High to

Low

t_PDHL

60

90

130

Propagation delay time –Low to

High

t_PDLH

60

90

130

ns

PWD

t_sk-pp

t_r

30

Pulse width distortion |t_PDHL–t_PDLH

Part to Part skew

|

Rising or Falling Propagation Delay

C_L= 10 nF

Driver output rise time

33

27

t_f

Driver output fall time

C_L= 10 nF

f_MAX

Maximum switching frequency

1

MHz

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6.11 Insulation Characteristics Curves

80

1400

1200

1000

800

600

400

200

0

VDD=15V; VEE=-5V

VDD=20V; VEE=-5V

60

40

20

0

25

50

75

100

125

150

0

20

40

60

80

100

120

140

160

Ambient Temperature (^oC)

Safe

图6-1. Thermal Derating Curve for Limiting Current 图6-2. Thermal Derating Curve for Limiting Power

per VDE

1.E+12

1.E+11

1.E+10

1.E+09

1.E+08

1.E+07

1.E+06

1.E+05

1.E+04

1.E+03

1.E+02

1.E+01

54 Yrs

TDDB Line (< 1 ppm Fail Rate)

VDE Safety Margin Zone

1800V_RMS

2200

200

1200

3200

4200

5200

6200

Applied Voltage (V_RMS

)

图6-3. Reinforced Isolation Capacitor Life Time Projection

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6.12 Typical Characteristics

22

20

18

16

14

12

10

8

22

20

18

16

14

12

10

8

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

6

4

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D016

D017

图6-4. Output High Drive Current vs Temperature

图6-5. Output Low Driver Current vs Temperature

6

4

VCC = 3.3V

VCC = 5V

VCC = 3.3V

VCC = 5V

5.5

3.5

5

4.5

4

3

2.5

2

3.5

1.5

3

1

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D015

D014

IN+ = High

IN- = Low

IN+ = Low

IN- = Low

图6-6. I_VCCQSupply Current vs Temperature

图6-7. I_VCCQSupply Current vs Temperature

5

4.5

4

6

5.5

5

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

3.5

3

4.5

4

2.5

3.5

2

3

30

70

110

150 190

Frequency (kHz)

230

270

310

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D018

D012

图6-8. I_VCCQSupply Current vs Input Frequency

IN+ = High

IN- = Low

图6-9. I_VDDQSupply Current vs Temperature

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6.12 Typical Characteristics (continued)

6

10

9

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

5.5

8

5

4.5

4

7

6

5

4

3.5

3

2

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

30

70

110

150

190

Frequency (kHz)

230

270

310

D013

D019

IN+ = Low

IN- = Low

图6-11. I_VDDQSupply Current vs Input Frequency

图6-10. I_VDDQSupply Current vs Temperature

4

3.5

3

14

13.5

13

12.5

12

2.5

2

11.5

11

10.5

10

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D002

D001

图6-13. VDD UVLO vs Temperature

图6-12. VCC UVLO vs Temperature

100

90

80

70

60

50

100

90

80

70

60

50

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D022

D021

V_CC= 3.3V

V_DD=18V

R_OFF= 0Ω

C_L= 100pF

V_CC= 3.3V

V_DD=18V

R_OFF= 0Ω

C_L= 100pF

R_ON= 0Ω

图6-15. Propagation Delay t_PDHLvs Temperature

图6-14. Propagation Delay t_PDLHvs Temperature

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6.12 Typical Characteristics (continued)

60

50

40

30

20

10

50

40

30

20

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D023

D024

V_CC= 3.3V

V_DD=18V

C_L= 10nF

V_CC= 3.3V

V_DD=18V

C_L= 10nF

R_ON= 0Ω

R_OFF= 0Ω

R_ON= 0Ω

R_OFF= 0Ω

图6-16. t_rRise Time vs Temperature

图6-17. t_fFall Time vs Temperature

2.5

2.25

2

3

2.75

2.5

1.75

1.5

1.25

1

2.25

2

1.75

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

1.5

D025

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

图6-19. V_CLP-OUT(H)Short Circuit Clamping Voltage vs

D008

Temperature

图6-18. V_OUTPDOutput Active Pulldown Voltage vs Temperature

2

2.6

2.45

2.3

1.75

1.5

2.15

2

1.25

1

1.85

1.7

0.75

0.5

1.55

1.4

0.25

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D026

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

图6-20. V_CLP-OUT(L)Short Circuit Clamping Voltage vs

D007

Temperature

图6-21. V_CLMPTHMiller Clamp Threshold Voltage vs

Temperature

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6.12 Typical Characteristics (continued)

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D011

D010

图6-22. I_CLMPIMiller Clamp Sink Current vs Temperature

图6-23. t_DCLMPIMiller Clamp ON Delay Time vs Temperature

10

9.8

9.6

9.4

9.2

9

420

380

340

300

260

220

180

140

100

8.8

8.6

8.4

8.2

8

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D002

D001

图6-25. t_DESATLEBDESAT Leading Edge Blanking Time vs

图6-24. V_DESATDESAT Threshold Voltage vs Temperature

Temperature

680

660

640

620

600

580

560

540

520

500

300

290

280

270

260

250

240

230

220

210

200

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D004

D003

图6-27. t_DESATFLTDESAT Sense to /FLT Low Delay Time vs

图6-26. t_DESATOFFDESAT Propagation Delay to OUT(L) 90% vs

Temperature

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6.12 Typical Characteristics (continued)

320

310

300

290

280

270

260

250

240

230

220

560

550

540

530

520

510

500

490

480

470

460

450

440

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D005

D008

图6-28. t_DESATFILDESAT Deglitch Filter vs Temperature

图6-29. I_CHGDESAT Charging Current vs Temperature

20

19

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D009

图6-30. I_DCHGDESAT Discharge Current vs Temperature

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7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Regular Turn-OFF

图7-1 shows the propagation delay measurement for non-inverting configurations. 图7-2 shows the propagation

delay measurement with the inverting configurations.

50%

IN+

INÅ

t_PDLH

t_PDHL

90%

10%

OUT

图7-1. Non-inverting Logic Propagation Delay Measurement

IN+

INÅ

50%

t_PDLH

t_PDHL

90%

OUT

10%

图7-2. Inverting Logic Propagation Delay Measurement

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7.2 Input Deglitch Filter

In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input

pins, that is. IN+, IN–, RST/EN, a 40-ns deglitch filter is designed to filter out the transients and make sure there

is no faulty output responses or accidental driver malfunctions. When the IN+ or IN–PWM pulse is smaller than

the input deglitch filter width, T_INFIL, there is no responses on OUT drive signal. 图 7-3 and 图 7-4 show the IN+

pin ON and OFF pulse deglitch filter effect. 图7-5 and 图7-6 show the IN–pin ON and OFF pulse deglitch filter

effect.

IN+

t_PWM< T_INFIL

IN+

INÅ

OUT

图7-3. IN+ ON Deglitch Filter

图7-4. IN+ OFF Deglitch Filter

IN+

INÅ

t_PWM< T_INFIL

INÅ

OUT

图7-5. IN–ON Deglitch Filter

图7-6. IN–OFF Deglitch Filter

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7.3 Active Miller Clamp

7.3.1 Internal On-chip Active Miller Clamp

For a gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage,

active miller clamp can help add a additional low impedance path to bypass the miller current and prevent the

high dV/dt introduced unintentional turn-on through the miller capacitance. 图 7-7 shows the timing diagram for

on-chip internal miller clamp function.

IN

(”IN+‘ Å ”INÅ‘)

t_DCLMPI

V_CLMPTH

OUT

HIGH

CLMPI

Ctrl.

LOW

图7-7. Timing Diagram for Internal Active Miller Clamp Function

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7.4 Undervoltage Lockout (UVLO)

UVLO is one of the key protection features designed to protect the system in case of bias supply failures on VCC

—primary side power supply, and VDD —secondary side power supply.

7.4.1 VCC UVLO

The VCC UVLO protection details are discussed in this section. 图 7-8 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VCCFIL

t_{VCCÅ to OUT}

V_{VCC_ON}

VCC

V_{VCC_OFF}

VDD

COM

VEE

t_{VCC+ to OUT}

90%

V_CLMPTH

OUT

10%

t_{VCC+ to RDY}

t_RDYHLD

t_{VCCÅ to RDY}

Hi-Z

RDY

VCC

APWM

图7-8. VCC UVLO Protection Timing Diagram

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7.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. 图 7-9 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VDDFIL

VDD

t_{VDDÅ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

COM

VEE

VCC

t_{VDD+ to OUT}

V_CLMPTH

OUT

90%

t_RDYHLD

10%

t_{VDD+ to RDY}

t_{VDDÅ to RDY}

RDY

Hi-Z

VCC

APWM

图7-9. VDD UVLO Protection Timing Diagram

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7.5 Desaturation (DESAT) Protection

7.5.1 DESAT Protection with Soft Turn-OFF

DESAT function is used to detect V_DSfor SiC-MOSFETs or V_CEfor IGBTs under over current conditions. 图 7-10

shows the timing diagram of DESAT operation with soft turn-off during the turning on transition.

图7-10. DESAT Protection With Soft Turn-OFF During Turn-ON Transition

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图7-11 shows the timing diagram of DESAT protection while the power device is already turned on.

IN

(”IN+‘ Å ”INÅ‘)

V_DESAT

t_DESATLEB

t_DESATFIL

DESAT

t_DESATOFF

90%

GATE

V_CLMPTH

t_DESATFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

图7-11. DESAT Protection With Soft Turn-OFF While Power Device is ON

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8 Detailed Description

8.1 Overview

The UCC21750-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features

for SiC MOSFETs and IGBTs. The device can support up to 2121-V DC operating voltage based on SiC

MOSFETs and IGBTs, and can be used to above 10-kW applications, such as HEV/EV traction inverter, motor

drive, on-board and off-board battery charger, solar inverter, and so forth. The galvanic isolation is implemented

by the capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage

DSP/MCU and high voltage side.

The ±10-A peak sink and source current of the UCC21750-Q1 can drive the SiC MOSFET modules and IGBT

modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel

modules with external buffer stage. The input side is isolated with the output side with a reinforced isolation

barrier based on capacitive isolation technology. The device can support up to 1.5-kV_RMSworking voltage, 12.8-

kV_PKsurge immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the

device fast and reduce the switching loss, while the 150-V/ns minimum CMTI assures the reliability of the system

with fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting,

so the conduction loss can be reduced.

The device includes extensive protection and monitor features to increase the reliability and robustness of the

SiC MOSFET and IGBT based systems. The 12-V output side power supply UVLO is suitable for switches with

gate voltage ≥ 15 V. The active miller clamp feature prevents the false turn on causing by miller capacitance

during fast switching. The device has the state-of-art DESAT detection time and fault reporting function to the

low voltage side DSP/MCU. The soft turn-off is triggered when the DESAT fault is detected, minimizing the short

circuit energy while reducing the overshoot voltage on the switches.

The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,

auxiliary power supply sensing, and so forth. The PWM signal can be fed directly to DSP/MCU or through a low-

pass-filter as an analog signal.

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3 V to 5.5 V. The device supports both

unipolar and bipolar power supply on the output side, with a wide range from 13 V to 33 V from VDD to VEE.

The negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on

when the other switch in the phase leg is turned on. The negative voltage is especially important for SiC

MOSFET due to its fast switching speed.

8.3.2 Driver Stage

The UCC21750-Q1 has ±10-A peak drive strength and is suitable for high power applications. The high drive

strength can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra

buffer stage. The UCC21750-Q1 can also be used to drive higher power modules or parallel modules with extra

buffer stage. Regardless of the values of VDD, the peak sink and source current can be kept at 10 A. The driver

features an important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is

held in LOW state. The split output of the driver stage is depicted in 图 8-1. The driver has rail-to-rail output by

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implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and

an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on

resistance R_NMOSis the same as R_OL. The hybrid pull-up structure delivers the highest peak-source current

when it is most needed, during the miller plateau region of the power semiconductor turn-on transient. The R_OH

in 图 8-1 represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up

resistance is much smaller than R_OH. Because the pull-up N-Channel MOSFET has much smaller on-resistance

than the P-Channel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the

voltage on OUTH pin is about 3 V below VDD voltage. The effective resistance of the hybrid pull-up structure

during this period is about 2 × R_OL. Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The

low pull-up impedance results in strong drive strength during the turn-on transient, which shortens the charging

time of the input capacitance of the power semiconductor and reduces the turn on switching loss.

The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. This

MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pull-down impedance not only

results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering

the miller effect.

VDD

R_OH

R_NMOS

OUTH

Input

Signal

Anti Shoot-

through

Circuitry

OUTL

R_OL

图8-1. Gate Driver Output Stage

8.3.3 VCC and VDD Undervoltage Lockout (UVLO)

The UCC21750-Q1 implements the internal UVLO protection feature for both input and output power supplies

VCC and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW.

The output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature

not only reduces the power consumption of the driver itself during low power supply voltage condition, but also

increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the

gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD

value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the

power stage. The UCC21750-Q1 implements a 12-V threshold voltage of VDD UVLO, with 800-mV hysteresis.

This threshold voltage is suitable for both SiC MOSFET and IGBT.

The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity

of the power supply. During the turn-on and turn-off switching transient, the driver sources and sinks a peak

transient current from the power supply, which can result in sudden voltage drop of the power supply. With

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hysteresis and UVLO deglitch filter, the internal UVLO protection block ignores small noises during the normal

switching transients.

The timing diagrams of the UVLO feature of VCC and VDD are shown in 图7-8, and 图7-9. The RDY pin on the

input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO condition, the

RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to VCC to indicate

the power good. The AIN-APWM function stops working during the UVLO status. The APWM pin on the input

side is held LOW.

8.3.4 Active Pulldown

The UCC21750-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE

when the VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active

pulldown feature can prevent the output be false turned on before the device is back to control.

VDD

OUTL

R_a

Control

Circuit

VEE

COM

图8-2. Active Pulldown

8.3.5 Short Circuit Clamping

During short circuit condition, the miller capacitance can cause a current sinking to the OUTH/OUTL/CLMPI pin

due to the high dV/dt and boost the OUTH/OUTL/CLMPI voltage. The short circuit clamping feature of the

UCC21750-Q1 can clamp the OUTH/OUTL/CLMPI pin voltage to be slightly higher than VDD, which can protect

the power semiconductors from a gate-source and gate-emitter overvoltage breakdown. This feature is realized

by an internal diode from the OUTH/OUTL/CLMPI to VDD.

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VDD

D₁D₂D₃

OUTH

Control

Circuitry

OUTL

CLMPI

图8-3. Short Circuit Clamping

8.3.6 Internal Active Miller Clamp

Active miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In

applications which the device can be in synchronous rectifier mode, the body diode conducts the current during

the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same

and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-

down impedance of the UCC21750-Q1 can provide a strong pulldown to hold the OUTL to VEE. However,

external gate resistance is usually adopted to limit the dV/dt. The miller effect during the turn on transient of the

other power semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source

or gate-emitter voltage. If the voltage on V_GSor V_GEis higher than the threshold voltage of the power

semiconductor, a shoot through can happen and cause catastrophic damage. The active miller clamp feature of

the UCC21750-Q1 drives an internal MOSFET, which connects to the device gate. The MOSFET is triggered

when the gate voltage is lower than V_CLMPTH, which is 2 V above VEE, and creates a low impedance path to

avoid the false turn on issue.

V_CLMPTH

VCC

OUTH

+

3V to 5.5V

IN+

œ

CLMPI

OUTL

Control

Circuitry

µC

MOD

DEMOD

IN-

VEE

COM

VCC

图8-4. Active Miller Clamp

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8.3.7 Desaturation (DESAT) Protection

The UCC21750-Q1 implements a fast overcurrent and short circuit protection feature to protect the IGBT module

from catastrophic breakdown during fault. The DESAT pin of the device has a typical 9-V threshold with respect

to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the output is

held in low state, the DESAT pin is pulled down by an internal MOSFET and held in LOW state, which prevents

the overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is

activated only during the driver ON state, which means the overcurrent and short circuit protection feature only

works when the power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the

voltage of DESAT pin when the power semiconductor is turned off. The UCC21750-Q1 features a 200-ns

internal leading edge blanking time after the OUTH switches to high state. The internal current source is

activated to charge the external blanking capacitor after the internal leading edge blanking time. The typical

value of the internal current source is 500 µA.

图8-5. DESAT Protection

8.3.8 Soft Turn-Off

The UCC21750-Q1 initiates a soft turn-off when the overcurrent and short circuit protection is triggered. When

the overcurrent and short circuit fault happens, the IGBT transits from the active region to the desaturation

region very fast. The channel current is controlled by the gate voltage and decreasing in a soft manner, thus the

overshoot of the IGBT is limited and prevents the overvoltage breakdown. There is a tradeoff between the

overshoot voltage and short circuit energy. The turn off speed must to be slow to limit the overshoot voltage, but

the shutdown time must not be too long that the large energy dissipation can breakdown the device. The 400-

mA soft turn-off current of the UCC21750-Q1 makes sure the power switches is safely turned off during short

circuit events. The timing diagram of soft turn-off shows in 图7-10.

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图8-6. Soft Turn-Off

8.3.9 Fault (FLT, Reset, and Enable (RST/EN)

The FLT pin of the UCC21750-Q1 is open drain and can report a fault signal to the DSP/MCU when the fault is

detected through the DESAT pin. The FLT pin is pulled down to GND after the fault is detected, and is held low

until a reset signal is received from RST/EN. The device has a fault mute time t_FLTMUTE, within which the device

ignores any reset signal.

The RST/EN is pulled down internally by a 50-kΩ resistor, and is thus disabled by default when this pin is

floating. Pull up externally to enable the driver. The pin has two purposes:

• To reset the FLT pin: to reset, then RST/EN pin is pulled low; if the pin is set and held in low state for more

than t_RSTFILafter the mute time t_FLTMUTE, then the fault signal is reset and FLT is reset back to the high

impedance status at the rising edge of the input signal at RST/EN pin.

• Enable and shutdown the device: if the RST/EN pin is pulled low for longer than t_RSTFIL, the driver disables

and OUTL is activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be pulled up

externally to enable the part, otherwise the device is disabled by default.

8.3.10 Isolated Analog to PWM Signal Function

The UCC21750-Q1 features an isolated analog to PWM signal function from AIN to APWM pin, which allows the

isolated temperature sensing, high voltage dc bus voltage sensing, and so forth. An internal current source I_AIN

in AIN pin is implemented in the device to bias an external thermal diode or temperature sensing resistor. The

UCC21750-Q1 encodes the voltage signal V_AINto a PWM signal, passing through the reinforced isolation

barrier, and output to APWM pin on the input side. The PWM signal can either be transferred directly to

DSP/MCU to calculate the duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input

range is from 0.6 V to 4.5 V, and the corresponding duty cycle of the APWM output ranges from 88% to 10%.

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The duty cycle increases linearly from 10% to 88% while the AIN voltage decreases from 4.5 V to 0.6 V. This

action corresponds to the temperature coefficient of the negative temperature coefficient (NTC) resistor and

thermal diode. When AIN is floating, the AIN voltage is 5 V and the APWM operates at 400 kHz with

approximately 10% duty cycle. The accuracy of the duty cycle is ±3% across temperature without one time

calibration. The accuracy can be improved using calibration. The accuracy of the internal current source I_AINis

±3% across temperature.

The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high

voltage dc bus voltage, and so forth. The internal current source I_AINmust be taken into account when designing

the potential divider if sensing a high voltage.

UCC217xx

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

图8-7. Isolated Analog to PWM Signal

表8-1. Function Table

8.4 Device Functional Modes

The 表8-1 lists the device function.

INPUT

OUTPUT

OUTH/

OUTL

VCC

VDD

VEE

IN+

IN-

RST/EN

AIN

RDY

FLT

CLMPI

APWM

PU

PD

PU

PD

PU

X

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

P^*

PU

X

Low

X

Open

PU

X

Open

PU

X

Low

High

Low

HiZ

PU

Low

X

High

PU

High

Low

P^*

PU

High

P^*

PU

P^*

PU: Power Up (VCC ≥ 2.85 V, VDD ≥ 13.1 V, VEE ≤ 0 V); PD: Power Down (VCC ≤ 2.35 V, VDD ≤ 9.9 V);

X: Irrelevant; P^*: PWM Pulse; HiZ: High Impedance

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9 Applications and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The UCC21750-Q1 device is very versatile because of the strong drive strength, wide range of output power

supply, high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working

voltage and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus

voltage up to 2121 V. The device can be used in both low power and high power applications such as the

traction inverter in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power

supplies and so forth. The device can drive the high power SiC MOSFET module, IGBT module or paralleled

discrete device directly without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole

structure, which allows the driver to have more control to the power semiconductor and saves the cost and

space of the board design. The UCC21750-Q1 can also be used to drive very high power modules or paralleled

modules with external buffer stage. The input side can support power supply and microcontroller signal from 3.3

V to 5 V, and the device level shifts the signal to output side through reinforced isolation barrier. The device has

wide output power supply range from 13 V to 33 V and support wide range of negative power supply. This

feature allows the driver to be used in SiC MOSFET applications, IGBT application and many others. The 12-V

UVLO benefits the power semiconductor with lower conduction loss and improves the system efficiency. As a

reinforced isolated single channel driver, the device can be used to drive either a low-side or high-side driver.

The UCC21750-Q1 device features extensive protection and monitoring features, which can monitor, report and

protect the system from various fault conditions.

• Fast detection and protection for the overcurrent and short circuit fault. The semiconductor is shutdown when

the fault is detected and FLT pin is pulled down to indicate the fault detection. The device is latched unless

reset signal is received from the RST/EN pin.

• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and

short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is

limited.

• UVLO detection to protect the semiconductor from excessive conduction loss. After the device is detected to

be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is

back to normal operation mode after the power supply is out of the UVLO status. The power good status can

be monitored from the RDY pin.

• Analog signal sensing with isolated analog to PWM signal feature. This feature allows the device to sense the

temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus voltage

with resistor divider. A PWM signal is generated on the low voltage side with reinforced isolated from the high

voltage side. The signal can be fed back to the microcontroller for the temperature monitoring, voltage

monitoring and so forth.

• The active miller clamp feature protects the power semiconductor from false turn on.

• Enable and disable function through the RST/EN pin.

• Short circuit clamping.

• Active pulldown.

9.2 Typical Application

图 9-1 shows the typical application of a half bridge using two UCC21750-Q1 isolated gate drivers. The half

bridge is a basic element in various power electronics applications such as traction inverter in HEV/EV to convert

the DC current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion

system. The topology can also be used in motor drive applications to control the operating speed and torque of

the AC motors.

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UCC

21750

1

2

3

4

5

6

PWM

3-Phase

Input

1

2

3

4

5

6

µC

M

APWM

FLT

UCC

21750

图9-1. Typical Application Schematic

9.2.1 Design Requirements

The design of the power system for end equipment must consider some design requirements to ensure the

reliable operation of the UCC21750-Q1 through the load range. The design considerations include the peak

source and sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for

analog signal sensing and so forth.

A design example for a half bridge based on IGBT is given in this subsection. 表 9-1 shows the design

parameters.

表9-1. Design Parameters

PARAMETER

Input supply voltage

IN-OUT configuration

Positive output voltage VDD

Negative output voltage VEE

DC bus voltage

VALUE

5 V

Non-inverting

15 V

–5 V

800 V

Peak drain current

300 A

Switching frequency

Switch type

50 kHz

IGBT module

9.2.2 Detailed Design Procedure

9.2.2.1 Input Filters for IN+, IN–, and RST/EN

In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With

the strong drive strength of the UCC21750-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise cannot

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only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal

PCB layout and coupled capacitance.

The UCC21750-Q1 features a 40-ns internal deglitch filter to IN+, IN– and RST/EN pin. Any signal less than 40

ns can be filtered out from the input pins. For noisy systems, external low-pass filter can be added externally to

the input pins. Adding low-pass filters to IN+, IN– and RST/EN pins can effectively increase the noise immunity

and increase the signal integrity. When not in use, the IN+, IN– and RST/EN pins must not be floating. IN–

must be tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low-

pass filter is to filter out the high frequency noise generated by the layout parasitics. While choosing the low-pass

filter resistors and capacitors, both the noise immunity effect and delay time must be considered according to the

system requirements.

9.2.2.2 PWM Interlock of IN+ and IN–

The UCC21750-Q1 features the PWM interlock for IN+ and IN– pins, which can be used to prevent the phase

leg shoot through issue. As shown in 表8-1, the output is logic low while both IN+ and IN–are logic high. When

only IN+ is used, IN– can be tied to GND. To use the PWM interlock function, the PWM signal of the other

switch in the phase leg can be sent to the IN– pin. As shown in 图 9-2, the PWM_T is the PWM signal to top

side switch, the PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal

is given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the

PWM_B signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and

PWM_B signals are high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

IN+

IN-

R_ON

OUTH

OUTL

R_OFF

PWM_T

PWM_B

R_ON

IN+

IN-

OUTH

OUTL

R_OFF

图9-2. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has a 50-kΩ internal pulldown resistor, so the

driver is in OFF status if the RST/EN pin is not pulled up externally. A 5 kΩ resistor can be used as pullup

resistor for the FLT, RDY and RST/EN pins.

To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be

added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100 pF to 300

pF can be added.

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3.3V to 5V

VCC

15

9

1µF

0.1µF

GND

IN+

10

INt

11

5kQ

5kQ 5kQ

FLT

12

13

100pF

RDY

100pF

RST/EN

14

16

100pF

APWM

图9-3. FLT, RDY, and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

The RST/EN pin has two functions. The pin is used to enable or shutdown the outputs of the driver and to reset

the fault signaled on the FLT pin after DESAT is detected. RST/EN pin must to be pulled up to enable the device;

when the pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal

50kΩpulldown resistor at this pin.

When the driver is latched after DESAT is detected, the FLT pin and output are latched low and must be reset by

the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the fault to reset the driver. The

driver does not respond until after the mute time t_FLTMUTE. The reset signal must be held low for at least t_RSTFIL

after the mute time.

This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied

to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If

the PWM is applied to the non-inverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is

applied to the inverting input IN–, then a NOT logic is needed between the PWM signal from the microcontroller

and the RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without

an extra control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater

than t_RSTFILin order to reset the driver in cause of a DESAT fault.

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3.3V to 5V

0.1µF

3.3V to 5V

VCC

15

1µF

0.1µF

GND

IN+

GND

IN+

9

10

INt

5kQ

11

5kQ

11

5kQ

FLT

12

13

12

13

100pF

RDY

RST/EN

APWM

RST/EN

APWM

14

16

14

16

图9-4. Automatic Reset Control

9.2.2.5 Turn-On and Turn-Off Gate Resistors

The UCC21750-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn

on and turn off switching speed. The turn on and turn off resistance determine the peak source and sink current,

which controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver must be

considered to ensure the device is in the thermal limit. At first, the peak source and sink current are calculated

as:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

I_{sink _ pk}= min(10A,

)

VDD - VEE

R_OL+R_OFF+R_{G _Int}

)

(1)

Where

• R_{OH_EFF}is the effective internal pull up resistance of the hybrid pull-up structure, shown in 图8-1, which is

approximately 2 × R_OL, about 0.7 Ω. This is the dominant resistance during the switching transient of the pull

up structure.

• R_OLis the internal pulldown resistance, about 0.3 Ω.

• R_ONis the external turn on gate resistance.

• R_OFFis the external turn off gate resistance.

• R_{G_Int}is the internal resistance of the SiC MOSFET or IGBT module.

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VDD

C_ies=C_gc+C_ge

+

C_gc

VDD

R_{OH_EFF}

OUTH

t

R_ON

R_{G_Int}

OUTL

R_OFF

C_ge

+

VEE

R_OL

t

VEE

COM

图9-5. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

• Q_g= 3300 nC

• R_{G_Int}= 1.7 Ω

• R_ON= R_OFF= 1 Ω

The peak source and sink current in this case are:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

) ö 5.9A

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

) ö 6.7A

(2)

Thus, by using a 1-Ω external gate resistance, the peak source current is 5.9 A, the peak sink current is 6.7 A.

The collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller

plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless

the turn on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the

turn on switching loss is. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn off switching transient, the

drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After V_ce

reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled

by V_ge. The peak sink current determines the dI/dt, which dominates the V_cevoltage overshoot accordingly. If

using relatively large turn off gate resistance, the V_ceovershoot can be limited. The overshoot can be estimated

by:

DV = L_stray∂I_load/ ((R_OFF+R_OL+R_{G_Int})∂C_ies∂ln(V_plat/ V ))

ce

th

(3)

Where

• L_strayis the stray inductance in power switching loop, as shown in 图9-6

• I_loadis the load current, which is the turn off current of the power semiconductor

• C_iesis the input capacitance of the power semiconductor

• V_platis the plateau voltage of the power semiconductor

• V_this the threshold voltage of the power semiconductor

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L_DC

L_c1

L_stray=L_DC+L_e1+L_c1+L_e1+L_c1

R_G

L_load

t

+

L_e1

+

VDC

t

L_c2

VDD

C_gc

C_ies=C_gc+C_ge

R_G

OUTH

OUTL

COM

C_ge

L_e2

图9-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation must be taken into account to maintain the gate driver within the thermal limit. The power

loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

P

= P_Q+P

DR

SW

(4)

P_Qis the quiescent power loss for the driver, which is I_qx (VDD-VEE) = 5 mA × 20 V = 0.100 W. The quiescent

power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic

circuits, protection circuits when the driver is switching when the driver is biased with VDD and VEE, and also

the charging and discharing current of the internal circuit when the driver is switching. The power dissipation

when the driver is switching can be calculated as:

R_{OH_EFF}

2 R_{OH_EFF}+R_ON+R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g

SW

(5)

Where

• Q_gis the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD

• f_swis the switching frequency

In this example, the P_SWcan be calculated as:

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R_{OH_EFF}

2 R_{OH_EFF}+ R_ON+ R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g= 0.505W

SW

(6)

Thus, the total power loss is:

P =P +P = 0.10W +0.505W = 0.605W

DR

Q

SW

(7)

When the board temperature is 125°C, the junction temperature can be estimated as:

T_j= T + y_jb∂P ö 150^oC

b

DR

(8)

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency

is approximately 50 kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or

increasing external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 Overcurrent and Short Circuit Protection

A standard desaturation circuit can be applied to the DESAT pin. If the voltage of the DESAT pin is higher than

the threshold V_DESAT, the soft turn-off is initiated. A fault is reported to the input side to DSP/MCU. The output is

held to LOW after the fault is detected, and can only be reset by the RST/EN pin. The state-of-art overcurrent

and short circuit detection time helps to ensure a short shutdown time for SiC MOSFET and IGBT.

If DESAT pin is not in use, it must be tied to COM to avoid overcurrent fault false triggering.

• TI recommends fast reverse recovery high voltage diode in the desaturation circuit. A resistor is

recommended in series with the high voltage diode to limit the inrush current.

• Ti recommends a Schottky diode from COM to DESAT to prevent driver damage caused by negative voltage.

• TI recommends a Zener diode from COM to DESAT to prevent driver damage caused by positive voltage.

9.2.2.7 Isolated Analog Signal Sensing

The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature

detection, voltage sensing and so forth. One typical application of this function is the temperature monitor of the

power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or

IGBT module close to the dies to monitor the junction temperature. The UCC21750-Q1 has an internal 200-uA

current source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a

voltage drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the

isolation barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly

from 10% to 88% when the AIN voltage changes from 4.5 V to 0.6 V and can be represented using 方程式9.

D_APWM(%) = -20 * V_AIN+100

(9)

9.2.2.7.1 Isolated Temperature Sensing

A typical application circuit is shown in 图 9-7. To sense temperature, the AIN pin is connected to the thermal

diode or thermistor which can be discrete or integrated within the power module. TI recommends a low pass filter

for the AIN input. Because the temperature signal does not have a high bandwidth, the low pass filter is mainly

used for filtering the noise introduced by the switching of the power device, which does not require stringent

control for propagation delay. The filter capacitance for C_filtcan be chosen between 1 nF to 100 nF and the filter

resistance R_filtbetween 1 Ω to 10 Ω according to the noise level.

The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the

voltage input at AIN, using 方程式9.

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UCC217xx

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

图9-7. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of UCC21750-Q1 the duty cycle

output of APWM can also be filtered and the voltage measured using the microcontroller's ADC input pin, as

shown in 图 9-8. The frequency of APWM is 400 kHz, so the value for R_{filt_2}and C_{filt_2}must be such that the

cutoff frequency is below 400 kHz. Temperature does not change rapidly, thus the rise time due to the RC

constant of the filter is not under a strict requirement.

UCC217xx

VDD

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

图9-8. APWM Channel with Filtered Output

The example below shows the results using a 4.7-kΩNTC, NTCS0805E3472FMT, in series with a 3-kΩresistor

and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4

MMBT3904 thermal diodes connected in series ranges from about 2.5 V to 1.6 V from 25°C to 135°C,

corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the

3-kΩ resistor ranges from about 1.5 V to 0.6 V from 25°C to 135°C, corresponding to 70% to 88% duty cycle.

The voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in 图9-9.

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2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

90

84

Thermal Diode V_AIN

NTC V_AIN

Thermal Diode APWM

NTC APWM

78

72

66

60

54

48

20

40

60

80

Temperature (èC)

100

120

140

VAIN

图9-9. Thermal Diode and NTC V_AINand Corresponding Duty Cycle at APWM

The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in 图

9-10 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in 图9-11.

1.5

Thermal Diode APWM Duty Error

NTC APWM Duty Error

1.25

1

0.75

0.5

0.25

0

-0.25

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-10. APWM Duty Error Without Calibration

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0.8

Thermal Diode APWM Duty Error

NTC APWM Duty Error

0.6

0.4

0.2

0

-0.2

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-11. APWM Duty Error With Single-Point Calibration

9.2.2.7.2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel can be used for other applications such as the DC-link voltage sensing, as shown in

图 9-12. The same filtering requirements as given above can be used in this case, as well. The number of

attenuation resistors, R_{atten_1}through R_{atten_n}, is dependent on the voltage level and power rating of the resistor.

The voltage is finally measured across R_{LV_DC}to monitor the stepped-down voltage of the HV DC-link which

must fall within the voltage range of AIN from 0.6 V to 4.5 V. The driver must be referenced to the same point as

the measurement reference, thus in the case shown below the UCC21750-Q1 is driving the lower IGBT in the

half-bridge and the DC-link voltage measurement is referenced to COM. The internal current source I_AINmust be

taken into account when designing the resistor divider. The AIN pin voltage is:

R_{LV _DC}

n

V_AIN

=

∂ V_DC+R_{LV _DC}∂I_AIN

R_{LV _DC}

+

R

atten _ i

ƒ

i=1

(10)

R_{atten_1}

R_{atten_2}

UCC217xx

VDD

VCC

R_{atten_n}

13V to

33V

+

3V to 5.5V

APWM

œ

C_DC

+

AIN

DEMOD

MOD

µC

R_filt

C_filt

R_{filt_2}

C_{filt_2}

GND

R_{LV_DC}

OSC

COM

图9-12. DC-link Voltage Sensing Configuration

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9.2.2.8 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in 图

9-13) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be

avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/ D45VH10

pair is up to 20-A peak.

In the case of an over-current detection, the soft turn off (STO) is activated. External components must be added

to implement STO instead of normal turn off speed when an external buffer is used. C_STOsets the timing for soft

turn off and R_STOlimits the inrush current to below the current rating of the internal FET (10A). R_STOmust be at

least (VDD–VEE)/10. The soft turn off timing is determined by the internal current source of 400 mA and the

capacitor C_STO. C_STOis calculated using 方程式11.

I_STO∂ t_STO

VDD

-

VEE

C_STO

=

(11)

• I_STOis the internal STO current source, 400 mA

• t_STOis the desired STO timing

图9-13. Current Buffer for Increased Drive Strength

9.2.3 Application Curves

Step Input (0.6 V to 4.5 V)

APWM Output

图9-15. AIN Step Input (Green) and APWM Output

(Pink)

图9-14. PWM Input (Yellow) and Driver Output

(Blue)

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10 Power Supply Recommendations

During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and

VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a

voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, TI

recommends a set of decoupling capacitors at the power supplies. Considering the UCC21750-Q1 has ±10-A

peak drive strength and can generate high dV/dt, TI recommends a 10-µF bypass cap between VDD and COM,

VEE and COM. TI recommends a 1-µF bypass cap between VCC and GND due to less current comparing with

output side power supplies. A 0.1-µF decoupling cap is also recommended for each power supply to filter out

high frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and

must be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system

parasitics of PCB layout.

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11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of the UCC21750-Q1, careful considerations must be taken in PCB design.

Below are some key points:

• The driver must be placed as close as possible to the power semiconductor to reduce the parasitic

inductance of the gate loop on the PCB traces.

• The decoupling capacitors of the input and output power supplies must be placed as close as possible to the

power supply pins. The peak current generated at each switching transient can cause high dI/dt and voltage

spike on the parasitic inductance of PCB traces.

• The driver COM pin must be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If

the power device does not have a split Kelvin source or emitter, the COM pin must be connected as close as

possible to the source or emitter terminal of the power device package to separate the gate loop from the

high power switching loop

• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the

high frequency noise generated by the output side switching transients. The ground plane provides a low-

inductance filter for the return current flow.

• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the

ground plane on the output side to shield the output signals from the noise generated by the switch node; if

the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground

plane is not recommended

• If ground plane is not used on the output side, separate the return path of the DESAT and AIN ground loop

from the gate loop ground which has large peak source and sink current.

• No PCB trace or copper is allowed under the gate driver. TI recommends a PCB cutout to avoid any noise

coupling between the input and output side which can contaminate the isolation barrier.

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11.2 Layout Example

图11-1. Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21750-Q1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 IGBT/SiC MOSFET 且具有 DESAT 和内部钳位的汽车类 5.7kVrms、±10A 单通道隔离式栅极驱动器栅极驱动双极性晶体管驱动器
文件：	总53页 (文件大小：2657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21750-Q1 [TI]

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