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UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

UCC28780 高频有源钳位反激式控制器

1 特性

3 说明

1

•

通过自适应控制对初级 FET 进行完全和部分零电压

UCC28780 是一款高频有源钳位反激式控制器，可实

开关 (ZVS)

现符合严格全球效率标准（如美国能源部 6 级和欧盟

CoC V5 Tier-2 能效标准）的高密度交流/直流电源。

用户可编程高级控制律特性可以针对硅 (Si) 和氮化镓

(GaN) 功率 FET 进行性能优化。由于具有逻辑电平栅

极信号和使能输出，因此使用组合了驱动器和 GaN

FET 的开关器件进行直接运行的能力得到进一步增

强。

•

外部硅或氮化镓 FET 可编程时序

开关频率高达 1MHz

可编程自适应突发控制和待机模式，可提高轻载效

率，并具有低输出纹波和可闻噪声抑制功能

•

无需直接的线路感应即可检测掉电

通过精确的可编程过功率保护 (OPP) 支持峰值功率

模式

此器件凭借先进的自动调谐技术、自适应死区时间优化

和可变开关频率控制律，可在宽广的工作范围内实现零

电压开关 (ZVS)。使用可根据输入和输出条件改变运行

方式的自适应多模式控制，UCC28780 可在提高效率

的同时减轻可闻噪声。凭借高达 1MHz 的可变开关频

率和精确的可编程过功率保护功能（该功能可在宽广的

线路范围内为散热设计提供始终如一的功率），无源组

件的尺寸可进一步缩小，并实现高功率密度。

•

故障保护：过热、输出过压、输出短路、过流和引

脚故障

与基于光耦合器的反馈直接相连，因此支持可动态

扩展的输出电压

•

内部软启动

带外部使能端的 NTC 热敏电阻接口

2 应用

•

用于笔记本电脑、平板电脑、电视机、机顶盒和打

UCC28780与 VDS 感应同步整流器控制器（如

UCC24612）结合使用，可实现更高的转换效率和非常

紧凑的设计。

印机的高密度直流/交流适配器

USB 供电、直接和快速移动充电器

交流/直流或直流/直流辅助电源

•

器件信息⁽¹⁾

可订购器件型号

UCC28780RTE

UCC28780D

封装

WQFN-16

SOIC-16

封装尺寸（标称值）

3.00mm × 3.00mm

10.33mm × 7.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

45W、20V GaN-ACF 适配器效率

D_BD

+

C_CLAMP

N_P

N_S

96

~

R_BLEED

V_AC

V_O

115V_AC

N_PS:1

V_SW

œ

V_BULK

C_O

94

Q_SEC

Q_H

C_BULK

R_CCS

230V_AC

CoC V5 Tier 2 Average

92

90

88

86

84

82

80

78

Q_L

D_AUX

V_AUX

N_A

VS

VD

VG

Half-bridge Driver

UCC24612 VDD

REG

C_VDD

R_VS1

R_OPP

R_CS

C_REG

DOE Level VI Average

RUN PWMH PWML CS

VDD

VS

C_DIFF

HV Startup +

ZVS Sense

R_DIFF

NTC

R_VS2

SWS

UCC28780

GND

RDM

HVG

FB

4-Point Avg. Efficiency:

R_BIAS1

C_HVG

93.9% at 115V_AC

92.5% at 230V_AC

CC/CV

Regulator

R_FB

R_RDM

CoC 10%

load

REF

SET

RTZ

BUR

R_BIAS2

R_RTZ

R_BUR2

R_BUR1

C_REF

0

25

50

75

100

Output Load (%)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSD12

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 37

8.1 Application Information............................................ 37

8.2 Typical Application Circuit....................................... 37

Power Supply Recommendations...................... 51

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information of SOIC.................................... 6

6.5 Thermal Information of WQFN.................................. 6

6.6 Electrical Characteristics........................................... 7

6.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 13

7.3 Detailed Pin Description.......................................... 14

8

9

10 Layout................................................................... 52

10.1 Layout Guidelines ................................................. 52

10.2 Layout Example .................................................... 54

11 器件和文档支持 ..................................................... 58

11.1 文档支持 ............................................................... 58

11.2 接收文档更新通知 ................................................. 58

11.3 社区资源................................................................ 58

11.4 商标....................................................................... 58

11.5 静电放电警告......................................................... 58

11.6 Glossary................................................................ 58

12 机械、封装和可订购信息....................................... 59

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2017 年（2018 年）

A

第一版.

2

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

5 Pin Configuration and Functions

D Package

16-Pin SOIC

Top View

1

2

16

15

VDD

GND

CS

REF

BUR

RDM

3

4

14

13

PWML

PWMH

RTZ

FB

5

6

7

8

12

11

10

9

RUN

SWS

NTC

SET

HVG

VS

RTE Package

16-Pin WQFN

Top View

16

15

14

13

CS

PWML

PWMH

RDM

RTZ

FB

1

2

3

12

11

10

4

9

RUN

NTC

5

6

7

8

3

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

SOIC

WQFN

BUR

15

13

I

This pin is used to program the burst level of the converter at light load. A resistive divider

between REF and GND is used to set a voltage at this pin to determine the peak current level

when the converter enters the adaptive burst mode. In addition, the Thevenin resistance on

BUR pin (equivalent resistance of the divider resistors in parallel) is used to set an offset

voltage for smooth mode transition which increases the peak current level when the converter

enters the low power mode.

CS

FB

3

1

I

This is the current sense input pin. This pin couples through a line-compensation resistor to a

current-sense resistor to sense and control the peak primary current in each switching cycle. A

current sourced from this pin, which magnitude is proportional to the converter’s input voltage

derived from the VS-pin input signal, creates an offset voltage across the line-compensation

resistor to program an OPP level at high line.

12

10

The feedback current signal to close the converter’s regulation loop is coupled to this pin. This

pin presents a 4-V output that is designed to have 0-µA to 75-µA current pulled out of the pin

corresponding to the converter operating from full-power to zero-power conditions.

GND

HVG

2

8

16

6

G

O

Ground reference and return for all controller signals.

The high-voltage gate pin is used to control the gate of an external depletion-mode MOSFET

for start-up and switch-node voltage sensing. A 2.2-nF ceramic bypass capacitor to ground is

required.

NTC

11

9

I

This is an interface to an external NTC (negative temperature coefficient) thermistor for remote

temperature sensing. Pulling this pin low shuts down PWM action and initiates a fault

response.

PWMH

PWML

RDM

5

4

3

2

O

I

The PWMH pin is a logic-level output signal used to control the gate of the high-side clamp

switch through an external gate driver.

The PWML pin is a logic-level output signal used to control the gate of the low-side primary

switch through an external gate driver.

14

12

A resistor to ground on this pin programs a synthesized demagnetization time used to control

the on-time of the high-side switch to achieve zero voltage switching on the low-side switch.

The controller applies a voltage on this pin that varies with the output voltage derived from the

VS pin signal.

REF

RTZ

RUN

16

13

6

14

11

4

O

I

5V reference output that requires a 0.1-µF ceramic bypass capacitor to ground. This reference

is used to power internal circuits and can supply a limited external load current.

A resistor to ground on this pin programs an adaptive transition-to-zero delay from the turn-off

edge of the high-side clamp switch to the turn-on edge of the low-side switch.

O

This output pin is high when the controller is in a run state. During start-up and wait states this

output is low. It can be used to enable and disable the external gate drivers to reduce the

static power consumption. There is a preset delay, t_D(RUN-PWML), of about 2.2 µs that delays

the initiation of PWML switching after this pin has gone high.

SET

10

7

8

5

I

This pin is used to configure the controller to be optimized for Gallium Nitride (GaN) power

FETs or silicon (Si) power FETs on the primary side. Depending on setting, it will optimize

parameters of the ZVS control loop, dead-time adjustment, and protection features. When

pulled high to REF pin, it is optimized for Si FETs. When pulled low to GND, it is optimized for

GaN FETs .

SWS

This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal

operation. During start-up, this pin is connected to the VDD pin internally to allow the high-

voltage sensing network to provide start-up current.

VDD

VS

1

9

15

7

P

I

Bias power input to the controller. A hold-up capacitor to ground is required for the bias power

supplied from the transformer auxiliary winding to this pin.

This voltage sensing input pin is coupled to the auxiliary winding of the converter’s transformer

via a resistor divider. The pin and the associated external resistors are used to monitor the

output and input voltages of the converter.

(1) I = Input, O = Output, P = Power, G = Ground

4

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Input Voltage

VDD

38

V

SWS

–6

-20

38

VDD-SWS (Run state)

38

CS

–0.3

–0.75

–1

3.6

NTC

7

FB

7

VS (Continuous)

7

VS (Transient, 100ns Max.)

7

RTZ

–0.3

7

BUR

7

SET

7

RDM

7

Output Voltage

Source Current

REF

7

V

HVG

25

PWML, PWMH, RUN

7

REF

5

mA

HVG

Self-limiting

VS (Continuous)

2

VS (Transient, 100ns Max.)

2.5

FB

1

PWML, PWMH, RUN

1

RTZ

Self-limiting

RDM

Self-limiting

Sink Current

PWML, PWMH, RUN

SWS

1

mA

°C

5

Operating junction temperature, T_J

Storage temperature, T_stg

–55

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

12

NOM

MAX

UNIT

V

V_VDD

C_VDD

C_REF

C_HVG

T_J

Bias-supply operating voltage

VDD capacitor

34

0.3

0.1

2.2

-40

µF

nF

°C

REF bypass capacitor

HVG bypass capacitor

Operating Junction temperature

125

6.4 Thermal Information of SOIC

D

THERMAL METRIC⁽¹⁾

SOIC

16 PINS

83.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

43.0

42.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

10.9

ψ_JB

42.2

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Thermal Information of WQFN

RTE + PAD

THERMAL METRIC⁽¹⁾

WQFN

16 PINS

47.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

48.9

22.0

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.0

ψ_JB

22.0

R_θJC(bot)

6.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

6.6 Electrical Characteristics

Over operating free-air temperature range, V_VDD= 15V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50

kΩ, V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, I_HVG= 25 μA, and -40 ⁰C < T_J= T_A< 125 ⁰C (unless otherwise noted)

PARAMETER

BIAS SUPPLY INPUT CURRENT

I_RUN(STOP)Supply current, run

TEST CONDITION

MIN

TYP

MAX

UNIT

No switching

2.3

2.5

400

70

3

mA

µA

I_RUN(SW)

I_WAIT

Supply current, run

Supply current, wait

Supply current, start

Switching, I_VSL= 0 µA

I_FB= -85 µA

3.3

550

140

I_START

V_VDD= V_VDD(ON)– 100 mV, V_VS= 0

V

µA

I_FAULT

Supply current, fault

Fault state

265

350

µA

UNDER-VOLTAGE LOCKOUT (UVLO)

V_VDD(ON)VDD turn-on threshold

V_VDD(OFF)VDD turn-off threshold

V_VDDincreasing

V_VDDdecreasing

16.7

17.5

9.8

1

18.2

10.4

1.5

V

9.35

0.3

V_VDD(PCT)Offset to power cycle for long output Offset above V_VDD(OFF), I_FB= -85 μA

voltage overshoot

VS INPUT

V_VSNC

Negative clamp level

I_VSL= -1.25 mA, voltage below

ground

170

250

325

mV

V_ZCD

t_ZC

Zero-crossing detection (ZCD) level V_VSdecreasing

Zero-crossing timeout delay

10

30

2.2

20

55

2.7

45

mV

µs

1.8

t_D(ZCD)

Propagation delay from ZCD high to V_VSstep from 4 V to -0.1 V

PWML high

ns

I_VSB

Input bias current

V_VS= 4 V

-0.25

0

0.25

µA

CS INPUT

V_CST(MAX)Maximum CS threshold voltage

V_CSincreasing

765

123

175

115

800

150

200

130

15

825

170

225

145

25

mV

ns

V_CST(MIN)

t_CSLEB

Minimum CS threshold voltage

Leading-edge blanking time

V_CSdecreasing, I_FB= -85 μA

V_SET= 5 V, V_CS= 1 V

V_SET= 0 V, V_CS= 1 V

t_D(CS)

K_LC

RUN, PWML, PWMH

Propagation delay of CS comparator V_CSstep from 0 V to 1 V

ns

high to PWML low

Line-compensation current ratio

I_VSL= -1.25 mA, I_VSL/ current out of

CS pin

22.5

4.4

25

5

27

A/A

V_PWMLH

V_PWMHH

V_RUNH

V_PWMLL

V_PWMHL

V_RUNL

t_RISE

High level of PWML, PWMH, and

RUN pins

I_PWML(H)= -1 mA, I_RUN= -1 mA

V

Low level of PWML, PWMH, and

RUN pins

I_PWML(H)= +1 mA, I_RUN= +1 mA

0.5

Turn-on rise time, 10% to 90%⁽¹⁾

Turn-off fall time, 90% to 10%⁽¹⁾

Delay from RUN high to PWML high

C_LOAD= 10 pF

10

ns

µs

t_FALL

t_D(RUN-

1.8

44

34

5.4

PWML)

t_D(VS-PWMH)Dead-time between VS high and

PWMH high

V_SET= 5 V

55

42

70

51

ns

t_D(PWML-H)Dead-time between PWML low and V_SET= 0 V

PWMH high

t_ON(MIN)

Minimum on-time of PWML in low

power mode

V_SET= 5 V, I_FB= -85 μA, V_CS= 1 V

V_SET= 0 V, I_FB= -85 μA, V_CS= 1 V

70

48

90

65

115

80

ns

(1) Not tested in protection, and limits guaranteed by design.

7

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range, V_VDD= 15V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50

kΩ, V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, I_HVG= 25 μA, and -40 ⁰C < T_J= T_A< 125 ⁰C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

PROTECTION

V_OVP

V_OCP

Over-voltage threshold

Over-current threshold

V_VSincreasing

4.4

4.5

1.2

4.6

V

V_CSincreasing

I_VSL= 0 μA

0.97

574

492

426

405

1.36

1.35

627

595

492

452

1.44

V_CST(OPP)Over-power threshold on CS pin

600

545

460

425

1.4

mV

I_VSL= -333 μA

I_VSL= -666 μA

I_VSL= -1.25 mA

K_OPP

OPP threshold voltage ratio

V_CST(OPP)ratio between I_VSL= 0 μA

V/V

and I_VSL= -1.25 mA

t_OPP

OPP fault timer

I_FB= 0 A

115

330

275

0.81

35

160

365

305

200

400

335

0.85

75

ms

µA

I_VSL(RUN)

VS line-sense run current

Current out of VS pin increasing

Current out of VS pin decreasing

I_VSL(STOP)/ I_VSL(RUN)

I_VSL< I_VSL(STOP)

I_VSL(STOP)VS line-sense stop current

K_VSL

VS line-sense ratio

0.836

60

A/A

ms

kΩ

µs

t_BO

Brown-out detection delay time

R_RDMthreshold for CS pin fault

R_RDM(TH)

t_CSF1

41

50

59

Max. PWML on time for detecting

CS pin fault

V_SET= 5 V

1.6

2

2.3

t_CSF0

t_FDR

Max. PWML on time for detecting

CS pin fault

R_RDM< R_RDM(TH)for V_SET= 0 V

0.8

1

1.15

1.9

µs

s

Fault-reset delay timer

OCP, OPP, OVP, SCP, or CS pin

fault

1.5

T_J(STOP)

NTC INPUT

V_NTCTH

R_NTCTH

R_NTCR

Thermal shut-down temperature

Internal junction temperature

125

°C

NTC shut-down voltage

Voltage decreasing

R_NTCdecreasing

R_NTCincreasing

R_NTC= 12 kΩ

0.9

8.7

1.0

9.5

1.1

10.3

24

V

NTC shut-down resistance

NTC recovery resistance

NTC pull-up current, out of pin

kΩ

µA

19.5

85

21.7

105

I_NTC

120

BUR INPUT AND LOW POWER MODE

K_BUR-CST

f_BR(UP)

Ratio from V_BURto V_CST

V_CSTbetween V_CST(OPP1)and 0.7 V

3.9

29

4

4.13

39

V/V

kHz

Upper threshold of burst rate

34

frequency in adaptive burst mode⁽¹⁾

f_BR(LR)

f_LPM

Lower threshold of burst rate

21

22

25

29

28

kHz

µA

frequency in adaptive burst mode⁽¹⁾

Burst rate frequency in low power

mode

I_BUR

Bias current of V_BURoffset in LPM

2.1

2.7

3.4

RTZ INPUT

t_Z(MAX)

Maximum programmable dead-time R_RTZ= 280 kΩ, I_VSL= -1 mA, V_SET

=

380

66

480

72

565

86

ns

from PWMH low to PWML high

5 V

t_Z(MIN)

t_Z

Minimum programmable dead-time

from PWMH low to PWML high

R_RTZ= 78.4 kΩ, I_VSL= -1 mA, V_SET

= 0 V

Dead-time from PWMH low to

PWML high

I_VSL= -150 μA

I_VSL= -450 μA

I_VSL= -733 μA

144

123

110

1.26

172

150

125

1.4

205

177

145

1.57

ns

s/s

K_TZ

T_Zcompensation ratio

T_Zratio between I_VSL= -200 μA and

I_VSL= -733 μA

8

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Electrical Characteristics (continued)

Over operating free-air temperature range, V_VDD= 15V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50

kΩ, V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, I_HVG= 25 μA, and -40 ⁰C < T_J= T_A< 125 ⁰C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

SWS INPUT

V_TH(SWS)

SWS zero voltage threshold

V_SET= 5 V

8.8

9

4

9.6

4.3

28

V

V_SET= 0 V

3.7

t_D(SWS-

PWML)

Time between SWS low to PWML

high

V_SWSstep from 5 V to 0 V

12

ns

FB INPUT

I_FB(SBP)

V_FB(REG)

R_FBI

Maximum control FB current

Regulated FB voltage level

FB input resistance

I_FBincreasing

75

4.3

8

95

µA

V

4

7

4.65

9.5

kΩ

REF OUTPUT

V_REF

REF voltage level

I_REF= 0 A

4.9

8

5

5.1

18

7

V

I_S(REF)

V_R(LINE)

V_R(LOAD)

Short current of REF pin

Line regulation of V_REF

Load regulation of V_REF

Short REF pin

V_VDD= 12 V to 35 V

14

mA

mV

-5

I_REF= 0 mA to 1 mA, change in

V_REF

-10

10

HVG OUTPUT

V_HVG

HVG voltage level

I_HVG= +/-200 μA, run state

9.7

55

10.5

90

1

11.4

140

1.6

V

I_SE(HVG)

I_S(HVG)

HVG max sink current during startup V_HVG= 13 V, start state

µA

mA

mV

V

Short current of HVG pin

Line regulation of V_HVG

HVG over voltage threshold

Short HVG pin

0.4

V_HR(LINE)

V_HVG(OV)

RDM INPUT

t_DM(MAX)

V_VDD= 12 V to 35 V

-25

13.0

25

13.8

14.6

Maximum PWMH pulse width with

maximum tuning

V_SWS= 12 V

V_SWS= 0 V

6.08

3.05

6.76

3.4

7.6

3.8

µs

t_DM(MIN)

Minimum PWMH pulse width with

minimum tuning

9

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

6.7 Typical Characteristics

V_VDD= 15V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_SET= 0 V, and T_J= T_A= 25 ⁰C (unless otherwise noted)

10

I_RUN

I_RUN(STOP)

1

I_WAIT

1

I_RUN(WAIT)

I_FAULT

0.1

I_START

0.1

0.01

0.001

0.01

0

5

10

15

20

25

30

35

40

-50

-25

0

25

50

75

100

125

V_VDD- Bias Supply Voltage (V)

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 1. VDD Bias-Supply Current vs. VDD Bias-Supply Voltage

图 2. VDD Bias-Supply Current vs. Junction Temperature

395

8

6

I_VSL(RUN)

375

(V_CST(MIN)- 0.15 V) / 0.15 V

4

355

335

(V_CST(MAX)- 0.8 V) / 0.8 V

2

0

-2

-4

-6

-8

I_VSL(STOP)

315

295

275

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 3. VS Line-Sense Currents vs. Temperature

图 4. Percentage Variation of Maximum and Minimum CS

Thresholds vs. Temperature

0.65

0.6

1.5

1.4

K_TZat 25öC

V_CST(OPP)at 25öC

V_CST(OPP)at -40öC

V_CST(OPP)at 125öC

1.3

1.2

1.1

1

K_TZat -40öC

K_TZat 125öC

0.55

0.5

0.45

0.4

0.9

0

200

400

600

800

1000

1200

1400

1600

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

I_VSL- VS Line-Sense Current (JA)

I_VSL- VS Line-Sense Current (mA)

图 6. t_ZCompensation Ratio (K_TZ) vs. VS Line-Sense

图 5. CS Over-Power Threshold vs. VS Line-Sense Currents

Currents

10

UCC28780

www.ti.com.cn

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Typical Characteristics (接下页)

V_VDD= 15V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_SET= 0 V, and T_J= T_A= 25 ⁰C (unless otherwise noted)

4.6

4.56

4.52

4.48

4.44

4.4

5.06

5.04

5.02

5

I_REF= 0 A

4.98

4.96

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 8. REF Voltage vs. Temperature

图 7. VS Over-Voltage Threshold vs. Temperature

11

10.8

10.6

10.4

10.2

11.5

11

10.5

10

9.5

-50

-25

0

25

50

75

100

125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

I_HVG- HVG Current (mA)

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 10. HVG Voltage vs. HVG Current

图 9. HVG Voltage vs. Temperature

25

23

21

19

17

15

13

11

9

R_NTCR

R_NTCTH

7

5

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 11. NTC Thresholds vs. Junction Temperature

11

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www.ti.com.cn

7 Detailed Description

7.1 Overview

The UCC28780 is a transition-mode (TM) active clamp flyback (ACF) controller, equipped with advanced control

schemes to enable significant size reduction of passive components for higher power density and higher average

efficiency. The control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a half-bridge

configuration and is capable of driving high-frequency AC/DC converters up to 1 MHz. The zero voltage

switching (ZVS) control of the UCC28780 is capable of auto-tuning the on-time of a high-side clamp switch (Q_H)

by using a unique lossless ZVS sensing network connected between the switch-node voltage (V_SW) and SWS

pin. The ACF controller is designed to adaptively achieve targeted full-ZVS or partial-ZVS conditions for the low-

side main switch (Q_L) with minimum circulating energy over wide operating conditions. Auto-tuning eliminates the

risk of losing ZVS due to component tolerance, input/output voltage changes, and temperature variations, since

the Q_Hon-time is corrected cycle-by-cycle.

Dead-times between PWML (controls Q_L) and PWMH (controls Q_H) are optimally adjusted to help minimize the

circulating energy required for ZVS. Therefore, the overall system efficiency can be significantly improved and

more consistent efficiency can be obtained in mass production of the soft-switching topology. The programming

features of the RTZ, RDM, BUR, and SET pins provide rich flexibility to optimize the power stage efficiency

across a range of output power and operating frequency levels.

The UCC28780 uses four different operating modes to maximize efficiency over wide load and line ranges.

Adaptive amplitude modulation (AAM) adjusts the peak primary current at the higher load levels. Adaptive burst

mode (ABM) modulates the pulse count of each burst packet in the medium to light load range. Low power mode

(LPM) reduces the peak primary current of each two-pulse burst packet in the very light load range. Standby

power (SBP) mode minimizes the loss during no load conditions.

The unique burst mode control of the UCC28780 maximizes the light load efficiency of the ACF power stage,

while avoiding the concerns of conventional burst operation - such as output ripple and audible noise. The burst

control provides an enable signal through the RUN pin to dynamically manage the static current of the half-bridge

driver and also adaptively disables the on-time of Q_H. These functions can be used to manage the quiescent

power consumed by the half-bridge driver, further improving the converter’s light-load efficiency and reducing its

standby power.

Instead of using a conventional high-voltage resistor, the UCC28780 starts up the VDD supply voltage with an

external high-voltage depletion-mode MOSFET between the SWS pin and the switch node. Fast startup is

achieved with low standby power overhead. Moreover, the HVG pin controls the gate of the depletion-mode FET

to also allow this MOSFET to be used in a lossless ZVS sensing. This arrangement avoids additional sensing

devices.

The UCC28780 also integrates a robust set of protection features tailored to maximize the reliability. These

features include internal soft start, brown in/out, output over-voltage, output over-power, system over-

temperature, switch over-current, output short-circuit protection, and pin open/short.

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UCC28780

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

7.2 Functional Block Diagram

OCP FAULT

VDD_OK

UVLO

VDD

LINE FAULT

OTP FAULT

HVG FAULT

V_VDD(ON)/ V_VDD(OFF)

V_NTCTH

V_NTCR

/

OP FAULT

I_NTC

+

Power and

Fault Management

OV FAULT

WAIT

œ

NTC

GND

TSH FAULT

T_J

Thermal

Shutdown

S

R

S

R

RUN_EN

QH_EN

PWMH

PWML

HVG

SWS

V_CST

Adaptive

ZVS

Control

S = Start

R = RUN

TZ COMP

S

R

Q

I_VSL

K_LC

HVG Regulator

HVG FAULT

+

CS

RDM

RTZ

VS

V_CST

œ

t_CSLEB

TDM COMP

OV FAULT

OCP FAULT

T_Z

+

NVo

Sensing

V_OCP

œ

SWS

SET

TUNE

ZVS

Discriminator

ZCD

Zero Crossing

Detect

OP FAULT

WAIT

QH_EN

FB

OP COMP

TZ COMP

ZCD

Over-Power

Protection

Line

Sense

Control Law

V_CST

N_SWEND

BUR

LINE FAULT

I_VSL

I_BUR

PWML

WAIT

RUN_EN

Adaptive Burst

Control

RUN

REF

REF Regulator

13

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

7.3 Detailed Pin Description

7.3.1 BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (V_BUR) sets a target peak current threshold (V_CST(BUR)) which programs the onset of

adaptive burst mode (ABM) and determines the clamped peak current level of switching cycles in each burst

packet. When V_BURis designed higher, ABM will start at heavier output load conditions with higher peak current,

so the benefit is the higher light-load efficiency but the side effect is a larger burst output voltage ripple.

Therefore, 50% to 60% of output load at high line is the recommended highest load condition entering into ABM

(I_o(BUR)) for both Si and GaN-based ACF designs. The gain between V_BURand V_CST(BUR)is a constant gain of

K_BUR-CST, so setting V_CST(BUR)just requires properly selecting the resistor divider on the BUR pin formed by R_BUR1

and R_BUR2. V_BURshould be set between 0.7 V and 2.4 V. If V_BURis less than 0.7 V, V_CST(BUR)holds at 0.7 V /

K_BUR-CST. If V_BURis higher than 2.4 V, V_CST(BUR)stays at 2.4 V / K_BUR-CST

.

R

_BUR1K_BUR-CSTV_{CST (BUR)}

4ì R_BUR1V_{CST (BUR)}

R_BUR2

=

V_REF- K_BUR-CSTV_{CST (BUR)}5V - 4ìV_{CST (BUR)}

(1)

In order to enhance the mode transition between ABM and Low Power Mode (LPM), a programmable offset

voltage (ΔV_BUR) is generated on top of the V_BURsetting in ABM through an internal 2.7-μA current source (I_BUR),

as shown in 图 12. In ABM mode, V_BURis set through the resistor voltage divider to fulfill the target average

efficiency. After transition from ABM to LPM, the current source is enabled in LPM and flows out of the BUR pin,

so ΔV_BURcan be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

R_BUR1R_BUR2

DV_BUR= I_BUR

ì

R_BUR1+ R_BUR2

(2)

I_O

I_BUR

REF

BUR

R_BUR1

V_BUR

LPM

ûV_BUR

LPM

SBP

K_CST-BURV_CST(BUR)

R_BUR2

PWMH

C_BUR

图 12. Hysteresis Voltage Generation on BUR Pin

When V_BURbecomes higher after transition to LPM, the initial peak magnetizing current in LPM is increased with

larger energy per switching cycle in a burst packet, which forces UCC28780 to stay in LPM with a higher

feedback current than ABM. If ΔV_BURis designed too small, it is possible that mode toggling between LPM and

ABM can occur resulting in audible noise. For that situation, ΔV_BURgreater than 100 mV is recommended. To

minimize the noise coupling effect on V_BUR, a filter capacitor on the BUR pin (C_BUR) may be needed. C_BURneeds

to be properly designed to minimize the delay of generating ΔV_BURin time during mode transition. It is

recommended that C_BURshould be sized small enough to ensure ΔV_BURsettles within 40 μs, corresponding to

the burst frequency of 25 kHz in LPM (f_LPM). Based on three RC time constants representing 95% of a settled

steady state value from a step response, the design guide of C_BURis expressed as

R_BUR1+ R_BUR2

3R_BUR1R_BUR2

C_BURÇ 40ms ì

(3)

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UCC28780

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Detailed Pin Description (接下页)

7.3.2 FB Pin (Feedback Pin)

The FB pin connects to the collector of an optocoupler output transistor through an external current-limiting

resistor (R_FB). Depending on the operating mode, the controller uses different content of the collector current

flowing out of the FB pin (I_FB) to regulate the output voltage. For the operating modes based on peak current

control, I_FBis converted into an internal peak current threshold (V_CST) to modulate the amplitude of the current

sense signal on the CS pin. For example, when the output voltage (V_O) is lower than the regulation level set by

the shunt regulator, the “current level” of I_FBmoves to lower value, so V_CSTgoes up to deliver more power to the

output load.

As the burst control takes over the V_Oregulation, where V_CSTis clamped to V_CST(BUR), the “current ripple” of I_FBis

used to modulate burst off time, as shown in 图 13. Specifically, after a group of pulses stop bursting, the output

load current starts to discharge the output capacitor, which makes V_Ostart to decay. A proper type-III

compensation on the secondary side of V_Ofeedback loop minimizes the phase-delay between I_FBcurrent ripple

and output voltage ripple. For a detailed design guide on each passive component of the type-III compensator,

please refer to Application and Implementation. When the decaying I_FBintersects with an internal reference

current (I_TH(FB)), the ripple regulator generates a new set of grouped burst pulses to deliver more power, which

makes V_Oand I_FBripples move upward.

I_FB

I_TH(FB)

RUN

PWML

V_CST(BUR)

CS

图 13. Concept of Burst Control

The nature of ripple-based control in burst mode requires additional care on the noise level of I_FBto improve the

consistency of burst off-time between burst cycles. Firstly, a high-quality ceramic-bypass capacitor between FB

pin and REF pin (C_FB) is required for decoupling I_FBnoise. A minimum of 100 pF is recommended. There is an

internal 8-kΩ resistor (R_FBI) connected to the FB pin that in conjunction with an external C_FBforms an effective

low-pass filter. On the other hand, too strong low-pass filtering with too large C_FBcan attenuate the I_FBripple

creating slope distortion of the intersection point between I_FBand I_TH(FB), which can cause inconsistent burst off-

times, even though V_Ostays in regulation and the I_FBnoise is low. Secondly, since ABM utilizes the falling-edge

burst-ripple content of I_FBto determine the beginning of every burst packet, the operation is affected if the burst-

ripple content of the output voltage is too small due to using a low-ESR output capacitor, or if there is an

additional low-frequency ringing on the output ripple due to using a second-order output filter.

Compared with an electrolytic-type of output capacitor, the advantage of ACF using a low-ESR output capacitor

such as a polymer capacitor is to minimize the switching-ripple content of the output voltage to meet the ripple

specification, but the burst-ripple content is also reduced. Therefore, the switching ripple and noise on I_FBmay be

very close to I_TH(FB), which triggers the next burst event prematurely. For a converter using a second-order output

filter, a π filter design as example, even though both switching-ripple and burst-ripple contents are further

attenuated, additional low-frequency ringing caused by the resonance between the output filter inductor and one

of the output filter capacitors is generated, which may trigger the next burst event too early as well. Therefore,

applying an active ripple compensation (ARC) technique is recommended to generate a noise-free burst ripple

artificially to stabilize the ABM operation of ACF using either a low-ESR output capacitor or a second-order

output filter.

图 14 illustrates the implementation of ARC formed by a high-impedance resistor (R_COMP) in series with a small-

signal enhancement MOSFET (Q_COMP) where its gate is controlled by the RUN pin of UCC28780. When RUN pin

is in a high state which turns on Q_COMP, R_COMPconnected to FB pin creates a compensation current (I_COMP), with

a magnitude around V_FB/ R_COMP. When RUN pin changes to a low state which turns off Q_COMP, R_COMPand the

drain-source junction capacitor of Q_COMPcreates a slow falling edge of I_COMP, with a ramp slope dependent on

15

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Detailed Pin Description (接下页)

the RC time constant. Then, the summation of the current from the optocoupler (I_OPTO) and I_COMPbecomes the

total feedback current out of FB pin (I_FB) to compare with I_TH(FB). As the ARC operation in 图 15 explains, the

magnitude of I_COMPhelps to push any switching and noise content of I_FBaway from I_TH(FB), and the slow falling

edge of I_COMPfurther pushes the undesirable ripple content away from I_TH(FB), especially the low-frequency

ringing of the π output filter. The magnitude of I_COMPcan be adjusted by R_COMP, and 1 MΩ to 2 MΩ is the

recommended value which injects around 2 μA to 4 μA of compensation ripple current into the loop.

V_O

Passive Ripple

Compensation

REF

FB

C_FB

I_FB

I_OPTO

V_FB(REG)

R_FBI

R_FB

I_COMP

I_FB

RUN

Control

Law

OPTO

COUPLER

Regulator

R_COMP

Active Ripple

Compensation

Q_COMP

图 14. Implementation of Active Ripple Compensation (ARC)

I_FB

I_TH(FB)

I_COMP

I_OPTO

V_o

PWML

RUN

图 15. Concept of Burst Control with ARC

7.3.3 VDD Pin (Device Bias Supply)

The VDD pin is the primary bias for the internal 5-V REF regulator, internal 11-V HVG regulator, other internal

references, and the undervoltage lock-out (UVLO) circuit. As shown in Functional Block Diagram, the UVLO

circuit connected to the VDD pin controls three power-path switches among VDD, HVG, and SWS pins, in order

to allow Q_Sto be able to perform both V_VDDstartup and V_SWsensing for ZVS control after startup. During startup,

SWS and HVG pins are connected to VDD pin allowing an external depletion-mode MOSFET (Q_S) to charge the

16

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Detailed Pin Description (接下页)

VDD capacitor (C_VDD) from the switch-node voltage (V_SW). After VDD startup competes, the ZVS discriminator

block is enabled, so as switching logics. Then, the transformer starts delivering energy to the output capacitor

(C_O) every switching cycle, so both output voltage (V_O) and auxiliary winding voltage (V_AUX) increase. As V_AUXis

high enough, the auxiliary winding will take over to power V_VDD. The UVLO circuit provides a turn-on threshold of

V_VDD(ON)at 17.5 V and turn-off threshold of V_VDD(OFF)at 9.8 V. The range can accommodate lower values of VDD

capacitor (C_VDD) and support shorter power-on delays. 38-V maximum operating level on V_VDDalleviates

concerns with leakage energy charging of C_VDDand gives added flexibility when a varying output voltage must be

supported.

As V_VDDreaches V_VDD(ON), SWS pin is disconnected from the VDD pin, so the C_VDDsize has to be sufficient to

hold V_VDDhigher than V_VDD(OFF)until the positive auxiliary winding voltage is high enough to take over bias power

delivery during V_Osoft start. Therefore, the calculation of minimum capacitance (C_VDD(MIN)) needs to consider the

discharging effect from the sink current of the UCC28780 during switching in its run state (I_RUN(SW)), the average

operating current of driver (I_DR), and the average gate charge current of half-bridge FETs (I_Qg) throughout the

longest time of V_Osoft start (t_SS(MAX)).

(I_{RUN (SW )}+ I_DR+ I_Qg)t_{SS(MAX )}

C_{VDD(MIN )}

=

V_{VDD(ON )}-V_{VDD(OFF )}

(4)

t_SS(MAX)estimation should consider the averaged soft-start current (I_SEC(SS)) on the secondary side of ACF, the

constant-current output load (I_O(SS)) (if any), maximum output capacitance (C_O(MAX)), and a 1-ms time-out

potentially being triggered in the startup sequence.

C_{O(MAX )}V_O

t_{SS(MAX )}

=

+1ms

I_{SEC(SS )}- I_{O(SS )}

(5)

During V_Osoft start, V_CSTreaches the maximum current threshold on the CS pin (V_CST(MAX)) , so I_SEC(SS)at the

minimum voltage of the input bulk capacitor (V_BULK(MIN)) can be approximated as:

N_PSV_{CST (MAX )}

V_{BULK (MIN )}

I_{SEC(SS )}

=

2R_CS

V_{BULK (MIN )}+ N_PS(V_O+V_F)

(6)

where R_CSis the current sense resistor, N_PSis primary-to-secondary turns ratio, and V_Fis the forward voltage

drop of the secondary rectifier.

For details of the startup sequencing, one can refer to the Device Functional Modes of this datasheet.

7.3.4 REF Pin (Internal 5-V Bias)

The output of the internal 5-V regulator of the controller is connected to this pin. It requires a high-quality

ceramic-bypass capacitor (C_REF) to GND for decoupling switching noise and lowering the voltage droop as the

controller transitions from wait state to run state. The minimum C_REFvalue is 0.1 μF, and a high quality dielectric

material should be used, such as a X7R. The output short current (I_S(REF)) of the REF regulator is self-limited to

approximately 14 mA. 5-V bias is only available after the under-voltage lock-out (UVLO) circuit enables the

operation of UCC28780 after V_VDDreaches V_VDD(ON)

.

7.3.5 HVG and SWS Pins

The HVG pin provides a controlled voltage to the gate of the depletion-mode MOSFET (Q_S), enabling Q_Sto

serve both V_VDDstartup and lossless ZVS sensing from the high-voltage switch node (V_SW). During V_VDDstartup,

the UVLO circuit commands two power-path switches connecting SWS and HVG pins to VDD pin with two

internal current-limit resistors (R_DDSand R_DDH) separately, as shown in 图 16. In this configuration, Q_Sbehaves

as a current source to charge the VDD capacitor (C_VDD). R_DDSis set at 12 kΩ when V_VDDis below 1 V to limit the

maximum fault current under VDD pin short events. R_DDSis reduced to 1 kΩ when V_VDDrises above 1 V to allow

V_VDDto charge faster. The maximum charge current (I_SWS) is affected by R_DDS, the external series resistance

(R_SWS) from SWS pin to Q_S, and the threshold voltage of Q_S(V_TH(Qs)). I_SWScan be calculated as

V_{TH (Qs)}

I_SWS

=

R_DDS+ R_SWS

(7)

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Detailed Pin Description (接下页)

C_VDD

UVLO

VDD

I_SWS

R_DDS

R_SWS

SWS

HVG

V_SW

+

V_TH(Qs)

Q_S

-

R_DDH

C_HVG

图 16. Operation of the VDD Startup Circuit

After V_VDDreaches V_VDD(ON), the two power-path switches open the connections among SWS, HVG, and VDD

pins. At this point, a third power-path switch connects an internal 11-V regulator to the HVG pin for configuring

Q_Sto perform lossless ZVS sensing. As Q_Sgate is fixed at 11 V and the drain pin voltage of Q_Sbecomes higher

than the sum of Q_Sthreshold voltage (V_TH(Qs)) and the 11-V gate voltage, Q_Sturns off and the source pin voltage

of Q_Scan no longer follow the drain pin voltage change, so this gate control method makes Q_Sact as a high-

voltage blocking device with the drain pin connected to V_SW. When the controller is switching, V_SWcan be lower

than 11 V, so Q_Sturns on and forces the source pin voltage to follow V_SW, becoming a replica of the V_SW

waveform at the lower voltage level, as illustrated in 图 17.

The limited window for monitoring the V_SWwaveform suffices for ZVS control of the UCC28780, since the ZVS

tuning threshold (V_TH(SWS)) is lower than that, which is at 9 V for V_SET= 5 V and at 4 V for V_SET= 0 V. The 9-V

threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial ZVS condition

on the ACF using Si primary switches. On the other hand, performing full ZVS operation is more suitable for the

ACF with GaN primary switches. The 4-V threshold can help to better compensate sensing delay between V_SW

and the SWS pin more than using a 0-V threshold. The internal 11-V regulator requires a high quality ceramic

bypass capacitor (C_HVG) between the HVG pin and GND for noise filtering and providing compensation to the

regulator circuitry. The minimum C_HVGvalue is 2.2 nF and an X7R-type dielectric capacitor is recommended. The

controller enters a fault state if the HVG pin is open or shorted to GND during V_VDDstart-up, or if V_HVGovershoot

is higher than V_HVG(OV)of 13.8 V in run state. The output short current of HVG regulator (I_S(HVG)) is self-limited to

around 1mA.

C_VDD

VDD

V_SW

V_BULK+N_PS(V_O+V_F)

R_SWS

ZVS

Discriminator

SWS

HVG

V_SW

+

V_TH(Qs)

Q_S

-

V_SWS

11V+V_TH(Qs)

11-V Regulator

C_HVG

图 17. ZVS Sensing by Reusing the VDD Startup Circuit

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Detailed Pin Description (接下页)

7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)

The dead-time between PWMH falling edge and PWML rising edge (t_Z) serves as the wait time for V_SWtransition

from its high level down to the target ZVS point. Since the optimal t_Zvaries with V_BULK, the internal dead-time

optimizer automatically extends t_Zas V_BULKis less than the highest voltage of the input bulk capacitor

(V_BULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line versus

a fixed dead-time over a wide line voltage range. A resistor on RTZ pin (R_RTZ) programs the minimum t_Z(t_Z(MIN)

)

at V_BULK(MAX), which is the sum of the propagation delay of the high-side driver (t_D(DR)) and the minimum resonant

transition time of V_SWfalling edge (t_LC(MIN)).

R_RTZ= K_TZìt_{Z (MIN )}= K_TZì(t_D(DR)+ t_{LC(MIN )}

)

(8)

where K_TZis equal to 11.2×10¹¹(unit: F^-1) for V_SET= 0 V, and 5.6×10¹¹(unit: F^-1) for V_SET= 5 V. As illustrated in

图 18, after PWMH turns off Q_Hafter t_D(DR)delay, the negative magnetizing current (i_M-) becomes an initial

condition of the resonant tank formed by magnetizing inductance (L_M) and the switch-node capacitance (C_SW).

C_SWis the total capacitive loading on the switch-node, including all junction capacitance (C_OSS) of switching

devices, stray capacitance of the boot-strap diode, intra-winding capacitance of the transformer, the snubber

capacitor, and parasitic capacitance of the PCB traces between switch-node and ground. Unlike a conventional

valley-switching flyback converter, the resonance of an active clamp flyback converter at high line does not begin

at the peak of the sinusoidal trajectory. The transition time of V_SWtakes less than half of the resonance period.

The following t_LC(MIN)expression quantifies the transition time for R_RTZcalculation, where an arccosine term

represents the initial angle at the resonance beginning. The value of π minus the arccosine term at V_BULK(MAX)of

375 V, V_Oof 20 V, and N_PSof 5 is around 0.585π, which is close to one quarter of the resonance period.

N_PS(V_O+V_F)

V_{BULK (MAX )}

t_{LC(MIN )}= [

p

- cos^-1(

)]ì L_MC_SW

(9)

V_SW

N_PS(V_O+V_F)

V_BULK(MAX)

I_M

I_M-

t_D(DR)

t_LC(MIN)

t_Z(MIN)

PWMH

PWML

图 18. RTZ Setting for the Falling-edge Transition of V_SW

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Detailed Pin Description (接下页)

7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)

The R_RDMresistor provides the power stage information to the t_DMoptimizer for auto-tuning the on-time of PWMH

to achieve ZVS within a given t_Zdischarge time. The following equation calculates the resistance, based on the

knowledge of the primary magnetizing inductance (L_M), auxiliary-to-primary turns ratio (N_A/N_P), the values of the

resistor divider (R_VS1and R_VS2) from the auxiliary winding to VS pin, and the current sense resistor (R_CS). Among

those parameters, L_Mcontributes the most variation due to its typically wider tolerance. The optimizer is

equipped with wide enough on-time tuning range of PWMH to cover tolerance errors. Therefore, just typical

values are enough for the calculation.

N_AR_{VS 2}

K_DML_M

R_RDM

=

N_P(R_VS1+ R_{VS 2}) R_CS

(10)

where K_DMis equal to 5×10⁹(unit: F^-1) for both V_SET= 5 V and 0 V.

7.3.8 RUN Pin (Driver Enable Pin)

The RUN pin is a logic-level output signal to enable the gate driver. It generates a 5-V logic output when the

driver should be active, and pulls down to less than 0.5 V when the driver should be disabled. During burst mode

operation, the RUN pin serves as a power management function to dynamically reduce the static current of the

driver, so light-load efficiency can be further improved and standby power can be minimized. In addition, there

are two delays between RUN going high to first PWML pulse going high in each burst packet. The first delay is a

fixed 2.2-μs delay time, intended to provide an appropriate wake-up time for UCC28780 and the gate driver to

transition from a wait state to a run state. The second delay is another 2.2-μs timeout, t_ZCin the electrical table,

intended to turn on the low-side switch of the first switching cycle per burst packet around the valley point of

DCM ringing by waiting for the zero crossing detection (ZCD) on the auxiliary winding voltage (V_AUX). Therefore,

the minimum total delay time is 2.2 μs typically if ZCD is detected immediately after the first 2.2-μs wake-up time,

while the maximum total delay time is 4.4 μs if ZCD is not triggered after the timeout. The total delay time with

tolerance over temperature are listed as t_D(RUN-PWML)in the electrical table. RUN pin can also be used to control

the external active ripple compensation network to enhance the stability of the burst regulation loop.

7.3.9 SET Pin

Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation

delays of their drivers, SET pin is provided to program critical parameters of UCC28780 for the two distinctive

power stages. Firstly, this pin sets the zero voltage threshold (V_TH(SWS)) at the SWS input pin to be two different

auto-tuning targets for ZVS control. When SET pin is tied to GND, V_TH(SWS)is set at its low level of 4 V for

realizing full ZVS, which allows the low-side switch (Q_L) to be turned on when the switch-node voltage drops

close to 0 V. When SET pin is tied to REF pin, V_TH(SWS)is set at 9 V for implementing partial ZVS, which makes

Q_Lturn on at around 9V. Secondly, this pin generates different PWML-to-PWMH dead-time (t_D(PWML-H)) to achieve

ZVS on the high-side clamp switch (Q_H). A fixed 40ns for V_SET= 0 V and an adaptive adjustment for V_SET= 5 V.

Thirdly, this setting also selects the current sense leading edge blanking time (t_CSLEB) to accommodate different

delays of the gate drivers; 130 ns for V_SET= 0 V and 200 ns for V_SET= 5 V. Fourthly, the minimum PWML on-

time (t_ON(MIN)) in low-power mode and standby-power mode varies based on the driver capability; 65 ns for V_SET

=

0 V and 90 ns for V_SET= 5 V. Finally, the maximum PWML on-time for detecting CS pin fault (t_CSF). t_CSFfor V_SET

= 5 V (t_CSF1) is set at 2 μs. t_CSFfor V_SET= 0 V (t_CSF0) depends on R_RDM, which is configured to 1 μs under R_RDM

<

R_RDM(TH)and to 2 μs under R_RDM≥ R_RDM(TH)

.

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7.4 Device Functional Modes

7.4.1 Adaptive ZVS Control with Auto-Tuning

图 19 shows the simplified block diagram explaining the ZVS control of UCC28780. A high-voltage sensing

network provides the replica of the switch node voltage waveform (V_SW) with a limited “visible” voltage range that

the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment

direction for the on-time of PWMH (t_DM) by detecting if V_SWreaches a predetermined ZVS threshold, V_TH(SWS)

,

within t_Z, where t_Zis the targeted zero voltage transition time of V_SWcontrolled by the PWMH-to-PWML dead-

time optimizer.

In 图 19, V_SWof the current switching cycle in the dashed line has not reached V_TH(SWS)after t_Zexpires. The ZVS

discriminator sends a TUNE signal to increase t_DMfor the next switching cycle in the solid line, such that the

negative magnetizing current (I_M-) can be increased to bring V_SWdown to a lower level in the same t_Z. After a few

switching cycles, the t_DMoptimizer settles and locks into ZVS operation of the low-side switch (Q_L). In steady-

state, there is a fine adjustment on t_DM, which is the least significant bit (LSB) of the ZVS tuning loop. This small

change of t_DMin each switching cycle is too small to significantly move the ZVS condition away from the desired

operating point. 图 20 demonstrates how fast the ZVS control can lock into ZVS operation. Before the ZVS loop

is settled, UCC28780 starts in a valley-switching mode as t_DMis not long enough to create sufficient I_M-. Within 15

switching cycles, the ZVS tuning loop settles and begins toggling t_DMwith an LSB.

t_D(PWML-H)

V_CST

L_K

D_SEC

I_M/ R_CS

PWML

PWMH

N_P:N_S

V_BULK

V_O

I_M

L_M

R_Co

C_O

R_O

C_CLAMP

t_DM

Q_H

SET

VS

RTZ

Adaptive ZVS Control

PWMH

PWML

RDM

SET

t_Z

t_DM

Optimizer

Dead-Time Optimizer

(t_D(PWML-H)and t_Z)

Q_L

Driver

V_SW

R_CS

TUNE

t_Z

V_TH(SWS)

Peak Current

Loop

V_CST

ZVS Discriminator

PWMH

PWML

SET

SWS

HV Sense

HVG

图 19. Block Diagram of Adaptive ZVS Control

PWML

PWMH

1.2

0.8

0.4

0

I_M(A)

18

12

6

V_SWS(V)

V_TH(SWS)

0

400

300

200

V_SW(V)

100

0

5 µs/div

12

6

12

6

12

6

V_SWS(V)

0

400

V_SW(V)

200

0

200

0

200

0

图 20. Auto-Tuning Process of Adaptive ZVS Control

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Device Functional Modes (接下页)

7.4.2 Dead-Time Optimization

The dead-time optimizer in 图 19 controls the two dead-times: the dead-time between PWMH falling edge and

PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge (t_D(PWML-H)).

The adaptive control law for t_Zof UCC28780 utilizes the line feed-forward signal to extend t_Zas V_BULKreduces,

as shown in 图 21. The VS pin senses V_BULKthrough the auxiliary winding voltage (V_AUX) when the low-side

switch (Q_L) is on. The auxiliary winding creates a line-sensing current (I_VSL) out of the VS pin flowing through the

upper resistor of the voltage divider on VS pin (R_VS1). Minimum t_Z(t_Z(MIN)) is set at V_BULK(MAX)through the RTZ

pin. When I_VSLis lower than 666 μA, t_Zlinearly increases and the maximum t_Zextension is 140% of t_Z(MIN)

.

140%

t_Z(I_VSL

)

t_Z(MIN)

100%

I_VSL

666 µA

233 µA

图 21. t_ZControl Optimized for Wide Input Voltage Range

The control law for t_D(PWML-H)of UCC28780 is programmable based on the SET pin voltage. When V_SET= 0 V, a

fixed delay around 40 ns is used to fit a GaN-based ACF with a fast dV/dt on the V_SWrising edge. With V_SET= 5

V, the dead-time optimization is enabled to intelligently adapt to the effect of nonlinear junction capacitance of Si

MOSFETs on the dV/dt of V_SWrising edge. The high capacitance region of the C_OSScurve for the Si Q_Lcreates a

shallow ramping on V_SWafter PWML turns off. When C_OSSof Si Q_Lmoves to the low capacitance region with

V_SWincreasing, V_SWstarts to ramp up very quickly. Since the changing slope varies with different peak

magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on

the high-side clamp switch (Q_H) if the dead-time is not long enough. UCC28780 utilizes the zero crossing detect

(ZCD) signal on the auxiliary-winding voltage to identify if V_SWovercomes the shallow ramping, and generates a

50-ns delay (t_D(VS-PWMH)) before turning on PWMH. This feature allows cycle-by-cycle dead-time adjustment to

avoid hard-switching of Q_H, while providing fast turn-on timing for Q_Hto minimize the body-diode conduction time.

Si FET (V_SET= 5 V)

GaN FET (V_SET= 0 V)

Heavy Load

Light Load

Heavy Load

Light Load

V_SW

0 V

40-ns

delay

V_AUX

ZCD

PWML

PWMH

50-ns

delay

t_D(VS-PWMH)

t_D(PWML-H)

PWML

PWMH

t_D(PWML-H)

图 22. t_D(PWML-H)Control Optimized for GaN and Si FETs

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Device Functional Modes (接下页)

7.4.3 Control Law across Entire Load Range

UCC28780 contains four modes of operation summarized in 表 1. Starting from heavier load, the AAM mode

forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a group

of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output voltage. At

the same time, the burst frequency variation is confined above 20kHz by adjusting the number of PWML and

PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In LPM and SBP modes,

PWMH and the ZVS tuning loop are disabled, so the converter operates in valley-switching.

表 1. Functional Modes

MODE

Adaptive

Amplitude

OPERATION

PWMH

ZVS

AAM

ABM

ACF operation with PWML and PWMH in complementary

switching

Enabled

Yes

Modulation

Adaptive Burst

Mode

Variable f_BUR> 20 kHz, ACF operation in complementary

switching

Enabled

Yes

LPM

SBP

Low Power Mode Fix f_BUR≈ 25 kHz, valley-switching

StandBy Power Variable f_BUR< 25 kHz, valley-switching

Disabled

No

图 23 addresses the critical parameter changes among the four operating modes, where V_CSTis the peak current

threshold compared with the current-sense voltage from CS pin, f_SWis the switching frequency of PWML, f_BURis

the burst frequency, and N_SWis the pulse number of PWML per burst packet. The following section explains the

detailed operation of each mode.

SBP

LPM

V_CST

ABM

AAM

V_CST(OPP)

V_CST(BUR)

V_CST(MIN)

I_O

Frequency

f_SW

f_BUR

f_BUR(UP)

f_BUR(LR)

f_LPM

I_O

N_SW

9

2

I_O

I_O(BUR)

I_O(OPP)

图 23. Control Law Over Entire Load Range

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7.4.4 Adaptive Amplitude Modulation (AAM)

The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time

in between, as shown in 图 24. As the load current reduces, the negative magnetizing current (I_M-) stays the

same, while the positive magnetizing current (I_M+) reduces by the internal peak current loop to regulate the output

voltage. I_M+generates a current-feedback signal (V_CS) on CS pin through a current-sense resistor (R_CS) in series

with Q_L, and a peak current threshold (V_CST) in the current loop controls the peak current variation. Due to the

nature of transition-mode (TM) operation, lowering the peak current with lighter load conditions results in higher

switching frequency. When the load current increases to an over-power condition (I_O(OPP)) where V_CST

correspondingly reaches an OPP threshold (V_CST(OPP)) of the peak current loop, the OPP fault response will be

triggered after a 160-ms timeout. The RUN signal stays high in AAM, so the half-bridge driver remains active.

Heavy Load

I_M

Light Load

0 A

I_M-

PWML

PWMH

RUN

图 24. PWM Pattern in AAM

7.4.5 Adaptive Burst Mode (ABM)

As the load current reduces to I_O(BUR)where V_CSreaches to V_CST(BUR)threshold, ABM starts and V_CSis clamped.

The peak magnetizing current and the switching frequency (f_SW) of each switching cycle are fixed for a given

input voltage level. V_CST(BUR)is programmed by the BUR pin voltage (V_BUR). The PWM pattern of ABM is shown

in 图 25. When RUN goes high, a delay time between RUN and PWML (t_D(RUN-PWML)) is given to allow both the

gate driver and the UCC28780 time to wake up from a wait state to a run state. PWML is set as the first pulse to

build up the bootstrap voltage of the high-side driver before PWMH starts switching. The first PWML pulse turns

on Q_Lclose to a valley point of the DCM ringing on the switch-node voltage (V_SW) by sensing the condition of

zero crossing detection (ZCD) on the auxiliary winding voltage (V_AUX). The following switching cycles operate in a

ZVS condition, since PWMH is enabled. As the number of PWML pulses (N_SW) in the burst packet reaches its

target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces the half-

bridge driver and UCC28780 into a wait state for the quiescent current reduction of both devices. In this mode,

the minimum off-time of the RUN signal is 2.2 µs and the minimum on-time of PWML is limited to the leading-

edge blanking time (t_CSLEB) of the peak current loop. However, more grouped pulses means more risk of higher

output ripple and higher audible noise. The following equation estimates how burst frequency (f_BUR) varies with

output load and other parameters.

I_O

f_SW

f_BUR

=

I_O(BUR)N_SW

(11)

As I_O< I_O(BUR), f_BURcan become lower than the audible noise range if N_SWis fixed. In ABM, N_SWis modulated to

ensure f_BURstays above 20 kHz by monitoring f_BURin each burst period. As I_Oreduces, f_BURbecomes lower and

reaches a predetermined low-level frequency threshold (f_BUR(LR)) of 25 kHz. The ABM loop commands N_swof

both PWML and PWMH to be reduced by one pulse to maintain f_BURabove f_BUR(LR). At the same time, the burst

frequency ripple on the output voltage reduces as N_SWdrops with the load reduction. As I_Oincreases, f_BUR

becomes higher and reaches a predetermined high-level frequency threshold (f_BUR(UP)) of 34 kHz. The ABM loop

commands N_SWto be increased by one pulse to push f_BURback below f_BUR(UP)

.

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also

limiting the burst output ripple and audible noise. As I_Omoves below the boundary between AAM and ABM, the

maximum N_SWis nine and the minimum N_SWis two. As I_Ois close to the boundary between AAM and ABM, the

maximum N_SWcan be higher than nine, to provide a smoother mode transition. When the load slightly increases

in this boundary, more than nine pulses are generated in a burst packet as 图 26 shows. f_BURstarts to move

lower than 20kHz. The burst pattern with disordered N_SWand inconsistent f_BURamong the asymmetric burst

packets generates a frequency spreading effect to weaken the strength of potential audible noise, when the

controller operates in the transition region. It is found that dip varnishing the transformer is a very effective way to

mitigate the minor audible noise around the mode transition. ABM operation with lower peak magnetizing current

through lower BUR-pin voltage can also help to minimize the potential audible noise. Generally speaking,

entering ABM at around 50 to 60% of output load and using a varnished transformer provides good balance

between the light-load efficiency and smooth mode transitions with minimal audible noise.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

I_M

0 A

ZCD

through V_aux

f_SW

ZVS

t_CSLEB

PWML

PWMH

f_BUR

2.2 µs

RUN

图 25. PWM Pattern in ABM

RUN

PWML

PWMH

RUN

PWML

PWMH

RUN

PWML

PWMH

RUN

PWML

PWMH

RUN

PWML

PWMH

图 26. Mode Transition Behavior between AAM and ABM

7.4.6 Low Power Mode (LPM)

As N_SWdrops to two in ABM and the condition of f_BURless than f_BUR(LR)is qualified under two consecutive burst

periods, UCC28780 enters into LPM mode and disables PWMH. The purpose of LPM is to provide a soft peak

current transition between V_CST(BUR)and V_CST(MIN). LPM fixes N_SWat two and sets f_BURequal to f_LPMof 25 kHz. In

LPM mode, V_CSTis controlled to regulate the output voltage. At the start of each burst packet, after RUN pulls

high, t_D(RUN-PWML)is used to wake up both the gate driver and UCC28780. With PWMH disabled, the two PWML

pulses turn on Q_Lclose to valley-switching by sensing ZCD. When ZCD is detected again at the end of the

second pulse, the RUN pin goes low and the UCC28780 enters its low-power wait state. In LPM mode, the

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minimum on-time of PWML can be further reduced to t_ON(MIN), to allow the peak magnetizing current to be

reduced beyond the level limited by t_CSLEBof the peak current loop. In this condition, operation of the LPM control

loop is changed from a current-mode control to a voltage-mode control, so the on-time adjustment of PWML is

not limited to t_CSLEB. With this feature, before f_BURstarts to fall below f_LPMand enters the audible frequency range

of SBP mode, the peak current is low enough to limit the magnitude of audible excitation.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

V_CST(MIN)/ R_CS

I_M

0 A

t_ON(MIN)

ZCD through V_AUX

PWML

f_BUR= f_LPM

PWMH

RUN

图 27. PWM Pattern in LPM

7.4.7 Standby Power Mode (SBP)

As V_CSTdrops to V_CST(MIN), UCC28780 enters into SBP mode and PWMH continues to stay disabled. The

purpose of SBP is to lower f_BURin order to minimize standby power. SBP fixes N_SWat two and V_CSTto V_CST(MIN)

,

while the burst off-time is adjusted to regulate the output voltage. As f_BURis well below f_LPM, the switching-related

loss can be minimized. In addition, lowering f_BURforces both the gate driver and UCC28780 to remain in wait

states longer to minimize the static power loss. The equivalent static current of the UCC28780 in SBP can be

represented as

2

I_VDD(SBP)= (I_RUN- I_WAIT)(

+ t_D(RUN-PWML)) f_BUR+ I_WAIT

f_{SW (SBP)}

(12)

t_D(RUN-PWML)

V_CST(MIN)/ R_CS

I_M

t_ON(MIN)

PWML

PWMH

f_BUR

RUN

I_VDD

I_RUN

I_WAIT

图 28. PWM Pattern in SBP

7.4.8 Startup Sequence

图 29 shows the simplified block diagram related with the VDD startup function of UCC28780, and 图 30

addresses the startup sequence. The detailed description on the startup waveforms is :

1. Time interval A: The UVLO circuit commands the two internal power-path switches (Q_DDSand Q_DDH) to build

connections among SWS, VDD, and HVG pins through two serial current-limiting resistors (R_DDSand R_DDH).

The depletion-mode MOSFET (Q_S) starts sourcing charge current (I_SWS) safely from the high-voltage switch-

node voltage (V_SW) to the VDD capacitor (C_VDD). Before V_VDDreaches 1 V, I_SWSis limited by the high-

resistance R_DDSof 12 kΩ to prevent potential device damage if C_VDDor VDD pin is shorted to ground.

2. Time interval B: After V_VDDrises above 1 V, R_DDSis reduced to a smaller resistance of 1 kΩ. I_SWSis

increased to charge C_VDDfaster. The maximum charge current during VDD startup can be quantified by 公式

7.

3. Time interval C: As V_VDDreaches V_VDD(ON)of 17.5 V, the ULVO circuit turns-off Q_DDSto disconnect the

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source pin of Q_Sto C_VDD, and turns-off Q_DDHto break the gate-to-source connection of Q_S, so Q_Sloses its

current-charge capability. V_DDthen starts to drop, because the 5-V regulator on REF pin starts to charge up

the reference capacitor (C_REF) to 5 V, which maximum charge current (I_SE(REF)) is self-limited at around 14

mA. After V_REFis settled, the UVLO circuit turns-on another power-path switch (Q_11H), so an internal 11-V

regulator is connected to the HVG pin. The voltage on the HVG pin capacitor (C_HVG) starts to be discharged

by the regulator.

4. Time interval D: During discharging C_HVGof the recommended 2.2 nF, the sink current of the 11-V regulator

(I_SE(HVG)) is self-limited at around 90 μA, so it takes longer than 25 μs for settling to 11 V. If V_HVGreaches 11

V in less than 10 to 25 μs, the HVG pin open fault is triggered to protect the device. Once V_HVGis settled to

11 V without the fault event, RUN pin goes high and UCC28780 enters a run state with I_VDD= I_RUN

.

5. Time interval E: There is a 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up

the gate driver and UCC28780.

6. Time interval F: This is the soft-start region of peak magnetizing current. The first purpose is to limit the

supply current if the output is short. The second purpose is to push the switching frequency higher than the

audible frequency range during repetitive startup situations. At the beginning of V_Osoft-start, the peak

current is limited by two V_CSTthresholds. The first V_CSTstartup threshold (V_CST(SM1)) is clamped at 0.28 V and

the following second threshold (V_CST(SM2)) is 0.6 V. When V_CST= V_CST(SM1), PWMH is disabled if the VS pin

voltage (V_VS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After V_VS

exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from

V_CST(SM1)to V_CST(SM2). In case of the inability to build up V_Owith V_CST(SM1)at the beginning of the V_Osoft-start

due to excessively large output capacitor and/or constant-current output load, there is an internal time-out of

1ms to force V_CSTto switch to V_CST(SM2)

.

7. Time interval G: When V_VSrises above 0.6 V, V_CSTis allowed to reach V_CST(MAX)of 0.8 V, so the rising rate

of V_Ostartup becomes faster. When PWML is in a high state, I_VDDcan be larger than I_RUN, because the 5-V

regulator provides the line-sensing current pulse (I_VSL) on the VS pin to sense V_BULKcondition.

8. Time interval H: V_Oand V_CSTsettle, and the auxiliary winding takes over the VDD supply. There is a

switching ripple on C_HVGduring PWML switching, due to the dV/dt coupling of V_SWthrough the junction

capacitance of Q_S. UCC28780 provides an over-voltage protection on HVG pin to avoid the risk of high

overshoot under high dV/dt conditions. The over-voltage threshold of HVG pin (V_HVG(OV)) is 13.8V.

I_SWS

D_AUX

I_VDD

R_SWS

C_SWS

R_DDS

Q_S

V_AUX

Q_DDS

VDD

SWS

V_SW

D_SWS

C_VDD

5-V

R_HVG

UVLO

Q_DDH

Regulator

N_A

I_REF

R_DDH

11-V

Regulator

HVG

REF

Q_11H

C_HVG

D_HVG

I_HVG

C_REF

图 29. Functional Startup Block Diagram

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V_VDD(ON)

V_TH(Qs)

V_VDD

V_HVG

V_HVG(OV)

11V

V_VDD(OFF)

V_REF

1 V

I_HVG

I_SE(HVG)

I_SWS

RUN

PWML

I_VSL

I_RUN

I_VDD

V_CST(SM2)

V_CST(MAX)

V_CST

V_CST(SM1)

V_O

(A)

(B)

(C)

(D)

(E)

(F)

(G)

(H)

图 30. Startup Timing Waveforms

7.4.9 Survival Mode of VDD

When the output voltage overshoot occurs during step-down load transients, the V_Ofeedback loop commands

the UCC28780 to stop switching quickly through increasing I_FB, in order to prevent additional energy from

aggravating the overshoot. Since V_VDDkeeps dropping during this time, the conventional way to prevent a

controller from shutting down is to oversize the VDD capacitor so as to hold V_VDDabove V_VDD(OFF). Instead,

UCC28780 is equipped with the survival-mode operation to hold V_VDDabove V_VDD(OFF)during the transient event,

so the size of VDD capacitor can be significantly reduced and the PCB footprint for the auxiliary power can be

minimized. Specifically, there is a ripple comparator to regulate V_VDDabove a 11-V threshold, which is V_VDD(OFF)

plus V_VDD(PTC)in the electrical table. The ripple regulator is enabled when the V_Ofeedback loop requests the

UCC28780 to stop switching due to V_Oovershoot.

The regulator initiates unlimited PWML pulses when V_VDDdrops lower than 11 V, and stops switching after V_VDD

rises above 11 V. Since V_VDDis lower than the reflected output voltage overshoot, most of the magnetizing

energy is delivered to the auxiliary winding and brings V_VDDabove the 11-V threshold quickly. After V_Omoves

back to the regulation level, V_Ofeedback loop forces the UCC28780 to begin switching again by reducing I_FB

,

and the PWML and PWMH pulses are then controlled by the normal operating mode.

To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival

mode at zero load, some guidelines on the auxiliary power delivery path to VDD can be considered:

1. The normal V_VDDlevel under regulated V_Omust be away from the 11-V threshold.

2. VDD capacitor should not be over-sized, but designed just big enough to hold V_VDD> V_VDD(OFF)under the

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longest V_Osoft-start time.

3. The current-limiting resistor (R_VDD1) in series with the auxiliary rectifier diode (D_AUX) should not be too large,

so the delivery path with lower series impedance can help the VDD capacitor charge faster.

4. Ensure good coupling between the auxiliary winding (N_AUX) and the secondary winding (N_S) of the

transformer.

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7.4.10 System Fault Protections

The UCC28780 provides extensive protections on different system fault scenarios. The protection features are

summarized in 表 2.

表 2. System Fault Protection

PROTECTION

VDD UVLO

SENSING

THRESHOLD

_VDD(OFF)≤ V_VDD≤ V_VDD(ON)

DELAY TO ACTION

ACTION

VDD

voltage

V

None

UVLO reset

Over-power

CS voltage

_CST(OPP)≤ V_CST≤ V_CST(MAX)

t_OPP(160 ms)

t_FDRrestart (1.5s)

protection (OPP)

Peak current limit

(PCL)

CS voltage V_CST≤ V_CST(MAX)

Over-current

protection (OCP)

CS voltage

V

_CS≥ V_OCP

3 PWML pulses

t_FDRrestart

Output short-circuit

protection (SCP)

CS, VS,

and VDD

voltages

(1) V_VDD= V_VDD(OFF)& V_CST≥ V_CST(OPP); (2) V_VDD

= V_VDD(OFF)& V_VS≤ 0.6 V

≤ t_OPP

Output over-voltage VS voltage V_VS≥ V_OVP

3 PWML pulses

t_FDRrestart

protection (OVP)

Brown-in detection

VS current

I

_VSL≤ I_VSL(RUN)

_VSL≤ I_VSL(STOP)

_NTC≤ R_NTCTH

4 PWML pulses

t_BO(60ms)

UVLO reset

Brown-out detection VS current

I

Over-temperature

protection (OTP)

NTC

voltage

R

3 PWML pulses

UVLO reset until R_NTC

R_NTCR

≥

Thermal shutdown

Junction

T_J≥ T_J(STOP)

3 PWML pulses

UVLO reset

temperature

7.4.10.1 Brown-In and Brown-Out

The VS pin senses the negative voltage level of the auxiliary winding during the on-time of low-side switch (Q_L)

to detect an under-voltage condition of the input AC line. When the bulk voltage (V_BULK) is too low, UCC28780

stops switching and no V_Orestart attempt is made until the AC input line voltage is back into normal range. As Q_L

turns on with PWML, the negative voltage level of auxiliary winding voltage (V_AUX) is equal to V_BULKdivided by

primary-to-auxiliary turns ratio (N_PA) of the transformer, which is N_P/ N_A,. During this time, the voltage on VS pin

is clamped to about 250 mV below GND. As a result, V_AUXcan create a line-sensing current (I_VSL) out of the VS

pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). With I_VSLproportional to V_BULK, it

can be used to compare against two under-voltage thresholds, I_VSL(RUN)and I_VSL(STOP)

.

The target brown-in AC voltage (V_AC(BI)) can be programmed by the proper selection of R_VS1. For every UVLO

cycle of VDD, there are at least four initial test pulses from PWML to check I_VSLcondition. I_VSLof the first test

pulse is ignored. If I_VSL≤ I_VSL(RUN)is valid for the rest three consecutive test pulses, the controller stops switching,

the RUN pin goes low, and a new UVLO start cycle is initiated after V_VDDreaches V_VDD(OFF). On the other hand, if

I_VSL> I_VSL(RUN)occurs, V_Osoft start sequence is initiated.

V_{AC(BI )}

2

V_{AC(BI )}2

N_A

R_VS1

=

N_PAì I_{VSL(RUN )}N_P365

m

A

(13)

The brown-out AC voltage (V_AC(BO)) is set internally by around 83% of V_AC(BI), which provides enough hysteresis

to compensate for possible sensing errors through the auxiliary winding. A 60-ms timer (t_BO) is used to bypass

the effect of line ripple content on the I_VSLsensing. Only when the I_VSL≤ I_VSL(STOP)condition lasts longer than 60

ms, i.e. typically three line cycles of 50 Hz, the brown-out fault is triggered. The fault is reset after V_VDDreaches

V_VDD(OFF). 图 31 shows an example of the timing sequence of brown-in and brown-out protections.

I_VSL(STOP)

V_AC(BO)

=

V_{AC(BI )}= 0.83ìV_{AC(BI )}

I_{VSL(RUN )}

(14)

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V_BULK

V_AC(BI)√2

V_AC(BO)√2

t_BOTimer

60 ms

Brown-Out Fault

V_VDD

V_VDD(ON)

V_VDD(OFF)

PWML

图 31. Timing Diagram of Brown In/Out

7.4.10.2 Output Over-Voltage Protection

VS pin senses the positive voltage level of the auxiliary winding voltage (V_AUX) to detect an over-voltage

condition of V_O. When an OVP event is triggered, UCC28780 stops switching and there is a 1.5-s fault recovery

time (t_FDR) before any V_Orestart attempt is made. As Q_Lturns off, the settled V_AUXis equal to (V_O+V_F) x N_AS

,

where N_ASis the auxiliary-to-secondary turns ratio of the transformer, N_A/ N_S, and V_Fis the forward voltage drop

of the secondary-side rectifier. The VS pin senses V_AUXthrough a voltage divider formed by R_VS1and R_VS2. The

pin voltage (V_VS) is compared with an internal OVP threshold (V_OVP). If V_VS≥ V_OVPcondition is qualified for three

consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay.

During this long delay time, only the UVLO-cycle of V_VDDis active, and there are no test pulses of PWML. After

the 1.5-s timeout is completed and V_VDDreaches the next V_VDD(OFF), a normal start sequence begins. The

calculation of R_VS2is

R_VS1ìV_OVP

R_VS1ì4.5V

R_VS2

=

N_ASì(V_O(OVP)+V_F) -V_OVP(N_A/ N_S)(V_O(OVP)+V_F) - 4.5V

(15)

The long t_FDRtimer helps to protect the power stage components from the large current stress during every

restart. After OVP is triggered, V_Omay be brought down quickly by the output load current. If OVP were reset

directly after one UVLO cycle of VDD without the 1.5-s delay, the first PWMH pulse turns on Q_Hunder the

condition of a large voltage difference between the high clamp capacitor voltage (V_CLAMP) and the low reflected

voltage. A large current can flow through the clamp switch (Q_H) and secondary rectifier. Therefore, the 1.5-s

timer of UCC28780 allows V_CLAMPto drop to a lower voltage level through a bleeding resistor (R_BLEED) in parallel

with C_CLAMPbefore the next V_Orestart attempt, such that the current stress can be minimized. A large R_BLEEDcan

be used with the long time-out to minimize the impact on standby power. For example, to discharge V_CLAMPto

10% of its normal level in 1.5 s, only 3 mW of additional standby power is added with R_BLEED= 2.8 MΩ and

C_CLAMP= 220 nF. 图 32 illustrates the timing sequence as V_CLAMPis discharged to a residual voltage (V_RESIDUAL

)

in 1.5 s. R_BLEEDalso helps to reduce the voltage overcharge on the clamp capacitor in LPM and SBP modes in

which PWMH is disabled, so the voltage stress in the passive-clamp operation can be controlled.

During LPM to ABM mode transition, it is possible to falsely trigger OVP if the setting does not have enough

design margin. In LPM mode with a disabled PWMH, the leakage energy of the transformer charges V_CLAMP

higher than the reflected voltage. When the controller enters into ABM and the PWMH is enabled, the active-

clamp circuit of ACF needs to take some time to balance the voltage difference, depending on the clamp

capacitor value. As a result, V_AUXcan sense the higher V_CLAMPcondition during the voltage balancing and the

controller may treat this as an OVP event, even though V_Ostill stays in regulation and does not reach the actual

OVP point. It may only happen with a large C_CLAMPdesign, so slightly increasing the OVP setting can resolve the

problem.

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t_FDRTimer

1.5 s

V_VDD(ON)

V_VDD

V_VDD(OFF)

V_CLAMP

N_PS(V_O+V_F)

V_RESIDUAL

PWML

图 32. Timing Diagram of C_CLAMPDischarging During 1.5-s Recovery Time

7.4.10.3 Over-Temperature Protection

The UCC28780 uses an external NTC resistor (R_NTC) tied to the NTC pin to program a thermal shutdown

temperature near the hotspot of the converter. The NTC shutdown threshold (V_NTCTH) of 1 V with an internal 105-

μA current source flowing through R_NTCresults in a 9.5-kΩ thermistor shutdown threshold. If the NTC resistance

stays lower than 9.5 kΩ for more than three consecutive PWML pulses, an OTP fault event is triggered, and the

1-V threshold is increased to 2.25 V. The NTC resistance has to increase above 21.7 kΩ to reset the OTP fault.

This threshold change provides a safe temperature hysteresis to help the hot-spot temperature cool down before

the next V_Orestart attempt, reducing the thermal stress to the components. This pin can also be used as an

electrical shutdown function by shorting this pin with a controlled switch to GND. With the pin shorted to GND,

V_VDDperforms UVLO cycling, and there is at least three consecutive PWML pulses generated to check the state.

The NTC pin can be left floating or tied to the REF pin if not used.

2.25 V

V_NTC

1 V

OTP Fault

V_VDD(ON)

V_VDD(OFF)

V_VDD

PWML

图 33. Timing Diagram of OTP with NTC

7.4.10.4 Programmable Over-Power Protection

The over-power protection (OPP) enables the ACF to operate in an over-power condition for a limited amount of

time, so the UCC28780 can support a power stage design with peak power requirements. As shown in 图 34,

when V_CSTis higher than the threshold voltage of the OPP curve (V_CST(OPP)), a 160-ms timer starts. If V_CST

remains higher than V_CST(OPP)continuously for 160 ms, the long 1.5-s timer starts and the controller stays in fault

state without switching. This long recovery time reduces the average current during a sustained over-power

event. The system benefits includes the reduction of thermal stress in high density adapters and the protection of

its output cable.

The OPP function uses I_VSLas a line feed-forward signal to vary V_CST(OPP)depending on V_BULK, in order to make

the OPP trigger point constant over a wide line voltage range. The UCC28780 allows programing of the OPP

curve by adding a line-compensation offset voltage on the CS pin through a resistor (R_OPP) connected between

the CS pin and current-sense resistor (R_CS). An internal current source flowing out of CS pin creates the offset

voltage on R_OPP. This current level is equal to I_VSLdivided by a constant gain of K_LC. As R_OPPincreases, the OPP

trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run continuously.

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The highest threshold of OPP curve (V_CST(OPP1)) of 0.6 V helps to determine R_CSvalue at V_BULK(MIN)

.

V_{CST (OPP1)}

R_CS=

P

V_{BULK (MIN )}t_{D(CST )}

2

O(OPP)

-

V_{BULK (MIN )}

h

D_MAX

L_M

(16)

where P_O(OPP)is the output power that triggers OPP, and t_D(CST)is the sum of all delays in the peak current loop

which contributes additional peak current overshoot. t_D(CST)consists of propagation delay of the low-side driver,

current sense filter delay (R_OPPx C_CS), internal CS comparator delay (t_D(CS)), and nonlinear capacitance delay of

Q_L. After R_CSis determined, R_OPPcan be adjusted to keep a similar OPP point at highest line. Note that setting

the OPP trigger point too far away from the full power may introduce more challenge on the thermal design,

since the converter runs continuously with more power as long as the corresponding peak current is slightly less

than OPP threshold.

V_OCP

V_CS(MAX)

OCP

PCL

V_CST(OPP1)

V_CST(OPP4)

OPP (R_OPP= 0 Ω)

OPP (R_OPP> 0 Ω)

I_VSL

233 µA 433 µA

966 µA

图 34. CS-Pin Related Faults

t_OPPTimer

t_FDRTimer

160ms

1.5s

V_VDD(ON)

V_VDD

V_VDD(OFF)

I_O

V_CST(MAX)

V_CST(OPP)

V_CST

V_CST(SM2)

V_CST(SM1)

PWML

V_O

图 35. Timing Diagram of OPP

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7.4.10.5 Peak Current Limit

The peak current threshold of the OPP curve is used to initiate the 160-ms timer, while the peak current limit

(PCL) determines the highest controllable peak current of the peak current loop, V_CST(MAX)= 0.8 V. In other

words, this feature provides the highest “short duration” peak power (P_O(MAX)) that the converter can reach. For

example, to supply a highest peak power of 150%, R_CSshould be chosen to ensure that the peak current at

150% load and V_BULK(MIN)must not be above V_CST(MAX). Then, the threshold of the OPP power (P_O(OPP)) can be

programmed to around 112% to support 150% peak power design, based on the following equation. Additionally,

before V_Oreaches steady state during a V_Osoft-start, the highest V_CSTcan also reach to V_CST(MAX). The

transformer must have enough design margin separating its maximum flux density from the saturation limit of the

core material under the peak current level in PCL.

V_{CST (OPP1)}

0.6V

0.8V

P

=

P

=

P

O(MAX )

O(OPP)

O(MAX )

V_{CST (MAX )}

(17)

7.4.10.6 Output Short-Circuit Protection

When an output short-circuit is applied, the peak current reaches the PCL limit and triggers the 160-ms OPP fault

timer. During this event, the VDD power supply is lost due to the auxiliary winding voltage being close to 0 V.

Without additional short-circuit detection, if V_VDDreaches V_VDD(OFF)before the 160-ms timeout, the 1.5-s recovery

time for the OPP fault cannot be triggered but only a UVLO recycle is performed. To remedy this scenario, as

V_VDDreaches V_VDD(OFF), UCC28780 checks two additional parameters to identify the short-circuit event at the

output, and initiates the 1.5-s recovery without waiting for 160 ms to expire. Specifically, when V_VDDreaches

V_VDD(OFF), if either V_CSTis greater than the OPP threshold (V_CST(OPP)) or the VS-pin voltage is less than 0.6 V, the

1.5-s recovery delay is initiated. With this additional layer of intelligence, the average load current during

continued short-circuit event can be greatly reduced, and thus also the thermal stress on the power supply.

7.4.10.7 Over-Current Protection

The UCC28780 operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS

pin is 0.15 V to 0.8 V. If the CS-pin voltage exceeds the 1.2-V over-current level, any time after the internal

leading edge blanking time (t_CSLEB) and before the end of the transformer demagnetization, for three consecutive

PWML cycles, the device stop switching, RUN pin goes low, and 1.5-s recovery time is initiated. Similar to OVP,

OPP, and SCP, only the UVLO-cycle of VDD is active, there are no test PWML pulses at all. After the 1.5-s time-

out is completed and V_VDDreaches the next V_DD(OFF), a normal start sequence begins.

7.4.10.8 Thermal Shutdown

The internal over-temperature shutdown threshold is higher than 125°C. If the junction temperature of the device

reaches this threshold, the device initiates a UVLO reset and re-start fault cycle. If the temperature is still high at

the end of the UVLO cycle, the protection cycle repeats. This internal protection is not suitable to substitute for

the NTC for the hotspot temperature protection. The NTC thermistor can provide more accurate and remote

temperature sensing with less compromise on PCB layout.

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7.4.11 Pin Open/Short Protections

As summarized in 表 3, UCC28780 strengthens the protections of several critical pins under open and short

conditions, such as CS, HVG, RDM and RTZ pins.

表 3. Protections for Open and Short of Critical Pins

DELAY TO

ACTION

PROTECTION

SENSING

CONDITION

ACTION

> 2 μs (V_SET= 5 V)

> 2 μs (V_SET= 0 V, R_RDM≥ R_RDM(TH)

> 1 μs (V_SET= 0V, R_RDM< R_RDM(TH)

PWML on-time at first PWML

pulse only

CS pin short

)

none

t_FDRrestart (1.5 s)

)

3 PWML

pulses

CS pin open

CS voltage

HVG voltage at UVLO_ON

HVG voltage

V

_CS≥ V_OCP

t_FDRrestart (1.5 s)

UVLO reset

HVG pin open

V_HVGdrops to 12 V within 10 μs

V_HVG≥ V_HVG(OV)

none

HVG pin over

voltage

3 PWML

pulses

UVLO reset

RDM pin short

RDM pin open

RTZ pin short

RTZ pin open

RDM current at UVLO_ON

RTZ current at UVLO_ON

V_RDM= 0 V, self-limited I_RDM

RDM = Open

none

UVLO reset

V_RTZ= 0 V, self-limited I_RTZ

RTZ = Open

7.4.11.1 Protections on CS pin Fault

UCC28780 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML

pulse after V_VDDstartup is completed. As shown in 图 30, the normal first on-time pulse width should be limited

by the clamped V_CST(SM1)level of 0.28 V and the rising slope of the current-loop feedback signal from the current-

sense resistor (R_CS) to the CS pin. When the current feedback path is gone due to a CS pin short to GND, the

peak magnetizing current increases and potentially can damage the power stage. Therefore, a maximum on-time

of the first PWML pulse under V_SET= 5 V, t_CSF1of 2 μs in the electrical table, is used to limit the first peak-current

stress of the silicon-based converter and then will trigger a CS pin short protection which initiates the t_FDR

recovery of 1.5 s.

Additionally, t_CSF0in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-

based converter with V_SET= 0 V. There are two corresponding values based on two predetermined ranges of the

RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically, t_CSF0is

set at 2 μs with R_RDMhigher than the R_RDM(TH)threshold of 50 kΩ, while t_CSF0is reduced to 1 μs under R_RDM

<

R_RDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency by lowering the

magnetizing inductance (L_M), it is possible that the peak current can increase higher than a lower switching-

frequency design under the same V_CST(SM1)level and same on-time of PWML. The RDM pin can provide a good

indication on the switching frequency range of a GaN power stage, since the lower L_Mrequires smaller R_RDM

setting. With a different t_CSF0setting, the CS pin fault adapts to a wide switching frequency range.

Unlike a CS pin short protection which senses the first on-time pulse width of PWML only, CS pin open

protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is

used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition.

When the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML

pulses, the CS pin open protection is triggered which initiates the 1.5-s recovery.

7.4.11.2 Protections on HVG pin Fault

As shown in 图 30, after V_VDDreaches V_VDD(ON), an internal 11-V regulator on the HVG pin should force V_HVG

back to the regulation level before PWML starts switching. If the recommended HVG-pin capacitor (C_HVG) of 2.2

nF and the connection to the depletion-mode MOSFET (Q_S) are in place, the settling time of V_HVGto 11 V is

much longer than 10 μs with a limited sink current of the regulator (I_SE(HVG)) to discharge C_HVG

.

The first fault scenario is that if C_HVGis too small, or the HVG pin is open, the pin is not able to control Q_S

correctly for the high-voltage sensing function of ZVS control, so no switching action will be performed. When

either two situations happen, V_HVGsettles to 11 V very quickly instead. Therefore, after a 10-μs delay from the

instance of V_VDDreaching V_VDD(ON), UCC28780 checks if V_HVGis below 12 V for the pin-fault detection, and then

performs one UVLO cycle of VDD directly without switching as the protection response. The above protection is

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to prevent the controller from generating PWM signals. However, when the HVG pin is open and disconnected

from the Q_Sgate, the source voltage of Q_Skeeps increasing until the TVS on the SWS pin (D_SWS) starts to clamp

the voltage continuously. To shrink the size of D_SWSwithout incurring too much thermal stress in the small

package in this fault condition, it is highly recommended that a small Zener diode (D_HVG) between Q_Sgate to

ground should be used to limit the Q_Ssource voltage. Same as D_SWS, D_HVGshould be higher than V_VDD(ON), so

as to prevent interference with normal VDD startup.

The second fault scenario is the over-voltage condition of HVG pin after the converter starts switching. When the

switch-node voltage (V_SW) rises with a high dV/dt condition, there is a charge current flowing through the junction

capacitance of Q_S, and part of the current can charge up C_HVG. If the overshoot is too large, the voltage on the

SWS pin also increases due to the nature of the depletion-mode MOSFET operation. UCC28780 detects the

overshoot event on HVG pin with an over-voltage threshold (V_HVG(OV)) of 13.8V cycle-by-cycle. When V_HVGis

higher than V_HVG(OV)for three consecutive PWML pulses, the HVG over-voltage protection is triggered which

performs one UVLO cycle of VDD.

The third fault scenario is an HVG pin short event at the beginning of VDD startup, and Q_Sis not able to charge

up the VDD capacitor to V_DD(ON), so there is no chance to enable the controller.

7.4.11.3 Protections on RDM and RTZ pin Faults

Since RDM and RTZ pins are the critical programming pins for ZVS control, UCC28780 offers both open and

short protections to those pins. After V_VDDreaches V_VDD(ON), a fixed voltage level is applied to the pin and the

corresponding current level flowing out of the pin is sensed to detect the pin fault event. As a result, too small of

a current represents the pin-open state, and too large of a current represents the pin-short state where the short

current level is self-limited. When the fault event is identified, one UVLO cycle of VDD is triggered as the

protection response.

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UCC28780

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

A typical application of a high-frequency active-clamp AC-to-DC flyback converter is to enable high-density AC-

to-DC power supply design which complies with stringent global efficiency standards. Both Silicon (Si) and

Gallium Nitride (GaN) power FETs may be used, with appropriate drivers for each.

8.2 Typical Application Circuit

The following application circuit applies to a GaN-based power stage with SET pin connected to ground, and to a

Si-based power stage with SET pin tied to the REF pin.

L_DAMP

R_DAMP

Transformer

V_BULK

C_BULK

V_O

R_SWS

R_HVG

C_HVG

L_K

L_O

Q_S

R_BLEED

D_BG

N_P

N_S

R_Co1

C_O1

R_Co2

C_O2

+

-

L_M

C_SWS

Q_SEC

C_CLAMP

D_SWS

V_IN

VD

VG VS

V_O

D_HVG

RUN

REG

VDD

UCC24612

SWS HVG

BUR

R_BIAS1

V_INV_SW

R_RDM

R_RTZ

RUN

RDM

R_FB

PWMH

PWML

VDD

RTZ

SET

REF

Half Bridge

FET + Driver

UCC28780

R_DIFF

(GaN)

C_DIFF

(Si)

R_VDD2

R_Vo1

R_BIAS2

R_BUR1

PGND

NTC VS GND CS

FB

C_VDD2

C_VDD1

Opto

coupler

C_REF

R_COMP

R_BUR2

R_OPP

R_VDD1

C_FB

C_CS

R_CS

R_INT

C_BUR

C_INT

NTC

Q_COMP

RUN

D_AUX

R_VS2

R_VS1

R_Vo2

ATL431

N_A

图 36. Typical Application Circuit

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Typical Application Circuit (接下页)

8.2.1 Design Requirements

表 4. UCC28780 Electrical Performance Specifications for GaN FET⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Input line voltage (RMS)

90 115 / 230

264

63

V

f_LINE

Input line frequency

47

50 / 60

41.1

Hz

V_IN= 115 V_RMS, I_O= 0 A

mW

P_STBY

Input power at no-load

V_IN= 230 V_RMS, I_O= 0 A

52.8

V_IN= 115 V_RMS, P_O= 250.6 mW

V_IN= 230 V_RMS, P_O= 250.6 mW

383.8

435.0

P_0.25W

Input power at 0.25W load

OUTPUT CHARACTERISTICS

V_IN= 115 V_RMS, I_O= 2.25 A

V_IN= 230 V_RMS, I_O= 2.25 A

V_IN= 115 V_RMS, I_O= 0 A

19.853

19.852

19.943

19.948

2.25

V_O

Output voltage

V

V_IN= 230 V_RMS, I_O= 0 A

I_O(FL)

Full-load rated output current

Output ripple voltage

V_IN= 90 to 264 V_RMS

A

V_IN= 115 V / 230 V_RMS, I_O= 0 A to 2.25 A

V_IN= 115 V / 230 V_RMS, I_O= 2.25 A

V_IN= 115 V / 230 V_RMS, I_O= 0 A

80

V_{O_pp}

45

mVpp

50

Over-power protection power

limit

P_O(OPP)

t_OPP

V_IN= 90 to 264 V_RMS

55

160

< 5

W

ms

%

Over-power protection duration

V_IN= 90 to 264 V_RMS, P_O= P_O(OPP)

I_Ostep between 0 A to 2.25 A

Output voltage deviation during

step load transient

ΔV_O

SYSTEMS CHARACTERISTICS

V_IN= 115 V_RMS, I_O= 2.25 A

V_IN= 230 V_RMS, I_O= 2.25 A

V_IN= 90 V_RMS, I_O= 2.25 A

V_IN= 115 V_RMS

94.59

94.74

93.98

93.88

92.47

88.69

85.86

%

η

Full-load efficiency

4-point average efficiency⁽²⁾

Efficiency at 10% load

V_IN= 230 V_RMS

V_IN= 115 V_RMS, I_O= 10% of I_O(FL)

V_IN= 230 V_RMS, I_O= 10% of I_O(FL)

η

Ambient operating temperature

range

T_AMB

V_IN= 90 to 264 V_RMS, I_O= 0 to 2.25 A

25

°C

(1) The performance listed in this table is achieved using secondary-resonance and based on the test results from a single board.

(2) Average efficiency of four load points, I_O= 25%, 50%, 75%, and 100% of I_O(FL)

.

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

8.2.2 Detailed Design Procedure

8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage

In an offline application, the input bulk capacitor (C_BULK) should be sized for the minimum input AC line voltage

(V_IN(MIN)) and minimum voltage of the input bulk capacitor (V_BULK(MIN)). Due to the transition-mode operation, too

low of V_BULK(MIN)selection results in higher RMS current at V_IN(MIN)and affects the full load efficiency, while too

high of V_BULK(MIN)enlarges the volume of the bulk capacitor. This equation does not account for the hold-up time

requirement over line drop-outs.

V_{BULK (MIN )}

P

1

O

ì[0.5+ ìarcsin(

)]

h

p

2 ìV_{IN (MIN )}

(2ìV_{IN (MIN )}²-V_{BULK (MIN )}²) ì f_LINE

C_{BULK (MIN )}

=

(18)

8.2.2.2 Transformer Calculations

8.2.2.2.1 Primary-to-Secondary Turns Ratio (N_PS

)

N_PSinfluences the design tradeoffs on the voltage rating between primary and secondary switches, and the

balance between the magnetic core and winding loss of the transformer, which are explained in detail as follows:

1. Maximum N_PS(N_PS(MAX)) is limited by the maximum derated drain-to-source voltage of Q_L(V_{DS_QL(MAX)}). In

the expression below, ∆V_CLAMPis the voltage above the reflected output voltage. It can be either the ripple

voltage of C_CLAMPin AAM mode, or the voltage over-charge of C_CLAMPby the leakage energy as Q_His

disabled in LPM mode. V_Ois the output voltage, and V_Fis the forward voltage drop of the secondary rectifier.

V_{DS _QL(MAX )}-V_{BULK (MAX )}- DV_CLAMP

N_{PS(MAX )}

=

V_O+V_F

(19)

2. Minimum N_PS(N_PS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier

(V_{DS_SR(MAX)}). In the expression for N_PS(MIN), ∆V_SPIKEshould account for any additional voltage spike higher

than V_BULK(MAX)/N_PSthat occurs when Q_His active and turns-off at non-zero current in AAM mode.

V_{BULK(MAX )}

N_{PS(MIN )}

=

V_{DS _ SR(MAX )}-V_O- DV_SPIKE

(20)

3. Since the high-frequency transformer is usually a core-loss limited design instead of a saturation-limited

design, the minimum duty cycle (D_MIN) at V_BULK(MAX)is more important. Lower D_MINincreases core loss at

V_BULK(MAX), so this constraint creates another limitation on N_PS(MIN)

.

D_MINV_{BULK(MAX )}

N_{PS(MIN )}

=

(1- D_MIN)(V_O+V_F)

(21)

4. The winding loss distribution between the primary and secondary side of the transformer is the final

consideration. As N_PSincreases, primary RMS current reduces, while secondary RMS current increases.

8.2.2.2.2 Primary Magnetizing Inductance (L_M)

After N_PSis chosen, L_Mcan be estimated based on minimum switching frequency (f_SW(MIN)) at V_BULK(MIN)

,

maximum duty cycle (D_MAX), and output power at nominal full load current (P_O(FL)). K_RESrepresents the duty cycle

loss to wait for the switch-node voltage transition from the reflected output voltage to zero. 5% to 6% of K_RESis

used as a initial estimated value. The selection of minimum switching frequency (f_SW(MIN)) has to consider the

impact on full-load efficiency and EMI filter design.

N_PS(V_O+V_F)

V_{BULK(MIN )}+ N_PS(V_O+V_F)

D_MAX

=

(22)

(23)

D_MAXV_{BULK (MIN )}²h

2

(1- K_RES

)

L_M=

ì

2P

f_{SW (MIN )}

O(FL)

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UCC28780

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8.2.2.2.3 Primary Turns (N_P)

The turn number on the primary side of the transformer (N_P) is determined by two design considerations:

1. The maximum flux density (B_MAX) must be kept below the saturation limit (B_SAT) of the magnetic core under

the highest peak magnetizing current (I_M+(MAX)) condition, a given cross-section area (A_E) of the core

geometry, and highest core temperature. When I_FB= 0 A, such as V_Osoft-start or step-up load transient, the

peak magnetizing current reaches I_M+(MAX), since V_CST= V_CST(MAX)in those conditions. I_M+(MAX)can be

calculated based on the output power triggering an OPP fault (P_O(OPP)) with V_CST= V_CST(OPP1)at V_BULK(MIN)

After N_Pis chosen, N_Scan be calculated through N_PS

.

2P

V_{CST (MAX )}

h V_{CST (OPP1)}

O(OPP)

I_{M +(MAX )}

=

D_MAXV_{BULK (MIN )}

(24)

L_MI_{M +(MAX )}

N_PA_E

B_MAX

=

< B_SAT

(25)

2. The AC flux density (ΔB) affects the core loss of a transformer. For a transition-mode active clamp flyback,

the core loss at high line is usually highest, since the switching frequency is highest and duty cycle is

smallest for a given load condition. The following equation is the ΔB calculation including the contribution of

negative magnetizing current (I_M-), used to put into the Steinmetz equation for more accurate core loss

estimation. For V_BULK≥ N_PS(V_O+V_F), I_M-is calculated with V_BULKdivided by the characteristic impedance of L_M

and the lumped time-related switch-node capacitance (C_SW). The expression of f_SWis derived based on the

triangular approximation of the magnetizing current, which also considers I_M-effect over wide AC line

condition.

C_SW

I_{M -}= -

V_BULK

L_M

(26)

P

1

O(FL)

I_IN=

D =

h

V_BULK

N_PS(V_O+V_F)

V_BULK+ N_PS(V_O+V_F)

(27)

(28)

D²V_BULK

2L_MI_IN- DL_MI_{M -}+ DV_BULKì0.5

2P

f_SW

=

p

L_MC_SW

(29)

O(FL)

2

I_{M +}

=

+ I_{M -}

h

L_Mf_SW

(30)

(31)

L_M(I_{M +}- I_{M -}

)

DB =

N_PA_E

8.2.2.2.4 Secondary Turns (N_S)

N_Sand N_Pare adjusted to the nearest suitable integers. With the new N_PS, Primary Magnetizing Inductance (L_M)

is recalculated to update the parameter change.

N_P

N_S=

N_PS

(32)

8.2.2.2.5 Turns of Auxiliary Winding (N_A)

Turns of the auxiliary winding (N_A) is an integer value usually chosen to provide a nominal V_VDDthat satisfies all

devices powered from V_VDD, such as the gate driver, UCC28780, etc. N_Ais determined by the following design

considerations:

1. V_VDDmust be lower than the maximum rating voltage of VDD pin (V_VDD(MAX)) at maximum output voltage

(V_O(MAX)). V_VDD(MAX)is limited by the lowest voltage rating of the devices connected to VDD pin.

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

V_{VDD(MAX )}

N_{A(MAX )}

=

N_S

V_{O(MAX )}+V_F

(33)

2. The nominal V_VDDshould consider the impact on the standby power. Higher V_VDDresults in the static-loss

increase with the total bias current of the devices connected to VDD pin.

3. V_VDDshould be higher than the 11-V threshold voltage of survival mode, which is the sum of V_VDD(OFF)and

V_VDD(PCT), at the minimum sustained output voltage (V_O(MIN)). ΔV represents the voltage difference between

the nominal V_VDDand the survival-mode threshold. A minimum of 3 V is a recommended design margin of

ΔV.

V_{VDD(OFF )}+V_{VDD(PCT )}+ DV

N_{A(MIN )}

=

N_S

V_{O(MIN )}+V_F

(34)

8.2.2.2.6 Winding and Magnetic Core Materials

Not only by the control of AC flux density (ΔB) with L_Mand N_Pdesign, the core loss of the transformer can also

be significantly reduced by a proper selection of the magnetic core material. For a converter operating at 200

kHz to 400 kHz of switching frequencies (at full load condition), core materials such as 3F36 from Ferroxcube

and N49 from TDK exhibit low core loss density in the frequency range. Litz wires are recommended for both

primary and secondary windings, in order to reduce the AC winding loss caused by the proximity effect and the

skin effect of the transformer windings.

8.2.2.3 Clamp Capacitor Calculation

There are two resonance approaches for an active clamp flyback (ACF) converter, primary resonance and

secondary resonance, which affect the design guide on the clamp capacitor (C_CLAMP). Referring to 图 36, if C_O1

serves as the energy-storage capacitor at the output with larger capacitance and C_O2is a high-frequency

decoupling capacitor, leakage inductance of transformer (L_K) mainly resonates with C_CLAMPduring the

demagnetization time of the magnetizing inductance (L_M). This configuration is called the primary-resonance ACF

converter. On the other hand, if C_O2serves as the energy-storage capacitor at the output with larger capacitance

and C_O1is much smaller than the equivalent capacitance of C_CLAMPreflected to the secondary side

(C_CLAMP/N_PS²), L_Kmainly resonates with C_O1. This configuration is called the secondary-resonance ACF

converter.

For primary-resonance ACF, the design tradeoff between conduction loss and turn-off switching loss of Q_Hneeds

to be considered. Higher C_CLAMPresults in less RMS current flowing through the transformer windings and

switching devices, so the conduction loss can be reduced. However, a higher C_CLAMPdesign results in Q_H

turning-off before the clamp current returns to 0 A. The condition of non zero current switching (ZCS) increases

the turn-off switching loss of Q_H. This is aggravated if the turn-off speed of Q_His not fast enough. Therefore,

C_CLAMPneeds to be fine-tuned based on the loss attribution. If the resonance between L_Kand C_CLAMPis designed

to be completed by the time Q_His turned-off, the clamp current should reach close to 0 A around three quarters

of the resonant period. The following equation can be used to design C_CLAMPfor obtaining ZCS at V_BULK(MIN)and

full load. This design results in a non-ZCS condition at V_BULK(MAX), since the switching frequency at V_BULK(MAX)is

higher in transition-mode operation. A low-ESR clamp capacitor is recommended to minimize the conduction

loss. If a ceramic capacitor is used as the low-ESR capacitor, the DC bias effect on the capacitance reduction

also needs to be considered.

L_MI_{M +(FL)}

1

2

]

C_CLAMP

=

[

L_K1.5

p

N_PS(V_O+V_F)

(35)

For secondary-resonance ACF, C_O1is used to adjust the resonance time with L_Kto fulfill the ZCS condition, so a

large C_CLAMPwill not compromise ZCS. Besides, during the on-time of low-side switch (Q_L), the small C_O1is

partially discharged by the load current at the same time. After Q_Lturns off and the resonance begins, the

discharged C_O1makes the initial resonance voltage lower than the reflected clamp capacitor voltage across

C_CLAMP, which forces more magnetizing current delivered to output, so the conduction loss is reduced with less

RMS current flowing through Q_Hand the primary winding.

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8.2.2.4 Bleed-Resistor Calculation

R_BLEEDis used to discharge the clamp capacitor voltage to a residual voltage (V_RESIDUAL) during the 1.5-s fault

delay recovery time (t_FDR). After the converter recovers from the fault mode, lower V_RESIDUALreduces the

maximum current stress (I_SHORT(MAX)) flowing through the switching devices within their respective safe operating

areas, even if the output voltage is shorted. V_RESIDUALcan be determined by the target I_SHORT(MAX)multiplied with

the characteristic impedance between the leakage inductance (L_K) and the clamp capacitor (C_CLAMP). I_SHORT(MAX)

is based on the de-rated maximum pulse current of Q_Hor the output-rectifier current reflected to the primary side,

whichever is lower. This design guide can be applied to both primary and secondary resonance ACF converters.

An excessively low value of R_BLEEDresults in over-discharging of C_CLAMP, and introduces excess continuous

power loss which affects standby power.

L_K

V_RESIDUALö I_{SHORT (MAX )}

C_CLAMP

(36)

t_FDR

R_BLEED

=

N_PS(V_O+V_F) + DV_CLAMP

C_CLAMPln[

]

V_RESIDUAL

(37)

8.2.2.5 Output Filter Calculation

The bulk output capacitor of active clamp flyback (ACF) converters, C_O1of the primary-resonance ACF or C_O2of

the secondary-resonance ACF, is often determined by the transient-response requirement from no load to full

load transition. For a target output voltage undershoot (ΔV_O) with the load step-up transient of ΔI_O, the minimum

bulk output capacitance (C_O(MIN)) can be expressed as

DI_Ot_RESP

DV_O

C_{O(MIN )}

=

(38)

where t_RESPis the time delay from the moment ΔI_Ois applied to the moment when I_FBfalls below 1 μA.

The output filter inductor (L_O) is an essential component for the secondary-resonance ACF, not only to filter the

large switching voltage ripple across C_O1but also to decouple the effect of C_O2on the resonance period. The

sum of L_Oimpedance, ESR of C_O2(R_Co2), and C_O2impedance at minimum switching frequency (f_SW(MIN)) must be

much higher than C_O1impedance at the same frequency to force most of switching resonance current to flow

through C_O1

.

1

R_Co2

L_O>>

-

(2p

f

_{SW (MIN )})²C_O1(2

p

f

_{SW (MIN )})²C_O2

2p

f_{SW (MIN )}

(39)

One benefit of lowering the ESR on C_O1(R_Co1) is to help to reduce the switching ripple on the output voltage.

Another benefit is reducing the conduction loss of C_O1for the secondary-resonance ACF converter. However, the

issue is that the damping between L_Oand C_O1is weakened. Without proper damping, the magnitude of low-

frequency resonance ripple between L_Oand C_O1enlarges output ripple, affects the loop stability, and affects the

operation of synchronous rectifier (Q_SEC). The secondary-resonance ACF converter is the most vulnerable since

C_O1with low capacitance significantly weakens the damping. To resolve this issue, it is found that a serial

damping network formed by L_DAMPand R_DAMPis a very effective way to minimize the impact. However, too strong

of a damping design results in noticeable conduction loss increase and full load efficiency drop. Therefore, it is

recommended that L_DAMPand R_DAMPshould be higher than the theoretical strong damping value as the following

equations suggest. Even though the damping network is an additional component, the physical size or the

footprint is much smaller than L_O, not only because of the small value but also the wide selection of a small-size

chip inductor which winding resistance can be a free R_DAMP. For the 45W secondary-resonance ACF design with

primary GaN FETs and a polymer-type C_O2, when a 0.68-µH chip inductor is in parallel with a 1-µH output filter

inductor, there is only 0.15% full-load efficiency drop at 90-V AC input, and there is a negligible efficiency

difference at 230-V AC input.

L_DAMP> 0.13ì L_O

(40)

L_O

R_DAMP

>

C_O1

(41)

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8.2.2.6 Calculation of ZVS Sensing Network

There are four components in the application circuit to help the depletion MOSFET (Q_S) perform ZVS sensing

safely, C_SWS, R_SWS, D_SWS, and R_HVG. Design considerations and selection guidelines for the values of these

components are given here.

At the rising edge of the switch node, the fast dV/dt coupling through the drain-to-source capacitance of Q_S

(C_OSS(Qs)) generates a charge current flowing into the capacitive loading of the Q_Ssource pin. The result is a

voltage overshoot on both the SWS pin and across the gate-to-source of Q_S(V_GS(Qs)). The SWS pin, with an

absolute maximum voltage of 38 V, can handle higher voltage stress than V_GS(Qs). Therefore, a capacitor

between the SWS pin and GND (C_SWS) should be selected properly to prevent the voltage overshoot from

damaging the Q_Sgate. Since C_OSS(Qs)and C_SWSform a voltage divider, the minimum C_SWS(C_SWS(MIN)) can be

derived as

C_OSS(Qs)ì[V_{BULK (MAX )}+ N_PS(V_O+V_F)]

C_{SWS(MIN )}

=

- C_Dsws

V_HVG+V_{GS _ MAX (Qs)}

(42)

where V_{GS_MAX(Qs)}is the de-rated maximum gate-to-source voltage of Q_S, V_HVGis the steady-state voltage level

of 11 V, and C_Dswsis the parasitic capacitance of TVS diode (D_SWS) on the SWS pin.

Without resistive damping, both the charge current on the rising edge of V_SWand the discharge current on the

falling edge of V_SWare oscillatory with the parasitic inductance within the ZVS sensing network resonating with

C_SWS. Therefore, a series resistor (R_SWS) between SWS pin and source-pin of Q_Sis used to dampen the high-

frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency

current from interfering with other noise-sensitive signals. R_SWScan be expressed as:

L_SWS

R_SWS

>

C_SWS+ C_Dz

(43)

where L_SWSis the lumped parasitic inductance including the packaging of Q_Sand PCB traces of Q_Sand C_SWS

return path.

Based on the above design guide, even though R_SWSand C_SWSmay be sufficient to manage the voltage

overshoot in normal operation, a low-capacitance TVS diode (D_SWS) is still highly recommended to serve as a

safety backup of the ZVS sensing network. A regular Zener diode is not suitable due to its high capacitance and

slow clamping response.

Based on the above equations, a general recommendation is that a 50 V C0G-type ceramic capacitor of 22 pF

for C_SWS, a chip resistor no higher than 120 Ω for R_SWS, and a TVS diode with the clamp voltage between 18 V

to 24 V for D_SWS. Too large of R_SWSor C_SWSintroduces a sensing delay between V_SWand SWS pin, so the ZVS

control pulls down V_SWearlier than expected before the end of t_Zby unnecessarily extending t_DM. The

recommended R_SWSand C_SWSvalues only introduce a minor 2.6-ns delay, so the ZVS control is not be affected.

Another issue with too large of R_SWSis that an additional voltage drop may be created by the charge current

through C_OSS(Qs)during high dV/dt events of V_SW, which becomes another voltage stress onto the gate-to-source

voltage of Q_S. For the power stage that can generate very high dV/dt, lowering R_SWSand increasing C_SWSmay

be necessary to enhance the protection on Q_S. Alternatively, a back-to-back TVS can be added between the

gate and source pins of Q_Sto provide a direct clamping to the possible over-voltage stress condition.

Furthermore, a high-impedance discharge resistor (R_HVG) between the gate and source pins of Q_Shelps to

discharge the residual voltage on the gate capacitance, and R_HVGaround 1 MΩ should be enough to serve the

purpose. Note that too small R_HVGcan hurt standby power, since it creates a continuous current flowing through

Q_S.

8.2.2.7 Calculation of Compensation Network

UCC28780 integrates two control concepts to benefit high-efficiency operation: peak current-mode control and

burst ripple control. The peak current loop in AAM can be analyzed based on the linear control theory, so the

compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic

of an active clamp flyback converter. For transition-mode operation, the power stage can be modeled as a

voltage-controlled current source charging an output capacitor (C_O) with an equivalent-series resistance (R_Co

)

and the output load (R_O) as shown in 图 37. The first-order plant characteristic and high switching frequency

operation in AAM make the peak current loop easier to stabilize than ABM.

43

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^

Equivalent Circuit of ACF

V_O

^

K_FV_BULK

K_EI_FB

R_Co

C_O

R_O

R_E

H_V(s)

Compensation

V_O(REF)

^

I_FB

图 37. Small-Signal Model of ACF in AAM Loop

The adaptive burst mode (ABM) is a ripple-based control, so the linear control theory for AAM cannot be applied.

The most critical stability criterion of burst control is to make the burst ripple content of I_FBto be in-phase with the

burst ripple voltage of V_O. In normal operation, the fundamental burst frequency (f_BUR) in ABM varies between 20

kHz and 40 kHz. An example of normal burst operation is illustrated in 图 38.

f_BUR

RUN

PWML

V_CST(BUR)

V_CS

图 38. Expected Burst Pattern Example

Strong phase-delay in the frequency range creates slope distortion around the intersection point between I_FBand

I_TH(FB), so the ripple regulator generates inconsistent burst off-times. As shown in 图 39, the sub-harmonic

oscillation at half of f_BURis a typical phenomenon of an unstable ABM loop. Two burst packets are adjacent to

each other and the pulse count (N_SW) is different by one pulse count.

f_BUR/ 2

RUN

PWML

V_CST(BUR)

V_CS

图 39. Typical Behavior of Unstable ABM Loop

44

UCC28780

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Passive Ripple

Compensation

V_O

R_DIFF

C_DIFF

R_BIAS1

REF

FB

C_FB

I_FB

I_OPTO

R_Vo1

V_FB(REG)

CTR

I_D

R_FBI

R_FB

I_COMP

I_FB

R_BIAS2

RUN

C_opto

Control

Law

Active Ripple

Compensation

C_INTR_INT

R_Vo2

ATL431

图 40. Compensation Network, H_v(s)

In order to minimize the phase-delay of I_FB, the transfer function from I_FBto V_Oguides the pole/zero placement of

the secondary-side passive ripple compensation network in 图 40. In the primary-side control circuitry, two poles

at ω_FBand ω_OPTOintroduce phase-delay on I_FB. ω_FBpole is formed by the external filter capacitor C_FBand the

parallel resistance of the internal R_FBIand the external current-limiting resistor (R_FB). ω_OPTOpole is formed by the

parasitic capacitance of the optocoupler output (C_OPTO) and the series resistance of R_FBIand R_FB. For C_FB= 100

pF, R_FBI= 8 KΩ, and R_FB= 20 KΩ, the delay effect of ω_FBpole located at 278 kHz is negligible. However, ω_OPTO

pole is located less than 10 kHz, and introduces large phase delay in the interested f_BURrange of ABM, since

C_OPTOis in a few nF range contributed by the Miller effect of the collector-to-base capacitance of the BJT in the

optocoupler output. Therefore, an RC network (R_DIFFand C_DIFF) in parallel with R_BIAS1is used to compensate the

phase-delay of the optocoupler, which introduces an extra pole/zero pair located at ω_P1and ω_Z1respectively. The

basic design guide is to place the ω_Z1zero close to the ω_OPTOpole, and to place ω_P1pole away from highest f_BUR

.

(44)

(45)

(46)

(47)

(48)

(49)

I_FB(s) CTR 1+ (s / w_{Z 0}

)

1

1+ (s / w_Z1

)

1

=

V_O(s) R_BIAS1(s /

w_{Z 0}) 1+ (s /

w

_P1) 1+ (s / _OPTO) 1+ (s / w_FB)

w

1

w_{Z 0}

w_Z1

w_P1

=

(R_Vo1+ R_INT)C_INT

1

(R_DIFF+ R_BIAS1)C_DIFF

1

R_DIFFC_DIFF

1

w_OPTO

w_FB

=

(R_FB+ R_FBI)C_OPTO

1

=

(R_FBI/ /R_FB)C_FB

45

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Case 2: Larger I_FBripple

Case 1: Small I_FBripple

I_FB

∆I_FB

I_FB

Noise

floor

Noise

floor

I_REF

∆I_FB

RUN

∆t_BUR

图 41. Effect of Signal-to-Noise Ratio of i_FBto ABM Operation

Another guideline of obtaining a more consistent burst off-time is to maintain large enough ripple amplitude of I_FB

in ABM mode (ΔI_FB) for better signal-to-noise ratio. 图 41 shows that when the noise floor alters the intersection

point of each burst cycle, larger ΔI_FBperforms much less burst off-time variation if the noise floor stays the same.

ΔI_FBaround 10 μA is a recommended initial design value. The ripple ratio (K_RIPPLE) between ΔI_FBand the burst

voltage ripple of V_Oin ABM (ΔV_O(ABM)) is obtained by simplifying the small-signal gain of I_FB(s)/V_O(s) transfer

function between 20 kHz and 40 kHz.

DI_FB= K_RIPPLEìDV_{O( ABM )}ö10

I_FB(s)

mA

(50)

CTR w_OPTOCTR (R_DIFF+ R_BIAS1)C_DIFF

K_RIPPLE

ô

ö

=

V_o(s)

R_BIAS1w_Z1

R_BIAS1(R_FB+ R_FBI)C_OPTO

20kHz< f <40kHz

(51)

With the above understanding on burst control, the step-by-step design procedure is:

1. R_FBselection needs to consider both the output voltage regulation and compensation challenge on the low-

frequency pole at ω_OPTO. R_FBshould be less than the maximum value of 28 kΩ to provide a sufficient

feedback current of 95 μA for the output voltage regulation in SBP mode, under the worst-case V_FB(REG)and

R_FBI. R_FB= 28 kΩ and C_OPTO= 2 nF result in the ω_OPTOpole located at 2.8 kHz. Such a low-frequency pole

forces the ω_Z1zero to be designed around 2.8 kHz to compensate the phase-delay.

V_FB(REG)-V_CE(OPTO)

R_{FB(MAX )}

=

- R_FBI

I_FB(SBP)

(52)

2. R_BIAS1is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔV_O(ABM), and target

10 μA of ΔI_FBas example.

CTR

R_BIAS1

=

DV_{O( ABM )}

=

DV_{O( ABM )}

DI_FB

10mA

(53)

3. C_DIFFis designed to position ω_Z1≈ ω_OPTOand locate ω_P1at least two-times higher frequency than 2π x

f_BUR(UP)as example.

(4

p

f_BUR(UP)) -w_OPTO

f_BUR(UP))ìw_OPTO

1

w_P1

-

ì

w_Z1

1

C_DIFF

=

R_BIAS1w_P1

w_Z1R_BIAS1(4

p

(54)

4. R_DIFFis designed to position ω_P1two-times higher than 2π x f_BUR(UP), but lower than the switching frequency

in ABM (2π x f_SW(BUR)). Too small of R_DIFFmoves ω_P1higher than 2π x f_SW(BUR), so the high differentiation gain

on the secondary-side compensator amplifies the switching ripple and increases the noise floor. Therefore,

R_DIFFshould be fine-tuned based on the actual noise level of a given design.

1

R_DIFF

=

w

_P1C_DIFF

4p

f

_BUR(UP)C_DIFF

(55)

5. R_INTselection is not designed for the small-signal compensation, but to resolve the slow large-signal

response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load

occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage

continuously by the integrator configuration of ATL431 until the output voltage gets back to normal regulation

level. If the load step-up transient happens before the output voltage is settled from the previous load step-

down event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a

46

UCC28780

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ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

new steady-state. Since the time for ATL431 moving from lower voltage to a high voltage delays i_FB

reduction, the controller response from SBP mode to AAM mode is delayed as well, which slows down the

energy delivery to the output and results in a large voltage undershoot. To resolve this problem, R_INT

behaves like a current-limiting resistor for C_INT, which slows down the reduction on the cathode voltage of

ATL431. R_INTneeds to be adjusted based on the voltage undershoot requirement under the lowest repetitive

rate of load change.

47

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

8.2.3 Application Curves

96

97

95

93

91

89

87

85

83

115V_AC

90V_AC

95

94

93

230V_AC

264V_AC

85

115

145

175

205

235

265

0

25

50

Output Load (%)

75

100

AC Input Voltage (V_AC

)

图 42. Full-Load Efficiency in Universal AC Line

图 43. Light-Load Efficiency in Universal AC Line

V_O

PWML

图 44. Output Voltage Ripple at V_IN= 115 V_RMSand I_O

=

图 45. Output Voltage Ripple at V_IN= 115 V_RMSand I_O= 0.9

2.25 A

A

48

UCC28780

www.ti.com.cn

PWML

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

350

300

250

200

150

PWMH

V_SW

I_PRI

85

115

145

175

205

235

265

AC Input Voltage (V_AC

)

图 47. Switching Frequency in Universal Line and I_O= 2.25

A

图 46. AAM Waveforms at V_IN= 230 V_RMSand I_O= 2.25 A

PWML

PWMH

PWML

PWMH

V_SW

I_PRI

图 48. ABM Waveforms at V_IN= 115 V_RMSand I_O= 0.9 A

图 49. ABM Waveforms at V_IN= 115 V_RMSand I_O= 0.2 A

49

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

PWML

PWMH

V_O

V_SW

I_O

I_PRI

图 51. Load Transient between 0 A to 2.25 A at V_IN= 115

V_RMS

图 50. SBP Waveforms at V_IN= 115 V_RMSand I_O= 0 A

140

PWML

130

120

110

100

RUN

V_DD

I_PRI

85

115

145

175

205

235

265

AC Input Voltage (V_AC

)

图 52. OPP Level in Universal AC Line

图 53. Fault Delay Recovery of OPP

50

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

9 Power Supply Recommendations

The UCC28780 is intended to control active clamp flyback (ACF) converters in high efficiency offline applications,

and is optimized to be used with universal AC input, from 85 V_ACto 265 V_AC, at 47 Hz to 63 Hz. An external

depletion-mode MOSFET connected between the switch node of the converter and the SWS / HVG pins of this

controller is required to charge the VDD capacitor during start-up, and to perform ZVS sensing during normal

operation. Once the V_VDDreaches the UVLO turn-on threshold at 17.5 V, the VDD rail should be kept within the

limits of the Bias Supply Input section of Specifications. To avoid the possibility that the device might stop

switching, V_VDDmust not be allowed to fall below the UVLO turn-off threshold at 9.8 V.

51

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

The active clamp flyback converter (ACF) designed with the UCC28780 not only recovers clamp energy but also

eliminates switching loss with minimum circulating energy, so higher switching frequencies, efficiencies, and

greater power densities can be achieved. However, when designing for higher switching frequencies, good layout

practices as discussed below need to be followed to ensure for a more reliable and robust design.

10.1.1 General Considerations

Designing for high power density requires to consider noise coupling and thermal management. A four-layer PCB

structure is highly recommended to use inner layers to help reduce current loop areas and provide heat-

spreading for surface-mount semiconductors.

•

Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for

MOSFETs and power diodes.

To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas with high-frequency

switching voltage.

To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal

tracks in parallel with such loops.

图 54 summarizes the critical layout guidelines, and more detail will be also be further elaborated in the

descriptions below.

52

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Layout Guidelines (接下页)

Minimize the high di/dt switching loops to reduce EMI, voltage

stress on power devices, and noise coupling on control loop.

V_AC

V_BULK

V_O

L_O

N_P

N_S

C_O1

R_BLEED

C_CLAMP

C_O2

C_BULK

Q_H

D_BG

Keep signal and

power ground

separate

Q_SEC

Output

Power

Ground

UCC24612

High-Side Driver

+ Level Shifter

Star grounding for less common ground noise:

- Keep signal and power ground separate

- Connect grounds close to C_BULKand R_CS

Control loop away

from dB/dt coupling

of transformer

R_CS

V_SW

Q_L

Keep compensator

away from dV/dt, di/dt,

or dB/dt noise sources

Power

Ground

Shorten high dV/dt

traces for less EMI

and noise coupling;

Orthogonally across

other traces

Low-side

Driver

Shorten V_SWStrace with

dV/dt; away from

feedback loop

Separate C_SWSand

D_SWSground return

Enable

R_BIAS1

C_SWS

R_SWS

R_HVG

V_SWS

R_DIFF

C_DIFF

R_Vo1

Q_S

D_SWS

R_OPPand R_FB

R_BIAS2

close to IC and the

filter capacitor for less

dV/dt coupling

R_OPP

D_HVG

Shorten V_AUXtrace with

dV/dt; away from

feedback loop

R_INT

C_INT

OPTO

COUPLER

PWML RUN PWMH

UCC28780

HVG

CS

ATL431

SWS

VDD

VS

C_HVG

R_VDD1

R_Vo2

R_FB

V_AUX

C_VDD

FB

Secondary Signal

Ground Plane

D_AUX

N_A

C_FB

C_CS

SET

R_COMP

Q_COMP

REF

BUR NTC RDM RTZ

R_VS1

R_VS2

GND

Minimize the high

di/dt switching loops

C_REF

C_BUR

Minimize FB loop and

away from dV/dt, di/dt,

or dB/dt noise sources

RUN

R_BUR1

Primary Signal

Ground Plane

R_BUR2

图 54. Schematic with Layout Considerations

10.1.2 RDM and RTZ Pins

Minimize stray capacitance to RDM and RTZ pins.

•

Place R_RDMand R_RTZas close as possible between the controller pins and GND pin.

Avoid putting ground plane under RDM and RTZ pins to reduce parasitic capacitance. This can be

accomplished by putting cutouts in the ground plane below these pins.

10.1.3 SWS Pin

Minimize potential stray noise coupling from SWS pin to noise-sensitive signals.

•

Keep some distance between SWS pin and other connections.

The RC damping network (R_sws, C_sws) and the TVS diode (D_SWS) should be as close to the source pin of Q_S

as possible instead of SWS pin, so the gate-to-source pin of Q_Scan be effectively protected.

•

Keep the return path for di/dt current through C_SWSand D_SWSseparate from the IC local GND and FB signal

return paths.

53

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Layout Guidelines (接下页)

10.1.4 VS Pin

Minimize stray capacitance at the VS pin to reduce the time delay effect on ZVS control.

•

Avoid putting GND plane under VS Pin to reduce parasitic capacitance. This can be accomplished by putting

a cutout in the ground plane below this pin.

10.1.5 BUR Pin

The resistor divider (R_BUR1and R_BUR2) and the filter capacitor (C_BUR) on the BUR pin should to be as close to the

BUR pin and IC GND as possible.

•

It is recommended to provide shielding on the BUR-pin trace with ground planes to minimize the noise-

coupling effect on peak current variation during burst-mode operation. This can be accomplished by adding a

ground plane under the BUR traces and pins.

10.1.6 FB Pin

This pin can be noise-sensitive to capacitive coupling from the high dV/dt switch nodes, or the flux coupling from

magnetic components and high di/dt switching loops.

•

Minimize the loop area for the PCB traces from the opto-coupler to the FB pin in order to avoid the possible

flux coupling effect.

•

Keep PCB traces away from the high dV/dt signals, such as the switch node of the converter (V_SW), the

auxiliary winding voltage (V_AUX), and the SWS-pin voltage (V_SWS). If possible, it is recommended to provide

shielding for the FB trace with ground planes.

•

The filter capacitor between FB pin and REF pin (C_FB) needs to be as close to the two IC pins as possible.

The current-limiting resistor of FB pin (R_FB) should be as close to the FB pin as possible to enhance the noise

rejection of nearby capacitively-coupled noise sources.

10.1.7 CS Pin

The OPP-programming resistor (R_OPP) and the filter capacitor (C_CS) should be as close to the CS pin as possible

to improve the noise rejection of nearby capacitively-coupled noise sources, and to filter any ringing that may be

present during non-ZVS conditions.

10.1.8 GND Pin

The GND pin is the bias-power and signal ground connection for the controller. The effectiveness of the filter

capacitors on the signal pins depends upon the integrity of the ground return.

•

Place the decoupling and filter capacitors on VDD, REF, CS, and HVG pins as close as possible to the device

pins and GND pin with short traces.

The device ground and power ground should meet at the return of the current-sense resistor (R_CS). Try to

ensure that high frequency/high current from the power stage does not go through the signal ground.

The thermal pad of the QFN package should be tied to the IC GND pin with a short trace, and be connected

to the signal ground plane with multiple vias which becomes a low-impedance ground return of external

components to the GND pin.

10.2 Layout Example

The layout techniques described in above sections were applied to the layout of the 45-W 20-V high-density GaN

active clamp flyback converter. 图 55 and 图 56 are the schematics of the evaluation module (EVM), the other

figures are the layout of each layer, which critical traces are highlighted.

54

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Layout Example (接下页)

图 55. Schematic A of the 45-W EVM

图 56. Schematic B of the 45-W EVM

55

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

Layout Example (接下页)

Isolation Boundary

Ground Plane Shielding

Make Current Loops as Small and Short as Possible

图 57. Top Assembly and First Layer of PCB

Add Multiple Vias to Increase Current Handling Capability and Dissipate Heat Through PCB and PCB Copper

图 58. Second Layer of PCB

56

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

Layout Example (接下页)

Signal Ground Plane

Remove Ground Plane Under RDM, RTZ and VS Pins to Reduce Capacitance

图 59. Third Layer of PCB

Get Supporting Resistors and Capacitors as Close

to the UCC28780 as Possible

图 60. Bottom Assembly and Fourth Layer of PCB

57

UCC28780

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

如需相关文档，请参阅：

•

使用 UCC28780EVM-002 45W 20V 高密度 GaN 有源钳位反激式转换器

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

58

UCC28780

www.ti.com.cn

ZHCSH21A –OCTOBER 2017–REVISED FEBRUARY 2018

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

59

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC28780DR

UCC28780RTER

UCC28780RTET

SOIC

WQFN

D

16

2500

3000

250

330.0

180.0

16.4

12.4

6.5

3.3

10.3

3.3

2.1

1.1

8.0

16.0

12.0

Q1

Q2

RTE

3.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC28780DR

UCC28780RTER

UCC28780RTET

SOIC

WQFN

D

16

2500

3000

250

340.5

367.0

210.0

336.1

367.0

185.0

32.0

35.0

RTE

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

UCC28780D

D

16

40

507

8

3940

4.32

Pack Materials-Page 3

GENERIC PACKAGE VIEW

RTE 16

3 x 3, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225944/A

www.ti.com

PACKAGE OUTLINE

RTE0016C

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

6

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

SIDE WALL

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

1.68 0.07

(DIM A) TYP

5

8

EXPOSED

THERMAL PAD

12X 0.5

4

9

4X

SYMM

17

1.5

1

12

0.30

16X

0.18

PIN 1 ID

(OPTIONAL)

13

16

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.68)

SYMM

13

16

16X (0.6)

1

12

16X (0.24)

SYMM

(2.8)

17

(0.58)

TYP

12X (0.5)

9

4

(

0.2) TYP

VIA

5

8

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.55)

16

13

16X (0.6)

1

12

16X (0.24)

17

SYMM

(2.8)

12X (0.5)

9

4

METAL

ALL AROUND

5

8

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	UCC28780D
厂家：	TEXAS INSTRUMENTS
描述：	1MHz 高频有源钳位反激式控制器 \| D \| 16 \| -40 to 125 控制器开关光电二极管
文件：	总70页 (文件大小：3709K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28780D [TI]

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