UCC28781_技术文档

UCC28781

ZHCSOY9 – DECEMBER 2021

UCC28781 具有专用同步整流器栅极驱动的

零电压开关反激式控制器

1 特性

3 说明

•

开关频率：> 500 kHz

UCC28781 是一款零电压开关 (ZVS) 控制器，可用于

超高开关频率，从而充分减小变压器尺寸并实现高功率

密度。

实现超过 93% 的峰值效率

实现低于 45mW 的待机功耗

零电压开关 (ZVS) 自适应控制和死区时间优化

EMI 频率抖动，无需权衡瞬态响应或可闻噪声

具有内部补偿的可编程自适应突发模式 (ABM)

X 电容器放电能力

该控制器采用直接同步整流器 (SR) 控制，可直接驱

动 SR FET，充分提高效率并简化设计，因此无需独

立 SR 控制器。（隔离式应用需要隔离式栅极驱动器

IC。）

过热、过压、输出短路、过流、过功率和引脚故障

保护

自动恢复故障响应

4 mm x 4 mm 24 引脚 QFN 封装

ZVS 采用自适应死区时间控制，可有效降低开关损耗

和 EMI。该设计使控制器在整个工作范围内具有极高

转换效率。

•

可编程自适应突发模式 (ABM) 可灵活控制控制器进入

和退出待机模式的时机，从而降低轻负载和空载待机功

耗。ABM 还有助于减少纹波并有效降低可闻噪声。

2 应用

•

条形音箱

智能扬声器

商用网络和服务器 PSU

电器电池充电器

商用电池充电器

工业交流/直流电源

该控制器提供多种具有自动重启（重试）响应功能的保

护模式。

器件信息

器件型号

封装⁽¹⁾

封装尺寸

UCC28781

WQFN (24)

4.00mm x 4.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

C_X

~

Isolated driver

(primary side)

V_OUT

–

+

Isolated driver

(secondary side)

P13

PGND

SWS

P13

VS

AGND

FB

XCD

REF

CC/CV

controller

T

简化版应用

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSEP2

UCC28781

ZHCSOY9 – DECEMBER 2021

www.ti.com.cn

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................7

6.4 Thermal Information....................................................7

6.5 Electrical Characteristics.............................................7

6.6 Typical Characteristics..............................................13

7 Detailed Description......................................................16

7.1 Overview...................................................................16

7.2 Functional Block Diagram.........................................18

7.3 Detailed Pin Description............................................19

7.4 Device Functional Modes..........................................36

8 Application and Implementation..................................57

8.1 Application Information............................................. 57

8.2 Typical Application Circuit.........................................57

9 Power Supply Recommendations................................67

10 Layout...........................................................................68

10.1 Layout Guidelines................................................... 68

10.2 Layout Example...................................................... 71

11 Device and Documentation Support..........................76

11.1 Documentation Support.......................................... 76

11.2 支持资源..................................................................76

11.3 Trademarks............................................................. 76

11.4 静电放电警告...........................................................76

11.5 术语表..................................................................... 76

12 Mechanical, Packaging, and Orderable

Information.................................................................... 77

4 Revision History

DATE

REVISION

NOTES

December 2021

*

Initial release.

English Data Sheet: SLUSEP2

2

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5 Pin Configuration and Functions

24

23

22

21

20

19

FLT

RTZ

RDM

IPC

1

2

3

4

5

6

18

17

16

15

14

13

XCD

SWS

PWMH

P13

Thermal

Pad

BUR

FB

S13

7

8

9

10 11 12

图 5-1. RTW Package, 24-Pin WQFN (Top View)

表 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5

V. A 50-µA current source interfaces directly with an external NTC (negative temperature coefficient)

thermistor to AGND pin for remote temperature sensing. The current source is active during the run

state and inactive during the wait state. A 50-µs fault delay allows a filter capacitor to be placed on

the FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state

from a wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input

capacitor voltage for line-OVP detection, and a 750-µs fault delay helps to prevent false triggering

the 4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and

ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be

implemented on CS pin.

FLT

1

I

A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage

from the turn-off edge of the PWMH signal to the turn-on edge of the PWML signal. Parasitic

capacitance between this pin and any other net, including AGND, must be minimized to avoid noise

coupling and its effect on the dead-time calculation.

RTZ

2

3

I

A resistor between this pin and AGND pin programs a synthesized demagnetization time used to

control the on-time of the PWMH signal to achieve zero voltage switching on the primary switch. The

controller applies a voltage on this pin that varies with the output voltage derived from the VS pin

signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized

to avoid noise coupling and its effect on the internal PWMH on-time calculation.

RDM

This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-µA current

source directly interfaces with a resistor (R_IPC) to AGND pin to program an increase in the peak

current level at very light load; the burst frequency can be further reduced, helping to achieve low

standby power and tiny-load power. If the IPC pin is connected to AGND without R_IPC, the peak

current level in very light load is set to a minimum level for the output ripple or audible noise sensitive

designs. R_IPCcan also be connected between this pin and the CS pin or IPC pin can be directly

connected to CS pin, so the 50-µA IPC current can create an output voltage dependent offset voltage

on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at

lower output voltage level of a wide output voltage range design.

IPC

4

I

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English Data Sheet: SLUSEP2

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表 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

This pin is used to program the burst threshold of the converter at light load. A resistor divider

between REF and AGND is used to set a voltage at BUR to determine the peak current level when

the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on BUR is used

to activate offset voltages for smooth mode transitions. A 2.7-µA pull up current increases the peak

current threshold when the converter enters low-power mode (LPM) from ABM. A 5-µA pull down

current reduces the peak current threshold when the converter enters into high-power mode (adaptive

amplitude modulation, AAM) from ABM.

BUR

5

I

A current signal is coupled to this pin to close the converter regulation feedback loop. This pin

presents a 4.25-V output that is designed to have 0-µA to 75-µA current pulled out of the pin

corresponding to the converter operating from full-power to zero-power conditions. A 220-pF filter

capacitor between FB pin and REF pin is recommended to desensitize the feedback signal from noise

interference.

FB

6

I

This pin is a 5-V reference output that requires a 0.22-µF ceramic bypass capacitor to the AGND pin.

This reference is used to power internal circuits and can supply a limited external load current. Pulling

this pin low shuts down PWM action and initiates a VDD restart.

REF

7

8

O

G

Analog ground and the ground return of PWMH and RUN drivers. Return all analog control signals to

this ground.

AGND

This is the current-sense input pin. This pin couples to the current-sense resistor through a line-

compensation resistor to control the peak primary current in each switching cycle. An internal current

source on this pin, proportional to the converter’s input voltage, creates an offset voltage across the

line-compensation resistor to balance the over-power protection (OPP) threshold level across input

line. The CS pin can also provide an alternative OTP function, when the FLT pin is being used

for the line input-OVP. A small-signal diode in series with an NTC resistor is connected between

PWMH pin and CS pin to form the OTP detection. When PWMH is high, the NTC resistor and the

line-compensation resistor become a resistor divider from 5 V and creates a temperature dependent

voltage on CS pin. When CS pin voltage is higher than 1.2 V in PWMH on state for 2 consecutive

cycles, the OTP fault on CS pin is triggered.

CS

9

I

This output pin is high when the controller is in the run state. This output is low during start-up, wait,

and fault states. A 2.2-µs timer delays the initiation of PWML switching after this pin has gone high

and S13-pin voltage is above its 10-V power-good threshold. The pull-up driving capability of both

RUN and PWMH pins allows bias power management of a digital isolator through a common-cathode

small-signal diode, so the power consumption can be reduced in the wait state.

RUN

10

11

O

G

Low-side ground return of the PWML driver to the primary switch. The internal level shifter allows the

common return impedance to be eliminated and improves higher frequency operation by decoupling

the additional voltage spike on the current-sense resistor and layout parasitic inductance of the gate

driving loop. For a silicon (Si) power FET, this pin can be connected to the source for a smaller gate

driving loop. For a GaN power IC with a logic PWM input, this pin can be connected to AGND.

PGND

For a GaN-based gate-injection transistor (GIT), this pin can be directly connected to the separate

source pin of a GIT GaN device, which enhances the turn-off speed.

Primary switch gate driver output. The high-current capability (-0.5A/+1.9A) of PWML enables driving

of a silicon power MOSFET with higher capacitive loading, a GIT GaN with continuous on-state

current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped to the

P13 pin voltage.

PWML

S13

12

13

O

S13 is a switched bias-voltage source coupled to P13 through an internal 2.8-Ω switch controlled by

the RUN pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V by an internal

current limiter. The S13 pin voltage must increase above 10 V to initiate PWML switching. When RUN

is low, S13 is discharged by its load. The power-on delay of any device powered by S13 must be less

than 2 µs to be responsive to PWML. A 22-nF ceramic capacitor between S13 and the driver ground

is recommended. S13 can also perform power management on a PFC controller at the same time

through a diode, such that PFC can be disabled at very light-load condition.

P13 is a regulated 13-V bias-voltage source derived from V_VDD. During V_VDDstartup, P13 pin is

connected to the VDD pin internally, so an external high-voltage depletion MOSFET, such as BSS126,

can provide controlled startup current to charge the VDD capacitor. After the initial startup, P13

recovers back to 13-V regulation. A 1-µF ceramic bypass capacitor is required from P13 to AGND.

A 20-V Zener diode between P13 and AGND is recommended to protect this pin from overstress,

such as if the connection between this pin and the depletion MOSFET gate is fail-open or if line surge

energy is coupled to this pin.

P13

14

O

4

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English Data Sheet: SLUSEP2

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表 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

PWM output signal used to control the gate of a secondary-side synchronous rectifier (SR) MOSFET

through an external isolating gate driver. The driving capability is designed to bias a level-shifting

isolator through a small-signal diode, or can also transmit the signal to secondary-side driving circuitry

through a pulse transformer. The maximum voltage level of PWMH is clamped to REF.

PWMH

15

O

This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal

operation for ZVS auto-tuning. The source of a high-voltage depletion-mode MOSFET, such as

BSS126, is coupled to this pin through a current-limiting resistor so only the useful switching

characteristic below 15 V is monitored. During start-up, this pin is connected to the VDD pin internally

to allow the depletion-mode MOSFET to provide start-up current. The external current-limit resistor

and a small bidirectional TVS across gate and source should be added to protect the V_GSfrom

potential abnormal voltage stress. The resistor should be higher than 500 Ω and less than 820 Ω.

The clamping voltage of TVS should be less than the MOSFET voltage rating but greater than 15

V. Moreover, the resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input

capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS

characteristic correctly.

SWS

16

I

X-cap Discharge input pins with 2-mA maximum discharge current capability. A line zero-crossing

(LZC) threshold of 6.5 V on XCD is used to detect AC-line presence. When LZC is not detected within

an 84-ms test period, the discharge current is enabled for a maximum period of 300 ms followed

by a no-current blanking time of 700 ms. When AC-line recovers and LZC is detected again, the

controller can reset the fault state almost immediately and will attempt to restart without waiting to

fully discharge the bulk input capacitor. For the auto-recovery fault protections, if the controller is in

1.5-s auto-recovery fault state, LZC can reset the timer and speed up the restart attempt. The two

redundant XCD pins help to provide the X-cap discharge function even when one pin is in fail-open

condition. To form the discharge path, an anode of two high-voltage diode rectifiers is connected

to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ high-voltage

current-limiting resistance, and the drain-to-source connection of a high-voltage depletion MOSFET

couples the resistance to the XCD pins. Two series 13-kΩ SMD resistors in 1206 size can be used

as the current limiting device, and share the potential transient voltage from the AC-line. A 600-V

rated MOSFET such as BSS126 is needed as the high voltage blocking device. The MOSFET gate is

connected to the P13 pin, so the XCD pins can obtain enough signal headroom for LZC detection. If

the X-cap discharge function is not needed, XCD pins must be connected to AGND pin to disable the

function, and the diode-resistor-MOSFET path must be removed.

XCD

17, 18

I

Controller bias power input. A ceramic capacitor with 10-µF or 15-µF capacitance is recommended,

and the minimum voltage rating is 25 V.

VDD

19

P

GTP1

GTP2

GTP3

20

21

22

G

Ground This Pin. This pin must be connected to AGND for proper operation of the device.

This voltage-sensing input pin is coupled to an auxiliary winding of the converter’s transformer via a

resistor divider. The pin and associated external resistors are used to monitor the output and input

voltages and switching edges of the converter at different moments within each switching cycle.

Parasitic capacitance between VS and any net, including AGND, must be minimized to avoid adverse

effects on output voltage sensing, edge detection, and the dead-time calculation.

VS

23

24

I

This pin is used to configure the controller to be optimized for gallium nitride (GaN) power FETs or

silicon (Si) power FETs on the primary side. Depending on the setting, it will optimize parameters of

the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it

is optimized for Si FETs. When pulled low to AGND, it is optimized for GaN FETs.

SET

I

Thermal

Pad

G

The thermal pad (TP) must be connected to AGND.

(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power

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English Data Sheet: SLUSEP2

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ZHCSOY9 – DECEMBER 2021

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

VDD

38

SWS

–6

–10

–20

–0.3

–0.75

–1

38

SWS (transient, negative pulse width of 20 ns max., duty cycle ≤ 1%)

38

VDD-SWS

CS

38

3.6

Input Voltage

VS

7

V

VS (transient, 100 ns max.)

PGND

7

–1

4

PGND (transient, 25 ns max.)

RTZ, BUR, SET, RDM, IPC, FLT, FB

XCD

5

–0.3

7

30

REF, PWMH, RUN

P13, S13, PWML

REF, P13, RTZ, RDM, IPC

S13 (average)

7

Output Voltage

V

20

Self–limiting

15

VS

2

VS (transient, 100 ns max.)

2.5

Source Current FB

RUN (continuous)

1

mA

5

PWML (continuous)

PWMH (continuous)

CS (transient, 30 ns max.)

RUN (continuous)

PWML (continuous)

PWMH (continuous)

SWS

50

10

1

8

50

10

Sink Current

mA

Self–limiting

XCD

25

0.3

FLT

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

150

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001¹

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002²

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

English Data Sheet: SLUSEP2

6

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

14

NOM

MAX

UNIT

V

V_VDD

C_VDD

C_P13

C_REF

T_J

Bias supply operating voltage

VDD capacitor

34

10

µF

°C

P13 bypass capacitor

1

REF bypass capacitor

Operating junction temperature

0.22

–40

140

6.4 Thermal Information

UCC28781

THERMAL METRIC¹

RTW (WQFN)

24 PINS

43.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

31.6

Junction-to-board thermal resistance

20.3

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

Ψ_JB

20.3

R_θJC(bot)

5.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD INPUT

I_RUN(STOP)

I_RUN(SW)

I_WAIT

Supply current, run state

Supply current, wait state

Supply current, start state

Supply current, fault state

No switching

0.88

2.45

465

150

2.2

3

2.66

3.55

658

301

630

mA

µA

Switching, I_VSL= 0 µA

I_FB= -85 µA, I_VDDonly

V_VDD= V_VDD(ON)- 100 mV, V_VS= 0 V

fault state

540

235

500

I_START

I_FAULT

VDD startup current limit

during startup

V_VDDincreasing, V_SWS- V_VDD= 1 V,

V_VDD= 16.5 V

I_VDD(LIMIT)

1.2

2

2.53

mA

V_VDD(ON)

V_VDD(OFF)

VDD turnon threshold

VDD turnoff threshold

V_VDDincreasing

V_VDDdecreasing

16.2

9.94

17

17.91

11.17

V

10.6

Offset to power cycle

for long output voltage

overshoot

V_VDD(PCT)

Offset above V_VDD(OFF), I_FB= -85 µA

1.54

2.2

2.98

V

P13 OUTPUT

P13 voltage level including 0 mA to 60 mA out of P13, run state,

V_P13

12.0

1.53

12.8

2.2

13.6

3.04

V

load regulation

V_VDD= 20 V

Max sink current of P13 pin

during startup

I_P13(START)

V_P13= 14 V

mA

Current sourcing limit of

P13 pin

I_P13(MAX)

VR13_(LINE)

V_P13(OV)

P13 shorted to AGND, V_VDD= 20 V

V_VDD= 15 V to 35 V

103.3

-6

133

2

160

8.7

mA

mV

V

Line regulation of V_P13

Over voltage fault threshold

above V_P13

1.35

2

2.54

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Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Dropout resistance of P13

regulator switch between

VDD and P13 pins

(V_VDD- V_P13) / 30 mA, V_VDD= 11 V,

30 mA out of P13

R_P13

8.5

13

22.7

Ω

S13 OUTPUT

R_S13

R_DS(on)of internal

disconnect switch between

P13 and S13 pins

(V_P13- V_S13) / 30 mA, V_VDD= 11 V,

30 mA out of S13

2.1

2.8

3.82

Ω

S13_OK threshold to

enable switching

V_{S13_OK}

I_S13(MAX)

V_RUN= 5 V

9.63

10.2

350

10.7

V

Current sourcing limit of

S13 pin

S13 shorted to AGND, V_VDD= 20 V

260.7

452.5

mA

REF OUTPUT

V_REF

REF voltage level

I_REF= 0 A

4.9

5

5.13

20.3

V

Current sourcing limit of

REF pin

I_REF(MAX)

REF shorted to AGND, V_VDD= 20 V

14.3

17

mA

VR5_(LINE)

VR5_(LOAD)

VS INPUT

V_VSNC

Line regulation of V_REF

Load regulation of V_REF

V_VDD= 12 V to 35 V

-7

-3

1

mV

0 mA to 1 mA out of REF, Change in V_REF

-16

0.1

25

Negative clamp level

I_VSL= -1.25 mA, voltage below ground

V_VSdecreasing

221

12.4

287

35

344

67.2

mV

µA

Zero-crossing detection

(ZCD) level

V_ZCD

I_VSB

Input bias current

V_VS= 4 V

-0.23

242.4

0

0.31

VS threshold voltage in

SM1 startup mode

V_VS(SM1)

282

318.3

mV

VS threshold voltage in

SM2 startup mode

V_VS(SM2)

458.3

2.41

500

543

2.6

mV

V

VS upper threshold out of

low output voltage mode

(LV mode)

V_VSLV(UP)

V_VSincreasing

V_VSdecreasing

2.49

VS lower threshold into low

output voltage mode (LV

mode)

V_VSLV(LR)

t_ZC

2.3

1.95

23

2.39

2.3

50

2.49

2.73

81

V

Zero-crossing timeout delay

µs

ns

Propagation delay from

ZCD high to PWML 10%

high

t_D(ZCD)

V_VSstep from 4 V to -0.1 V

CS INPUT

I_VSL= 0 μA, V_VS≥ V_VSLV(UP)

I_VSL= -333 μA, V_VS≥ V_VSLV(UP)

I_VSL= -666 μA, V_VS≥ V_VSLV(UP)

I_VSL= -1.25 mA, V_VS≥ V_VSLV(UP)

I_VSL= 0 mA, V_VS≤ V_VSLV(LR)

I_VSL= -666 μA, V_VS≤ V_VSLV(LR)

I_VSL= -1.25 mA, V_VS≤ V_VSLV(LR)

767.4

650

801

727

600

570

628

570

540

836.4

788.7

651.8

612

mV

Peak-power threshold on

CS pin out of LV mode

V_CST(MAX)

570

537.2

593.7

540

663.9

609.5

584.7

Peak-power threshold on

CS pin in LV mode

V_{CST(MAX)_LV}

511.2

Minimum CS threshold

voltage

V_CST(MIN)

K_LC

V_CSincreasing, I_FB= -85 µA

120.7

21.6

78.4

153

25

200.1

29

mV

A/A

mV

Line-compensation current

ratio

I_VSL= -1.25 mA, I_VSL/ current out of CS pin

EMI dithering magnitude on (V_BUR/ K_BUR-CST) < V_CST< V_CST(MAX)

CS pin out of LV mode I_VSL> -646 μA, V_VS≥ V_VSLV(UP)

,

1 2

V_CST(EMI)

96

113.6

English Data Sheet: SLUSEP2

8

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Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EMI dithering magnitude on (V_BUR/ K_BUR-CST) < V_CST< V_CST(MAX)

,

1 2

V_{CST(EMI)_LV}

V_CST(SM1)

V_CST(SM2)

29.3

36

42.7

mV

CS pin in LV mode

I_VSL> -646 μA, V_VS≤ V_VSLV(LR)

V_VS< V_VS(SM1)

CS threshold voltage in

SM1 startup mode

177.5

470.4

200

500

222.9

531.4

mV

CS threshold voltage in

SM2 startup mode

V_VS< V_VS(SM2)

V_SET= 5 V, V_CS= 1 V

V_SET= 0 V, V_CS= 1 V

171.2

94.4

190

108

216.1

125

ns

t_CSLEB

Leading-edge-blanking time

Propagation delay of CS

t_D(CS)

comparator high to PWML V_CSstep from 0 V to 1 V

90 % low

10

20

26

23

37

27

ns

EMI dithering frequency on (V_BUR/ K_BUR-CST) < V_CST< V_CST(OPP)

,

1 2

f_DITHER

kHz

CS pin

I_VSL> -646 μA

BUR INPUT and Low-power MODE

K_BUR-CST

I_BUR(LPM)

Ratio of V_BURto V_CST

V_BURbetween 0.7 V and 2.4 V

3.82

2.09

3.98

2.65

4.09

3.16

V/V

µA

Bias source current of V_BUR

offset in LPM

Bias sink current of V_BUR

offset in AAM

I_BUR(AAM)

f_BUR(UP1)

f_BUR(UP2)

f_BUR(LR)

f_LPM

V_CST> V_BUR/ K_BUR-CST

3.76

30.7

41.8

21.3

23.3

4.85

34.4

51.2

24.5

25

5.81

38.5

58.9

28.1

26.9

µA

First upper threshold of

burst frequency in ABM

kHz

Second upper threshold of

burst frequency in ABM

V_VS= 2.2 V

Lower threshold of burst

frequency in ABM

Burst frequency in low-

power mode

IPC INPUT and SBP2 MODE

Highest programmable

V_CSTrange of SBP2 by IPC V_IPC= 5 V

V_{CST_IPC(UP)}

373.8

405

438.5

mV

Ratio of the programmable

IPC voltage to V_CST

K_IPC

V_IPCbetween 1.8 V and 3.8 V

V_IPC= 1 V

59.3

247.5

128.1

40.7

6

64

273

154

49

68.4

307.7

191.5

55.7

13.4

2

mV/V

mV

Lowest programmable V_CST

range of SBP2 by IPC pin

V_{CST_IPC(LR)}

V_{CST_IPC(MIN)}

I_IPC(SBP2)

f_SBP2(UP)

f_SBP2(LR)

Minimum V_CSTof SBP2 by

grounding IPC pin

V_IPC= 0 V

mV

Bias source current of V_IPC

offset in SBP2

I_FB= -85 µA

µA

Upper threshold of burst

frequency in SBP2

8.5

1.7

kHz

Lower threshold of burst

frequency in SBP2

V_IPC= 2 V

1

RUN

V_RUNH

V_RUNL

RUN pin high-level

RUN pin low-level

I_RUN= -0.2 mA

I_RUN= 1 mA

4.6

0.1

4.78

0.25

5

V

0.3

V_RUN= 2.3 V

V_RUN= 3 V

33

14

44

20

52

25

mA

I_SRC(RUN)

RUN peak source current

Turn-on rise time of RUN

pin, from 0 V to 2.5 V

t_R(RUN)

C_LOAD= 22 nF, V_RUNfrom 0 V to 2.5 V

0.2

0.79

1

µs

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Product Folder Links: UCC28781

English Data Sheet: SLUSEP2

UCC28781

ZHCSOY9 – DECEMBER 2021

www.ti.com.cn

Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Turn-off fall time of RUN

pin, 90 % to 10 %

t_F(RUN)

C_LOAD= 10 pF

20

32

ns

PWML

V_PWMLH

PWML pin high-level

PWML pin low-level

I_PWML= -1 mA

I_PWML= 1 mA

12.1

12.85

0.002

0.5

13.6

0.1

0.8

2.8

6.1

1.9

V

A

Ω

V_PWMLL

1

I_SRC(PWML)

I_SNK(PWML)

PWML peak source current V_PWML= 0 V

0.25

1.2

3.1

0.5

PWML peak sink current

PWML pull-up resistance

V_PWML= 13 V

1.9

R_SRC(PWML)

R_SNK(PWML)

I_PWML= -20 mA

4.3

PWML pull-down resistance I_PWML= 20 mA

1.1

Turn-on rise time of PWML

C_LOAD= 1.5 nF

t_R(PWML)

30

9

53

20

ns

µs

ns

pin, 10 % to 90 %

Turn-off fall time of PWML

C_LOAD= 1.5 nF

t_F(PWML)

pin, 90 % to 10 %

Delay from RUN high to

V_S13> 11 V

t_D(RUN-PWML)

t_ON(MIN)

1.92

68

4.7

105

7.43

180

PWML high

Minimum on-time of PWML

in LPM

V_SET= 5 V, I_FB= -85 µA, V_CS= 1 V

PWMH

V_PWMHH

PWMH pin high-level

PWMH pin low-level

I_PWMH= -1 mA

I_PWMH= 1 mA

4.39

0.1

4.66

4.83

0.21

V

V_PWMHL

0.198

V_PWMH= 2.5 V

V_PWMH= 3.5 V

16.5

3.8

21

6

26.2

7.6

mA

I_SRC(PWMH)

PWMH peak source current

Turn-on rise time of PWMH

pin, 10 % to 90 %

t_R(PWMH)

C_LOAD= 10 pF

8

22

18

24

29

28

ns

Turn-off fall time of PWMH

pin, 90 % to 10 %

t_F(PWMH)

Dead time between VS high

and PWMH 10 % high

t_D(VS-PWMH)

10

PROTECTION

V_OVP

Over-voltage threshold

Over-current threshold

V_VSincreasing

V_CSincreasing

4.4

4.55

1.22

4.67

1.27

V

V_OCP

1.14

Ratio of over-power

threshold to peak-power

threshold

V_CST(OPP)/ V_CST(MAX), and

V_{CST(OPP)_LV}/ V_{CST(MAX)_LV}

K_OPP-PPL

0.72

0.75

0.78

V/V

I_VSL(RUN)

I_VSL(STOP)

K_VSL

VS line-sense run current

Current out of VS pin increasing

313

255

365

305

408.6

336.4

0.9

µA

VS line-sense stop current Current out of VS pin decreasing

VS line sense ratio

I_VSL(STOP)/ I_VSL(RUN)

0.72

0.836

A/A

R_RDMthreshold for CS pin

fault

R_RDM(TH)

35

55

70

kΩ

Thermal-shutdown

temperature

1

T_J(STOP)

Internal junction temperature

I_FB= 0 A

125

130

162

164

55

°C

ms

3

t_OPP

OPP fault timer

210

Brown-out detection delay

time

t_BO

I_VSL< I_VSL(STOP)

28.8

85.2

Maximum PWML on-time

for detecting CS pin fault

t_CSF1

t_CSF0

V_SET= 5 V

1.6

2.05

2.5

µs

Maximum PWML on-time

for detecting CS pin fault

R_RDM< R_RDM(TH)for V_SET= 0 V

0.85

1.2

1.05

1.5

1.27

2.4

µs

s

3

t_FDR

Fault reset delay timer

OCP, OPP, OVP, SCP or CS pin fault

English Data Sheet: SLUSEP2

10

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Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FLT INPUT

V_NTCTH

NTC shut-down voltage

FLT voltage decreasing

0.47

8.9

0.5

9.91

23

0.52

11.18

26.4

V

R_NTCTH

R_NTCR

NTC shut-down resistance R_NTCdecreasing

kΩ

NTC recovery resistance

R_NTCincreasing

V_FLT= 4.5 V

21.2

Input bias current for V_FLT

at V_IOVPTH

I_FLT

-0.1

4.3

0

0.1

µA

V

Shut-down voltage of input

OVP

V_IOVPTH

FLT voltage increasing

FLT voltage decreasing

4.5

4.67

V_IOVPR

Hysteresis of input OVP

Delay time of NTC fault

57.7

14

74

50

87

mV

µs

t_FLT(NTC)

100

Delay time of input OVP

fault

t_FLT(IOVP)

555

750

5.5

917

µs

V

V_FLTZ

Clamp voltage of FLT pin

I_FLT= 150 µA

5.08

5.61

RTZ INPUT

ratio of t_Zat I_VSL= -200 µA to

t_Zat I_VSL= -733 µA

K_TZ

t_Zcompensation ratio

1.27

1.41

478

1.54

s/s

ns

Maximum programmable

t_Z(MAX)

dead time from PWMH low R_RTZ= 280 kΩ, I_VSL= -1 mA, V_SET= 5 V

to PWML high

397.8

592.8

Minimum programmable

t_Z(MIN)

dead time from PWMH low R_RTZ= 78.4 kΩ, I_VSL= -1 mA, V_SET= 0 V

to PWML high

56.1

70

89.1

ns

I_VSL= -200 µA

152.2

129.2

109.7

175

150

125

212.7

190

ns

Dead time from PWMH low

to PWML high

t_Z

I_VSL= -450 µA

I_VSL= -733 µA

147.2

SWS INPUT

V_SET= 5 V

SWS zero voltage threshold

V_SET= 0 V

8.1

3.7

8.5

9.1

4.4

V

V_TH(SWS)

4.04

Time between SWS low to

V_SWSstep from 5 V to 0 V

PWML 10 % high

t_D(SWS-PWML)

FB INPUT

I_FB(SBP)

11.4

17

26

ns

Maximum control FB

I_FBincreasing

current

64.2

75

87.1

µA

V_FB(REG)

R_FBI

Regulated FB voltage level

FB input resistance

4.02

7.4

4.25

8.3

4.53

9.6

V

kΩ

Slope of internal ramp

compensation current

dI_COMP/dt¹

0.192

4

0.214

6.75

0.236

8

A/s

µA

Magnitude of internal ramp

compensation current

I_COMP

RDM INPUT

t_DM(MAX)

Maximum PWMH width

V_SWS= 12 V

6.0

3.0

6.95

3.43

7.53

3.77

µs

with maximum tuning

Minimum PWMH width with

V_SWS= 0 V

t_DM(MIN)

minimum tuning

XCD INPUT

V_XCD(LR)

XCD lower zero-crossing

threshold

5.9

6.8

6.62

7.5

7.2

7.9

V

XCD upper zero-crossing

threshold

V_XCD(UP)

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Product Folder Links: UCC28781

English Data Sheet: SLUSEP2

UCC28781

ZHCSOY9 – DECEMBER 2021

www.ti.com.cn

Unless otherwise stated: V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ, V_VS= 4 V,

V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Leakage current in XCD

wait state

I_XCD(0)

I_XCD(1)

I_XCD(2)

I_XCD(3)

I_XCD(4)

V_XCD= 15 V

0.3

1.7

µA

First-step XCD sense

current

0.32

0.61

0.73

1.2

0.4

0.775

1.15

0.46

0.91

1.6

mA

Second-step XCD sense

current

Third-step XCD sense

current

Fourth-step XCD sense

current

1.53

1.81

Maximum XCD discharge

current

I_XCD(MAX)

V_XCD(OVP)

t_XCD(STEP)

1.65

23

9

2

26

12

2.5

30

mA

V

Clamp voltage of XCD OVP I_XCD= 20 mA

Dwell time for each XCD

sense step

14.6

ms

Maximum XCD discharge

time

t_XCD(MAX)

t_XCD(WAIT)

230.4

300

700

373.3

1071

ms

XCD wait time

(1) Specified by design. Not production tested.

(2) The EMI-Dither feature is disabled in UCC28781A.

(3) The OPP feature is disabled in UCC28781A.

English Data Sheet: SLUSEP2

12

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6.6 Typical Characteristics

V_VDD= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_SET= 0 V, and T_J= T_A= 25 ⁰C (unless otherwise noted)

10

I_RUN

I_WAIT

1

I_RUN(STOP)

I_FAULT

0.1

0.01

1

I_RUN(WAIT)

I_START

0.1

0.001

0

5

10

15

20

25

30

35

40

45

-50

-25

0

25

50

75

100

125

V_VDD- Bias Supply Voltage (V)

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-1. VDD Bias-Supply Current vs. VDD Bias-

图 6-2. VDD Bias-Supply Current vs. Temperature

Supply Voltage

415

395

4

3

(V_CST(MIN)- 0.15 V) / 0.15 V

2

I_VSL(RUN)

375

(V_CST(MAX)- 0.8 V) / 0.8 V

1

355

0

-1

-2

-3

-4

335

I_VSL(STOP)

315

295

275

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-3. VS Line-Sense Currents vs. Temperature

图 6-4. Percentage Variation of Maximum and

Minimum CS Thresholds vs. Temperature

0.9

0.8

V_CST(MAX)at 25öC

0.8

0.7

0.6

0.5

V_{CST(MAX)_LV}at 25öC

V_{CST(MAX)_LV}at -40öC

V_{CST(MAX)_LV}at 125öC

V_CST(MAX)at -40öC

V_CST(MAX)at 125öC

0.7

0.6

0.5

0

200

400

600

800

1000

1200

1400

1600

0

200

400

600

800

1000

1200

1400

1600

I_VSL- VS Line-Sense Current (mA)

图 6-5. CS Peak-Power Threshold for V_VS

>

图 6-6. CS Peak-Power Threshold for V_VS

<

V_VSLV(UP)vs. VS Line-Sense Currents

V_VSLV(LR)vs. VS Line-Sense Currents

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Product Folder Links: UCC28781

English Data Sheet: SLUSEP2

UCC28781

ZHCSOY9 – DECEMBER 2021

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1.5

1.4

1.3

1.2

1.1

1

4.6

4.56

4.52

4.48

4.44

4.4

K_TZat 25öC

K_TZat -40öC

K_TZat 125öC

0.9

0

200

400

600

800

1000

1200

1400

1600

I_VSL- VS Line-Sense Current (JA)

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-7. t_ZCompensation Ratio (K_TZ) vs. VS Line-

图 6-8. VS Over-Voltage Threshold vs. Temperature

Sense Currents

5.06

5.04

5.02

5

13.1

13

12.9

12.8

12.7

12.6

12.5

4.98

4.96

4.94

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-9. REF Voltage vs. Temperature

图 6-10. P13 Voltage vs. Temperature

25

23

21

19

17

15

13

11

9

7.6

7.4

7.2

7

V_XCD(UP)

R_NTCR

6.8

6.6

6.4

R_NTCTH

V_XCD(LR)

7

5

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-12. XCD Thresholds vs. Junction Temperature

图 6-11. FLT OTP Thresholds vs. Junction

Temperature

14

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ZHCSOY9 – DECEMBER 2021

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2.4

2.3

2.2

2.1

2

1.9

1.8

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

图 6-13. Max. XCD Discharge Current vs. Junction Temperature

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English Data Sheet: SLUSEP2

UCC28781

ZHCSOY9 – DECEMBER 2021

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7 Detailed Description

7.1 Overview

The UCC28781 is a transition-mode zero-voltage-switching flyback (ZVSF) controller equipped with advanced

control schemes to enable significant size reduction of passive components for higher power density and higher

average efficiency. Its control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a

single-switch flyback configuration at high frequencies. In burst mode at very light loads the switching frequency

may increase up to 1.5 MHz.

The ZVSF control of the UCC28781 controller is capable of auto-tuning the on-time of a secondary-side

synchronous rectifier switch (Q_SR) by using a unique lossless ZVS-sensing network connected between the

switch-node voltage (V_SW) and the SWS pin. The ZVSF controller is designed to adaptively achieve targeted full-

ZVS or partial-ZVS conditions for the primary-side main switch (Q_L) with minimum circulating energy over wide

operating conditions. Auto-tuning eliminates the risk of losing ZVS due to component tolerance, temperature,

and input/output voltage variations, since the Q_SRon-time is corrected cycle-by-cycle.

Dead-times between PWML (controls Q_L) and PWMH (controls Q_SR) are optimally adjusted to help minimize the

circulating energy required for ZVS as operating conditions change. Therefore, the overall system efficiency is

improved and more consistent in mass production of the soft-switching topology. The programming features of

the RTZ, RDM, BUR, IPC, and SET pins provide rich flexibility to optimize the power stage efficiency across a

range of output power and operating frequency levels.

The controller uses five different steady-state operating modes to maximize efficiency over wide load and line

ranges:

1. At higher load levels, adaptive amplitude modulation (AAM) adjusts the peak primary current.

2. In the medium-load range, adaptive burst mode (ABM) modulates the pulse count of each burst packet.

3. In the light-load range, low power mode (LPM) reduces the peak primary current of each two-pulse burst

packet.

4. During very light-load conditions, stand-by power mode 1 (SBP1) minimizes the power loss.

5. During no-load conditions, stand-by power mode 2 (SBP2) minimizes the power loss.

During the system transient events such as the output load step down and output voltage overshoots, V_VDDmay

be reduced close to the 10.5-V UVLO-off threshold. In such cases, a sixth non-steady-state mode called survival

mode (SM) is triggered to maintain V_VDDabove 13 V and to reduce the size of the hold-up VDD capacitor.

Except in the UCC28781A version, the switching frequency-dither function is active in AAM to help reduce

conducted-EMI noise and allow EMI filter size reduction. The 23-kHz dithering pattern and magnitude are

designed to avoid audible noise, minimize efficiency influence, and desensitize the effect of the output voltage

feedback loop response effect on the EMI attenuation. The dither function at low line can be programmed into

disable mode based on the brown-in voltage setting, so the option provides design flexibility to balance the

worst-case low-line efficiency and EMI. The dither fading feature smoothly disables the dither signal when the

output load is close to the transition point between AAM and ABM. The 23-kHz dither frequency is high enough

to allow a higher control-loop bandwidth for improved load transient response without distorting the dither signal

and impairing EMI. The frequency-dithering function is disabled in the UCC28781A.

The unique burst mode control in ABM, LPM, and two SBP modes maximizes the light-load efficiency of the

ZVSF power stage while avoiding the concerns of conventional burst operation - such as high output ripple

and audible noise. The internal ramp compensation can stabilize the burst control loop without an external

compensation network. The burst control provides an enable signal through the RUN pin to dynamically manage

the static current of the SR gate-driver and also adaptively disables the drive signal of Q_SR. The internal drivers

of RUN and PWMH can supply and disconnect the 5-V bias voltage to a digital isolator through a small-signal

diode. The disconnect switch inside the S13 pin can directly control the 13-V bias voltage to a low-side GaN

driver. These power management functions with RUN, PWMH, and S13 pins can be used to minimize the

quiescent power consumed by those devices during burst off time, further improving the converter’s light-load

efficiency and reducing its stand-by power.

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The S13 and IPC pins of the controller can be adapted to manage an upstream PFC stage to maximize the

light-load efficiency of higher power applications. The S13 pin can supply a 13-V bias voltage to the PFC

controller whenever the ZVSF controller is in the run state. The pin disconnects the bias voltage during the wait

states of the burst mode operation. When the burst frequency is reduced in very light load conditions, the bias

voltage will decay below UVLO and shut down PFC controller, so the power loss from PFC can be eliminated.

The PWML output is a strong driver for a Si power MOSFET with high capacitive loading, a GaN-based gate

injection transistor (GIT) with continuous on-state current, or a GaN power IC with logic input. The maximum

voltage level of PWML is clamped at 13 V to balance the conduction loss reduction and gate charge loss of Si

MOSFET. A dedicated driver ground return pin (PGND) minimizes the parasitic impedance and noise coupling

of the PWML gate-drive loop to achieve faster switching speed and reduced turn-off loss of Q_L. The short 15-ns

propagation delay and narrow 110-ns minimum on-time enable more accurate ZVS control and higher switching

frequency operation.

During initial power up or VDD restart, the ZVSF stops switching, so the controller starts up the VDD supply

voltage with an external high-voltage depletion-mode MOSFET between the ZVSF switch node and the SWS

pin. Fast startup is achieved with low stand-by power overhead, compared with using the conventional high-

voltage startup resistance to VDD. Moreover, the P13 pin biases the gate of the depletion-mode FET to also

allow this MOSFET to be used in lossless ZVS-sensing. This arrangement avoids additional sensing devices.

The enhanced switching control of controller mitigates excessive drain-to-source voltage stress on a

synchronous rectifier (SR) caused by temporary continuous conduction mode (CCM), so the power loss of

an SR snubber can be reduced for higher efficiency. Additional PWML timing controls can avoid premature

Q_Lturn-on before the magnetizing current reaches to zero through an improved zero-crossing detection (ZCD)

scheme of the VS pin.

The controller also integrates more robust protection features tailored to maximize system reliability and safety.

These features include active X-capacitor discharge, internal soft start, brown in/out, output over-voltage (OVP),

input line over-voltage (IOVP), output over-power (OPP) (except not in UCC28781A), system over-temperature

(OTP), switch over-current (OCP), output short-circuit protection (SCP), and pin faults. All fault responses are

auto-recovery, which means that the controller will attempt to restart after the shut-down time elapses. The

over-power protection (OPP) function is disabled in the UCC28781A.

The X-capacitor discharge function can actively discharge the residual voltage on X2 safety capacitors to a safe

level after AC-line voltage removal is detected through the XCD pins of the UCC28781 controller and its external

sensing circuit. If the AC-line voltage recovers within two seconds after the line removal, the controller resets the

fault state immediately and attempts to restart without waiting to fully discharge the bulk input capacitor or VDD

capacitor. Grounding the two XCD pins disables this function and eliminates the sensing circuit. Unlike other

conventional flyback controllers, the UCC28781 controller provides the design flexibility of using the X-capacitor

discharge function based on application power level as it is decoupled from VDD startup and brown-in/out

detection functions. Because those two functions are implemented on the SWS and VS pins, respectively, the

controller maintains the two functions even when the XCD-related components are fully removed.

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7.2 Functional Block Diagram

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7.3 Detailed Pin Description

7.3.1 BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (V_BUR) sets a target peak current-sense threshold at the CS pin (V_CST(BUR)) which

programs the onset of adaptive burst mode (ABM). V_BURalso determines the clamped peak current level of

switching cycles in each burst packet. When V_BURis set higher, ABM will start at heavier output load conditions

with higher peak primary current, so the benefit is higher light-load efficiency but the side effect is larger

burst-mode output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest

load condition to enter ABM (I_o(BUR)) for both Si and GaN-based designs. The gain between V_BURand V_CST(BUR)

is a constant gain of K_BUR-CST, so setting V_CST(BUR)just requires properly selecting the resistor divider on the

BUR pin formed by R_BUR1and R_BUR2. V_BURshould be set between 0.7 V and 2.4 V. If V_BURis less than 0.7 V,

V_CST(BUR)holds at 0.7 V / K_BUR-CST. If V_BURis higher than 2.4 V, V_CST(BUR)stays at 2.4 V / K_BUR-CST

.

R

_BUR1K_BUR-CSTV_{CST (BUR)}

4ì R_BUR1V_{CST (BUR)}

R_BUR2

=

V_REF- K_BUR-CSTV_{CST (BUR)}5V - 4ìV_{CST (BUR)}

(1)

In order to enhance the mode transition between ABM and LPM, a programmable offset voltage (ΔV_BUR(LPM)

)

is generated on top of the V_BURsetting in ABM through an internal 2.7-μA current source (I_BUR(LPM)), as shown

in 图 7-1. In ABM, V_BURis set through the resistor voltage divider to fulfill the target average efficiency. On

transition from ABM to LPM, I_BUR(LPM)is enabled in LPM and flows out of the BUR pin, so ΔV_BUR(LPM)can be

programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

(

//

)

(2)

I_O

I_BUR(LPM)

LPM

REF

ûV_BUR(LPM)

R_BUR1

V_BUR

ûV_BUR(AAM)

BUR

ABM

LPM

R_BUR2

ABM

I_BUR(AAM)

C_BUR

图 7-1. Hysteresis Voltage Generation on BUR Pin

When V_BURsteps higher on transition into LPM, the initial peak magnetizing current in LPM is increased with

larger energy per switching cycle in each burst packet. This increases the output voltage which forces higher

feedback current to restore regulation. Higher feedback current causes UCC28781 to stay in LPM, forming a

hysteresis effect. If ΔV_BUR(LPM)is designed too small, it is possible that mode toggling between LPM and ABM

can occur resulting in audible noise. For that situation, ΔV_BUR(LPM)greater than 100 mV is recommended.

To minimize the effects of external noise coupling on V_BUR, a filter capacitor on the BUR pin (C_BUR) may

be needed. C_BURneeds to be properly designed to minimize the delay in generating ΔV_BURduring mode

transitions. It is recommended that C_BURshould be sized small enough to ensure ΔV_BUR(LPM)settles within

40 μs, corresponding to the burst frequency of 25 kHz in LPM (f_LPM). Based on three RC time constants,

representing 95% of a settled steady-state value from a step response, the design guide for C_BURis expressed

as

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R_BUR1+ R_BUR2

C_BURÇ 40ms ì

3R_BUR1R_BUR2

(3)

In order to enhance the mode transition between ABM and AAM, a programmable offset voltage (ΔV_BUR(AAM)

)

is generated to lower the V_BURwith an internal 5-μA pull-down current (I_BUR(AAM)), as shown in 图 7-1. After

transition from ABM to AAM, I_BUR(AAM)is enabled in AAM and flows into the BUR pin, so ΔV_BUR(AAM)is also

programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

(

//

)

(4)

When V_BURreduces after transition to AAM, the initial peak magnetizing current in AAM is reduced with less

energy per switching cycle, which forces controller to continu operating in AAM. If ΔV_BUR(AAM)is too small, it

is possible that either mode toggling between ABM and AAM or low-frequency ABM burst packets less than

20 kHz can occur and result in audible noise concern. For that situation, ΔV_BUR(AAM)greater than 150 mV

is recommended. In some power stage designs, LPM in hard switching condition may cover a wider output

load current range, so the light-load efficiency in LPM may be lower than ABM with ZVS condition. Besides,

the ABM-to-AAM mode transition may be affected potentially when the load current condition of LPM-to-ABM

transition is too close to the load current condition of ABM-to-AAM transition.

In order to optimize the output load current range in LPM, lower V_BUR(ABM), smaller ΔV_BUR(LPM), larger R_OPP

,

and smaller C_CShelp to reduce the peak magnetizing current in LPM. If the LPM energy needs to be further

reduced but V_BURin AAM is limited by the 0.7-V minimum programmable level, the optional application circuit in

图 7-2 can be considered. When the output load current is reduced, duty cycle of each burst packet becomes

smaller, so as the duty cycle of RUN-pin voltage. C_BURis discharged by the RUN driver through the small-signal

diode (D_BUR) and the current limit resistor (R_RUN). Proper selection of R_RUNvalue can further reduce V_BUR(ABM)

when the load current is reduced close to the transition point from ABM to LPM. One example BUR-pin setting is

R_BUR1= 182 kΩ, R_BUR2= 37.4 kΩ, C_BUR= 330 pF, and R_RUN= 20 kΩ.

I_O

RUN

R_RUN

REF

D_BUR

V_BUR

R_BUR1

ûV_BUR(AAM)

ûV_BUR(LPM)

BUR

ABM

LPM

R_BUR2

C_BUR

图 7-2. Optional Application Circuit to Reduce V_BURin LPM

7.3.2 FB Pin (Feedback Pin)

The FB pin usually connects to the collector of an optocoupler output transistor through an external current-

limiting resistor (R_FB). A maximum of 20 kΩ for R_FBis recommended. The feedback network of UCC28781 is

shown in 图 7-3. A high-quality ceramic by-pass capacitor between FB pin and REF pin (C_FB) is required for

decoupling I_FBfrom switching noise interference. A minimum of 220 pF is recommended for C_FB. An internal

8-kΩ resistor (R_FBI) at the FB pin in conjunction with the external C_FBforms an effective low-pass filter. 节 8

provides a detailed design guide on the secondary-side compensation network of V_Ofeedback loop, to improve

the load transient response and also limit the I_FBripple of ABM mode within the recommended range.

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V_O

Compensation

Network

REF

FB

C_FB

I_FB

I_OPTO

V_FB(REG)

R_FBI

R_FB

I_FB

I_COMP

+

Internal Ramp

Compensation

-

OPTO

COUPLER

Regulator

RUN

Control

Law

图 7-3. External Feedback Network Connected to the FB Pin

Depending on the operating mode, the controller interprets the current flowing out of the FB pin (I_FB) to regulate

the output voltage. For AAM and LPM modes based on peak current control, I_FBis converted into an internal

peak current-sense threshold (V_CST) to modulate the amplitude of the current-sense signal on the CS pin. For

example, when the output voltage (V_O) is lower than the regulation level set by the shunt regulator, the absolute

current level of I_FBreduces, causing a higher V_CSTto increase more power to the output load. In ABM, the burst

control loop takes over the V_Oregulation, where V_CSTis clamped to V_CST(BUR)and the ripple component of I_FB

participates in the modulation of the burst off time.

图 7-4 illustrates the operating principle of the ABM. A burst of switching pulses raises the output voltage V_O

which increases I_FB. At the end of the burst, the load current discharges the output capacitor, which decreases

V_Oand I_FB. UCC28781 injects a noise-free internal ramp compensation current (I_COMP) superimposed on I_FBin

order to stabilize the ABM operation. When the RUN pin is high, I_COMPis reset to 0 μA. When the RUN pin goes

low, I_COMPis gradually increased to 6 μA with a positive slope of 0.214 A/s. The summation of I_FBand I_COMP

is compared with I_TH(FB)to trigger the next burst event. The magnitude and sharp slope of I_COMPhelp to push

switching ripple and high-frequency noise component of I_OPTOaway from I_TH(FB)

.

I_FB- I_COMP

I_TH(FB)

0.214 A/s

I_COMP

6µA

I_OPTO≈ I_FB

V_o

PWML

RUN

图 7-4. Concept of Burst Control with an Internal Ramp Compensation

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7.3.3 REF Pin (Internal 5-V Bias)

The output of the internal 5-V regulator of the controller is connected to the REF pin. REF provides bias current

to most of the functional blocks within the UCC28781. It requires a high-quality ceramic by-pass capacitor (C_REF

)

to AGND to decouple switching noise and to reduce the voltage transients as the controller transitions from wait

state to run state. The minimum C_REFvalue is 0.22 μF, and a high quality dielectric material should be used,

such as X7R.

The output short-circuit current (I_S(REF)) of the REF regulator is self-limited to approximately 17 mA. 5-V bias is

only available after the under-voltage lock-out (UVLO) circuit enables the operation of the controller when V_VDD

reaches V_VDD(ON)

.

This pin can be used to perform an external shutdown function. A small-signal switch can be used to pull this pin

voltage below the power-good threshold of 4.5V so the controller will stop switching, force a VDD restart cycle,

and turn off the REF current.

7.3.4 VDD Pin (Device Bias Supply)

The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal

references, and the undervoltage lock-out (UVLO) circuit. As shown in 图 7-5, the UVLO circuit connected to

the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an

external depletion-mode MOSFET (Q_S) to be able to perform both V_VDDstartup and switch-node voltage (V_SW

sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing Q_S

to charge the VDD capacitor (C_VDD) from the V_SW

)

.

After the VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the

transformer starts delivering energy to the output capacitor (C_O) every switching cycle, so both output voltage

(V_O) and auxiliary winding voltage (V_AUX) increase.

As V_AUXis high enough, the auxiliary winding takes over to power V_VDD. The UVLO circuit provides a turn-on

threshold of V_VDD(ON)at 17 V and turn-off threshold of V_VDD(OFF)at 10.6 V. For fixed output voltage designs, the

wide V_VDDrange can accommodate lower values of VDD capacitor (C_VDD) and support shorter power-on delays.

For a fixed output voltage design, the rectified V_AUXis directly connected to the VDD pin. As V_VDDreaches

V_VDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the C_VDDsize has

to be sufficient to hold V_VDDhigher than V_VDD(OFF)until the positive auxiliary winding voltage is high enough to

take over bias power delivery during V_Osoft start. Therefore, the calculation of minimum capacitance (C_VDD(MIN)

)

needs to consider the discharging effect from the sink current of the UCC28781 during switching in its run state

(I_RUN(SW)), the average operating current of driver (I_DR), and the average gate charge current of half-bridge FETs

(I_Qg) throughout the longest duration of V_Osoft-start (t_SS(MAX)) sequence.

I

+ I

DR

+ I × t

Qg

RUN SW

V

SS max

VDD off

C

=

(5)

VDD min

× V

VDD on

t_SS(MAX)estimation should consider the averaged soft-start current (I_SEC(SS)) on the secondary side of the

converter, load current on the output (I_O(SS)) during start-up (if any), maximum output capacitance (C_O(MAX)), and

a 0.7-ms time-out potentially being triggered in the startup sequence. Include 1 ms in the equation to be the

worst-case condition of the 0.7-ms timer.

C

× V

O

O max

− I

t

=

+ 1 ms

(6)

SS max

I

SEC SS

O SS

During the V_Osoft-start sequence, V_CSTreaches the maximum current threshold on the CS pin (V_CST(MAX)) , so

I_SEC(SS)at the minimum voltage of the input bulk capacitor (V_BULK(MIN)) can be approximated as:

N

× V

V

BULK min

PS

CST max

2 × R

I

=

×

(7)

SEC SS

V

+ N × V + V

F

CS

BULK min

PS

O

where

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•

R_CSis the current sense resistor

N_PSis primary-to-secondary turns ratio

V_Fis the forward voltage drop of the secondary rectifier

7.3.5 P13 and SWS Pins

The P13 pin provides a regulated voltage to the gate of the depletion-mode MOSFET (Q_S), enabling Q_Sto

serve both V_VDDstart-up and loss-less ZVS-sensing from the high-voltage switch node (V_SW) through the SWS

pin. During V_VDDstart-up, the UVLO circuit controls two power-path switches connecting SWS and P13 pins to

VDD pin with two internal current-limit resistors (R_DDSand R_DDH), as shown in 图 7-5. In this configuration, Q_S

behaves as a current source to charge the VDD capacitor (C_VDD). R_DDSis set at 5 kΩ when V_VDD< 1.8 V to

limit the maximum fault current under a VDD short-to-GND condition. R_DDSis reduced to 500 Ω when V_VDD

>

1.8 V to allow V_VDDto charge faster. The maximum charge current (I_SWS) is affected by R_DDS, the external series

resistance (R_SWS) from SWS pin to Q_S, and the threshold voltage of Q_S(V_TH(Qs)). I_SWScan be calculated as

V

TH Qs

I

=

R

(8)

SWS

+ R

DDS

SWS

C_VDD

UVLO

VDD

I_SWS

R_DDS

R_SWS

SWS

P13

V_SW

+

V_TH(Qs)

-

C_SWS

Q_S

R_DDH

D_SWS

C_P13

D_P13

图 7-5. Operation of the VDD Startup Circuit

After V_VDDreaches V_VDD(ON), the two power-path switches open the connections between SWS, P13, and VDD

pins. At this point, a third power-path switch connects an internal 13-V regulator to the P13 pin for configuring

Q_Sto perform loss-less ZVS sensing. Because the Q_Sgate is fixed at 13 V, when the drain pin voltage of Q_S

becomes higher than the sum of Q_Sthreshold voltage (V_TH(Qs)) and the 13-V gate voltage, Q_Sturns off and the

source pin voltage of Q_Scan no longer follow the drain pin voltage change. This gate control method makes

Q_Sact as a high-voltage blocking device with the drain pin connected to V_SW. When the controller is switching,

whenever V_SWis lower than 13 V, Q_Sturns on and forces the source pin voltage to follow V_SW, becoming a

replica of the V_SWwaveform at the lower voltage level, as illustrated in 图 7-6.

The limited window for monitoring the V_SWwaveform is sufficient for ZVS control of the UCC28781, since the

ZVS tuning threshold (V_TH(SWS)) is set at 8.5 V for V_SET= 5 V and set at 4 V for V_SET= 0 V. The 8.5-V threshold

is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial-ZVS condition using Si

primary switches. On the other hand, performing full ZVS operation is more suitable with GaN primary switches.

Using a 4-V threshold helps to compensate for sensing delay between V_SWand the SWS pin.

The internal 13-V regulator requires a high-quality ceramic by-pass capacitor (C_P13) between the P13 pin and

AGND pin for noise filtering and providing compensation to the P13 regulator. The minimum C_P13value is 1 μF

and an X7R-type dielectric capacitor with 25-V rating or better is recommended. The controller enters a fault

state if the P13 pin is open or shorted to AGND during V_VDDstart-up, or if V_P13overshoot is higher than V_P13(OV)

of 15 V in run state. The output short-circuit current of P13 regulator (I_P13(MAX)) is self-limited to approximately

130 mA.

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Since the P13 pin interfaces to the external depletion-FET, during input surge or EFT testing the Cgd of the

depletion-FET can inject charge into the P13 pin and may cause an over-voltage stress. Under such condition

it is recommended to place an 18-V Zener diode (D_P13) on the P13 pin to clamp its voltage below its absolute

maximum level.

During AAM and ABM if the negative magnetizing current is large enough, a GaN device may operate in the

reverse conduction condition before it turns on each switching cycle, so V_SWmay be around -5 V for a brief

inteval and it appears on the SWS pin. The SWS-pin design of UCC28781 can sustain –6 V (continuous) and

–10 V (transient) stress to enhance the robust operation of the GaN power stage.

During this interval, Q_Sis in the on-state and its body diode may conduct for a short time when the voltage drop

across the on-state resistance of Q_Sis high enough. The external R_SWScan limit the forward current flowing

through the Q_Sbody diode, so the reverse recovery charge of the body diode can be significantly reduced. Too

high of R_SWSvalue weakens the start-up charge current of C_VDDand results in a longer start-up time. R_SWS

can be expected be slightly higher than 500 Ω. A small back-to-back TVS across BSS126 gate-to-source should

be added to protect the gate-to-source voltage from potential abnormal voltage stress. Ensure that the TVS

clamping voltage is less than the BSS126 gate-to-source voltage rating but does not conduct below 15 V.

R_SWSand a ceramic capacitor (C_SWS) between the SWS pin and the bulk input capacitor ground form a small

sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. The delay is to

ensure that the ZCD detection on the VS pin happens earlier than the ZVS detection on the SWS pin, such that

the ZVS control can auto-tune the PWMH on-time in the proper direction. The minimum value of C_SWSis 22 pF.

C_VDD

VDD

V_SW

V_BULK+N_PS(V_O+V_F)

R_SWS

ZVS

Discriminator

SWS

P13

V_SW

+

V_TH(Qs)

-

C_SWS

Q_S

V_SWS

13V+V_TH(Qs)

0V

13-V Regulator

D_SWS

C_P13

D_P13

PWML

图 7-6. ZVS Sensing by Reusing the VDD Startup Circuit

7.3.6 S13 Pin

As shown in 图 7-7, the S13 pin (switched 13-V rail) is used to perform bias-power management for a primary-

side GaN power IC, along with an example application where it also powers a PFC controller. This configuration

enables to minimize the power-loss contribution to so-called tiny-load input power and stand-by power.

S13 is sourced by P13 through an internal 2.8-Ω switch controlled by the RUN pin. 图 7-8 illustrates the

power-up sequence of the S13 pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V and

the charge current is controlled by an internal soft-start current limiter. The S13-pin voltage must increase above

the 10-V power-good threshold (V_S13(OK)) in order to initiate PWML switching of each burst cycle. When RUN is

low, V_S13is discharged by the loading on S13. The power-on delay of the GaN power IC on the S13 pin must

be less than 2 µs to be responsive to PWML. If not, the VDD or P13 pin may be a more suitable bias supply

for a GaN power IC with long power-on delay, but the wait-state power consumption is compromised. A 22-nF

ceramic capacitor as C_S13(ZVSF)is recommended. If the S13 pin is not used, it can be connected to the P13 pin

in order to eliminate the delay effect on PWML switching in every low-frequency burst cycle.

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PFC Controller

VCC

GaN + Driver

D_S13

R_S13

VCC

C_S13(PFC)

C_S13(ZVSF)

R_OPP

S13

CS

COMP

GND

Q_IPC

R_IPC

R_CS

C_IPC

IPC

R_IPC2

D_IPC

R_IPC3

图 7-7. Power Management Function for a GaN Power IC and PFC Controller

RUN

t_D(RUN-PWML)

PWML

13V

V_P13

V_S13(OK)

10V

V_S13

0V

S13_OK

I_S13(OCP)

I_S13

图 7-8. Power-up Sequence of the S13 Pin

When the S13 pin supplies both the GaN power IC and a PFC controller at the same time, a low-voltage

rectifier diode (D_S13) between the S13 pin and the PFC controller bias VCC pin is needed, so the local

decoupling capacitor for each powered controller can be separated. The decoupling capacitor of the PFC

controller (C_S13(PFC)) is usually larger than the one for a GaN power IC, such that the bias voltage of the GaN

power IC discharges more quickly without affecting the PFC bias voltage and PFC output voltage regulation. If

the S13 pin supplies a PFC controller only, the rectifier diode is not needed.

During start-up before VDD reaches the V_VDD(ON)threshold, the S13 switch stays off, so the S13-pin loading

does not consume any of the charging current of VDD capacitor flowing from SWS pin to VDD pin, thereby

enabling a fast start-up sequence. Under this condition, the PFC controller is off resulting in a lower PFC bus

voltage below 400 V.

7.3.7 IPC Pin (Intelligent Power Control Pin)

Under certain conditions, the IPC pin provides a 50-µA current from an internal source (I_IPC(SBP2)) which is

controlled by logic as shown in 图 7-9. The voltage on the VS pin is sampled during the demagnetization time to

obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the 2.4-V lower

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LV mode threshold (V_VSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is enabled

during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).

When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (V_VSLV(UP)), the LOW_NVO

logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of

SBP2 mode only.

To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode.

Additionally, if V_VDDfalls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high

and the current source is disabled during survival mode operation, irrespective of the V_VSlevel.

LOW_NVO

I_IPC(SBP2)

INT_STOP

RUN

IPC

R_IPC

SBP2

图 7-9. Control Circuit Diagram to the IPC-Pin Current Source

The multi-function IPC pin can be programmed to obtain one or more of the following benefits:

1. Reduction of input power for special light-load and stand-by conditions

2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V

3. Reduction of burst-mode output ripple at lower output voltages

4. Reduction of the over-power limit at lower output voltages

5. Power management of a PFC controller, together with the S13 pin

To implement the benefit No. 1, connect a resistor R_IPCfrom IPC pin to AGND pin. The 50-µA current source

establishes a voltage (V_IPC) across R_IPCto program an increase in the CS-pin peak primary current threshold at

very light loads. The transfer function between V_IPCand the CS threshold (V_{CST_IPC}) in SBP2 mode is illustrated

in 图 7-10.

Proper sizing of R_IPCto AGND can further reduce the burst frequency in SBP2 for so-called tiny-load power and

for stand-by power.

When V_IPCis less than 0.9 V (or IPC is shorted to AGND), V_{CST_IPC}threshold stays at the minimum level of

0.15 V. When V_IPCis set between 0.9 V and 1.8 V, V_{CST_IPC}is clamped at 0.27 V. For V_IPCbetween 1.8 V and

3.8 V, there is a linear programmable V_{CST_IPC}range between 0.27 V and 0.4 V. When V_IPCis greater than 3.8

V, V_{CST_IPC}remains clamped to 0.4 V. Be aware that high settings of V_{CST_IPC}may, in some cases, introduce

higher output ripple in deep light-load condition or provoke audible noise.

V_CST

V_{CST_IPC(UP)}

V_{CST_IPC(LR)}

0.4V

0.27V

V_{CST_IPC(MIN)}

0.15V

V_IPC

0V

0.9V

1.8V

3.8V

5V

图 7-10. IPC Transfer Function to Program the SBP2 Peak Current Threshold

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Because the enable status of the IPC current source contains the very useful output voltage information from the

LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output

voltage range. To gain benefits No.2, No. 3, and No. 4 of the IPC function, connect R_IPCbetween the IPC pin

and the CS pin, so that the current source can create additional CS-pin offset voltage on R_OPPwhen V_VS< 2.4 V.

With higher CS offset, the operating range of the V_CSTsignal is higher than the actual power stage peak current.

This situation forces the controller to operate in AAM mode for a wider actual output load range, and forces the

burst-mode threshold down to a lower power level.

图 7-11 shows the side effect of the IPC-to-CS connection if the R_IPCsetting is the same. Because the controller

enables 50 µA in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes

the SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher

R_IPCis needed to increase V_{CST_IPC}to compensate the peak current change.

20 V / 100 W

5 V / 15 W

Hard Switching

(LPM, SBP1, SBP2)

Soft Switching

(AAM, ABM)

V_CST

Soft Switching

(AAM, ABM)

50µA·R_OPP

V_CST(BUR)

P_O

I_M(+)

R_IPCto AGND

R_IPCto CS

R_IPCto AGND

R_IPCto CS

P_O

15W

100W

图 7-11. Effect of the CS-pin Offset Voltage from the IPC Pin

For benefit No. 5, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for

lower voltage outputs to further improve the light-load efficiency. As shown in 图 7-7, the diode D_IPCin series with

R_IPCis placed between IPC and CS pins, and V_IPCestablished at IPC is used to drive a small-signal switch Q_IPC

to disable the PFC controller such as UCC28056.

When V_IPCis higher than its threshold voltage, Q_IPCcan pull low the COMP pin voltage of a PFC controller, so

its switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level

to the peak value of the AC line. This lowers the bulk voltage, which reduces the ZVS energy, which increases

power stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out of the

efficiency equation. One design example for those components are C_S13(ZVSF)= 22 nF, C_S13(PFC)= 0.22 µF, C_IPC

= 10 nF, R_IPC= 69.8 kΩ, R_IPC2= 10 MΩ, and R_IPC3= 20 kΩ. Choose Q_IPCwith threshold voltage less than 1.5 V

to ensure that V_IPCis sufficient to achieve low on-resistance (R_DS(on)) even at very low burst frequencies.

7.3.8 RUN Pin (Driver and Bias Source for Isolator)

The RUN pin is a logic-level output signal which enables PWM switching when active high. When RUN is low, all

PWML and PWMH switching is disabled and the controller enters a low-current wait state.

In addition to enabling switching, RUN is capable of sourcing considerable current to bias an external gate driver

and perform a power management function on the primary side of a digital isolator. It generates a 5-V logic

output when the driver should be active, and pulls down to less than 0.5 V when the driver should be disabled.

During the off-time of any burst mode, the RUN pin serves as a power-management function to dynamically

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reduce the static bias current of the isolator/ driver, so light-load efficiency can be further improved and stand-by

power can be minimized.

As RUN goes high, while its voltage is less than 3 V, a 44-mA peak pull-up current is supplied from the internal

P13 regulator. With this current, the RUN driver can quickly charge the primary-side decoupling capacitor of

a digital isolator above its UVLO(ON) threshold. A Schottky diode can block discharge of this capacitor when

RUN goes low. When the RUN voltage goes above 3 V, P13 stops providing current and the pull-up is supplied

from the REF regulator, so the peak driving capability will be limited in order to avoid triggering the over-current

protection of the REF regulator. When RUN is low for a long burst off-time, the decoupling capacitor of the

digital isolator will be gradually discharged below its UVLO(OFF) threshold, so the isolator power loss can be

minimized.

There are three delays between RUN going high to the first PWML pulse going high in each burst packet. The

first delay is a fixed 2.2-μs delay time, intended to provide an appropriate "wake-up" time for the controller and

the gate driver to transition from a wait state to a run state. The second delay is gated by the 10-V power-good

threshold of the S13 pin. PWML will not go high until S13 voltage exceeds 10 V. The third delay is another

2.2-μs timeout, t_ZCin the electrical table, intended to turn on the low-side switch of the first switching cycle per

burst packet around the valley point of DCM ringing by waiting for the zero-crossing detection (ZCD) on the

auxiliary winding voltage (V_AUX). If ZCD is detected (on the VS input) before the t_ZCtimeout elapses, PWML

is immediately driven. If no ZCD is detected, PWML is driven when t_ZCelapses. The first two delays can be

concurrent; the third delay is sequential.

Therefore, the minimum total delay time is 2.2 μs typically if V_S13> 10 V and ZCD is detected immediately

after the 2.2-μs wake-up time. If V_S13< 10 V, the total delay time with tolerance over temperature is listed as

t_D(RUN-PWML)in the electrical table.

Digital

Isolator

Controller

RUN

PWMH

PWML

D_RUN

VCC1

C_RUN

PWMH

AGND

IN

V

CC1

V

GND

V

CC1(UVLO+)

V

RUN

图 7-12. Power Management Circuit

图 7-13. Power Management Waveform

7.3.9 PWMH and AGND Pins

The PWMH pin controls the gate of an SR MOSFET through an external isolating gate-driver. PWMH may also

be used to bias the primary-side of the gate-driver. The PWMH driver ground return is referenced to the AGND

pin. The maximum voltage level of PWMH is clamped to 5-V REF level. As PWMH goes high, when its voltage

is less than 3 V, up to 21-mA peak pull-up current may be supplied from the P13 regulator. When the PWMH

voltage goes above 3 V, the pull-up is supplied from the REF regulator instead, so the peak driving capability is

limited to less than 6 mA to avoid tripping the over-current protection of the REF regulator.

As shown in 图 7-12, since the RUN driver charges the decoupling capacitor of a digital isolator first through one

small-signal diode at the beginning of every burst cycle, the sourcing current of PWMH is sufficient to send the

control signal to the isolator and supply the continuous isolator operating current together with the RUN driver

at the same time through another small-signal diode. The high peak driving capability of PWMH provides the

flexibility of signal transmission through a digitally isolated gate-driver with opto-compatible input.

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It is prudent to choose an isolated gate-driver with minimal power-up delay on both input and output sides to

avoid missing several PWMH pulses for SR control.

AGND pin is the ground return for all the analog control signals, RUN driver, and PWMH driver. It is required

to implement a careful layout separation from other noisy ground return paths, such as PGND and power stage

ground. The thermal pad should be connected to the AGND pin directly and could be a Kelvin connection

point to the related external components. For details of the grounding layout guideline and noise decoupling

techniques, refer to 节 10.1 of this datasheet.

7.3.10 PWML and PGND Pins

The PWML pin is the primary-side switch gate-drive, for which ground return is referenced to the PGND pin. The

strong driver with 0.5-A peak source and 1.9-A peak sink capability can control either a silicon power MOSFET

with a higher gate-to-source capacitance, a cascode GaN, an E-mode gate-injection-transistor (GIT) GaN with

continuous on-state current, or a GaN power IC with logic PWM input.

The maximum voltage level of PWML is clamped to the P13 pin voltage. The 13-V clamped gate voltage

provides an optimal gate-drive for low on-state resistance and lower gate-driving loss. An external gate resistor

in parallel with a fast recovery diode can be used to further reduce the turn-on speed without compromising

the turn-off switching loss. Slower turn-on speed of the primary switch mitigates the voltage stress across the

secondary-side rectifier when the SR switch is disabled in deep light-load condition, and reduces the switching-

node dV/dt to a safe level for reducing stress on the high-voltage isolating SR driver. A decoupling capacitor

much larger than the PWML capacitive loading should be placed between P13 and PGND pins to decouple

the gate-drive loop to allow operation at higher switching frequency. The 15-ns propagation delay of the PWML

driver enables a higher frequency operation and more consistent ZVS switching.

图 7-14 and 图 7-15 shows the example PWML driving network for a GIT GaN device and for a silicon MOSFET,

respectively. For the GIT GaN device case, resistor R_G2controls the turn-on speed. The turn-off speed can be

maintained by the two fast recovery diodes, D_G1and D_G2. R_G1provides a continuous driving path to maintain

the on state and low on-resistance (R_DS(on)) of a GIT GaN. C_Gavoids the small R_G2from affecting the on state

current. PGND can be directly connected to the separate source terminal of a GIT GaN to achieve a Kelvin

connection, so the driver loop parasitic inductance can be decoupled.

Q_L

R_G

R_G1

PWML

PGND

PWML

C_G

R_G2

AGND

PGND

D_G2

D_G

L_Stray

R_CS

L_Stray

R_CS

D_G1

图 7-14. Driving a GIT GaN Device

图 7-15. Driving a Si MOSFET

An internal low-voltage level shifter is included between PGND and the ground return pin for analog control

signals (AGND), so PGND can be connected separately to the source pin of the Si-MOSFET (Q_L) to achieve a

Kelvin connection, as shown in 图 7-15. When hard switching condition occurs, the lumped parasitic capacitor on

the switch node is discharged, so a positive voltage spike is created across R_CS. In soft switching condition, the

negative magnetizing current flowing through R_CScan create a negative voltage spike on R_CS. The level shifter

is designed to handle 5-V positive transient spike and -1-V negative stress between PGND pin and AGND pin.

7.3.11 SET Pin

Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation

delays of their drivers, the SET pin is provided to program critical parameters of UCC28781 for the two different

power stages.

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Firstly, this pin sets the zero-voltage threshold (V_TH(SWS)) at the SWS input pin to be one of two different

auto-tuning targets for ZVS control. When SET pin is tied to AGND, V_TH(SWS)is set at its low level of 4 V for

realizing full ZVS, which allows the low-side switch (Q_L) to be turned on when the switch-node voltage drops

close to 0 V. When SET pin is tied to REF pin, V_TH(SWS)is set at 8.5 V for implementing partial ZVS, which

makes Q_Lturn on at around 8.5 V.

Secondly, the SET pin also selects the current-sense leading-edge blanking time (t_CSLEB) to accommodate

different delays of the gate drivers; 110 ns for V_SET= 0 V and 190 ns for V_SET= 5 V.

Thirdly, the minimum PWML on-time (t_ON(MIN)) in low-power mode and standby-power mode is 110 ns for V_SET

0 V, and is 100 ns for V_SET= 5 V.

=

Finally, the maximum PWML on-time to detect CS pin fault (t_CSF) is adjusted. t_CSFfor V_SET= 5 V (t_CSF1) is set

at 2 μs. t_CSFfor V_SET= 0 V (t_CSF0) depends on the value of R_RDM. t_CSF0is configured to 2 μs when R_RDM

R_RDM(TH)and to 1 μs when R_RDM< R_RDM(TH)

≥

.

7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)

The dead-time between PWMH falling edge and PWML rising edge (t_Z) serves as the wait time for V_SW

transition from its high level down to the target ZVS point. Since the optimal t_Zvaries with V_BULK, the internal

dead-time optimizer automatically extends t_Zas V_BULKis less than the highest voltage of the input bulk capacitor

(V_BULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line

versus a fixed dead-time over a wide line voltage range. A resistor on the RTZ pin (R_RTZ) programs the minimum

t_Z(t_Z(MIN)) at V_BULK(MAX), which is the sum of the propagation delay of the synchronous rectifier driver (t_D(DR)) and

the minimum resonant transition time of V_SWfalling edge (t_LC(MIN)).

R

= K

× t

= K

× t

+ t

D DR LC min

(9)

RTZ

Z min

RTZ

where

•

K_RTZis equal to 11.2 × 10¹¹(unit: F^-1) for V_SET= 0 V

K_RTZis equal to 5.6 × 10¹¹(unit: F^-1) for V_SET= 5 V

V_SW

N_PS(V_O+V_F)

V_BULK(MAX)

I_M

I_M-

t_D(DR)

t_LC(MIN)

t_Z(MIN)

PWMH

PWML

图 7-16. RTZ Setting for the Falling-edge Transition of V_SW

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As illustrated in 图 7-16, when PWMH turns off Q_SRafter t_D(DR)delay, the negative magnetizing current (i_M-)

becomes an initial condition of the resonant tank formed by magnetizing inductance (L_M) and the switch-node

capacitance (C_SW). C_SWis the total capacitive loading on the switch-node, including the junction capacitance

(C_OSS) of the primary switch, reflected secondary-side capacitance, intra-winding capacitance of the transformer,

the snubber capacitor, and parasitic capacitance of the PCB traces between switch-node and ground. Unlike

a conventional valley-switching flyback converter, the resonance of the Zconverter at high line does not begin

at the peak of the sinusoidal trajectory. The transition time of V_SWtakes less than half of the resonant period.

The following t_LC(MIN)expression quantifies the transition time for R_RTZcalculation, where an arccosine term

represents the initial angle at the beginning of resonance. As an example, the value of π minus the arccosine

term at V_BULK(MAX)of 375 V, V_Oof 20 V, and N_PSof 5 is around 0.585π, which is close to one quarter of the

resonant period.

N_PS(V_O+V_F)

V_{BULK (MAX )}

t_{LC(MIN )}= [

p

- cos^-1(

)]ì L_MC_SW

(10)

7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)

The R_RDMresistor provides the power stage information to the t_DMoptimizer for auto-tuning the on-time of

PWMH to achieve ZVS within a given t_Zdischarge time. The following equation calculates the resistance, based

on the knowledge of the primary magnetizing inductance (L_M), auxiliary-to-primary turns ratio (N_A/N_P), the values

of the resistor divider (R_VS1and R_VS2) from the auxiliary winding to VS pin, and the current sense resistor (R_CS).

Among those parameters, L_Mcontributes the most variation due to its typically wider tolerance. The optimizer

is equipped with wide enough on-time tuning range of PWMH to cover tolerance errors. Therefore, just typical

values are enough for the calculation.

N

× R

VS1

K

× L

CS

A

VS2

+ R

DM

R

M

R

=

×

(11)

RDM

N

× R

P

VS2

where

K_DMis equal to 5.0×10⁹(unit: F^-1) for both V_SET= 5 V and V_SET= 0 V

7.3.14 XCD Pin

•

The XCD pin performs the X-capacitor discharge function in conjunction with the recommended external

detection circuit, shown in 图 7-17.

备注

The XCD application circuit must be connected to an AC input but not to a DC input, in order to

avoid the thermal stress on those sensing components caused by enabling the discharge current

repetitively.

If the XCD function is not needed, directly shorting the two XCD pins to the AGND pin disables the XCD pin

function, so the controller wait-state current is further reduced. The external sensing circuit must be removed.

(see 图 7-18)

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L

N

V_HV

R_XCD

Q_XCD

XCD

图 7-18. Disable XCD Functions

图 7-17. X-cap Discharge Circuit

To form the discharge path in the first circuit, the anode nodes of two high-voltage diode rectifiers are connected

to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ current limit resistance

(R_XCD), and the drain-to-source of a high-voltage depletion MOSFET (Q_XCD) couples the resistance to XCD pins.

Since R_XCDneeds to sustain the high voltage drop from the XCD-pin current, two series 13-kΩ SMD resistors in

1206 size with 26-kΩ total resistance are required to meet the voltage de-rating. A 600-V rated MOSFET such

as BSS126 is needed as the high voltage blocking device. The MOSFET gate is connected to the P13 pin, so

the highest voltage level of the XCD pins is limited to the sum of the P13-pin voltage and the threshold voltage of

BSS126. The voltage level gives sufficient headroom over the 6.5-V line zero-crossing (LZC) threshold.

In case of single-fault event where one XCD pin is in fail-open condition, the redundant XCD pin helps to

maintain the X-cap discharge function. In case of the single-fault event of BSS126 involving its drain-to-source

in fail-short condition, an internal 26-V clamp helps to protect the XCD pin from exceeding its voltage rating. The

current-limiting resistance (R_XCD) limits the fault current below the maximum clamping capability, however the

value of R_XCDshould avoid reducing the normal discharge current. A total resistance of 26 kΩ ±5% meets both

criteria. The internal clamping function can also help to dissipate some of the line surge energy accumulated on

the XCD pins in order to limit the pin voltage below its 30-V rating.

After the AC line is disconnected, X-capacitors in the EMI filters on the AC side of the diode-bridge rectifier

must have means to discharge its residual voltage to a safe level within a certain time. Typically a high voltage

discharge resistor bank is placed in parallel with the capacitor to form a discharge path. The value of the

resistance is chosen to discharge the capacitance within the required time period. However, if the capacitance is

large enough, the necessary lower value of discharge resistance will increase the standby power. The controller

provides an active X-capacitor discharge function with 2-mA maximum discharge current capability to reduce

the standby power. The discharge current is activated only when the detection criteria for the AC-line removal

condition is met. The 6.5-V line zero-crossing (LZC) threshold on XCD pins is used to detect AC-line presence.

When LZC is missing over an 84-ms detection timeout period, the discharge current is enabled for a maximum

period of 300 ms followed by a 700-ms blanking time with no current. To detect the zero crossing reliably, as

well as to save power consumption, a stair-case test current shown in 图 7-19 is generated within the 84-ms

detection time. The worst-case discharge current and timing are designed to discharge the X-capacitor up to 1

µF.

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I_XCD(MAX)

I_XCD(4)

I_XCD(3)

I_XCD(2)

I_XCD(1)

I_XCD(0)

t_XCD(MAX)

7 x t_XCD(STEP)

t_XCD(WAIT)

图 7-19. Step-current Profile into the XCD Pins for the X-cap Discharge Function

The four test current levels are designed to overcome the impact of leakage current from the bridge diode over

a wide line range. Without enough test current level in a 12-ms period, the diode leakage current will prevent

the XCD-pin voltage from reaching close to the 6.5-V LZC threshold. A higher AC line voltage or a higher diode

junction temperature requires a higher test current due to the increased diode leakage current. When the AC line

is connected, the four stair-case current levels and the 700-ms time out after the completion of LZC detection

helps to minimize the average current sink from AC main and thereby the static power loss. For the first three

current levels, every 12-ms time-out event commands the test current to increment. The last test current level

has to be sustained for 48 ms without LZC, before triggering the 2-mA discharge mode. Whenever LZC is

detected, any higher-level test-current steps are aborted and the 700-ms wait-state is initiated. 图 7-20 shows

the flow chart of X-capacitor discharge.

Note that the XCD-LATCH referenced in 图 7-20 is a latch that is set when loss of AC line is confirmed. When

set, this state allows X-capacitor discharge to proceed.

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V_XCD> 4V

Y

AFTER FIRST V_VDD

STARTUP

700ms

DONE

N

Disable XCD

700ms BLANK &

XCD_LATCH RESET

12ms LZC

DETECT

(I_XCD(1)

12ms

WAIT

LZC = 1

700ms

WAIT

(I_XCD(0)

)

12ms_DONE & LZC = 0

LZC = 1

12ms LZC

DETECT

12ms

WAIT

(I_XCD(2)

)

LZC = 1

12ms_DONE & LZC = 0

12ms LZC

DETECT

12ms

WAIT

(I_XCD(3)

)

LZC = 1

12ms_DONE & LZC = 0

48ms LZC

DETECT

48ms

WAIT

(I_XCD(4)

)

700ms

DONE

48ms_DONE & LZC = 0

300ms

DISCHARGE

(I_XCD(MAX)

700ms BLANK

(I_XCD(0)

XCD_LATCH

SET

)

300ms_DONE

OR LZC = 1

)

700ms

WAIT

300ms

WAIT

图 7-20. The State Diagram of the XCD-pin Function

Whenever any system protection is triggered, the converter switching is terminated and V_VDDrestart cycle

occurs between V_VDD(ON)and V_VDD(OFF). In this mode, the XCD pin function continues to operate, since the

internal circuitry is separately biased from V_VDDinstead of from V_REF

.

Shorting the XCD pins to AGND disables the XCD function. After V_VDDfirst reaches V_VDD(ON), an 80-µA test

current is sourced out of the XCD pin in order to reliably identify the XCD-pin short with a low-impedance path to

the AGND pin. If XCD is shorted to AGND, any path to L and N must be open to prevent R_XCDfrom overheating.

When V_XCDis lower than 4 V before the RUN-pin first pulls high, the XCD function is disabled and the internal

circuit will stop sourcing current from V_VDD

.

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7.3.15 CS, VS, and FLT Pins

The CS pin is the current-sense input. The internal peak current control loop limits the highest magnetizing

current, and 节 7.4.4 in this datasheet describes the peak current change in different operating modes.

The VS pin is a multi-function sensing input, which detects the input voltage, the output voltage, and the

zero-current-detection (ZCD) through the auxiliary winding voltage, to optimize ZVSF performance and provide

critical protections.

The FLT pin is a dual-purpose fault detection pin for either over-temperature protection or input over-voltage

protection, depending on how the external circuit is configured.

The system protection functions of these three pins are introduced in 节 7.4.12.

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7.4 Device Functional Modes

7.4.1 Adaptive ZVS Control with Auto-Tuning

图 7-21 shows the simplified block diagram explaining the ZVS control of the UCC28781 controller. A high-

voltage sensing network provides a replica of the switch node voltage waveform (V_SW) with a limited “visible”

lower voltage range that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and

determines the adjustment direction for the on-time of PWMH (t_DM) by detecting if V_SWreaches a predetermined

ZVS threshold, V_TH(SWS), within t_Z, where t_Zis the targeted zero voltage transition time of V_SWcontrolled by the

PWMH-to-PWML dead-time optimizer.

In 图 7-21, V_SWof the current switching cycle in the dashed line has not reached V_TH(SWS)after t_Zexpires. The

ZVS discriminator sends a TUNE signal to increase t_DMfor the next switching cycle in the solid line, such that

the negative magnetizing current (I_M-) can be increased to bring V_SWdown to a lower level in the same t_Z. After

a few switching cycles, the t_DMoptimizer settles and locks into ZVS operation of the low-side switch (Q_L). In

steady-state, there is a fine adjustment on t_DM, which is the least significant bit (LSB) of the ZVS tuning loop.

This small change of t_DMin each switching cycle is too small to significantly move the ZVS condition away from

the desired operating point. 图 7-22 demonstrates how fast the ZVS control can lock into ZVS operation. Before

the ZVS loop is settled, controller starts in a valley-switching mode as t_DMis not long enough to create sufficient

I_M-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling t_DMwith an LSB.

t_D(PWML-H)

V_CST

N_P:N_S

L_K

I_M/ R_CS

PWML

PWMH

V_O

V_BULK

I_M

L_M

R_Co

C_O

R_O

t_DM

SET

VS

RTZ

Adaptive ZVS Control

PWMH

PWML

Isolated Driver

(primary side)

Isolated Driver

(secondary side)

RDM

SET

t_DM

Optimizer

Dead-Time Optimizer

(t_D(PWML-H)and t_Z)

Q_L

t_Z

V_SW

R_CS

TUNE

t_Z

V_TH(SWS)

Peak Current

Loop

V_CST

ZVS Discriminator

PWMH

PWML

SET

SWS

HV Sense

P13

图 7-21. Block Diagram of Adaptive ZVS Control

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PWML

PWMH

1.2

0.8

0.4

0

I_M(A)

18

12

6

V_SWS(V)

V_TH(SWS)

0

400

300

200

V_SW(V)

100

0

5 µs/div

12

6

12

6

12

6

V_SWS(V)

0

400

V_SW(V)

200

0

200

0

200

0

图 7-22. Auto-Tuning Process of Adaptive ZVS Control

7.4.2 Dead-Time Optimization

The dead-time optimizer in 图 7-21 controls the two dead-times: the dead-time between PWMH falling edge

and PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge

(t_D(PWML-H)).

The adaptive control law for t_Zutilizes the line feed-forward signal to extend t_Zas V_BULKreduces, as shown in 图

7-23. The VS pin senses V_BULKthrough the auxiliary winding voltage (V_AUX) when the primary side switch (Q_L) is

on. The auxiliary winding creates a line-sensing current (I_VSL) out of the VS pin flowing through the upper resistor

of the voltage divider on VS pin (R_VS1). Minimum t_Z(t_Z(MIN)) is set at V_BULK(MAX)through the RTZ pin. When I_VSL

is lower than 666 μA, t_Zlinearly increases and the maximum t_Zextension is 140% of t_Z(MIN)

.

140%

t_Z(I_VSL

)

t_Z(MIN)

100%

I_VSL

233 µA

666 µA

图 7-23. t_ZControl Optimized for Wide Input Voltage Range

The control law for t_D(PWML-H)is adaptive with the slope variation of the switching node voltage, regardless of the

SET-pin voltage as shown in 图 7-24.

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V

SW

UV

V

AUX

ZCD

Heavy load

Light load

PWML

PWMH

t

D(PWML-H)

(Heavy load)

t

D(PWML-H)

(Light load)

图 7-24. t_D(PWML-H)Control Optimized for GaN and Si FETs

7.4.3 EMI Dither and Dither Fading Function

备注

In UCC28781A, the frequency-dither function is always disabled and this section does not apply.

The frequency-dither function in AAM reduces the conducted EMI noise and results in EMI filter size reduction.

Conventionally, the dither carrier frequency is in the range of hundreds of Hz. However, when the control loop

bandwidth is pushed higher in order to improve the load transient response, the control loop will be able to

correct the disturbance from the dither signal, and weakens the EMI frequency spreading effectiveness. Even

though increasing the dither frequency to few kHz can reduce the influence of the control loop, the audible

noise issue will occur. For UCC28781, since it is able to run at a higher switching frequency in AAM, the dither

frequency can be optimized at 23 kHz, so as to avoid audible noise and desensitize the loop response effect on

the EMI attenuation.

UCC28781 enhances the response of the ZVS control loop, such that the ZVS performance can be maintained

in most switching cycles even under a strong EMI dither condition. A triangular dither signal is superimposed

on the feedback voltage signal V_CST, The novel feed-forward control method is applied to allow the ZVS loop to

correct the timing error much faster, so ZVS can be maintained and the efficiency will not suffer.

Conventionally, the dither magnitude is fixed across the whole output voltage range. Since the higher output

voltage condition needs to deliver a higher output power, the EMI issue is typically more severe, so a stronger

dither signal is needed for more conducted EMI reduction. In the lower output voltage condition, the output ripple

specification is usually much tighter, so a strong dither signal may aggravate the output voltage ripple and create

the design tradeoff. For UCC28781, the two-level dither magnitude is adjusted automatically based on the output

voltage level, so the perturbed output ripple at the lower output voltage condition can be reduced to meet a more

stringent ripple requirement, and the strong dither can still be applied to the higher output voltage condition for

the better EMI performance. Specifically, when V_VSis lower than 2.4 V during the demagnetization time (the

LOW_NVO logic signal is high), the peak-to-peak dither magnitude on CS pin is reduced to around 36 mV. When

V_VSis higher than 2.5 V, the peak-to-peak dither magnitude on CS pin is increased to around 98 mV.

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Since the low-line efficiency usually determines the power stage thermal limit, the efficiency will drop further

when EMI dither is enabled. Since the bulk capacitor ripple voltage at low line is bigger than at high line and

AAM mode forces variable frequency operation, the line frequency causes nature dither frequency anyway even

without applying the internal EMI dither. Therefore, taking advantage of AAM mode, the dither function at low line

can be disabled based on the brown-in voltage setting, so the option provides design flexibility to trade-off the

worst-case low-line efficiency and EMI. Specifically, when i_VSLis higher than 646 μA, the EMI dither function is

enabled. When i_VSLis lower than 580 μA, the EMI dither function is disabled. If the brown-in point is set at 75

Vac, this means that the EMI dither is disabled for 90 Vac and 115 Vac.

The dither fading feature allows the dither signal to be smoothly disabled, when the output load current is close

to the transition point between AAM and ABM. As shown in 图 7-25, V_CST(MAX)and V_CST(BUR)are used as the

two voltage-clamping targets to the perturbed V_CSTsignal. When the V_CSTreaches V_CST(MAX), the top of the

V_CSTripple content is clipped by the internal clamp circuit, so the influence of the EMI dither on the peak power

capability can be eliminated. When the V_CSTreaches V_CST(BUR), the bottom of the V_CSTripple content is clipped

by an another internal clamp circuit, so the influence of the EMI dither on the ABM waveform is removed.

I_O

I_O(MAX)

I_O(OPP)

I_O(BUR)

V_CST(MAX)

V_CST(OPP)

V_CST+ V_CST(EMI)

V_CST

V_BUR/4

FAULT_OPP

ABM

DITHER_EN

图 7-25. Dither Fading Feature in AAM

7.4.4 Control Law Across Entire Load Range

The UCC28781 offers six modes of operation summarized in 表 7-1. Starting from heavier load, the AAM mode

forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a group

of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output voltage. At

the same time, the converter confines the burst frequency variation above 20 kHz by adjusting the number of

PWML and PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In LPM, SBP1,

and SBP2 modes, PWMH and the ZVS tuning loop are disabled, so the converter operates in valley-switching

mode. The survival mode is to maintain V_VDDhigher than V_VDD(OFF)during a long interval of no switching.

表 7-1. Functional Modes

MODE

Adaptive

OPERATION

PWMH

ZVS

AAM

PWML and PWMH in complementary switching

Enabled

Yes

Amplitude

Modulation

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表 7-1. Functional Modes (continued)

MODE

OPERATION

PWMH

ZVS

ABM

Adaptive Burst

Mode

Variable f_BUR> f_BUR(LR), PWML and PWMH in

complementary switching

Enabled

Yes

LPM

Low Power Mode Fix f_BUR≈ f_LPM, valley-switching

Disabled

No

SBP1

First StandBy

Power Mode

Variable f_BURbetween f_SBP2(LR)and f_SBP2(UP), valley-

switching

SBP2

Second StandBy Variable f_BUR< f_SBP2(UP)as V_BUR< 0.9 V; Variable f_BUR

<

Disabled

No

Power Mode

f_SBP2(LR)as V_BUR> 0.9 V; Both are in valley-switching

INT_STOP

Survival Mode

When V_VDD< V_VDD(OFF)+ V_VDD(PCT), a series of PWML

pulses followed by a long PWMH pulse is generated

Enabled in the last

switching cycle of

a survival-mode

burst packet

图 7-26 and 图 7-28 show the critical parameter changes among the five operating modes, where V_CSTis the

peak current threshold compared with the current-sense voltage from the CS pin, f_SWis the switching frequency

of PWML, f_BURis the burst frequency, and N_SWis the pulse number of PWML cycles per burst packet. 图 7-26

represents the control mode difference under the two VS-pin voltage ranges, when the IPC-pin voltage is less

than 0.9 V or IPC is connected to AGND. 图 7-28 illustrates the modified control mode, when the IPC-pin voltage

setting is higher than 0.9 V. The following section explains the detailed operation of each mode. The following

section discusses VS-pin voltage and IPC-pin voltage effects.

SBP2 SBP1

LPM

SBP2 SBP1

LPM

V_CST

ABM

AAM

ABM

AAM

V_CST(OPP)

V_{CST(OPP)_LV}

V_CST(BUR)

V

_{CST_IPC(MIN)}=V_CST(MIN)

=V_CST(MIN)

P_O

Frequency

f_SW

f_BUR(UP2)

f_BUR(LR)

f_BUR(UP1)

f_BUR

f_LPM

f_SBP2(UP)

f_BUR

f_BUR(LR)

f_LPM

f_SBP2(UP)

P_O

N_SW

9

5

4

2

4

2

P_O

P_O(BUR)P_{O(OPP)_LV}

P_O

P_O(BUR)

P_O(OPP)

图 7-27. Control law for V_VS< V_VSLV(LR)(LOW_NVO

图 7-26. Control law for V_VS> V_VSLV(UP)(LOW_NVO

= 1)

= 0)

Control Law Under Different Load Sweep Direction as V_IPC> 0.9 V and V_VS> V_VSLV(UP)

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SBP2 SBP1

LPM

SBP2 SBP1

LPM

V_CST

ABM

AAM

ABM

AAM

V_CST(OPP)

V_CST(BUR)

V_{CST_IPC}

V_CST(MIN)

V_CST(BUR)

V_{CST_IPC}

V_CST(MIN)

P_O

Frequency

f_SW

f_BUR(UP2)

f_BUR(UP1)

f_BUR

f_BUR(LR)

f_BUR

f_BUR(LR)

f_LPM

f_SBP2(UP)

f_LPM

f_SBP2(UP)

f_SBP2(LR)

P_O

N_SW

9

4

2

4

2

P_O

P_O(BUR)

P_O(OPP)

P_O(BUR)

P_O(OPP)

图 7-28. Full Load to Light Load

图 7-29. Light Load to Full Load

7.4.5 Adaptive Amplitude Modulation (AAM)

The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time

in between, as shown in 图 7-30. As the load current reduces, the negative magnetizing current (I_M-) stays the

same, while the positive magnetizing current (I_M+) reduces by the internal peak current loop to regulate the

output voltage. I_M+generates a current-feedback signal (V_CS) on the CS pin through a current-sense resistor

(R_CS) in series with Q_Lsource and a peak current threshold (V_CST) in the current loop controls the peak

current variation. Due to the nature of transition-mode (TM) operation, lowering the peak current with lighter load

conditions results in higher switching frequency. When the load current increases to an over-power condition

(I_O(OPP)) where V_CSTcorrespondingly reaches or exceeds an OPP threshold (V_CST(OPP)) of the peak current loop,

the OPP fault response will be triggered after a 160-ms timeout (except not in UCC28781A, where the OPP

timer function is always disabled). The RUN signal stays high in AAM, so the half-bridge driver remains active.

Heavy Load

I_M

Light Load

0 A

I_M-

PWML

PWMH

RUN

图 7-30. PWM Pattern in AAM

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7.4.6 Adaptive Burst Mode (ABM)

As the load current reduces to I_O(BUR)where V_CSreaches the V_CST(BUR)threshold, the control mode transitions

to ABM starts and V_CSis clamped. The peak magnetizing current and the switching frequency (f_SW) of each

switching cycle are fixed for a given input voltage level. V_CST(BUR)is programmed by the BUR pin voltage

(V_BUR). The PWM pattern of ABM is shown in 图 7-31. When RUN goes high, a delay time between RUN and

PWML (t_D(RUN-PWML)) is given to allow both the gate driver and the UCC28781 controller time to wake up from

a wait state to a run state. The first PWML pulse turns on Q_Lclose to a valley point of the DCM ringing on the

switch-node voltage (V_SW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding

voltage (V_AUX).

The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML

pulses (N_SW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last

switching cycle is detected, and forces the isolated gate driver and controller into a wait state for the quiescent

current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs and the

minimum on-time of PWML is limited to the leading-edge blanking time (t_CSLEB) of the peak current loop.

However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following

equation estimates how burst frequency (f_BUR) varies with output load and other parameters.

I

f

SW

O

f

=

×

N

(12)

BUR

I

O BUR

SW

As I_O< I_O(BUR), f_BURcan become lower than the audible noise range if N_SWis fixed. In ABM, N_SWis modulated

to ensure f_BURstays above 20 kHz by monitoring f_BURin each burst period. As I_Odecreases, f_BURdecreases

and reaches a predetermined low-level frequency threshold (f_BUR(LR)) of 25 kHz. The ABM loop commands N_sw

of both PWML and PWMH to be reduced by one pulse to maintain f_BURabove f_BUR(LR). At the same time, the

burst frequency ripple on the output voltage reduces as N_SWdrops with the load reduction. As I_Oincreases,

f_BURbecomes higher and reaches a predetermined high-level frequency threshold (f_BUR(UP)). The ABM loop

commands N_SWto be increased by one pulse to push f_BURback below f_BUR(UP)

.

The maximum N_SWand the f_BUR(UP)thresholds are modified based on the output voltage condition, i.e., the

positive VS-pin voltage level. When the V_VSsampled at the PWMH falling edge is less than the 2.4-V threshold

(V_VSLV(LR)), the maximum N_SWis 5 pulses and the f_BUR(UP2)is 50 kHz. When the sampled V_VSis higher than the

2.5-V threshold (V_VSLV(UP)), the maximum N_SWis 9 pulses, the f_BUR(UP2)is 50 kHz for N_SW≤ 3, and the f_BUR(UP1)

is 34 kHz for N_SW> 3. The IPC-pin voltage does not affect the parameters in ABM mode.

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also

limiting the burst output ripple and audible noise. As I_Ois close to the boundary between AAM and ABM, the

two burst packets with the maximum pulse count may start to bundle together. In order to mitigate the output

ripple and audible noise concerns, when the bundled burst packet appears two times within eight sequential

burst cycles, the 5-µA current sink into the BUR pin is enabled to reduce V_BUR. The less energy per cycle with

a lower V_BURwill force the control loop to transition from ABM to AAM smoothly in order to allow the peak current

increase to maintain the output voltage regulation.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

I_M

0 A

ZCD

through V_aux

f_SW

ZVS

t_CSLEB

PWML

PWMH

f_BUR

2.2 µs

RUN

图 7-31. PWM Pattern in ABM

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7.4.7 Low Power Mode (LPM)

As N_SWdrops to two in ABM and the condition of f_BURless than f_BUR(LR)is qualified under two consecutive burst

periods, the controller enters into LPM mode and disables PWMH. The purpose of LPM is to provide a soft peak

current transition between V_CST(BUR)and V_CST(MIN). LPM fixes N_SWat two and sets f_BURequal to f_LPMof 25 kHz.

In LPM mode, V_CSTis controlled to regulate the output voltage. At the start of each burst packet, after RUN pulls

high, t_D(RUN-PWML)is used to wake up both the isolated gate driver and the controller. With PWMH disabled, the

two PWML pulses turn on Q_Lclose to valley-switching by sensing ZCD. When ZCD is detected again at the end

of the second pulse, the RUN pin goes low and the controller enters its low-power wait state. For LPM mode

with the SET pin connected to REF, the minimum on-time of PWML can be further reduced to t_ON(MIN), to allow

the peak magnetizing current to be reduced below the level limited by t_CSLEBof the peak current loop. In this

condition, operation of the LPM control loop is changed from a current-mode control to a voltage-mode control,

so the on-time adjustment of PWML is not limited to t_CSLEB. With this feature, before f_BURstarts to fall below f_LPM

and enters the audible frequency range of SBP mode, the peak current is low enough to limit the magnitude of

audible excitation.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

V_CST(MIN)/ R_CS

I_M

0 A

t_ON(MIN)

ZCD through V_AUX

PWML

f_BUR= f_LPM

PWMH

RUN

图 7-32. PWM Pattern in LPM

7.4.8 First Standby Power Mode (SBP1)

As V_CSTdrops to V_CST(MIN), UCC28781 enters into SBP1 mode and PWMH continues to stay disabled. The

purpose of SBP1 is to lower f_BURin order to minimize power loss. SBP1 fixes N_SWat two and V_CSTto

V_CST(MIN), while the burst off-time is adjusted to regulate the output voltage. As f_BURis well below f_LPM, the

switching-related loss can be minimized. In addition, lowering f_BURforces both the isolated gate driver and

controller to remain in wait states longer to minimize the static power loss. The equivalent static current of the

controller in SBP can be represented as

2

I

= I

− I

×

+ t

× f

+ I

BUR WAIT

(13)

VDD SBP

RUN

WAIT

D RUN − PWML

f

SW SBP

t_D(RUN-PWML)

V_CST(MIN)/ R_CS

I_M

t_ON(MIN)

PWML

f_BUR

PWMH

RUN

I_VDD

I_RUN

I_WAIT

图 7-33. PWM Pattern in SBP1

7.4.9 Second Standby Power Mode (SBP2)

When f_BURis below the 8.5-kHz upper burst frequency threshold (f_SBP2(UP)), UCC28781 exits SBP1 mode

and enters into SBP2 mode. Compared with the SBP1 mode, the pulse count is doubled and V_CSTcan be

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programmed by the IPC pin. The V_CSTprogrammable range in SBP2 is between 0.27 V and 0.4 V. The purpose

of SBP2 is to further lower f_BURin order to minimize standby power.

The f_BURcondition to trigger the mode transition from SBP2 to SBP1 depends on the IPC pin voltage setting as

well. If V_IPCis set lower than 0.9 V or the IPC pin is shorted to AGND, V_CSTis equal to V_{CST_IPC(MIN)}, and the

mode transition occurs when f_BURis increased above the same 8.5-kHz threshold. On the other hand, if V_IPC

is set higher than 0.9 V, V_CSTis higher than 0.27 V, and the mode transition occurs when f_BURis increased

above the 1.7-kHz lower burst frequency threshold (f_SBP2(LR)). The purpose of skipping the burst frequency range

between 1.7 kHz and 8.5 kHz is to avoid the most sensitive audible frequency range to the human ear. The

frequency skipping is only enabled, when the peak current is set higher by V_IPC> 0.9 V.

SBP2 for V_IPC< 0.9 V

SBP2 for V_IPC≥ 0.9 V

t_D(RUN-PWML)

V_{CST_IPC}/ R_CS

V_CST(MIN)/ R_CS

I_M

t_ON(MIN)

PWML

PWMH

PWML

PWMH

RUN

I_VDD

RUN

I_VDD

I_RUN

I_WAIT

图 7-34. PWM Pattern in SBP2

7.4.10 Startup Sequence

图 7-35 shows the simplified block diagram related with the VDD startup function of UCC28781, and 图 7-36

addresses the startup sequence. 表 7-2 describes specific startup waveform time periods.

D_AUX

SWS

I

SWS

VDD

R

SWS

I

VDD

Q_DDS

R_DDS

Q

S

V

AUX

V

SW

C_SWS

D

UVLO

Q

DDP

SWS

C

VDD

N

AUX

P13

S13

R

DDP

13-V

Regulator

5-V

Regulator

Q

P13

I

P13

I_REF

REF

C

P13

D

RUN

P13

Q

S13

C_REF

C

S13

图 7-35. Functional Startup Block Diagram

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V

VDD(ON)

V

VDD

V

P13

V

P13(OV)

13 V

V

VDD(OFF)

1.8 V

I

P13

I

P13(START)

I

VDD(LIMIT)

I

SWS

RUN

V

S13_OK

V

REF

V

REF_OK

V

S13

PWML

I

VSL

I

RUN

I

VDD

V

CST(SM2)

CST(SM1)

(F)

V

CST(MAX)

V

CST

V

O

(A)

(B)

(C)

(D)

(E)

(H)

(J)

(K)

图 7-36. Startup Timing Waveforms

表 7-2. Startup Time Intervals

TIME

PERIOD

DESCRIPTION

The UVLO circuit commands the two internal power-path switches (Q_DDSand Q_DDP) to close the connections between SWS,

VDD, and P13 pins through two serial current-limiting resistors (R_DDSand R_DDP). The depletion-mode MOSFET (Q_S) starts

sourcing charge current (I_SWS) safely from the high-voltage switch-node voltage (V_SW) to the VDD capacitor (C_VDD). Before

V_VDDreaches 1.8 V, I_SWSis limited by the high-resistance R_DDSof 5 kΩ to prevent potential device damage if C_VDDor VDD pin

is shorted to ground.

A

B

After V_VDDrises above 1.8 V, R_DDSis reduced to a smaller resistance of 0.5 kΩ. I_SWSis increased to charge C_VDDfaster. The

maximum charge current during VDD startup can be quantified by Equation 8.

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表 7-2. Startup Time Intervals (continued)

TIME

PERIOD

DESCRIPTION

As V_VDDreaches V_VDD(ON)of 17 V, the ULVO circuit turns-off Q_DDSto disconnect the source pin of Q_Sto C_VDD, and turns-off

Q_DDPto break the gate-to-source connection of Q_S, so Q_Sloses its current-charge capability. V_VDDthen starts to drop, because

the 5-V regulator on REF pin starts to charge up the reference capacitor (C_REF) to 5 V, for which the maximum charge current

(I_SE(REF)) is self-limited at around 17 mA. After V_REFis settled, the UVLO circuit turns-on another power-path switch (Q_P13), so

an internal 13-V regulator is connected to the P13 pin. The voltage on the P13 pin capacitor (C_P13) starts to be discharged by

the regulator.

C

While discharging the recommended 1 µF on C_P13, the sink current of the 13-V regulator (I_P13(START)) is self-limited at around

2.2 mA, so it takes longer than 10 μs to settle to 13 V. If V_P13reaches 13 V in less than 10 μs, the P13 pin open fault is triggered

to protect the device. Once V_P13has settled to 13 V without the fault event, RUN pin goes high and the controller enters a run

D

E

state with I_VDD= I_RUN

.

There is a minimum 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up the isolated gate driver

and controller. In this interval, the 2.8-Ω power path switch between the P13 pin and the S13 pin is enabled, so the S13-pin

decoupling capacitor (C_S13) is charged up and the charge current is supplied from C_P13and the P13 regulator. If 2.2-μs delay is

timed out before V_S13reaches to the 10-V power good threshold (V_{S13_OK}), the PWML switching instance is further delayed.

This is the soft-start region of peak magnetizing current. The first purpose is to limit the supply current if the output is short. The

second purpose is to push the switching frequency higher than the audible frequency range during repetitive startup situations.

At the beginning of V_Osoft-start, the peak current is limited by two V_CSTthresholds. The first V_CSTstartup threshold (V_CST(SM1)

is clamped at 0.2 V and the following second threshold (V_CST(SM2)) is 0.5 V. When V_CST= V_CST(SM1), PWMH is disabled if

the sampled VS pin voltage (V_VS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After the

)

F

sampled V_VSexceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from V_CST(SM1)

to V_CST(SM2). In case of the inability to build up V_Owith V_CST(SM1)at the beginning of the V_Osoft-start due to excessively large

output capacitor and/or constant-current output load, there is an internal time-out of 0.7 ms to force V_CSTto switch to V_CST(SM2)

.

When V_VSrises above 0.5 V, V_CSTis allowed to reach V_CST(MAX), so the ramp rate of V_Ostartup becomes faster. When PWML

is in a high state, I_VDDcan be larger than I_RUN, because the 5-V regulator provides the line-sensing current pulse (I_VSL) on the

VS pin to sense V_BULKcondition.

H

J

When V_Ogets close to the target regulation level, V_CSTstarts to reduce from V_CST(MAX)

.

K

V_Oand V_CSTsettle, and the auxiliary winding takes over the VDD supply.

7.4.11 Survival Mode of VDD (INT_STOP)

When an output voltage overshoot occurs during step-down load transients, the V_Ofeedback loop commands

the UCC28781 controller to stop switching quickly by increasing I_FB, in order to prevent additional energy

from aggravating the overshoot. Since V_VDDdrops during this time, the typical way to prevent a controller

from shutting down is to oversize the VDD capacitor (C_VDD) so as to hold V_VDDabove V_VDD(OFF). Instead,

the controller is equipped with survival-mode operation to hold V_VDDabove V_VDD(OFF)during a transient event.

Therefore, the size of C_VDDcan be significantly reduced and the PCB footprint for the auxiliary power can be

minimized. Specifically, there is a ripple comparator to regulate V_VDDabove a 13-V threshold, which is V_VDD(OFF)

plus V_VDD(PCT)in the electrical table. The ripple regulator is enabled when the V_Ofeedback loop requests the

controller to stop switching due to V_Oovershoot.

The regulator initiates unlimited PWML pulses when V_VDDdrops lower than 13 V, and stops switching after V_VDD

rises above 13 V. Since V_VDDis lower than the reflected output voltage overshoot, most of the magnetizing

energy is delivered to the auxiliary winding and brings V_VDDabove 13 V quickly. After V_Omoves back to the

regulation level, V_Ofeedback loop forces the controller to begin switching again by reducing I_FB, and the PWML

and PWMH pulses are then controlled by the normal operating mode.

To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival

mode at zero load, follow these guidelines for the auxiliary power delivery path to VDD.

•

The normal V_VDDlevel under regulated V_Omust be designed to be above the 13-V threshold by an

appropriate turns count for the auxiliary winding.

C_VDDshould not be over-sized, but designed just large enough to hold V_VDD> V_VDD(OFF)under the longest V_O

soft-start time.

An auxiliary resistor in series with the auxiliary rectifier diode (D_AUX) should not be too large of value,

because the lower series impedance can help the VDD capacitor to charge faster.

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•

Ensure good coupling between the auxiliary winding (N_AUX) and the secondary winding (N_S) of the

transformer.

Ensure that the DC resistance of the auxiliary winding is less than 0.1 Ω.

7.4.12 System Fault Protections

The UCC28781 provides extensive protections on different system fault scenarios. The protection features are

summarized in 表 7-3.

表 7-3. System Fault Protection

DELAY TO

ACTION

ACTION BY UCC28781

PROTECTION

SENSING

THRESHOLD

VDD UVLO

Brown-in detection

VDD voltage

VS current

V_VDD(OFF)≤ V_VDD≤ V_VDD(ON)

I_VSL≤ I_VSL(RUN)

I_VSL≤ I_VSL(STOP)

None

UVLO reset

4 PWML pulses UVLO reset

Brown-out detection VS current

t_BO(60ms) plus 3 UVLO reset

confirming PWML

pulses

Over-power

CS voltage

V_CST(OPP)≤ V_CST≤ V_CST(MAX)

V_CST≤ V_CST(MAX)

t_OPP(160 ms)

t_FDRrestart (1.5s)

protection (OPP)¹

Peak-power limit

(PPL)

Over-current

V_CS≥ V_OCP

3 PWML pulses t_FDRrestart

protection (OCP)

Output short-circuit CS, VS, and

protection (SCP)

(1) V_VDD= V_VDD(OFF)& V_CST≥ V_CST(OPP), or

VDD voltages (2) V_VDD= V_VDD(OFF)& V_VS≤ V_VS(SM2)

≤ t_OPP

t_FDRrestart

Output over-voltage VS voltage

protection (OVP)

V_VS≥ V_OVP

3 PWML pulses t_FDRrestart

Over-temperature

protection on FLT

pin (OTP)

FLT voltage

CS voltage

FLT voltage

R_NTC≤ R_NTCTH

t_FLT(NTC)(50 µs) UVLO reset until

R_NTC≥ R_NTCR

Over-temperature

protection on CS pin

(OTP)

V_CS≥ V_OCP

2 PWMH pulses t_FDRrestart

Input over-voltage

protection (IOVP)

V_FLT≥ V_IOVPTH

T_J≥ T_J(STOP)

t_FLT(IOVP)(750 µs) UVLO reset until

V_FLT< V_IOVPTH- V_IOVPR

Thermal shutdown

Junction

3 PWML pulses UVLO reset

temperature

(1) OPP not available in UCC28781A.

7.4.12.1 Brown-In and Brown-Out

The VS pin senses the negative voltage level of the auxiliary winding during the on-time of the low-side switch

(Q_L) to detect an under-voltage condition of the input AC line. When the bulk voltage (V_BULK) is too low, the

UCC28781 controller stops switching and no V_Orestart attempt is made until the AC input line voltage is back

into normal range. As Q_Lturns on with PWML, the negative voltage level of the auxiliary winding voltage (V_AUX

)

is equal to V_BULKdivided by primary-to-auxiliary turns ratio (N_PA) of the transformer, which is N_P/ N_A. During this

time, the voltage on VS pin is clamped to about 250 mV below GND. As a result, V_AUXcan create a line-sensing

current (I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1).

With I_VSLproportional to V_BULK, it can be used to compare against two under-voltage thresholds, I_VSL(RUN)and

I_VSL(STOP)

.

The target brown-in AC voltage (V_AC(BI)) can be programmed by the proper selection of R_VS1. For every UVLO

cycle of VDD, there are at least four initial test pulses from PWML to check I_VSLcondition. I_VSLof the first

test pulse is ignored. If I_VSL≤ I_VSL(RUN)is valid for the next three consecutive test pulses, the controller stops

switching, the RUN pin goes low, and a new UVLO start cycle is initiated after V_VDDreaches V_VDD(OFF). On the

other hand, if I_VSL> I_VSL(RUN)occurs, V_Osoft start sequence is initiated.

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V_{AC(BI )}

2

V_{AC(BI )}2

N_A

R_VS1

=

N_PAì I_{VSL(RUN )}N_P365

m

A

(14)

The brown-out AC voltage (V_AC(BO)) is set internally by approximately 83% of V_AC(BI), which provides enough

hysteresis to compensate for possible sensing errors through the auxiliary winding.

I_VSL(STOP)

V_AC(BO)

=

V_{AC(BI )}= 0.83ìV_{AC(BI )}

I_{VSL(RUN )}

(15)

A 60-ms timer (t_BO) is used to bypass the effect of line ripple content on the I_VSLsensing. Only when the I_VSL

≤

I_VSL(STOP)condition lasts longer than 60 ms (i.e. typically three line cycles of 50 Hz) and 3 additional switching

cycles verify the condition, the brown-out fault is triggered. If switching is interrupted, the brown-out fault will

remain pending without shut-down until the 3 verification cycles complete. The fault is reset after V_VDDreaches

V_VDD(OFF). 图 7-37 shows an example of the timing sequence of brown-out and brown-in protections for the case

of an actual input brown-out condition.

图 7-37. Timing Diagram of Brown-Out/Brown-In Response on AC Line Events

The t_BOtimer is started at the moment I_VSL≤ I_VSL(STOP)is detected during the PWML on-time. The timer is

cleared when I_VSL> I_VSL(STOP)is detected. In the case of an overshoot voltage on the output, switching will stop

until the output voltage recovers to the regulation level. If the t_BOtimer is triggered by I_VSL≤ I_VSL(STOP)while in

the valley of the bulk ripple voltage, and then switching is stopped the status of I_VSLcannot be detected and

updated. The timer cannot be cleared without switching to sample I_VSL, and the 60-ms timer may elapse even

though no brown-out condition exists. To prevent an unwarranted shut-down, the 3 additional switching cycles

sample the condition once switching does resume, to verify or dismiss the pending apparent brown-out fault. An

extended output overshoot condition longer than t_BOcan result from a sudden load drop combined with a drop

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in the regulation reference due to reduction of cable compensation. Figure 8-38 shows an example of the timing

sequence for the case of an apparent brown-out cancelled by 3 verifying pulses.

图 7-38. Timing Diagram of Brown-Out Response on Extended Output Overshoot

7.4.12.2 Output Over-Voltage Protection (OVP)

The VS pin is used to sense the positive voltage level of the auxiliary winding voltage (V_AUX) to detect an

over-voltage condition of V_O. When an OVP event is triggered, the auto-recovery version of OVP stops switching

and there is a 1.5-s fault recovery time (t_FDR) before any V_Orestart attempt is made. As Q_Lturns off, the settled

V_AUXis equal to (V_O+V_F) x N_AS, where N_ASis the auxiliary-to-secondary turns ratio of the transformer, N_A/ N_S,

and V_Fis the forward voltage drop of the secondary-side rectifier. The VS pin senses V_AUXthrough a voltage

divider formed by R_VS1and R_VS2. The pin voltage (V_VS) is compared with an internal OVP threshold (V_OVP). If

V_VS≥ V_OVPcondition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN

pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of V_VDDis active, and

there are no test pulses of PWML. After the 1.5-s timeout is completed and V_VDDreaches the next V_VDD(OFF), a

normal start sequence begins. The calculation of R_VS2is

R_VS1ìV_OVP

R_VS1ì4.5V

R_VS2

=

N_ASì(V_O(OVP)+V_F) -V_OVP(N_A/ N_S)(V_O(OVP)+V_F) - 4.5V

(16)

The long t_FDRtimer (1.5 s) helps to protect the power stage components from the large current stress during

every restart and allows some time for V_Oto discharge in the case of light-load or no-load, before attempting

restart.

7.4.12.3 输入过压保护 (IOVP)

UCC28781 在 FLT 引脚上提供输入 OVP 功能。图 7-39 展示了用于输入 OVP 检测的应用电路。电阻分压器可检

测大容量电容器电压，当 V_FLT高于 4.5V 且持续时间超过 750µs 时会触发 IOVP 故障。750µs 延迟有助于降低对

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线路浪涌条件下突然出现的大容量电压尖峰的敏感性，从而使输出电压不会意外下降。IOVP 故障置位后，开关立

即停止，V_VDD重新启动。当 V_VDD达到下一个 VDD 周期的 V_VDD(ON)时，控制器会在开关之前首先确认 V_FLT，从

而避免开关器件暴露在高压应力条件下。当 V_FLT低于 4.43V 时清除故障。

如果需要超过 750µs 的延迟，FLT 引脚和 AGND 引脚之间的滤波电容器可以产生额外的可编程延迟。如果滤波电

容器过大，当 RUN 引脚被拉高后 V_FLT上升到高于 V_NTCTH的斜升时间超过 t_FLT(NTC)时，它可能会触发 FLT 引脚

上的 OTP 故障。由于控制器会在 V_FLT高于 2.5V 时禁用电流源，因而电阻分压器设计无需考虑来自 FLT 引脚的

50µA 电流源的失调电压影响。

FLT 引脚上的内部 5.5V 钳位器件的目标是在其中一个 IOVP 上检测电阻器发生短路时保护引脚不超过电压限值。

最大钳位电流为 150µA，电阻分压器设计需要考虑这一限制。

V_BULK

I_FLT

R_FLT1

V_IOVP

R_FLT2

INPUT OVP FAULT

OTP FAULT

œ

t_FLT(IOVP)delay

(750µs)

(4.5V/4.43V)

FLT

+

V_FLTZ

(5.5V)

R_FLT3

C_FLT

+

t_FLT(NTC)delay

(50µs)

V_NTCTH

(0.5V/1.15V)

œ

图 7-39. 用于输入 OVP 的大容量电容器电压检测

7.4.12.4 FLT 引脚上的过热保护 (OTP)

UCC28781 使用连接到 FLT 引脚的外部 NTC 电阻器 (R_NTC) 对转换器热点附近的热关断温度进行编程。NTC 关

断阈值 (V_NTCTH) 为 0.5V，流经 R_NTC的内部电流源为 50μA，产生 10kΩ 的热敏电阻关断阈值。如果 NTC 电阻

保持低于 10kΩ 状态的时间超过 50μs，则会触发 OTP 故障事件。当 NTC 电阻器远离控制器但靠近热点时，50μs

的延迟 (t_FLT(NTC)) 允许在 FLT 引脚和 AGND 引脚之间放置一个滤波电容器 (C_FLT)。为避免由于 RUN 变为高电平

而引起的 OTP 故障，C_FLT应设计为在 t_FLT(NTC)内允许 V_FLT增加到高于 V_NTCTH。另一方面，如果 NTC 电阻器靠

近控制器并且没有连接到检测布线的潜在噪声耦合路径，则不需要 C_FLT

。

为了恢复，在 OTP 故障后，0.5V 阈值会增加到 1.15V，因此 NTC 电阻必须增加到 23kΩ 以上才能复位 OTP 故

障。该阈值变化提供了安全的温度迟滞，有助于在下一次 V_O重新启动尝试之前使降低热点温度，从而降低元件的

热应力。如果不使用 FLT 引脚，该引脚可保持悬空，但不能连接到 REF 引脚，因为会错误触发线路 OVP。

重输出负载条件下的散热问题是 OTP 的主要设计考虑因素，重负载工作模式 AAM 允许控制器持续处于运行状

态，因此 50μs 延迟允许 V_FLT触发 OTP。根据实际的 BUR 引脚设置，在 AAM 下运行 50% 至 60% 的负载。

为节省待机功耗，在 ABM、LPM、SBP1 和 SBP2 等轻负载模式的突发关断时间内禁用 50μA 电流源。然而，在

这些模式下，当运行状态短于 50μs 且电流源在等待状态下被禁用时，由于没有足够的时间检测故障，因此将无法

触发 OTP。因此，如果某些设计注意事项仍然要求在轻负载模式下启动 OTP，则可以通过重复使用输入 OVP 的

4.5V 阈值来进行第二个 OTP 配置。如图 7-40 所示，上 NTC 电阻器和下电阻器在 REF 引脚与 FLT 引脚之间构

成一个电阻分压器。750μs 的延迟与控制器的等待状态条件无关，因此在轻负载模式下仍可触发 OTP 故障。

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1^stOTP Sensing

2^ndOTP Sensing

REF

R_NTC

FLT

R_NTC

R_FLT

C_FLT

图 7-40. 用于在 FLT 引脚上实现 OTP 的两个连接

1.15 V

V_NTC

0.5 V

t_FLT(NTC)

OTP Fault

V_VDD

V_VDD(ON)

V_VDD(OFF)

PWML

图 7-41. FLT 引脚和 AGND 引脚之间的 NTC 的 OTP 时序图

7.4.12.5 CS 引脚上的过热保护 (OTP)

如果 FLT 引脚已用于输入 OVP 检测，UCC28781 可在 CS 引脚上提供第三个和第四个 OTP 功能。这两种配置

不会影响 CS 引脚和 OPP 电平上的电流检测信号，因为两个检测电路仅在 PWML 关闭后偏置。图 7-42 展示了两

个应用电路。对于第三个 OTP 配置，当 PWMH 引脚被拉高时，R_NTC和 R_OPP构成一个电阻分压器，可在 CS 引

脚上创建与温度相关的电压信号。当电压超过在退磁时间 (T_DM) 结束前连续两个周期采样的 1.2V 阈值时，将触发

OTP 故障。OTP 检测电路不影响峰值电流环路的运行，因为 PWMH 在 PWML 导通时间持续时间内被拉至低电

平。1.5s 长时计时器启动，控制器保持故障状态而无需切换。较长的恢复时间可实现温度迟滞，有助于在下一次

V_O重新启动尝试之前使热点温度降低。与 FLT 引脚上的第一个 OTP 配置相比，此配置允许在 AAM 和 ABM 中启

动 OTP，因此仍可在大约 25% 的输出负载下触发 OTP。

采用小信号 PMOS 的第四个配置是覆盖宽输出负载范围的最全面方法。RUN 引脚用于偏置检测电路，PMOS 栅

极由 PWML 引脚控制，仅在 PWML 为低电平时才允许进行检测。

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3^rdOTP Sensing

4^thOTP Sensing

RUN

PWML

PWMH

Q_RUN

R_NTC

R_OPP

CS

R_CS

C_CS

图 7-42. 用于在 CS 引脚上实现 OTP 的两个连接

7.4.12.6 可编程过功率保护 (OPP)

备注

在 UCC28781A 中，始终禁用 OPP 计时器功能，并且本节中的 160ms 计时器项不适用。V_CST阈值和

下图的限制曲线（I_VSL上的 V_CSTOPP 曲线）保持有效和活动状态，但在 160ms 后没有关断或故障状

态。

过功率保护 (OPP) 允许在有限的时间内和过功率条件下运行，因此 UCC28781 能够支持具有临时峰值功率要求的

功率级设计。如下图所示（I_VSL上的 V_CSTOPP 曲线），当 V_CST高于 OPP 曲线的阈值电压 (V_CST(OPP)) 时，将

启动 160ms 计时器。如果 V_CST持续高于 V_CST(OPP)长达 160ms，则 1.5s 计时器启动，控制器保持故障状态而无

需切换。较长的恢复时间可降低持续过功率事件期间的平均电流。系统优势包括降低高密度适配器中的热应力以

及保护其输出电缆。

OPP 功能使用 I_VSL作为线路前馈信号，根据 V_BULK来改变 V_CST(OPP)，以便使 OPP 触发点在宽线路电压范围内

保持恒定。UCC28781 能够通过 CS 引脚和电流检测电阻器 (R_CS) 之间连接的电阻器 (R_OPP) 在 CS 引脚上添加线

路补偿失调电压，从而实现 OPP 曲线的可编程性。从 CS 引脚流出的内部电流源会在 R_OPP上产生失调电压。该

电流电平等于 I_VSL除以 K_LC的恒定增益。随着 R_OPP的增加，OPP 触发点在高压线路上变得更低，因此允许较低

的峰值磁化电流持续运行。

OPP 功能使用 V_VS作为输出电压前馈信号，将依赖于线路的 V_CST(OPP)曲线修改为两个不同的集，从而使 OPP

触发点在宽输出电压范围内更加一致。V_VS高于 2.5V 时的较高 OPP 阈值包含两个分段线性区域，而 V_VS低于

2.4V 时的较低 OPP 阈值包含一个分段线性区域。

OPP 曲线的最高阈值 (V_CST(OPP1)) 为 0.6V，有助于确定 V_BULK(MIN)时的 R_CS值。

V_{CST (OPP1)}

R_CS=

P

V_{BULK (MIN )}t_{D(CST )}

2

O(OPP)

-

V_{BULK (MIN )}

h

D_MAX

L_M

(17)

•

其中 P_O(OPP)是触发 OPP 的输出功率

t_D(CST)是峰值电流环路中所有延迟的总和，会导致额外的峰值电流过冲

t_D(CST)包括低侧驱动器的传播延迟、电流检测滤波器延迟 (R_OPPx C_CS)、内部 CS 比较器延迟 (t_D(CS)) 和 Q_L的非

线性电容延迟。确定 R_CS后，可以调整 R_OPP，在最高线保持类似的 OPP 点。请注意，如果所设置 OPP 触发点

与全功率差距过大，可能会给散热设计带来更多挑战，因为只要相应的峰值电流略小于 OPP 阈值，转换器就会以

更大的功率持续运行。

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V_CST

V_CST(MAX)for V_VS> V_VSLV(UP)

V_{CST(MAX)_LV}for V_VS< V_VSLV(LR)

V_CST(OPP)for V_VS> V_VSLV(UP)

V_{CST(OPP)_LV}for V_VS< V_VSLV(LR)

0.8 V

0.655 V

0.628 V

0.6 V

0.57 V

0.54 V

0.491 V

0.471 V

0.4275V

0.405V

i_VSL

233 µA 433 µA

966 µA

图 7-43. I_VSL上的 V_CSTOPP 曲线

t_OPPTimer

t_FDRTimer

160ms

1.5s

V_VDD(ON)

V_VDD

V_VDD(OFF)

I_O

V_CST(MAX)

V_CST(OPP)

V_CST

V_CST(SM2)

V_CST(SM1)

PWML

V_O

图 7-44. OPP 时序图

7.4.12.7 峰值功率限制 (PPL)

OPP 曲线的峰值电流阈值用于启动 160ms 计时器（UCC28781A 除外，其中 OPP 计时器始终处于禁用状态)，而

峰值功率限制 (PPL) 决定峰值电流环路的最高可控峰值电流 V_CST(MAX)。无论 V_VS如何，V_CST(MAX)和 V_CST(OPP)

之间的比率固定在大约 4/3。换句话说，此功能可提供转换器可提供的最长短时峰值功率 (P_O(MAX))。与线路相关

的 PPL 曲线能够在宽输入电压范围内实现一致的峰值功率电平。例如，要提供负载为标称额定负载的 150% 的最

高峰值功率，需选择一个 R_CS值，以此确保负载为 150% 时的峰值电流阈值和 V_BULK(MIN)不能高于 V_CST(MAX)

然后，可以根据以下公式将 OPP 功率 (P_O(OPP)) 的阈值编程为大约 112%，来支持 150% 的峰值功率设计。

。

V

CST OPP1

0.6 V

x P

O max

0.8 V

P

=

x P

=

(18)

O OPP

O max

V

CST max

此外，在 V_O软启动期间，在 V_O达到稳态调节之前，最高 V_CST也可以达到 V_CST(MAX)。变压器最大磁通密度必

须具有足够的设计裕度，以应对处于 PPL 时峰值电流下磁芯材料的高温饱和极限。

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7.4.12.8 输出短路保护 (SCP)

当施加输出短路时，峰值电流达到 PPL 限制并触发 160ms OPP 故障计时器，UCC28781A 除外。在此事件期

间，由于辅助绕组电压接近 0V，VDD 电源将会丢失。如果没有额外的短路检测，当 V_VDD在 160ms 超时之前

达到 V_VDD(OFF)时，不会触发 OPP 故障的 1.5s 恢复时间，而只会执行 UVLO 循环。为了纠正这种情况，当

V_VDD达到 V_VDD(OFF)时，UCC28781 会确认两个附加参数来识别输出端的短路事件，并触发故障响应而无需等待

160ms 超时。具体而言，当 V_VDD达到 V_VDD(OFF)时，如果 V_CST大于 OPP 阈值 (V_CST(OPP)) 或 VS 引脚电压低

于 0.5V，则会启动 1.5s 恢复延迟来实现自动恢复。借助这一额外智能功能，可大大降低持续短路事件期间的平均

负载电流，也可降低电源的热应力。

7.4.12.9 过流保护 (OCP)

UCC28781 控制器运行时采用逐周期初级峰值电流控制。CS 引脚的正常工作范围为 V_CST(MIN)至 V_CST(MAX)。如

果 CS 引脚电压超过 1.2V 过流电平，则在内部前沿消隐时间 (t_CSLEB) 之后以及变压器退磁结束之前的任何时间，

在连续三个 PWML 周期内，器件都会停止开关，RUN 引脚变为低电平，并触发故障响应。与 OVP、OPP 和

SCP 类似，只有 VDD 的 UVLO 周期有效，根本没有测试 PWML 脉冲。在 1.5s 超时完成且 V_VDD达到下一个

V_DD(OFF)时，开始正常的启动序列。

7.4.12.10 External Shutdown

The REF pin may be used as an external shutdown function by shorting this pin to AGND with a small-signal

control switch. This provides an additional design flexibility for the control function extension with external

circuitry. When the REF-pin voltage drops lower than its internal power good threshold (approximately 4.5 V), the

switching action will be terminated and V_VDDwill drop to V_VDD(OFF), and the controller begins the UVLO restart

cycle.

As long as the REF pin is shorted to AGND continuously, the UVLO restart cycle will repeat and switching action

is inhibited until the external pull-down on REF is released. During the switch-short condition on REF, the falling

slope of V_VDDwill drop faster than normal case due to the 17-mA over-current limit of the REF regulator which

discharges the VDD capacitor faster than the normal I_VDDcurrents in the run and wait states.

7.4.12.11 Internal Thermal Shutdown

The internal over-temperature shutdown threshold is higher than 125°C. If the junction temperature of the device

reaches this threshold, the device initiates a UVLO reset and restart fault cycle. If the temperature is still high at

the end of the UVLO cycle, the protection cycle repeats. This internal protection is not suitable as a substitute

for the NTC for hot-spot temperature protection. An NTC thermistor provides more accurate temperature sensing

and may be placed in a remote location for less compromise on PCB layout.

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7.4.13 Pin Open/Short Protections

As summarized in 表 7-4, UCC28781 strengthens the protections of several critical pins under "open" and "short"

conditions, such as CS, P13, RDM, and RTZ pins. The pin protections are all in auto-recovery modes. All "short"

conditions are defined as short-circuits to AGND.

表 7-4. Protections for Open and Short of Critical Pins

DELAY TO

ACTION

PROTECTION

SENSING

CONDITION

ACTION

> 2 μs (V_SET= 5 V)

PWML on-time at first PWML

pulse only

CS pin short

> 2 μs (V_SET= 0 V, R_RDM≥ R_RDM(TH)

)

none

t_FDRrestart (1.5 s)

> 1 μs (V_SET= 0V, R_RDM< R_RDM(TH)

)

3 PWML

pulses

CS pin open

P13 pin open

CS voltage

P13 voltage at UVLO_ON

P13 voltage

V_CS≥ V_OCP

t_FDRrestart (1.5 s)

UVLO reset

V_P13drops to 14 V within 10 μs

V_P13≥ V_P13(OV)+ V_P13(REG)

none

P13 pin over

voltage

3 PWML

pulses

UVLO reset

RDM pin short

RDM pin open

RTZ pin short

RTZ pin open

RDM current at UVLO_ON

RTZ current at UVLO_ON

V_RDM= 0 V, self-limited I_RDM

RDM = Open

none

UVLO reset

V_RTZ= 0 V, self-limited I_RTZ

RTZ = Open

XCD pin over

voltage

XCD voltage

V_XCD> V_XCD(OVP)

750 μs

UVLO reset

7.4.13.1 Protections on CS pin Fault

UCC28781 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML

pulse after V_VDDstartup is completed. As shown in 图 7-36, the normal first on-time pulse width should be

limited by the clamped V_CST(SM1)level of 0.2 V and the rising slope of the current-loop feedback signal from

the current-sense resistor (R_CS) to the CS pin. When the current feedback path is gone due to a CS pin short

to GND, the peak magnetizing current increases and potentially can damage the power stage. Therefore, a

maximum on-time of the first PWML pulse for V_SET= 5 V, t_CSF1of 2 μs in the electrical table, is used to limit

the first peak-current stress of the silicon-based converter and then will trigger a CS pin short protection which

initiates the t_FDRrecovery of 1.5 s in auto-recovery mode.

Additionally, t_CSF0in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-

based converter with V_SET= 0 V. There are two corresponding values based on two predetermined ranges

of the RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically,

t_CSF0is set at 2 μs with R_RDMhigher than the R_RDM(TH)threshold of 55 kΩ, while t_CSF0is reduced to 1 μs

under R_RDM< R_RDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency

with lower magnetizing inductance (L_M), it is possible that the peak current can be increased higher than a

lower switching-frequency design under the same V_CST(SM1)level and same on-time of PWML. The RDM pin can

provide a good indication of the switching frequency range of a GaN power stage, since the lower L_Mrequires

smaller R_RDMsetting. With a different t_CSF0setting, the CS pin fault adapts to a wide switching frequency range.

Unlike a CS pin short protection which senses only the first on-time pulse width of PWML only, CS pin open

protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is

used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition. If

the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML pulses,

the CS pin open protection is triggered which initiates the 1.5-s recovery.

7.4.13.2 Protections on P13 pin Fault

As shown in 图 7-36, after V_VDDreaches V_VDD(ON), an internal 13-V regulator on the P13 pin should force V_P13

back to the regulation level before PWML starts switching. If the recommended P13-pin capacitor (C_P13) of 1 µF

and the connection to the depletion-mode MOSFET (Q_S) are in place, the settling time of V_P13to 14 V is much

longer than 10 μs with a limited 1.9-mA sink current of the regulator (I_P13(START)) to discharge C_P13

.

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The first fault scenario is that if C_P13is too small, or the P13 pin is open, the pin is not able to control Q_Scorrectly

for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two

situations happen, V_P13settles to 13 V very quickly instead. Therefore, after a 10-μs delay from the instant of

V_VDDreaching V_VDD(ON), UCC28781 checks if V_P13is below 14 V for the pin-fault detection, and then performs

one UVLO cycle of VDD directly without switching as the protection response.

The above protection is to prevent the controller from generating PWM signals. However, when the P13 pin is

open and disconnected from the Q_Sgate, the source voltage of Q_Skeeps increasing. To protect the P13-pin

open event, a small Zener diode (D_P13) between Q_Sgate to AGND should be used to limit the Q_Ssource

voltage. D_P13should be higher than V_VDD(ON), so as to prevent interference with normal VDD startup. A 20-V

Zener diode is recommended.

The second fault scenario is the over-voltage condition of P13 pin after the converter starts switching. When

the switch-node voltage (V_SW) rises with a high dV/dt condition, there is a charge current flowing through the

junction capacitance of Q_S, and part of the current can charge up C_P13. If the overshoot is too large, the voltage

on the SWS pin also increases due to the nature of depletion-mode MOSFET operation. UCC28781 detects the

overshoot event on P13 pin with a 15-V over-voltage threshold cycle-by-cycle. When V_P13is higher than 15 V for

three consecutive PWML pulses, the P13 over-voltage protection is triggered which performs one UVLO cycle of

VDD.

The third fault scenario is an P13 pin short event at the beginning of VDD startup, and Q_Sis unable to charge up

the VDD capacitor to V_DD(ON), so there is no chance to enable the controller.

7.4.13.3 Protections on RDM and RTZ pin Faults

Since RDM and RTZ pins are the critical programming pins for ZVS control, UCC28781 offers both open-circuit

and short-to-GND protections for those pins. At initial start-up when V_VDDreaches V_VDD(ON)and before switching

begins, a fixed voltage level is applied to each pin and the corresponding current level flowing out of the pin is

sensed to detect a pin-fault condition. As a result, too small of a current represents the pin-open state, and too

large of a current represents the pin-short state where the short-circuit current level is self-limited.

In general, maintain 2 kΩ < R_RDM< 500 kΩ and 20 kΩ < R_RTZ< 1.1 MΩ with ample margins to avoid triggering

one of these faults. When a pin-fault condition is identified, no switching is allowed and one UVLO cycle of VDD

is triggered as the protection response. The normal start-up sequence will proceed on the next VDD cycle after

the fault condition is removed.

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8 Application and Implementation

备注

以下应用部分中的信息不属于 TI 元件规格，TI 不担保其准确性和完整性。TI 的客户负责确定元件是否

适合其用途，以及验证和测试其设计实现以确认系统功能。

8.1 Application Information

A typical application of a high-frequency zero-voltage switching flyback (ZVSF) converter, using the UCC28781

controller, is to enable high-density DC-to-DC or AC-to-DC power supply design which complies with stringent

global and application-specific efficiency standards and high-density power packaging. Both Silicon (Si) and

Gallium Nitride (GaN) power MOSFETs may be used, with appropriate gate drivers for either (if necessary).

8.2 Typical Application Circuit

The following application circuit implements a 60-W, 15-V Si-MOSFET-based ZVSF power stage.

Transformer

D_BG

F_AC

V_O

V_BULK

V_AC

L_K

C_X

C_BULK

L_M

N_P

N_S

C_O

GND

Q_SR

D_RUN

Isolated Driver

(primary side)

Isolated Driver

(secondary side)

R_XCD1

R_XCD2

V_P13

C_RUN

Q_S

D_SWS

Q_XCD

V_P13

PWMH

RUN

Q_L

R_SWS

PWML

V_SWS

PGND

R_BIAS1

C_SWS

V_RCS

D_AUX

R_CS

R_BIAS2

C_VDD1

N_A

CC/CV

Controller

V_P13

V_S13

D_P13

C_VDD2

C_P13

R_VS1

R_VS2

VS

XCD

GTP3 GTP2 GTP1

VDD

P13

S13

SWS

V_SWS

XCD

V_REF

RUN

UCC28781

PWMH

PWML

PGND

PWML

PGND

BUR

SET

REF

FB RDM RTZ TP AGND FLT IPC

CS

R_OPP

V_RCS

V_REF

C_FB

C_REF

C_CS

R_FB

图 8-1. Typical Application Circuit

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8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input

表 8-1. Electrical Performance Specifications for AC Input, using Si MOSFET¹

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Input AC-line voltage (RMS)

90

47

115 / 230

50 / 60

42

264

63

V

f_LINE

Input AC-line frequency

Hz

V_IN= 230 V_RMS, I_O= 0 A

mW

Input power at no-load,

V_O= 15 V

5

P_STBY

V_IN= 115 V_RMS, I_O= 0 A

36

OUTPUT CHARACTERISTICS

V_IN= 180 to 264 V_RMS, I_O= 0 to I_{O(FL_HI)}

V_IN= 90 to 180 V_RMS, I_O= 0 to I_{O(FL_LO)}

14.7

15

15.3

V

V_O

Output voltage

Full-load rated output current,

high input range

4

2

A

I_{O(FL_HI)}

I_{O(FL_LO)}

V_IN= 180 to 264 V_RMS

Full-load rated output current, low

input range

V_IN= 90 to 180 V_RMS

Output ripple voltage, peak to

peak, high input range

V_IN= 180 to 264 V_RMS, I_O= 0 to I_{O(FL_HI)}

TBD

TBD mVpp

TBD

V_{O_pp}

Output ripple voltage, peak to

peak, low input range

V_IN= 90 to 180 V_RMS, I_O= 0 to I_{O(FL_LO)}

4

P_O(OPP)

Over-power protection threshold V_IN= 90 to 264 V_RMS

70

W

4

t_OPP

Over-power protection duration

V_IN= 90 to 264 V_RMS, P_O> P_O(OPP)

160

ms

Output voltage transient deviation I_Osteps between 0 A and I_{O(FL_HI)}at 100 Hz

at load-step

±1000 mVpp

ΔV_O

SYSTEMS CHARACTERISTICS

V_IN= 230 V_RMS, I_O= I_{O(FL_HI)}

V_IN= 115 V_RMS, I_O= I_{O(FL_LO)}

V_IN= 230 V_RMS

0.9336

0.9271

0.9213

0.9150

0.8684

0.8480

25

η_FL

Full-load efficiency²

η_avg

4-point average efficiency^{2 3}

Efficiency at 10% load²

V_IN= 115 V_RMS

V_IN= 230 V_RMS, I_O= 10% of I_{O(FL_HI)}

V_IN= 115 V_RMS, I_O= 10% of I_{O(FL_LO)}

V_IN= 90 to 264 V_RMS, I_O= 0 to I_O(FL)

η_10%

T_AMB

Ambient operating temperature

range

°C

(1) The performance listed in this table is based on the test results from a single board, using either DC input or AC input for their

respective results.

(2) Power losses from external input and output cables are not included in efficiency results.

(3) Average efficiency of four load points: I_O= 100%, 75%, 50%, and 25% of I_O(FL)

(4) Over-power protection (OPP) is not available in UCC28781A.

(5) Input stand-by power measured with XCD function disabled.

.

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8.2.2 Detailed Design Procedure

8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage

For off-line rectified-AC applications, the total input bulk capacitor (C_BULK) should be sized to provide energy

from the peak of the minimum input AC-line rms voltage (V_IN(MIN)) to the minimum allowable voltage (V_BULK(MIN)

)

for the power conversion stage. Due to the transition-mode operation, too low of V_BULK(MIN)selection results in

higher rms current at V_IN(MIN)and affects the full-load efficiency, while too high of V_BULK(MIN)enlarges the volume

of the bulk capacitor. This equation does not account for the hold-up time requirement over AC-line dips and

drop-outs.

V_{BULK (MIN )}

P

1

O

ì[0.5+ ìarcsin(

)]

h

p

2 ìV_{IN (MIN )}

(2ìV_{IN (MIN )}-V_{BULK (MIN )}²) ì f_LINE

C_{BULK (MIN )}

=

2

(19)

For DC-input applications, the value of C_BULKdepends on the nature of the input:

•

If the DC source is subject to brief interruptions (similar to dips and drop-outs of an AC-line), then the value of

C_BULKis calculated in a similar manner as for C_BULK(MIN)above. Δt_{DC_drop}represents the maximum expected

interruption time of the DC input.

P

O

2 ×

× Δt

DC_drop

2

η

C

=

(20)

BULK MIN

2

V

− V

BULK MIN

DC_IN MIN

•

If the DC source is consistently steady such as from a high-voltage battery, then the value of C_BULKshould be

sufficient to effectively by-pass the high-frequency primary switching current to avoid conducting significant

EMI noise back to the source.C_BULKmay be made up of more than one capacitor. Select standard values with

sufficient margin to the calculated C_BULK(MIN)to allow for tolerance and aging.

8.2.2.2 Transformer Calculations

8.2.2.2.1 Primary-to-Secondary Turns Ratio (N_PS

)

N_PSis a ratio of primary winding turns to secondary winding turns and although each winding must have a whole

number of turns, the ratio of the two is not required to be a whole number. The choice of N_PSinfluences the

design tradeoffs on the voltage ratings between primary and secondary switches, and the balance between the

magnetic core and winding loss of the transformer, which are explained in more detail as follows:

1. Maximum N_PS(N_PS(MAX)) is limited by the maximum derated drain-to-source voltage of Q_L(V_{DS_QL(MAX)}). In

the expression below, ∆V_CLAMPis the total voltage deviation above V_BULKwhen the primary TVS or RCD

clamp absorbs the leakage inductance energy of the trasnformer when Q_Lturns off. V_Ois the output voltage,

and V_Fis the forward voltage drop of the secondary rectifier.

V_{DS _QL(MAX )}-V_{BULK (MAX )}- DV_CLAMP

N_{PS(MAX )}

=

V_O+V_F

(21)

2. Minimum N_PS(N_PS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier

(V_{DS_SR(MAX)}). In the expression for N_PS(MIN), ∆V_SPIKEshould account for any additional voltage spike higher

than V_BULK(MAX)/N_PSthat occurs when Q_SRis active and turns-off at non-zero current in AAM and ABM

modes.

V_{BULK(MAX )}

N_{PS(MIN )}

=

V_{DS _ SR(MAX )}-V_O- DV_SPIKE

(22)

3. The winding loss distribution between the primary and secondary side of the transformer is the final

consideration. As N_PSincreases, primary RMS current reduces, while secondary RMS current increases.

Conversely, as N_PSdecreases, primary RMS current increases, while secondary RMS current reduces.

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8.2.2.2.2 Primary Magnetizing Inductance (L_M)

After N_PSis chosen, L_Mcan be estimated based on minimum switching frequency (f_SW(MIN)) at V_BULK(MIN)

,

maximum duty cycle (D_MAX), and output power at highest nominal output voltage, nominal full-load current

(P_O(FL)). The choice of f_SW(MIN)should consider the expected range of switching frequency as bulk voltage

increases from minimum to maximum and as load falls from maximum to the burst mode threshold. K_RES

represents the duty cycle loss to wait for the switch-node voltage transition from the reflected output voltage

to zero. Typically, f_SWmay extend to 200% to 300% f_SW(MIN)or higher. A K_RESvalue of 5% to 6% is used

as an initial estimate for GaN-based power stages, while ~10% is more appropriate for Si-based designs. The

selection of minimum switching frequency (f_SW(MIN)) should consider the impact on full-load efficiency and EMI

filter design.

N_PS(V_O+V_F)

V_{BULK(MIN )}+ N_PS(V_O+V_F)

D_MAX

=

(23)

(24)

2

D_MAXV_{BULK (MIN )}

2

h

(1- K_RES

f_{SW (MIN )}

)

L_M=

ì

2P

O(FL)

8.2.2.2.3 Primary Winding Turns (N_P)

The number of turns on the primary winding (N_P) of the transformer is determined by two design considerations:

1. The maximum flux density (B_MAX) must be kept below the saturation limit (B_SAT) of the chosen magnetic

core under the highest peak magnetizing current (I_M+(MAX)) condition, the cross-sectional area (A_E) of the

core, and highest core temperature. When I_FB= 0 A, such as during V_Osoft-start or step-up load transient,

the peak magnetizing current reaches I_M+(MAX), since V_CST= V_CST(MAX)in those conditions. I_M+(MAX)can be

estimated based on the output power triggering an OPP fault (P_O(OPP)) with V_CST= V_CST(OPP1)at V_BULK(MIN)

.

2P

V_{CST (MAX )}

V_{CST (OPP1)}

O(OPP)

I_{M +(MAX )}

=

D_MAXV_{BULK (MIN )}

h

(25)

L_MI_{M +(MAX )}

B_MAX

=

< B_SAT

N_PA_E

(26)

2. The AC flux density (ΔB) affects the core loss of the transformer. For a transition-mode ZVS flyback, the

core loss is usually highest at high line, since the switching frequency is highest, duty cycle is smallest,

and peak-to-peak magnetizing current swing is greatest for a given load condition. The following equation

is the ΔB calculation including the contribution of negative magnetizing current (I_M-), used to put into the

Steinmetz equation for more accurate core loss estimation. For V_BULK≥ N_PS(V_O+V_F), I_M-is calculated with

V_BULKdivided by the characteristic impedance of L_Mand the lumped time-related switch-node capacitance

(C_SW). I_M-is always a negative value. The expression of f_SWis derived based on the triangular approximation

of the magnetizing current, which also considers the effect of I_M-over wide DC or AC input line conditions.

C_SW

I_{M -}= -

V_BULK

L_M

(27)

(28)

(29)

P

1

O(FL)

I_IN

=

h

V_BULK

N_PS(V_O+V_F)

D =

V_BULK+ N_PS(V_O+V_F)

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D²V_BULK

2L_MI_IN- DL_MI_{M -}+ DV_BULKì0.5

f_SW

=

p

L_MC_SW

(30)

2P

O(FL)

2

I_{M +}

=

+ I_{M -}

h

L_Mf_SW

(31)

(32)

L_M(I_{M +}- I_{M -}

N_PA_E

)

DB =

For the ΔB calculation, remember that I_M-is a negative value and that ΔB is a peak-to-peak flux swing. Core loss

is based on ½ of ΔB.

8.2.2.2.4 Secondary Winding Turns (N_S)

After N_Pis chosen, N_Scan be calculated using the target N_PS. N_Sand N_Pare adjusted to the nearest suitable

integers.

N_P

N_S=

N_PS

(33)

Once N_Pand N_Sare finalized, the actual N_PSis recalculated. With the new N_PSvalue, 节 8.2.2.2.2 and follow-on

parameters are also recalculated to reflect the updated N_PSparameter change.

8.2.2.2.5 Auxiliary Winding Turns (N_A)

Turns of the auxiliary winding (N_A) is an integer value usually chosen to provide a nominal V_VDDthat satisfies all

devices powered from V_VDD, such as a gate driver, or the UCC28781. N_Ais determined by the following design

considerations:

1. V_VDDmust be lower than the maximum rating voltage of VDD pin (V_VDD(MAX)) at maximum output voltage

and rectifier forward drop (V_O(MAX)+ V_F). V_VDD(MAX)is also limited by the lowest maximum voltage rating

of any other devices connected to the VDD pin. For designs with a fixed output voltage or a narrow output

range, the maximum Auxiliary winding turns (N_A(max)) is given by the following equation.

V_{VDD(MAX )}

N_{A(MAX )}

=

N_S

V_{O(MAX )}+V_F

(34)

2. The nominal V_VDDcalculation must consider the impact on the stand-by power. Higher V_VDDresults in a

static loss increase with the total bias current of all devices connected to the VDD pin.

3. V_VDDshould be higher than the 13-V threshold voltage of survival mode (which is the sum of V_VDD(off)and

V_VDD(PCT)) at the minimum sustained output voltage (V_O(min)). ΔV here represents the voltage difference

between the nominal V_VDDand the survival-mode threshold. A minimum of 3 V is a recommended design

margin for ΔV.

V_{VDD(OFF )}+V_{VDD(PCT )}+ DV

N_S

N_{A(MIN )}

=

V_{O(MIN )}+V_F

(35)

N_A(min)must also accommodate the highest V_VDD(off)threshold of other devices powered by VDD, if any. Select

an integer value for N_Abetween the lowest N_A(MAX)and the highest N_A(MIN)with consideration of #2. For best

performance, design the DC resistance of the auxiliary winding to be < 0.1 Ω.

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8.2.2.2.6 Winding and Magnetic Core Materials

Besides the choice of AC flux density (ΔB) with L_Mand N_P, the core loss of the transformer can also be

significantly reduced by proper selection of the magnetic core material. For converters operating at full-load

switching frequencies up to 250 kHz, ferrite materials such as Ferroxcube 3C97 or 3C98, for example, exhibit

low core-loss density. For converters operating at full-load switching frequencies over 400 kHz, materials such

as 3F36 from Ferroxcube and N49 from TDK/Epcos exhibit low core-loss density. Other ferrite materials with

equivalent or similar loss characteristics may also be used.

Litz wire is recommended for both primary and secondary windings, in order to reduce the R_AClosses caused

by high-frequency proximity effect and skin effect of the windings. Choose a suitable insulation class for the

windings based on the expected and measured maximum operating temperature under sustained over-stress

conditions.

8.2.2.3 Calculation of ZVS Sensing Network

There are three components in the application circuit to help the depletion MOSFET (Q_S) perform ZVS

sensing safely: C_SWS, R_SWS, and D_SWS. Design considerations and selection guidelines for the values of these

components are given here.

At the rising edge of the switch-node voltage, the fast dV/dt may couple through the drain-to-source capacitance

of Q_S(C_OSS(Qs)) and generate a charge current that flows into the circuit loading on the Q_Ssource pin. The

result may be a possible voltage overshoot on both the SWS pin and across the gate-to-source of Q_S(V_GS(Qs)

)

because the gate is tied to P13. The SWS pin, having an absolute maximum voltage rating of 38 V, can handle

higher voltage stress than V_GS(Qs). Therefore, carefully select a capacitor (C_SWS) between the SWS pin and

GND to prevent the voltage overshoot from damaging the Q_Sgate. Because C_OSS(Qs)and C_SWSform a voltage

divider, the minimum C_SWS(C_SWS(min)) can be derived as

C

× V

V

+ N

V + V

PS O F

OSS Qs

BULK MAX

+ V

C

=

(36)

SWS min

P13

GS

MAX Qs

where

•

V_{GS_MAX(Qs)}is the de-rated maximum gate-to-source voltage of Q_S

V_P13is the steady-state voltage level of 13 V

Without resistive damping, both the charge current on the rising edge of V_SWand the discharge current on the

falling edge of V_SWmay oscillate with the parasitic series inductance within the ZVS sensing network resonating

with C_SWS. Therefore, a series resistor (R_SWS) between SWS pin and source-pin of Q_Sis used to dampen

any high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any

high-frequency current from interfering with other noise-sensitive signals. R_SWScan be expressed as:

L_SWS

R_SWS

>

C_SWS+ C_Dz

(37)

where

•

L_SWSis the lumped parasitic inductance including the packaging of Q_Sand PCB traces of Q_Sand C_SWS

return path

C_Dzis the junction capacitance of any zener diode applied across C_SWS, if used (usually not necessary).

For most applications, use a resistor value slightly higher than 500 Ω. The resistor and a 22-pF ceramic

capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the

internal detection circuit to identify the ZVS characteristic correctly.

Based on the above design guide, even though R_SWSand C_SWSmay be sufficient to manage the voltage

overshoot in normal operation, a low-capacitance bi-directional TVS diode (D_SWS) across BSS126 gate and

source is highly recommended to serve as a safety backup of the ZVS sensing network. Regular Zener diodes

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are not suitable due to high capacitance and slow clamping response. Ensure the clamping voltage of D_SWSis

less than BSS126 voltage rating but greater than 15 V.

A general recommendation is to use a 50-V 22-pF C0G-type ceramic capacitor for C_SWS, a 510-Ω chip resistor

for R_SWS, and a bi-directional TVS diode with clamp voltage of 18 V for D_SWS. Too large of R_SWSor C_SWS

introduces a sensing delay between the actual V_SWand the SWS pin, causing the ZVS control to unnecessarily

extend t_DMin order to pull down V_SWearlier than expected before the end of t_Z. As shown in 图 7-5, the larger

R_SWSis, the smaller supply current to charge the VDD capacitor. If the reduced charge current (I_SWS) is lower

than the total consumed current from the controller (I_START) and from the external circuitry on the VDD and P13

pins, V_VDDmay not be able to reach V_VDD(ON)and the controller can not initiate any switching event.

8.2.2.4 Calculation of BUR Pin Resistances

Referring back to 节 7.3.1, it is recommended that ABM is entered at no higher than 50% to 60% of full load.

Equation 1 and Equation 2, or Equation 1 and Equation 4, provide two equations for calculating two unknowns

for the BUR-pin resistor values. However, choose the target values of V_CST(BUR), ΔV_BUR(AAM), and ΔV_BUR(LPM)

first. Because the ratio of I_BUR(AAM)to I_BUR(LPM)is fixed at 1.852 (5 µA / 2.7 µA), it is necessary to target

ΔV_BUR(AAM)= 185 mV to ensure that ΔV_BUR(LPM)= 100 mV, per guidance in 节 7.3.1.

The procedure to determine the value of V_CST(BUR)is quite complex and is not provided in this datasheet.

Instead, a soon-to-be-released UCC28781 Excel Calculator Tool automatically calculates this value based on

user input and determines the V_BURtarget voltage V_{BUR_tgt}. Using this target value, it further determines the

appropriate values for R_BUR2and R_BUR1to meet the BUR pin targets based on user selections for the following

set of equations.

Expected values are used to determine recommended resistances, then actual resistances are selected from

standard value series and the resulting actual voltages are calculated from the selected resistor values. Actual

voltage results should be close to the targeted values.

Calculate expected ΔV_BUR(LPM)value based on ΔV_BUR(AAM)target value.

R

× R

+ R

BUR1

BUR2

∆ V

= I

×

(38)

BUR LPM

Calculate the expected value for the parallel combination of R_BUR1with R_BUR2

.

∆ V

BUR AAM

R

=

BUR2

I

(39)

BUR1

BUR AAM

Calculate the recommended value for R_BUR1and choose a standard 1% tolerance value for R_{BUR1_act}that is

close to the recommended value.

∆ V

V

BUR AAM

REF

+ ∆ V

BUR AAM

R

=

×

V

(40)

BUR1_rec

I

BUR AAM

BUR_tgt

Calculate the recommended value for R_BUR2using R_{BUR1_act}and choose a standard 1% tolerance value for

R_{BUR2_act}that is close to the recommended value.

V

+ ∆ V

BUR_tgt

BUR AAM

+ ∆ V

BUR AAM

R

= R

×

(41)

BUR2_rec

BUR1

V

− V

BUR_tgt

REF

Calculate the actual values for V_BUR, ΔV_BUR(AAM), and ΔV_BUR(LPM)using R_{BUR1_act}and R_{BUR2_act}

.

R

× R

+ R

BUR2

+ R

BUR1

BUR2

V

= V

×

− I

×

(42)

(43)

BUR_act

REF

BUR AAM

R

BUR1

BUR2

R

×

R

× R

BUR1

BUR2

∆ V

= I

BUR AAM

+ R

BUR2

BUR1

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R

× R

+ R

BUR1

BUR2

∆ V

= I

×

(44)

BUR LPM

Finally, verify that the total summation of the BUR voltage with hysteresis does not exceed the BUR-pin upper

clamp voltage of 2.4 V.

V

+ ∆ V

≤ 2.4 V

BUR LPM

(45)

BUR_act

BUR AAM

8.2.2.5 Calculation of Compensation Network

The UCC28781 integrates two control concepts to benefit high-efficiency operation: peak current-mode control

and burst-ripple control. The peak current loop in AAM can be analyzed based on linear control theory, so the

compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic

of a zero-voltage switching flyback converter. For transition-mode operation, the power stage can be modeled as

a voltage-controlled current source charging an output capacitor (C_O) with an equivalent-series resistance (R_Co)

and the output load (R_O) as shown in 图 8-2. The first-order plant characteristic and high switching frequency

operation in AAM make the peak current loop easier to stabilize than when in ABM.

^

Equivalent Circuit of ZVSF

V_O

^

K_FV_BULK

K_EI_FB

R_Co

C_O

R_O

R_E

H_V(s)

Compensation

V_O(REF)

^

I_FB

图 8-2. Small-Signal Model of ZVSF in AAM Loop

The adaptive burst mode (ABM) uses ripple-based control, so the linear control theory for AAM cannot be

applied. As illustrated in 图 7-4, the internal ramp compensation feature of the controller stabilizes the ABM

control loop, so the external compensation network can be simplified.

Optional

Compensation

V_O

Controller

REF

FB

R_DIFF

C_DIFF

R_BIAS1

C_FB

I_FB

I_OPTO

R_Vo1

V_FB(REG)

CTR

R_FBI

I_COMP

R_FB

I_FB

I_D

R_BIAS2

Active Ripple

Compensation

C_opto

RUN

Control

Law

R_INT

C_INT

ATL431

R_Vo2

图 8-3. Compensation Network, H_v(s)

The transfer function from I_FBto V_Oguides the pole/zero placement of the general secondary-side compensation

network in 图 8-3. In the primary-side control circuitry, two poles at ω_FBand ω_OPTOintroduce phase-delay on

I_FB. ω_FBpole is formed by the external filter capacitor C_FBand the parallel resistance of the internal R_FBIand

the external current-limiting resistor (R_FB). ω_OPTOpole is formed by the parasitic capacitance of the optocoupler

output (C_OPTO) and the series resistance of R_FBIand R_FB. For C_FB= 220 pF, R_FBI= 8 KΩ, and R_FB= 20 KΩ, the

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delay effect of ω_FBpole located at 139 kHz is negligible. C_OPTOis in the range of a few nanoFarads contributed

by the Miller effect of the collector-to-base capacitance of the BJT in the optocoupler output, so ω_OPTOpole is

located at less than 10 kHz.

If the control loop bandwidth needs to be designed at higher frequency for a faster transient response, the phase

delay effect of ω_OPTOon the stability margin must be taken into account. Therefore, an RC network (R_DIFFand

C_DIFF) in parallel with R_BIAS1is used to compensate the phase-delay of the optocoupler, which introduces an

extra pole/zero pair located at ω_P1and ω_Z1respectively. The basic design guide is to place the ω_Z1zero close

to the ω_OPTOpole, and to place ω_P1pole away from highest f_BUR. On the other hand, if the stability margin and

transient response are sufficient to meet the requirements without R_DIFFand C_DIFF, then these two components

are optional for the controller.

I_FB(s) CTR 1+ (s /

w

)

1

1+ (s /

_P1) 1+ (s /

w

)

1

Z 0

Z1

=

V_O(s) R_BIAS1(s /

w

_{Z 0}) 1+ (s /

w

) 1+ (s /

w

)

FB

OPTO

(46)

(47)

(48)

(49)

(50)

(51)

1

w

=

Z 0

Z1

P1

(R_Vo1+ R_INT)C_INT

1

w

(R_DIFF+ R_BIAS1)C_DIFF

1

R_DIFFC_DIFF

1

=

OPTO

(R_FB+ R_FBI)C_OPTO

1

w

=

FB

(R_FBI/ /R_FB)C_FB

The step-by-step design procedure of the compensator without R_DIFFand C_DIFFis:

1. R_FBselection needs to consider both the output voltage regulation and compensation challenge on the

low-frequency pole at ω_OPTO. R_FBshould be less than the maximum value of 28 kΩ to provide a sufficient

feedback current of 95 μA for the output voltage regulation in SBP2 mode, under the worst-case V_FB(REG)

and R_FBI. However, R_FB= 28 kΩ and C_OPTO= 2 nF result in an ω_OPTOpole located at 2.8 kHz. This

low-frequency pole may reduce phase margin at the cross-over frequency. If the control bandwidth is around

this frequency range, R_FBvalue should be designed even lower to move the pole to a higher frequency.

V_FB(REG)-V_CE(OPTO)

I_FB(SBP)

R_{FB(MAX )}

=

- R_FBI

(52)

2. R_BIAS1is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔV_O(ABM), and target

4~5 μA of ΔI_FBas example. At collector currents less than 100 μA, the CTR of most optocouplers can be as

low as 10%, or 0.1 (used in this example), although some high performance devices can have higher CTR.

CTR

0.1

R

=

× ∆ V

=

× ∆ V

O ABM

5 μA

(53)

BIAS1

O ABM

∆ I

FB

3. R_INTselection is not designed for the small-signal compensation, but to resolve the slow large-signal

response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load

occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage

continuously by the integrator configuration until the output voltage gets back to normal regulation level. If

the load step-up transient happens before the output voltage is settled from the previous load step-down

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event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a new

steady-state. Because the time for ATL431 to move from lower voltage to a high voltage delays i_FBreduction,

the controller response from SBP mode to AAM mode is delayed as well, which slows down the energy

delivery to the output and results in a large voltage undershoot.

To resolve this problem, R_INTbehaves like a current-limiting resistor for C_INT, which slows down the

reduction of the cathode voltage of ATL431. R_INTneeds to be adjusted based on the voltage undershoot

requirement under the highest repetitive rate of load change.

8.2.3 Application Curves

The efficiency data shown below is obtained over limited input voltage conditions at this time. Additional data

over an expanded voltage range is to be forth-coming.

图 8-4. 4pt-Average Efficiency vs. AC Input Voltage 图 8-5. 10%-Load Efficiency vs. AC Input Voltage

图 8-6. Full-Load Efficiency vs. AC Input Voltage

图 8-7. Average Switching Frequency at Full-Load

vs. AC Input Voltage

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9 Power Supply Recommendations

The UCC28781 controller is intended to control high-efficiency zero-voltage-switching flyback (ZVSF) converters

in the universal AC input range (85 V_ACto 265 V_AC, 47 Hz to 63 Hz) applications, and can work in high DC input

voltage applications as well. An external depletion-mode MOSFET, connected between the switch node of the

converter and the SWS + P13 pins of this controller, is required to charge the VDD capacitor during start-up and

to perform ZVS sensing during normal operation.

When the V_VDDreaches the UVLO turn-on threshold at 17 V, the VDD rail should be kept within the bias supply

operating voltage range listed in the 节 6.3 table. To avoid the possibility that the device might stop switching,

V_VDDmust not be allowed to fall below the UVLO turn-off threshold at 10.6 V.

The rectifier on the output winding must be a synchronous-rectifier (SR) MOSFET in order to generate the

negative magnetizing current necessary to achieve ZVS for high efficiency. The current rating of this SR

MOSFET should be appropriate for the peak current flowing during the demagnetization interval at maximum

loading. In addition to the output voltage plus reflected bulk voltage impressed across the SR during PWML

on-time, consideration for additional voltage spikes from various transient conditions should be made. Sources

of voltage spikes on the SR include: hard switching of the primary-side MOSFET and non-ZCS turn-off of the

SR-MOSFET.

Regardless of the cause of each of these spike sources, it is important to ensure that the peak voltage across

the SR does not exceed its maximum rating. This limitation can be accomplished in several ways:

•

choose a MOSFET with a higher voltage rating

add a snubber or voltage clamp across the SR, or

investigate each cause and mitigate the associated spike separately

The simplest approach may be to include a TVS clamp across the rectifier.

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10 Layout

10.1 Layout Guidelines

The ZVSF converter designed with the UCC28781 virtually eliminates switching loss with minimum circulating

energy, so higher switching frequencies, efficiencies, and greater power densities can be achieved. However,

when designing for higher switching frequencies, good layout practices as discussed below should be followed

to ensure a reliable and robust design.

10.1.1 General Considerations

Designing for high power density requires consideration of noise coupling and thermal management. A four-layer

PCB structure is highly recommended to use inner layers to help reduce current-loop areas and provide heat-

spreading for surface-mount semiconductors.

•

Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for switching

MOSFETs and power diodes. Use multiple thermal-vias to conduct heat from outer pads to inner-layers and

supporting copper areas.

•

To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas that carry high-

frequency switching voltage.

To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal

tracks in parallel with such loops.

Arrange the conducted-EMI filter components such that they do not allow switching noise to bypass them and

affect the input. Avoid running switching signals through the EMI filter area.

Use multiple vias to connect high-current tracks and planes between layers.

图 10-1 summarizes the critical layout guidelines, and more detail is further elaborated in the descriptions below.

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Keep control loop away

from dB/dt coupling of

transformer

Minimize the high di/dt switching loops to reduce EMI, voltage

stress on power devices, and noise coupling to control loop

Transformer

V_O

D_BG

F_AC

V_BULK

V_AC

L_K

C_X

C_BULK

L_M

N_P

N_S

C_O

Primary Power Ground

R_OCP

Shorten high dv/dt

traces for less EMI

and noise coupling;

run orthogonally

GND

Q_SR

Isolated Driver

D_RUN

Secondary

Power

Ground

C_RUN

across other traces

Isolated Driver

(primary side)

R_XCD1

R_XCD2

(secondary side)

V_P13

Q_S

Keep signal and

power grounds

separate

D_SWS

Q_XCD

V_P13

PWMH

RUN

C_DIFF

Q_L

R_SWS

Shorten V_SWStrace

with dv/dt; keep away

from feedback loop

PWML

PGND

R_BIAS1

V_SWS

R_DIFF

Shorten VAUX trace

with dv/dt; keep away

from feedback loop

C_SWS

To C_BULK

ground

V_RCS

D_AUX

R_CS

Minimize high di/dt

switching loops

R_BIAS2

Dedicate C_SWS

return to R_CS

ground node

C_VDD1

N_A

V_P13

V_S13

Keep compensator

D_P13

C_VDD2

C_P13

C_INT

R_INT

away from dv/dt, di/

dt, and dB/dt noise

sources

R_VS1

R_VS2

VS

XCD

GTP3 GTP2 GTP1

VDD

P13

S13

SWS

RUN

Secondary Signal

Ground Plane

V_SWS

RUN

XCD

V_REF

UCC28781

PWMH

Follow grounding

arrangements shown in

this schematic diagram

PWML

PGND

PWML

PGND

BUR

SET

REF

FB RDM RTZ TP AGND FLT IPC

CS

R_OPP

To R_CS

ground

V_RCS

V_REF

C_FB

C_REF

C_CS

Primary Signal Ground Plane

R_FB

Keep signal

components close

to IC to minimize

noise coupling

Minimize FB loop area, keep away from noise sources, and

route emitter return back to AGND in parallel with FB path

图 10-1. Typical Schematic with Layout Considerations

10.1.2 RDM and RTZ Pins

Minimize stray capacitance to RDM and RTZ pins.

•

Place R_RDMand R_RTZas close as possible between the controller pins and AGND pin.

Avoid putting a ground plane or any other tracks under RDM and RTZ pins to minimize parasitic capacitance.

This can be accomplished by putting cutouts and/or keepouts in the layers below these pins.

10.1.3 SWS Pin

Minimize potential stray noise coupling from SWS pin to noise-sensitive signals.

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•

Keep some distance between SWS network and other connections.

The RC damping network (R_SWS, C_SWS) and the TVS diode (D_SWS) should be as close to the source pin of

Q_Sas possible instead of SWS pin, so the gate-to-source pin of Q_Scan be effectively protected.

Keep the return path for di/dt current through C_SWSand D_SWSseparate from the IC local GND and FB signal

return paths. Return C_SWSback to the ground node at R_CS, not at the IC.

•

10.1.4 VS Pin

Minimize stray capacitance at the VS pin to reduce the time-delay effect on ZVS control.

•

Avoid putting a GND plane under the VS pin to reduce parasitic capacitance. This can be accomplished by

inserting a cutout in the plane (if any) below this pin's pad and the tracks and pads of components connected

to VS. Minimize the track length of the VS net.

•

Do not run other tracks or planes over or under the VS net.

Do not run other tracks or planes under R_VS1and R_VS2

.

10.1.5 BUR Pin

The resistor divider (R_BUR1and R_BUR2) and the filter capacitor (C_BUR) on the BUR pin should to be as close to

the BUR pin and IC AGND as possible.

•

It is recommended to provide shielding on the BUR-pin trace with ground planes to minimize the noise-

coupling effect on peak current variation during burst-mode operation. This can be accomplished by adding a

ground plane under the BUR traces and pins.

10.1.6 FB Pin

This pin can be noise-sensitive to capacitive coupling from the high dV/dt switch nodes, or the flux coupling from

magnetic components and high di/dt switching loops.

•

Minimize the loop area for the PCB traces from the opto-coupler to the FB pin in order to avoid the possible

flux coupling effect. Run the opto-coupler emitter return track from AGND at the IC in parallel with the FB to

collector path, to minimize loop-area.

•

Keep PCB traces away from the high dv/dt signals, such as the switch node of the converter (V_SW), the

auxiliary winding voltage (V_AUX), and the SWS-pin voltage (V_SWS). If possible, it is recommended to provide

shielding for the FB trace with ground planes.

•

The filter capacitor between FB pin and REF pin (C_FB) needs to be as close to the two IC pins as possible.

The current-limiting resistor of FB pin (R_FB) should be as close to the FB pin as possible to enhance the noise

rejection of nearby capacitively-coupled noise sources.

10.1.7 CS Pin

The OPP-programming resistor (R_OPP) and the filter capacitor (C_CS) should be as close to the CS pin as

possible to improve the noise rejection of nearby capacitively-coupled noise sources, and to filter any ringing that

may be present during non-ZVS conditions.

10.1.8 AGND Pin

The AGND pin is the bias-power and signal-ground connection for the controller. The effectiveness of the filter

capacitors on the signal pins depends upon the integrity of this ground return.

•

Place the decoupling capacitors for VDD, REF, CS, BUR, and P13 pins as close as possible to the device

pins and AGND pin with short traces.

The device ground and power-stage ground should meet at the return pin of the current-sense resistor (R_CS).

Try to ensure that high frequency, high current from the power stage does not flow through the signal ground.

The thermal pad of the QFN package should be tied to the AGND pin with a short trace, and be connected

to the signal ground plane with multiple vias which becomes a low-impedance ground return of external

components to the AGND pin.

10.1.9 PGND Pin

The PGND pin is the gate-drive return for the PWML signal. It is NOT a ground return; do not confuse it as a

power ground pin. It is not connected to AGND within the device.

70

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•

The PGND signal is normally connected to the source pin of the low-side switching device, and run in parallel

with PWML to minimize loop area.

In certain cases, PGND may be connected to AGND at a location where PWML return currents do not create

ground noise to disturb control signals referenced to AGND.

For the individual low-side GaN power IC with logic PWM input, it is recommended to connect PGND to the

bottom of the current sense resistor (R_CS) directly.

10.1.10 Thermal Pad

The Thermal Pad (TP) is internally connected to the device substrate by an indeterminate impedance. Connect

this pad externally to AGND at the AGND pin and at other pins that may also be tied to AGND for the application.

This pad functions as a thermal dissipater for the device. Use multiple vias to connect this pad to other copper

planes and areas to help dissipate heat and to maintain the lowest GND impedance for signal integrity.

10.2 Layout Example

The layout techniques described in previous sections are applied to the layout of the 60-W high-density DC-to-

DC zero-voltage switching flyback converter. The schematic diagram of this converter is shown in the next three

figures, and the pcb layers are shown in the following four figures.

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3 ,

2 ,

1

8 ,

6 ,

7

5

,

3

2

1 A M T A 7 P 0 0 6 R 0 8 D P I

2

3

2

1

2

1

+

-

1

4

3

2

图 10-2. Power Stage of the 60-W EVM

English Data Sheet: SLUSEP2

72

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R105

VDD

2.10k

(at C100)

C17

C10

VAUX

0.1uF

10uF

22µF

R106

2.10k

VDD

(at R104)

Wire Adds

Track Cut

U1

REF

R36

DNP

1.0M

19

23

22

16

R20

VDD

SWS

GTP2

FB

SWS

FB

REF

15.4k

D101

75V

(at U100)

R108

27.4k

21

6

VS

C14

330pF

R30

20.0k

R23

6.98k

GTP3

OPTO_C

Wire Adds

R109

1.00k

P13

C23

1µF

12

15

14

13

PWML

PWMH

P13

S13

PWML

SRDRV

CS

R14

191k

D103

D102

27V

(at R101)

R110

10.0k

Q100

MMST3906-7-F

VAUX

R19

402

9

24

1

5

BUR

CS

BUR

RUN

QLSRC

39V

R13

39.2k

10

C21

C13

330pF

SET

FLT

RTZ

RDM

IPC

RUN

XCD

100pF

FLT

T rack Cut

R1

GND_P

17

18

XCD

3.32k

REF

C19

100pF

2

169kR8RTZ

93.1kR9RDM

IPC

RT1

47k

25

8

EP

AGND

GTP1

PGND

3

C100

2200pF

R104

2.21M

R100

DNP

DNP DNP

1.0M

4

CS

20

11

1.0M

GND_P

R17

0

7

4

3

REF

R103

CS

0

1

V+

DNP

QLSRC

V-

C12

0.22uF

RUN

UCC28781-Q1

470k

U100

TLV7021DCKR

Track Cut

1000pF

681k

GND_P

图 10-3. ZVSF Controller of the 60-W EVM

SRDRV

SR_DRV

U2

D7

1

2

1

8

7

6

5

IN

VDD

OUT

VSS

VOUT

3

2

C8

10µF

VCCI

GND

3

4

C11

RUN

VOUT

40V

R22

GND_S

UCC5304DWV

GND_P

TP5

VOUT_A

C25

0.015uF

R26

.0k

R25

150k

R27

U4

6

4

1

3

OPTO_C

22pF

C27

R29

R32

5.62k

10.0k

0 .01uF

TLP383(GR-TPL,E

GND_P

R31

30.0k

U3

ATL431AIDBZR

GND_S GND_S

图 10-4. SR Drive and Feedback Circuits of the 60-W EVM

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图 10-5. Top-Side Assembly and Top Layer of PCB

图 10-6. Bottom-Side Assembly and Bottom Layer of PCB

English Data Sheet: SLUSEP2

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图 10-7. Inner Layer 1 (Second Layer) of PCB

Inner Layer 2 (Third Layer) of PCB

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

11.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.4 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

English Data Sheet: SLUSEP2

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RTW 24

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224801/A

www.ti.com

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

4.15

3.85

A

B

4.15

3.85

PIN 1 INDEX AREA

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

(0.2) TYP

2X 2.5

EXPOSED

THERMAL PAD

12

7

20X 0.5

6

13

25

SYMM

2X

2.5

2.45±0.1

1

18

0.3

24X

0.18

19

0.5

24

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

C

24X

0.3

4219135/B 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.24)

(0.97)

25

SYMM

(3.8)

20X (0.5)

(R0.05)

TYP

13

6

(Ø0.2) TYP

VIA

7

12

(0.97)

(3.8)

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219135/B 11/2016

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

4X( 1.08)

(0.64) TYP

19

24

(R0.05) TYP

24X (0.6)

25

1

18

(0.64)

TYP

24X (0.24)

SYMM

(3.8)

20X (0.5)

13

6

7

12

METAL

TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED COVERAGE BY AREA UNDER PACKAGE

SCALE: 20X

4219135/B 11/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC28781
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 SR 控制的高密度零电压开关 (ZVS) 反激式控制器开关控制器
文件：	总84页 (文件大小：5306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28781 [TI]

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